David Daney | 5b3b168 | 2009-01-08 16:46:40 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2007 by Ralf Baechle |
| 7 | */ |
| 8 | #include <linux/clocksource.h> |
| 9 | #include <linux/init.h> |
| 10 | |
| 11 | #include <asm/time.h> |
| 12 | |
| 13 | #include <asm/octeon/octeon.h> |
| 14 | #include <asm/octeon/cvmx-ipd-defs.h> |
| 15 | |
| 16 | /* |
| 17 | * Set the current core's cvmcount counter to the value of the |
| 18 | * IPD_CLK_COUNT. We do this on all cores as they are brought |
| 19 | * on-line. This allows for a read from a local cpu register to |
| 20 | * access a synchronized counter. |
| 21 | * |
| 22 | */ |
| 23 | void octeon_init_cvmcount(void) |
| 24 | { |
| 25 | unsigned long flags; |
| 26 | unsigned loops = 2; |
| 27 | |
| 28 | /* Clobber loops so GCC will not unroll the following while loop. */ |
| 29 | asm("" : "+r" (loops)); |
| 30 | |
| 31 | local_irq_save(flags); |
| 32 | /* |
| 33 | * Loop several times so we are executing from the cache, |
| 34 | * which should give more deterministic timing. |
| 35 | */ |
| 36 | while (loops--) |
| 37 | write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT)); |
| 38 | local_irq_restore(flags); |
| 39 | } |
| 40 | |
Coly Li | d0ce9a5 | 2009-04-23 03:06:06 +0800 | [diff] [blame] | 41 | static cycle_t octeon_cvmcount_read(struct clocksource *cs) |
David Daney | 5b3b168 | 2009-01-08 16:46:40 -0800 | [diff] [blame] | 42 | { |
| 43 | return read_c0_cvmcount(); |
| 44 | } |
| 45 | |
| 46 | static struct clocksource clocksource_mips = { |
| 47 | .name = "OCTEON_CVMCOUNT", |
| 48 | .read = octeon_cvmcount_read, |
| 49 | .mask = CLOCKSOURCE_MASK(64), |
| 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 51 | }; |
| 52 | |
| 53 | void __init plat_time_init(void) |
| 54 | { |
| 55 | clocksource_mips.rating = 300; |
| 56 | clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); |
| 57 | clocksource_register(&clocksource_mips); |
| 58 | } |