David Collins | 0c19fa8 | 2012-01-30 11:23:38 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved. |
David Collins | 5c4a5ab | 2011-12-02 15:01:26 -0800 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __REGULATOR_PM8XXX_REGULATOR_H__ |
| 14 | #define __REGULATOR_PM8XXX_REGULATOR_H__ |
| 15 | |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 16 | #include <linux/kernel.h> |
David Collins | 5c4a5ab | 2011-12-02 15:01:26 -0800 | [diff] [blame] | 17 | #include <linux/regulator/machine.h> |
| 18 | |
| 19 | #define PM8XXX_REGULATOR_DEV_NAME "pm8xxx-regulator" |
| 20 | |
| 21 | /* Pin control input pins. */ |
| 22 | #define PM8XXX_VREG_PIN_CTRL_NONE 0x00 |
| 23 | #define PM8XXX_VREG_PIN_CTRL_EN0 0x01 |
| 24 | #define PM8XXX_VREG_PIN_CTRL_EN1 0x02 |
| 25 | #define PM8XXX_VREG_PIN_CTRL_EN2 0x04 |
| 26 | #define PM8XXX_VREG_PIN_CTRL_EN3 0x08 |
| 27 | #define PM8XXX_VREG_PIN_CTRL_ALL 0x0F |
| 28 | |
| 29 | #define PM8921_VREG_PIN_CTRL_NONE PM8XXX_VREG_PIN_CTRL_NONE |
| 30 | #define PM8921_VREG_PIN_CTRL_D1 PM8XXX_VREG_PIN_CTRL_EN0 |
| 31 | #define PM8921_VREG_PIN_CTRL_A0 PM8XXX_VREG_PIN_CTRL_EN1 |
| 32 | #define PM8921_VREG_PIN_CTRL_A1 PM8XXX_VREG_PIN_CTRL_EN2 |
| 33 | #define PM8921_VREG_PIN_CTRL_A2 PM8XXX_VREG_PIN_CTRL_EN3 |
| 34 | |
| 35 | /* Minimum high power mode loads in uA. */ |
| 36 | #define PM8XXX_VREG_LDO_50_HPM_MIN_LOAD 5000 |
| 37 | #define PM8XXX_VREG_LDO_150_HPM_MIN_LOAD 10000 |
| 38 | #define PM8XXX_VREG_LDO_300_HPM_MIN_LOAD 10000 |
| 39 | #define PM8XXX_VREG_LDO_600_HPM_MIN_LOAD 10000 |
| 40 | #define PM8XXX_VREG_LDO_1200_HPM_MIN_LOAD 10000 |
| 41 | #define PM8XXX_VREG_SMPS_1500_HPM_MIN_LOAD 100000 |
| 42 | #define PM8XXX_VREG_SMPS_2000_HPM_MIN_LOAD 100000 |
| 43 | |
| 44 | #define REGULATOR_TEST_BANKS_MAX 8 |
| 45 | |
| 46 | /** |
| 47 | * enum pm8xxx_vreg_pin_function - action to perform when pin control is active |
| 48 | * %PM8XXX_VREG_PIN_FN_ENABLE: pin control enables the regulator |
| 49 | * %PM8XXX_VREG_PIN_FN_MODE: pin control changes mode from LPM to HPM |
| 50 | */ |
| 51 | enum pm8xxx_vreg_pin_function { |
| 52 | PM8XXX_VREG_PIN_FN_ENABLE = 0, |
| 53 | PM8XXX_VREG_PIN_FN_MODE, |
| 54 | }; |
| 55 | |
| 56 | /** |
| 57 | * struct pm8xxx_regulator_platform_data - PMIC 8921 regulator platform data |
| 58 | * @init_data: regulator constraints |
| 59 | * @id: regulator id. Any value unique among pm8xxx_regulator |
| 60 | * devices is acceptable. |
| 61 | * @pull_down_enable: 0 = no pulldown, 1 = pulldown when regulator disabled |
| 62 | * @pin_ctrl: pin control inputs to use for the regulator; should be |
| 63 | * a combination of PM8XXX_VREG_PIN_CTRL_* values |
| 64 | * @pin_fn: action to perform when pin control pin is active |
| 65 | * @system_uA: current drawn from regulator not accounted for by any |
| 66 | * regulator framework consumer |
| 67 | * @enable_time: time in us taken to enable a regulator to the maximum |
| 68 | * allowed voltage for the system. This is dependent upon |
| 69 | * the load and capacitance for a regulator on the board. |
David Collins | d161f5a | 2012-05-25 14:44:45 -0700 | [diff] [blame] | 70 | * @slew_rate: worst case rate of change of regulator output voltage |
| 71 | * in units of uV/us (V/s). This is dependent upon the |
| 72 | * load and capacitance for a regulator on the board. |
David Collins | 0c19fa8 | 2012-01-30 11:23:38 -0800 | [diff] [blame] | 73 | * @ocp_enable: enable over current protection logic (available for |
| 74 | * LVS and MVS type switches) |
| 75 | * @ocp_enable_time: time in us to delay between enabling the switch and then |
| 76 | * enabling OCP for it. This delay is needed to avoid |
| 77 | * false triggering due to inrush current. |
David Collins | 5c4a5ab | 2011-12-02 15:01:26 -0800 | [diff] [blame] | 78 | */ |
| 79 | struct pm8xxx_regulator_platform_data { |
| 80 | struct regulator_init_data init_data; |
| 81 | int id; |
| 82 | unsigned pull_down_enable; |
| 83 | unsigned pin_ctrl; |
| 84 | enum pm8xxx_vreg_pin_function pin_fn; |
| 85 | int system_uA; |
| 86 | int enable_time; |
David Collins | d161f5a | 2012-05-25 14:44:45 -0700 | [diff] [blame] | 87 | int slew_rate; |
David Collins | 0c19fa8 | 2012-01-30 11:23:38 -0800 | [diff] [blame] | 88 | unsigned ocp_enable; |
| 89 | int ocp_enable_time; |
David Collins | 5c4a5ab | 2011-12-02 15:01:26 -0800 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | #endif |