blob: 32c00cd2d83fcb67fc641f46374da168ff8aea67 [file] [log] [blame]
Joerg Roedelb6c02712008-06-26 21:27:53 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedelb6c02712008-06-26 21:27:53 +02003 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010020#include <linux/ratelimit.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020021#include <linux/pci.h>
Joerg Roedelcb41ed82011-04-05 11:00:53 +020022#include <linux/pci-ats.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080023#include <linux/bitmap.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Joerg Roedel7f265082008-12-12 13:50:21 +010025#include <linux/debugfs.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020026#include <linux/scatterlist.h>
FUJITA Tomonori51491362009-01-05 23:47:25 +090027#include <linux/dma-mapping.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020028#include <linux/iommu-helper.h>
Joerg Roedelc156e342008-12-02 18:13:27 +010029#include <linux/iommu.h>
Joerg Roedel815b33f2011-04-06 17:26:49 +020030#include <linux/delay.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020031#include <linux/amd-iommu.h>
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010032#include <linux/notifier.h>
33#include <linux/export.h>
Joerg Roedel17f5b562011-07-06 17:14:44 +020034#include <asm/msidef.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020035#include <asm/proto.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090036#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010037#include <asm/gart.h>
Joerg Roedel27c21272011-05-30 15:56:24 +020038#include <asm/dma.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020039
40#include "amd_iommu_proto.h"
41#include "amd_iommu_types.h"
Joerg Roedelb6c02712008-06-26 21:27:53 +020042
43#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
44
Joerg Roedel815b33f2011-04-06 17:26:49 +020045#define LOOP_TIMEOUT 100000
Joerg Roedel136f78a2008-07-11 17:14:27 +020046
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020047/*
48 * This bitmap is used to advertise the page sizes our hardware support
49 * to the IOMMU core, which will then use this information to split
50 * physically contiguous memory regions it is mapping into page sizes
51 * that we support.
52 *
53 * Traditionally the IOMMU core just handed us the mappings directly,
54 * after making sure the size is an order of a 4KiB page and that the
55 * mapping has natural alignment.
56 *
57 * To retain this behavior, we currently advertise that we support
58 * all page sizes that are an order of 4KiB.
59 *
60 * If at some point we'd like to utilize the IOMMU core's new behavior,
61 * we could change this to advertise the real page sizes we support.
62 */
63#define AMD_IOMMU_PGSIZES (~0xFFFUL)
64
Joerg Roedelb6c02712008-06-26 21:27:53 +020065static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
Joerg Roedelbd60b732008-09-11 10:24:48 +020067/* A list of preallocated protection domains */
68static LIST_HEAD(iommu_pd_list);
69static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
Joerg Roedel8fa5f802011-06-09 12:24:45 +020071/* List of all available dev_data structures */
72static LIST_HEAD(dev_data_list);
73static DEFINE_SPINLOCK(dev_data_list_lock);
74
Joerg Roedel0feae532009-08-26 15:26:30 +020075/*
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
78 */
79static struct protection_domain *pt_domain;
80
Joerg Roedel26961ef2008-12-03 17:00:17 +010081static struct iommu_ops amd_iommu_ops;
Joerg Roedel26961ef2008-12-03 17:00:17 +010082
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010083static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
Joerg Roedel52815b72011-11-17 17:24:28 +010084int amd_iommu_max_glx_val = -1;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010085
Joerg Roedel431b2a22008-07-11 17:14:22 +020086/*
87 * general struct to manage commands send to an IOMMU
88 */
Joerg Roedeld6449532008-07-11 17:14:28 +020089struct iommu_cmd {
Joerg Roedelb6c02712008-06-26 21:27:53 +020090 u32 data[4];
91};
92
Joerg Roedel04bfdd82009-09-02 16:00:23 +020093static void update_domain(struct protection_domain *domain);
Joerg Roedel5abcdba2011-12-01 15:49:45 +010094static int __init alloc_passthrough_domain(void);
Chris Wrightc1eee672009-05-21 00:56:58 -070095
Joerg Roedel15898bb2009-11-24 15:39:42 +010096/****************************************************************************
97 *
98 * Helper functions
99 *
100 ****************************************************************************/
101
Joerg Roedelf62dda62011-06-09 12:55:35 +0200102static struct iommu_dev_data *alloc_dev_data(u16 devid)
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200103{
104 struct iommu_dev_data *dev_data;
105 unsigned long flags;
106
107 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
108 if (!dev_data)
109 return NULL;
110
Joerg Roedelf62dda62011-06-09 12:55:35 +0200111 dev_data->devid = devid;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200112 atomic_set(&dev_data->bind, 0);
113
114 spin_lock_irqsave(&dev_data_list_lock, flags);
115 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
116 spin_unlock_irqrestore(&dev_data_list_lock, flags);
117
118 return dev_data;
119}
120
121static void free_dev_data(struct iommu_dev_data *dev_data)
122{
123 unsigned long flags;
124
125 spin_lock_irqsave(&dev_data_list_lock, flags);
126 list_del(&dev_data->dev_data_list);
127 spin_unlock_irqrestore(&dev_data_list_lock, flags);
128
129 kfree(dev_data);
130}
131
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200132static struct iommu_dev_data *search_dev_data(u16 devid)
133{
134 struct iommu_dev_data *dev_data;
135 unsigned long flags;
136
137 spin_lock_irqsave(&dev_data_list_lock, flags);
138 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
139 if (dev_data->devid == devid)
140 goto out_unlock;
141 }
142
143 dev_data = NULL;
144
145out_unlock:
146 spin_unlock_irqrestore(&dev_data_list_lock, flags);
147
148 return dev_data;
149}
150
151static struct iommu_dev_data *find_dev_data(u16 devid)
152{
153 struct iommu_dev_data *dev_data;
154
155 dev_data = search_dev_data(devid);
156
157 if (dev_data == NULL)
158 dev_data = alloc_dev_data(devid);
159
160 return dev_data;
161}
162
Joerg Roedel15898bb2009-11-24 15:39:42 +0100163static inline u16 get_device_id(struct device *dev)
164{
165 struct pci_dev *pdev = to_pci_dev(dev);
166
167 return calc_devid(pdev->bus->number, pdev->devfn);
168}
169
Joerg Roedel657cbb62009-11-23 15:26:46 +0100170static struct iommu_dev_data *get_dev_data(struct device *dev)
171{
172 return dev->archdata.iommu;
173}
174
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100175static bool pci_iommuv2_capable(struct pci_dev *pdev)
176{
177 static const int caps[] = {
178 PCI_EXT_CAP_ID_ATS,
Joerg Roedel46277b72011-12-07 14:34:02 +0100179 PCI_EXT_CAP_ID_PRI,
180 PCI_EXT_CAP_ID_PASID,
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100181 };
182 int i, pos;
183
184 for (i = 0; i < 3; ++i) {
185 pos = pci_find_ext_capability(pdev, caps[i]);
186 if (pos == 0)
187 return false;
188 }
189
190 return true;
191}
192
Joerg Roedel6a113dd2011-12-01 12:04:58 +0100193static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
194{
195 struct iommu_dev_data *dev_data;
196
197 dev_data = get_dev_data(&pdev->dev);
198
199 return dev_data->errata & (1 << erratum) ? true : false;
200}
201
Joerg Roedel71c70982009-11-24 16:43:06 +0100202/*
203 * In this function the list of preallocated protection domains is traversed to
204 * find the domain for a specific device
205 */
206static struct dma_ops_domain *find_protection_domain(u16 devid)
207{
208 struct dma_ops_domain *entry, *ret = NULL;
209 unsigned long flags;
210 u16 alias = amd_iommu_alias_table[devid];
211
212 if (list_empty(&iommu_pd_list))
213 return NULL;
214
215 spin_lock_irqsave(&iommu_pd_list_lock, flags);
216
217 list_for_each_entry(entry, &iommu_pd_list, list) {
218 if (entry->target_dev == devid ||
219 entry->target_dev == alias) {
220 ret = entry;
221 break;
222 }
223 }
224
225 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
226
227 return ret;
228}
229
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100230/*
231 * This function checks if the driver got a valid device from the caller to
232 * avoid dereferencing invalid pointers.
233 */
234static bool check_device(struct device *dev)
235{
236 u16 devid;
237
238 if (!dev || !dev->dma_mask)
239 return false;
240
241 /* No device or no PCI device */
Julia Lawall339d3262010-02-06 09:42:39 +0100242 if (dev->bus != &pci_bus_type)
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100243 return false;
244
245 devid = get_device_id(dev);
246
247 /* Out of our scope? */
248 if (devid > amd_iommu_last_bdf)
249 return false;
250
251 if (amd_iommu_rlookup_table[devid] == NULL)
252 return false;
253
254 return true;
255}
256
Joerg Roedel657cbb62009-11-23 15:26:46 +0100257static int iommu_init_device(struct device *dev)
258{
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100259 struct pci_dev *pdev = to_pci_dev(dev);
Joerg Roedel657cbb62009-11-23 15:26:46 +0100260 struct iommu_dev_data *dev_data;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200261 u16 alias;
Joerg Roedel657cbb62009-11-23 15:26:46 +0100262
263 if (dev->archdata.iommu)
264 return 0;
265
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200266 dev_data = find_dev_data(get_device_id(dev));
Joerg Roedel657cbb62009-11-23 15:26:46 +0100267 if (!dev_data)
268 return -ENOMEM;
269
Joerg Roedelf62dda62011-06-09 12:55:35 +0200270 alias = amd_iommu_alias_table[dev_data->devid];
Joerg Roedel2b02b092011-06-09 17:48:39 +0200271 if (alias != dev_data->devid) {
Joerg Roedel71f77582011-06-09 19:03:15 +0200272 struct iommu_dev_data *alias_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +0100273
Joerg Roedel71f77582011-06-09 19:03:15 +0200274 alias_data = find_dev_data(alias);
275 if (alias_data == NULL) {
276 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
277 dev_name(dev));
Joerg Roedel2b02b092011-06-09 17:48:39 +0200278 free_dev_data(dev_data);
279 return -ENOTSUPP;
280 }
Joerg Roedel71f77582011-06-09 19:03:15 +0200281 dev_data->alias_data = alias_data;
Joerg Roedel26018872011-06-06 16:50:14 +0200282 }
Joerg Roedel657cbb62009-11-23 15:26:46 +0100283
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100284 if (pci_iommuv2_capable(pdev)) {
285 struct amd_iommu *iommu;
286
287 iommu = amd_iommu_rlookup_table[dev_data->devid];
288 dev_data->iommu_v2 = iommu->is_iommu_v2;
289 }
290
Joerg Roedel657cbb62009-11-23 15:26:46 +0100291 dev->archdata.iommu = dev_data;
292
Joerg Roedel657cbb62009-11-23 15:26:46 +0100293 return 0;
294}
295
Joerg Roedel26018872011-06-06 16:50:14 +0200296static void iommu_ignore_device(struct device *dev)
297{
298 u16 devid, alias;
299
300 devid = get_device_id(dev);
301 alias = amd_iommu_alias_table[devid];
302
303 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
304 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
305
306 amd_iommu_rlookup_table[devid] = NULL;
307 amd_iommu_rlookup_table[alias] = NULL;
308}
309
Joerg Roedel657cbb62009-11-23 15:26:46 +0100310static void iommu_uninit_device(struct device *dev)
311{
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200312 /*
313 * Nothing to do here - we keep dev_data around for unplugged devices
314 * and reuse it when the device is re-plugged - not doing so would
315 * introduce a ton of races.
316 */
Joerg Roedel657cbb62009-11-23 15:26:46 +0100317}
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100318
319void __init amd_iommu_uninit_devices(void)
320{
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200321 struct iommu_dev_data *dev_data, *n;
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100322 struct pci_dev *pdev = NULL;
323
324 for_each_pci_dev(pdev) {
325
326 if (!check_device(&pdev->dev))
327 continue;
328
329 iommu_uninit_device(&pdev->dev);
330 }
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200331
332 /* Free all of our dev_data structures */
333 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
334 free_dev_data(dev_data);
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100335}
336
337int __init amd_iommu_init_devices(void)
338{
339 struct pci_dev *pdev = NULL;
340 int ret = 0;
341
342 for_each_pci_dev(pdev) {
343
344 if (!check_device(&pdev->dev))
345 continue;
346
347 ret = iommu_init_device(&pdev->dev);
Joerg Roedel26018872011-06-06 16:50:14 +0200348 if (ret == -ENOTSUPP)
349 iommu_ignore_device(&pdev->dev);
350 else if (ret)
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100351 goto out_free;
352 }
353
354 return 0;
355
356out_free:
357
358 amd_iommu_uninit_devices();
359
360 return ret;
361}
Joerg Roedel7f265082008-12-12 13:50:21 +0100362#ifdef CONFIG_AMD_IOMMU_STATS
363
364/*
365 * Initialization code for statistics collection
366 */
367
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100368DECLARE_STATS_COUNTER(compl_wait);
Joerg Roedel0f2a86f2008-12-12 15:05:16 +0100369DECLARE_STATS_COUNTER(cnt_map_single);
Joerg Roedel146a6912008-12-12 15:07:12 +0100370DECLARE_STATS_COUNTER(cnt_unmap_single);
Joerg Roedeld03f0672008-12-12 15:09:48 +0100371DECLARE_STATS_COUNTER(cnt_map_sg);
Joerg Roedel55877a62008-12-12 15:12:14 +0100372DECLARE_STATS_COUNTER(cnt_unmap_sg);
Joerg Roedelc8f0fb32008-12-12 15:14:21 +0100373DECLARE_STATS_COUNTER(cnt_alloc_coherent);
Joerg Roedel5d31ee72008-12-12 15:16:38 +0100374DECLARE_STATS_COUNTER(cnt_free_coherent);
Joerg Roedelc1858972008-12-12 15:42:39 +0100375DECLARE_STATS_COUNTER(cross_page);
Joerg Roedelf57d98a2008-12-12 15:46:29 +0100376DECLARE_STATS_COUNTER(domain_flush_single);
Joerg Roedel18811f52008-12-12 15:48:28 +0100377DECLARE_STATS_COUNTER(domain_flush_all);
Joerg Roedel5774f7c2008-12-12 15:57:30 +0100378DECLARE_STATS_COUNTER(alloced_io_mem);
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +0100379DECLARE_STATS_COUNTER(total_map_requests);
Joerg Roedel399be2f2011-12-01 16:53:47 +0100380DECLARE_STATS_COUNTER(complete_ppr);
381DECLARE_STATS_COUNTER(invalidate_iotlb);
382DECLARE_STATS_COUNTER(invalidate_iotlb_all);
383DECLARE_STATS_COUNTER(pri_requests);
384
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100385
Joerg Roedel7f265082008-12-12 13:50:21 +0100386static struct dentry *stats_dir;
Joerg Roedel7f265082008-12-12 13:50:21 +0100387static struct dentry *de_fflush;
388
389static void amd_iommu_stats_add(struct __iommu_counter *cnt)
390{
391 if (stats_dir == NULL)
392 return;
393
394 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
395 &cnt->value);
396}
397
398static void amd_iommu_stats_init(void)
399{
400 stats_dir = debugfs_create_dir("amd-iommu", NULL);
401 if (stats_dir == NULL)
402 return;
403
Joerg Roedel7f265082008-12-12 13:50:21 +0100404 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
405 (u32 *)&amd_iommu_unmap_flush);
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100406
407 amd_iommu_stats_add(&compl_wait);
Joerg Roedel0f2a86f2008-12-12 15:05:16 +0100408 amd_iommu_stats_add(&cnt_map_single);
Joerg Roedel146a6912008-12-12 15:07:12 +0100409 amd_iommu_stats_add(&cnt_unmap_single);
Joerg Roedeld03f0672008-12-12 15:09:48 +0100410 amd_iommu_stats_add(&cnt_map_sg);
Joerg Roedel55877a62008-12-12 15:12:14 +0100411 amd_iommu_stats_add(&cnt_unmap_sg);
Joerg Roedelc8f0fb32008-12-12 15:14:21 +0100412 amd_iommu_stats_add(&cnt_alloc_coherent);
Joerg Roedel5d31ee72008-12-12 15:16:38 +0100413 amd_iommu_stats_add(&cnt_free_coherent);
Joerg Roedelc1858972008-12-12 15:42:39 +0100414 amd_iommu_stats_add(&cross_page);
Joerg Roedelf57d98a2008-12-12 15:46:29 +0100415 amd_iommu_stats_add(&domain_flush_single);
Joerg Roedel18811f52008-12-12 15:48:28 +0100416 amd_iommu_stats_add(&domain_flush_all);
Joerg Roedel5774f7c2008-12-12 15:57:30 +0100417 amd_iommu_stats_add(&alloced_io_mem);
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +0100418 amd_iommu_stats_add(&total_map_requests);
Joerg Roedel399be2f2011-12-01 16:53:47 +0100419 amd_iommu_stats_add(&complete_ppr);
420 amd_iommu_stats_add(&invalidate_iotlb);
421 amd_iommu_stats_add(&invalidate_iotlb_all);
422 amd_iommu_stats_add(&pri_requests);
Joerg Roedel7f265082008-12-12 13:50:21 +0100423}
424
425#endif
426
Joerg Roedel431b2a22008-07-11 17:14:22 +0200427/****************************************************************************
428 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200429 * Interrupt handling functions
430 *
431 ****************************************************************************/
432
Joerg Roedele3e59872009-09-03 14:02:10 +0200433static void dump_dte_entry(u16 devid)
434{
435 int i;
436
Joerg Roedelee6c2862011-11-09 12:06:03 +0100437 for (i = 0; i < 4; ++i)
438 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
Joerg Roedele3e59872009-09-03 14:02:10 +0200439 amd_iommu_dev_table[devid].data[i]);
440}
441
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200442static void dump_command(unsigned long phys_addr)
443{
444 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
445 int i;
446
447 for (i = 0; i < 4; ++i)
448 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
449}
450
Joerg Roedela345b232009-09-03 15:01:43 +0200451static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
Joerg Roedel90008ee2008-09-09 16:41:05 +0200452{
453 u32 *event = __evt;
454 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
455 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
456 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
457 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
458 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
459
Joerg Roedel4c6f40d2009-09-01 16:43:58 +0200460 printk(KERN_ERR "AMD-Vi: Event logged [");
Joerg Roedel90008ee2008-09-09 16:41:05 +0200461
462 switch (type) {
463 case EVENT_TYPE_ILL_DEV:
464 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
465 "address=0x%016llx flags=0x%04x]\n",
466 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
467 address, flags);
Joerg Roedele3e59872009-09-03 14:02:10 +0200468 dump_dte_entry(devid);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200469 break;
470 case EVENT_TYPE_IO_FAULT:
471 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
472 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
473 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
474 domid, address, flags);
475 break;
476 case EVENT_TYPE_DEV_TAB_ERR:
477 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
478 "address=0x%016llx flags=0x%04x]\n",
479 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
480 address, flags);
481 break;
482 case EVENT_TYPE_PAGE_TAB_ERR:
483 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
484 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
485 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
486 domid, address, flags);
487 break;
488 case EVENT_TYPE_ILL_CMD:
489 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200490 dump_command(address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200491 break;
492 case EVENT_TYPE_CMD_HARD_ERR:
493 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
494 "flags=0x%04x]\n", address, flags);
495 break;
496 case EVENT_TYPE_IOTLB_INV_TO:
497 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
498 "address=0x%016llx]\n",
499 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
500 address);
501 break;
502 case EVENT_TYPE_INV_DEV_REQ:
503 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
504 "address=0x%016llx flags=0x%04x]\n",
505 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
506 address, flags);
507 break;
508 default:
509 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
510 }
511}
512
513static void iommu_poll_events(struct amd_iommu *iommu)
514{
515 u32 head, tail;
516 unsigned long flags;
517
518 spin_lock_irqsave(&iommu->lock, flags);
519
520 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
521 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
522
523 while (head != tail) {
Joerg Roedela345b232009-09-03 15:01:43 +0200524 iommu_print_event(iommu, iommu->evt_buf + head);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200525 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
526 }
527
528 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
529
530 spin_unlock_irqrestore(&iommu->lock, flags);
531}
532
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100533static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
534{
535 struct amd_iommu_fault fault;
536 volatile u64 *raw;
537 int i;
538
Joerg Roedel399be2f2011-12-01 16:53:47 +0100539 INC_STATS_COUNTER(pri_requests);
540
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100541 raw = (u64 *)(iommu->ppr_log + head);
542
543 /*
544 * Hardware bug: Interrupt may arrive before the entry is written to
545 * memory. If this happens we need to wait for the entry to arrive.
546 */
547 for (i = 0; i < LOOP_TIMEOUT; ++i) {
548 if (PPR_REQ_TYPE(raw[0]) != 0)
549 break;
550 udelay(1);
551 }
552
553 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
554 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
555 return;
556 }
557
558 fault.address = raw[1];
559 fault.pasid = PPR_PASID(raw[0]);
560 fault.device_id = PPR_DEVID(raw[0]);
561 fault.tag = PPR_TAG(raw[0]);
562 fault.flags = PPR_FLAGS(raw[0]);
563
564 /*
565 * To detect the hardware bug we need to clear the entry
566 * to back to zero.
567 */
568 raw[0] = raw[1] = 0;
569
570 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
571}
572
573static void iommu_poll_ppr_log(struct amd_iommu *iommu)
574{
575 unsigned long flags;
576 u32 head, tail;
577
578 if (iommu->ppr_log == NULL)
579 return;
580
581 spin_lock_irqsave(&iommu->lock, flags);
582
583 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
584 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
585
586 while (head != tail) {
587
588 /* Handle PPR entry */
589 iommu_handle_ppr_entry(iommu, head);
590
591 /* Update and refresh ring-buffer state*/
592 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
593 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
594 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
595 }
596
597 /* enable ppr interrupts again */
598 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
599
600 spin_unlock_irqrestore(&iommu->lock, flags);
601}
602
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200603irqreturn_t amd_iommu_int_thread(int irq, void *data)
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200604{
Joerg Roedel90008ee2008-09-09 16:41:05 +0200605 struct amd_iommu *iommu;
606
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100607 for_each_iommu(iommu) {
Joerg Roedel90008ee2008-09-09 16:41:05 +0200608 iommu_poll_events(iommu);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100609 iommu_poll_ppr_log(iommu);
610 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200611
612 return IRQ_HANDLED;
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200613}
614
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200615irqreturn_t amd_iommu_int_handler(int irq, void *data)
616{
617 return IRQ_WAKE_THREAD;
618}
619
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200620/****************************************************************************
621 *
Joerg Roedel431b2a22008-07-11 17:14:22 +0200622 * IOMMU command queuing functions
623 *
624 ****************************************************************************/
625
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200626static int wait_on_sem(volatile u64 *sem)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200627{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200628 int i = 0;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200629
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200630 while (*sem == 0 && i < LOOP_TIMEOUT) {
631 udelay(1);
632 i += 1;
633 }
634
635 if (i == LOOP_TIMEOUT) {
636 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
637 return -EIO;
638 }
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200639
640 return 0;
641}
642
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200643static void copy_cmd_to_buffer(struct amd_iommu *iommu,
644 struct iommu_cmd *cmd,
645 u32 tail)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200646{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200647 u8 *target;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200648
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200649 target = iommu->cmd_buf + tail;
650 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200651
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200652 /* Copy command to buffer */
653 memcpy(target, cmd, sizeof(*cmd));
654
655 /* Tell the IOMMU about it */
656 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
657}
658
Joerg Roedel815b33f2011-04-06 17:26:49 +0200659static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
Joerg Roedelded46732011-04-06 10:53:48 +0200660{
Joerg Roedel815b33f2011-04-06 17:26:49 +0200661 WARN_ON(address & 0x7ULL);
662
Joerg Roedelded46732011-04-06 10:53:48 +0200663 memset(cmd, 0, sizeof(*cmd));
Joerg Roedel815b33f2011-04-06 17:26:49 +0200664 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
665 cmd->data[1] = upper_32_bits(__pa(address));
666 cmd->data[2] = 1;
Joerg Roedelded46732011-04-06 10:53:48 +0200667 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
668}
669
Joerg Roedel94fe79e2011-04-06 11:07:21 +0200670static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
671{
672 memset(cmd, 0, sizeof(*cmd));
673 cmd->data[0] = devid;
674 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
675}
676
Joerg Roedel11b64022011-04-06 11:49:28 +0200677static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
678 size_t size, u16 domid, int pde)
679{
680 u64 pages;
681 int s;
682
683 pages = iommu_num_pages(address, size, PAGE_SIZE);
684 s = 0;
685
686 if (pages > 1) {
687 /*
688 * If we have to flush more than one page, flush all
689 * TLB entries for this domain
690 */
691 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
692 s = 1;
693 }
694
695 address &= PAGE_MASK;
696
697 memset(cmd, 0, sizeof(*cmd));
698 cmd->data[1] |= domid;
699 cmd->data[2] = lower_32_bits(address);
700 cmd->data[3] = upper_32_bits(address);
701 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
702 if (s) /* size bit - we flush more than one 4kb page */
703 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
704 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
705 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
706}
707
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200708static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
709 u64 address, size_t size)
710{
711 u64 pages;
712 int s;
713
714 pages = iommu_num_pages(address, size, PAGE_SIZE);
715 s = 0;
716
717 if (pages > 1) {
718 /*
719 * If we have to flush more than one page, flush all
720 * TLB entries for this domain
721 */
722 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
723 s = 1;
724 }
725
726 address &= PAGE_MASK;
727
728 memset(cmd, 0, sizeof(*cmd));
729 cmd->data[0] = devid;
730 cmd->data[0] |= (qdep & 0xff) << 24;
731 cmd->data[1] = devid;
732 cmd->data[2] = lower_32_bits(address);
733 cmd->data[3] = upper_32_bits(address);
734 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
735 if (s)
736 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
737}
738
Joerg Roedel22e266c2011-11-21 15:59:08 +0100739static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
740 u64 address, bool size)
741{
742 memset(cmd, 0, sizeof(*cmd));
743
744 address &= ~(0xfffULL);
745
746 cmd->data[0] = pasid & PASID_MASK;
747 cmd->data[1] = domid;
748 cmd->data[2] = lower_32_bits(address);
749 cmd->data[3] = upper_32_bits(address);
750 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
751 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
752 if (size)
753 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
754 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
755}
756
757static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
758 int qdep, u64 address, bool size)
759{
760 memset(cmd, 0, sizeof(*cmd));
761
762 address &= ~(0xfffULL);
763
764 cmd->data[0] = devid;
765 cmd->data[0] |= (pasid & 0xff) << 16;
766 cmd->data[0] |= (qdep & 0xff) << 24;
767 cmd->data[1] = devid;
768 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
769 cmd->data[2] = lower_32_bits(address);
770 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
771 cmd->data[3] = upper_32_bits(address);
772 if (size)
773 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
774 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
775}
776
Joerg Roedelc99afa22011-11-21 18:19:25 +0100777static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
778 int status, int tag, bool gn)
779{
780 memset(cmd, 0, sizeof(*cmd));
781
782 cmd->data[0] = devid;
783 if (gn) {
784 cmd->data[1] = pasid & PASID_MASK;
785 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
786 }
787 cmd->data[3] = tag & 0x1ff;
788 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
789
790 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
791}
792
Joerg Roedel58fc7f12011-04-11 11:13:24 +0200793static void build_inv_all(struct iommu_cmd *cmd)
794{
795 memset(cmd, 0, sizeof(*cmd));
796 CMD_SET_TYPE(cmd, CMD_INV_ALL);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200797}
798
Joerg Roedel431b2a22008-07-11 17:14:22 +0200799/*
Joerg Roedelb6c02712008-06-26 21:27:53 +0200800 * Writes the command to the IOMMUs command buffer and informs the
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200801 * hardware about the new command.
Joerg Roedel431b2a22008-07-11 17:14:22 +0200802 */
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200803static int iommu_queue_command_sync(struct amd_iommu *iommu,
804 struct iommu_cmd *cmd,
805 bool sync)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200806{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200807 u32 left, tail, head, next_tail;
Joerg Roedel815b33f2011-04-06 17:26:49 +0200808 unsigned long flags;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200809
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200810 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100811
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200812again:
Joerg Roedel815b33f2011-04-06 17:26:49 +0200813 spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200814
815 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
816 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
817 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
818 left = (head - next_tail) % iommu->cmd_buf_size;
819
820 if (left <= 2) {
821 struct iommu_cmd sync_cmd;
822 volatile u64 sem = 0;
823 int ret;
824
825 build_completion_wait(&sync_cmd, (u64)&sem);
826 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
827
828 spin_unlock_irqrestore(&iommu->lock, flags);
829
830 if ((ret = wait_on_sem(&sem)) != 0)
831 return ret;
832
833 goto again;
Joerg Roedel136f78a2008-07-11 17:14:27 +0200834 }
835
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200836 copy_cmd_to_buffer(iommu, cmd, tail);
Joerg Roedel519c31b2008-08-14 19:55:15 +0200837
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200838 /* We need to sync now to make sure all commands are processed */
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200839 iommu->need_sync = sync;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200840
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200841 spin_unlock_irqrestore(&iommu->lock, flags);
842
Joerg Roedel815b33f2011-04-06 17:26:49 +0200843 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +0100844}
845
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200846static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
847{
848 return iommu_queue_command_sync(iommu, cmd, true);
849}
850
Joerg Roedel8d201962008-12-02 20:34:41 +0100851/*
852 * This function queues a completion wait command into the command
853 * buffer of an IOMMU
854 */
Joerg Roedel8d201962008-12-02 20:34:41 +0100855static int iommu_completion_wait(struct amd_iommu *iommu)
856{
Joerg Roedel815b33f2011-04-06 17:26:49 +0200857 struct iommu_cmd cmd;
858 volatile u64 sem = 0;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200859 int ret;
Joerg Roedel8d201962008-12-02 20:34:41 +0100860
861 if (!iommu->need_sync)
Joerg Roedel815b33f2011-04-06 17:26:49 +0200862 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +0100863
Joerg Roedel815b33f2011-04-06 17:26:49 +0200864 build_completion_wait(&cmd, (u64)&sem);
Joerg Roedel8d201962008-12-02 20:34:41 +0100865
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200866 ret = iommu_queue_command_sync(iommu, &cmd, false);
Joerg Roedel8d201962008-12-02 20:34:41 +0100867 if (ret)
Joerg Roedel815b33f2011-04-06 17:26:49 +0200868 return ret;
Joerg Roedel8d201962008-12-02 20:34:41 +0100869
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200870 return wait_on_sem(&sem);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200871}
872
Joerg Roedeld8c13082011-04-06 18:51:26 +0200873static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200874{
875 struct iommu_cmd cmd;
876
Joerg Roedeld8c13082011-04-06 18:51:26 +0200877 build_inv_dte(&cmd, devid);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200878
Joerg Roedeld8c13082011-04-06 18:51:26 +0200879 return iommu_queue_command(iommu, &cmd);
880}
881
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200882static void iommu_flush_dte_all(struct amd_iommu *iommu)
883{
884 u32 devid;
885
886 for (devid = 0; devid <= 0xffff; ++devid)
887 iommu_flush_dte(iommu, devid);
888
889 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200890}
891
892/*
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200893 * This function uses heavy locking and may disable irqs for some time. But
894 * this is no issue because it is only called during resume.
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200895 */
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200896static void iommu_flush_tlb_all(struct amd_iommu *iommu)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200897{
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200898 u32 dom_id;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200899
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200900 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
901 struct iommu_cmd cmd;
902 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
903 dom_id, 1);
904 iommu_queue_command(iommu, &cmd);
905 }
Joerg Roedel431b2a22008-07-11 17:14:22 +0200906
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200907 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200908}
909
Joerg Roedel58fc7f12011-04-11 11:13:24 +0200910static void iommu_flush_all(struct amd_iommu *iommu)
911{
912 struct iommu_cmd cmd;
913
914 build_inv_all(&cmd);
915
916 iommu_queue_command(iommu, &cmd);
917 iommu_completion_wait(iommu);
918}
919
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200920void iommu_flush_all_caches(struct amd_iommu *iommu)
921{
Joerg Roedel58fc7f12011-04-11 11:13:24 +0200922 if (iommu_feature(iommu, FEATURE_IA)) {
923 iommu_flush_all(iommu);
924 } else {
925 iommu_flush_dte_all(iommu);
926 iommu_flush_tlb_all(iommu);
927 }
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +0200928}
929
Joerg Roedel431b2a22008-07-11 17:14:22 +0200930/*
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200931 * Command send function for flushing on-device TLB
932 */
Joerg Roedel6c542042011-06-09 17:07:31 +0200933static int device_flush_iotlb(struct iommu_dev_data *dev_data,
934 u64 address, size_t size)
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200935{
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200936 struct amd_iommu *iommu;
937 struct iommu_cmd cmd;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200938 int qdep;
939
Joerg Roedelea61cdd2011-06-09 12:56:30 +0200940 qdep = dev_data->ats.qdep;
941 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200942
Joerg Roedelea61cdd2011-06-09 12:56:30 +0200943 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200944
945 return iommu_queue_command(iommu, &cmd);
946}
947
948/*
Joerg Roedel431b2a22008-07-11 17:14:22 +0200949 * Command send function for invalidating a device table entry
950 */
Joerg Roedel6c542042011-06-09 17:07:31 +0200951static int device_flush_dte(struct iommu_dev_data *dev_data)
Joerg Roedel3fa43652009-11-26 15:04:38 +0100952{
953 struct amd_iommu *iommu;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200954 int ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +0100955
Joerg Roedel6c542042011-06-09 17:07:31 +0200956 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel3fa43652009-11-26 15:04:38 +0100957
Joerg Roedelf62dda62011-06-09 12:55:35 +0200958 ret = iommu_flush_dte(iommu, dev_data->devid);
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200959 if (ret)
960 return ret;
961
Joerg Roedelea61cdd2011-06-09 12:56:30 +0200962 if (dev_data->ats.enabled)
Joerg Roedel6c542042011-06-09 17:07:31 +0200963 ret = device_flush_iotlb(dev_data, 0, ~0UL);
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200964
965 return ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +0100966}
967
Joerg Roedel431b2a22008-07-11 17:14:22 +0200968/*
969 * TLB invalidation function which is called from the mapping functions.
970 * It invalidates a single PTE if the range to flush is within a single
971 * page. Otherwise it flushes the whole TLB of the IOMMU.
972 */
Joerg Roedel17b124b2011-04-06 18:01:35 +0200973static void __domain_flush_pages(struct protection_domain *domain,
974 u64 address, size_t size, int pde)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200975{
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200976 struct iommu_dev_data *dev_data;
Joerg Roedel11b64022011-04-06 11:49:28 +0200977 struct iommu_cmd cmd;
978 int ret = 0, i;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200979
Joerg Roedel11b64022011-04-06 11:49:28 +0200980 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
Joerg Roedel999ba412008-07-03 19:35:08 +0200981
Joerg Roedel6de8ad92009-11-23 18:30:32 +0100982 for (i = 0; i < amd_iommus_present; ++i) {
983 if (!domain->dev_iommu[i])
984 continue;
985
986 /*
987 * Devices of this domain are behind this IOMMU
988 * We need a TLB flush
989 */
Joerg Roedel11b64022011-04-06 11:49:28 +0200990 ret |= iommu_queue_command(amd_iommus[i], &cmd);
Joerg Roedel6de8ad92009-11-23 18:30:32 +0100991 }
992
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200993 list_for_each_entry(dev_data, &domain->dev_list, list) {
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200994
Joerg Roedelea61cdd2011-06-09 12:56:30 +0200995 if (!dev_data->ats.enabled)
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200996 continue;
997
Joerg Roedel6c542042011-06-09 17:07:31 +0200998 ret |= device_flush_iotlb(dev_data, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200999 }
1000
Joerg Roedel11b64022011-04-06 11:49:28 +02001001 WARN_ON(ret);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001002}
1003
Joerg Roedel17b124b2011-04-06 18:01:35 +02001004static void domain_flush_pages(struct protection_domain *domain,
1005 u64 address, size_t size)
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001006{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001007 __domain_flush_pages(domain, address, size, 0);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001008}
Joerg Roedelb6c02712008-06-26 21:27:53 +02001009
Joerg Roedel1c655772008-09-04 18:40:05 +02001010/* Flush the whole IO/TLB for a given protection domain */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001011static void domain_flush_tlb(struct protection_domain *domain)
Joerg Roedel1c655772008-09-04 18:40:05 +02001012{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001013 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001014}
1015
Chris Wright42a49f92009-06-15 15:42:00 +02001016/* Flush the whole IO/TLB for a given protection domain - including PDE */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001017static void domain_flush_tlb_pde(struct protection_domain *domain)
Chris Wright42a49f92009-06-15 15:42:00 +02001018{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001019 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1020}
1021
1022static void domain_flush_complete(struct protection_domain *domain)
Joerg Roedelb6c02712008-06-26 21:27:53 +02001023{
1024 int i;
1025
1026 for (i = 0; i < amd_iommus_present; ++i) {
1027 if (!domain->dev_iommu[i])
1028 continue;
1029
1030 /*
1031 * Devices of this domain are behind this IOMMU
1032 * We need to wait for completion of all commands.
1033 */
1034 iommu_completion_wait(amd_iommus[i]);
1035 }
1036}
1037
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001038
Joerg Roedel43f49602008-12-02 21:01:12 +01001039/*
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001040 * This function flushes the DTEs for all devices in domain
Joerg Roedel43f49602008-12-02 21:01:12 +01001041 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001042static void domain_flush_devices(struct protection_domain *domain)
Joerg Roedelbfd1be12009-05-05 15:33:57 +02001043{
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001044 struct iommu_dev_data *dev_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001045
1046 list_for_each_entry(dev_data, &domain->dev_list, list)
Joerg Roedel6c542042011-06-09 17:07:31 +02001047 device_flush_dte(dev_data);
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001048}
1049
Joerg Roedel431b2a22008-07-11 17:14:22 +02001050/****************************************************************************
1051 *
1052 * The functions below are used the create the page table mappings for
1053 * unity mapped regions.
1054 *
1055 ****************************************************************************/
1056
1057/*
Joerg Roedel308973d2009-11-24 17:43:32 +01001058 * This function is used to add another level to an IO page table. Adding
1059 * another level increases the size of the address space by 9 bits to a size up
1060 * to 64 bits.
1061 */
1062static bool increase_address_space(struct protection_domain *domain,
1063 gfp_t gfp)
1064{
1065 u64 *pte;
1066
1067 if (domain->mode == PAGE_MODE_6_LEVEL)
1068 /* address space already 64 bit large */
1069 return false;
1070
1071 pte = (void *)get_zeroed_page(gfp);
1072 if (!pte)
1073 return false;
1074
1075 *pte = PM_LEVEL_PDE(domain->mode,
1076 virt_to_phys(domain->pt_root));
1077 domain->pt_root = pte;
1078 domain->mode += 1;
1079 domain->updated = true;
1080
1081 return true;
1082}
1083
1084static u64 *alloc_pte(struct protection_domain *domain,
1085 unsigned long address,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001086 unsigned long page_size,
Joerg Roedel308973d2009-11-24 17:43:32 +01001087 u64 **pte_page,
1088 gfp_t gfp)
1089{
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001090 int level, end_lvl;
Joerg Roedel308973d2009-11-24 17:43:32 +01001091 u64 *pte, *page;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001092
1093 BUG_ON(!is_power_of_2(page_size));
Joerg Roedel308973d2009-11-24 17:43:32 +01001094
1095 while (address > PM_LEVEL_SIZE(domain->mode))
1096 increase_address_space(domain, gfp);
1097
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001098 level = domain->mode - 1;
1099 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1100 address = PAGE_SIZE_ALIGN(address, page_size);
1101 end_lvl = PAGE_SIZE_LEVEL(page_size);
Joerg Roedel308973d2009-11-24 17:43:32 +01001102
1103 while (level > end_lvl) {
1104 if (!IOMMU_PTE_PRESENT(*pte)) {
1105 page = (u64 *)get_zeroed_page(gfp);
1106 if (!page)
1107 return NULL;
1108 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1109 }
1110
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001111 /* No level skipping support yet */
1112 if (PM_PTE_LEVEL(*pte) != level)
1113 return NULL;
1114
Joerg Roedel308973d2009-11-24 17:43:32 +01001115 level -= 1;
1116
1117 pte = IOMMU_PTE_PAGE(*pte);
1118
1119 if (pte_page && level == end_lvl)
1120 *pte_page = pte;
1121
1122 pte = &pte[PM_LEVEL_INDEX(level, address)];
1123 }
1124
1125 return pte;
1126}
1127
1128/*
1129 * This function checks if there is a PTE for a given dma address. If
1130 * there is one, it returns the pointer to it.
1131 */
Joerg Roedel24cd7722010-01-19 17:27:39 +01001132static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
Joerg Roedel308973d2009-11-24 17:43:32 +01001133{
1134 int level;
1135 u64 *pte;
1136
Joerg Roedel24cd7722010-01-19 17:27:39 +01001137 if (address > PM_LEVEL_SIZE(domain->mode))
1138 return NULL;
Joerg Roedel308973d2009-11-24 17:43:32 +01001139
Joerg Roedel24cd7722010-01-19 17:27:39 +01001140 level = domain->mode - 1;
1141 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1142
1143 while (level > 0) {
1144
1145 /* Not Present */
Joerg Roedel308973d2009-11-24 17:43:32 +01001146 if (!IOMMU_PTE_PRESENT(*pte))
1147 return NULL;
1148
Joerg Roedel24cd7722010-01-19 17:27:39 +01001149 /* Large PTE */
1150 if (PM_PTE_LEVEL(*pte) == 0x07) {
1151 unsigned long pte_mask, __pte;
1152
1153 /*
1154 * If we have a series of large PTEs, make
1155 * sure to return a pointer to the first one.
1156 */
1157 pte_mask = PTE_PAGE_SIZE(*pte);
1158 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1159 __pte = ((unsigned long)pte) & pte_mask;
1160
1161 return (u64 *)__pte;
1162 }
1163
1164 /* No level skipping support yet */
1165 if (PM_PTE_LEVEL(*pte) != level)
1166 return NULL;
1167
Joerg Roedel308973d2009-11-24 17:43:32 +01001168 level -= 1;
1169
Joerg Roedel24cd7722010-01-19 17:27:39 +01001170 /* Walk to the next level */
Joerg Roedel308973d2009-11-24 17:43:32 +01001171 pte = IOMMU_PTE_PAGE(*pte);
1172 pte = &pte[PM_LEVEL_INDEX(level, address)];
Joerg Roedel308973d2009-11-24 17:43:32 +01001173 }
1174
1175 return pte;
1176}
1177
1178/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001179 * Generic mapping functions. It maps a physical address into a DMA
1180 * address space. It allocates the page table pages if necessary.
1181 * In the future it can be extended to a generic mapping function
1182 * supporting all features of AMD IOMMU page tables like level skipping
1183 * and full 64 bit address spaces.
1184 */
Joerg Roedel38e817f2008-12-02 17:27:52 +01001185static int iommu_map_page(struct protection_domain *dom,
1186 unsigned long bus_addr,
1187 unsigned long phys_addr,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001188 int prot,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001189 unsigned long page_size)
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001190{
Joerg Roedel8bda3092009-05-12 12:02:46 +02001191 u64 __pte, *pte;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001192 int i, count;
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001193
Joerg Roedelbad1cac2009-09-02 16:52:23 +02001194 if (!(prot & IOMMU_PROT_MASK))
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001195 return -EINVAL;
1196
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001197 bus_addr = PAGE_ALIGN(bus_addr);
1198 phys_addr = PAGE_ALIGN(phys_addr);
1199 count = PAGE_SIZE_PTE_COUNT(page_size);
1200 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001201
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001202 for (i = 0; i < count; ++i)
1203 if (IOMMU_PTE_PRESENT(pte[i]))
1204 return -EBUSY;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001205
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001206 if (page_size > PAGE_SIZE) {
1207 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1208 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1209 } else
1210 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1211
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001212 if (prot & IOMMU_PROT_IR)
1213 __pte |= IOMMU_PTE_IR;
1214 if (prot & IOMMU_PROT_IW)
1215 __pte |= IOMMU_PTE_IW;
1216
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001217 for (i = 0; i < count; ++i)
1218 pte[i] = __pte;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001219
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001220 update_domain(dom);
1221
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001222 return 0;
1223}
1224
Joerg Roedel24cd7722010-01-19 17:27:39 +01001225static unsigned long iommu_unmap_page(struct protection_domain *dom,
1226 unsigned long bus_addr,
1227 unsigned long page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001228{
Joerg Roedel24cd7722010-01-19 17:27:39 +01001229 unsigned long long unmap_size, unmapped;
1230 u64 *pte;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001231
Joerg Roedel24cd7722010-01-19 17:27:39 +01001232 BUG_ON(!is_power_of_2(page_size));
1233
1234 unmapped = 0;
1235
1236 while (unmapped < page_size) {
1237
1238 pte = fetch_pte(dom, bus_addr);
1239
1240 if (!pte) {
1241 /*
1242 * No PTE for this address
1243 * move forward in 4kb steps
1244 */
1245 unmap_size = PAGE_SIZE;
1246 } else if (PM_PTE_LEVEL(*pte) == 0) {
1247 /* 4kb PTE found for this address */
1248 unmap_size = PAGE_SIZE;
1249 *pte = 0ULL;
1250 } else {
1251 int count, i;
1252
1253 /* Large PTE found which maps this address */
1254 unmap_size = PTE_PAGE_SIZE(*pte);
1255 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1256 for (i = 0; i < count; i++)
1257 pte[i] = 0ULL;
1258 }
1259
1260 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1261 unmapped += unmap_size;
1262 }
1263
1264 BUG_ON(!is_power_of_2(unmapped));
1265
1266 return unmapped;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001267}
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001268
Joerg Roedel431b2a22008-07-11 17:14:22 +02001269/*
1270 * This function checks if a specific unity mapping entry is needed for
1271 * this specific IOMMU.
1272 */
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001273static int iommu_for_unity_map(struct amd_iommu *iommu,
1274 struct unity_map_entry *entry)
1275{
1276 u16 bdf, i;
1277
1278 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1279 bdf = amd_iommu_alias_table[i];
1280 if (amd_iommu_rlookup_table[bdf] == iommu)
1281 return 1;
1282 }
1283
1284 return 0;
1285}
1286
Joerg Roedel431b2a22008-07-11 17:14:22 +02001287/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001288 * This function actually applies the mapping to the page table of the
1289 * dma_ops domain.
1290 */
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001291static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1292 struct unity_map_entry *e)
1293{
1294 u64 addr;
1295 int ret;
1296
1297 for (addr = e->address_start; addr < e->address_end;
1298 addr += PAGE_SIZE) {
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001299 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001300 PAGE_SIZE);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001301 if (ret)
1302 return ret;
1303 /*
1304 * if unity mapping is in aperture range mark the page
1305 * as allocated in the aperture
1306 */
1307 if (addr < dma_dom->aperture_size)
Joerg Roedelc3239562009-05-12 10:56:44 +02001308 __set_bit(addr >> PAGE_SHIFT,
Joerg Roedel384de722009-05-15 12:30:05 +02001309 dma_dom->aperture[0]->bitmap);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001310 }
1311
1312 return 0;
1313}
1314
Joerg Roedel431b2a22008-07-11 17:14:22 +02001315/*
Joerg Roedel171e7b32009-11-24 17:47:56 +01001316 * Init the unity mappings for a specific IOMMU in the system
1317 *
1318 * Basically iterates over all unity mapping entries and applies them to
1319 * the default domain DMA of that IOMMU if necessary.
1320 */
1321static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1322{
1323 struct unity_map_entry *entry;
1324 int ret;
1325
1326 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1327 if (!iommu_for_unity_map(iommu, entry))
1328 continue;
1329 ret = dma_ops_unity_map(iommu->default_dom, entry);
1330 if (ret)
1331 return ret;
1332 }
1333
1334 return 0;
1335}
1336
1337/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001338 * Inits the unity mappings required for a specific device
1339 */
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001340static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1341 u16 devid)
1342{
1343 struct unity_map_entry *e;
1344 int ret;
1345
1346 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1347 if (!(devid >= e->devid_start && devid <= e->devid_end))
1348 continue;
1349 ret = dma_ops_unity_map(dma_dom, e);
1350 if (ret)
1351 return ret;
1352 }
1353
1354 return 0;
1355}
1356
Joerg Roedel431b2a22008-07-11 17:14:22 +02001357/****************************************************************************
1358 *
1359 * The next functions belong to the address allocator for the dma_ops
1360 * interface functions. They work like the allocators in the other IOMMU
1361 * drivers. Its basically a bitmap which marks the allocated pages in
1362 * the aperture. Maybe it could be enhanced in the future to a more
1363 * efficient allocator.
1364 *
1365 ****************************************************************************/
Joerg Roedeld3086442008-06-26 21:27:57 +02001366
Joerg Roedel431b2a22008-07-11 17:14:22 +02001367/*
Joerg Roedel384de722009-05-15 12:30:05 +02001368 * The address allocator core functions.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001369 *
1370 * called with domain->lock held
1371 */
Joerg Roedel384de722009-05-15 12:30:05 +02001372
Joerg Roedel9cabe892009-05-18 16:38:55 +02001373/*
Joerg Roedel171e7b32009-11-24 17:47:56 +01001374 * Used to reserve address ranges in the aperture (e.g. for exclusion
1375 * ranges.
1376 */
1377static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1378 unsigned long start_page,
1379 unsigned int pages)
1380{
1381 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1382
1383 if (start_page + pages > last_page)
1384 pages = last_page - start_page;
1385
1386 for (i = start_page; i < start_page + pages; ++i) {
1387 int index = i / APERTURE_RANGE_PAGES;
1388 int page = i % APERTURE_RANGE_PAGES;
1389 __set_bit(page, dom->aperture[index]->bitmap);
1390 }
1391}
1392
1393/*
Joerg Roedel9cabe892009-05-18 16:38:55 +02001394 * This function is used to add a new aperture range to an existing
1395 * aperture in case of dma_ops domain allocation or address allocation
1396 * failure.
1397 */
Joerg Roedel576175c2009-11-23 19:08:46 +01001398static int alloc_new_range(struct dma_ops_domain *dma_dom,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001399 bool populate, gfp_t gfp)
1400{
1401 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
Joerg Roedel576175c2009-11-23 19:08:46 +01001402 struct amd_iommu *iommu;
Joerg Roedel17f5b562011-07-06 17:14:44 +02001403 unsigned long i, old_size;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001404
Joerg Roedelf5e97052009-05-22 12:31:53 +02001405#ifdef CONFIG_IOMMU_STRESS
1406 populate = false;
1407#endif
1408
Joerg Roedel9cabe892009-05-18 16:38:55 +02001409 if (index >= APERTURE_MAX_RANGES)
1410 return -ENOMEM;
1411
1412 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1413 if (!dma_dom->aperture[index])
1414 return -ENOMEM;
1415
1416 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1417 if (!dma_dom->aperture[index]->bitmap)
1418 goto out_free;
1419
1420 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1421
1422 if (populate) {
1423 unsigned long address = dma_dom->aperture_size;
1424 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1425 u64 *pte, *pte_page;
1426
1427 for (i = 0; i < num_ptes; ++i) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001428 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001429 &pte_page, gfp);
1430 if (!pte)
1431 goto out_free;
1432
1433 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1434
1435 address += APERTURE_RANGE_SIZE / 64;
1436 }
1437 }
1438
Joerg Roedel17f5b562011-07-06 17:14:44 +02001439 old_size = dma_dom->aperture_size;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001440 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1441
Joerg Roedel17f5b562011-07-06 17:14:44 +02001442 /* Reserve address range used for MSI messages */
1443 if (old_size < MSI_ADDR_BASE_LO &&
1444 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1445 unsigned long spage;
1446 int pages;
1447
1448 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1449 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1450
1451 dma_ops_reserve_addresses(dma_dom, spage, pages);
1452 }
1453
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001454 /* Initialize the exclusion range if necessary */
Joerg Roedel576175c2009-11-23 19:08:46 +01001455 for_each_iommu(iommu) {
1456 if (iommu->exclusion_start &&
1457 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1458 && iommu->exclusion_start < dma_dom->aperture_size) {
1459 unsigned long startpage;
1460 int pages = iommu_num_pages(iommu->exclusion_start,
1461 iommu->exclusion_length,
1462 PAGE_SIZE);
1463 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1464 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1465 }
Joerg Roedel00cd1222009-05-19 09:52:40 +02001466 }
1467
1468 /*
1469 * Check for areas already mapped as present in the new aperture
1470 * range and mark those pages as reserved in the allocator. Such
1471 * mappings may already exist as a result of requested unity
1472 * mappings for devices.
1473 */
1474 for (i = dma_dom->aperture[index]->offset;
1475 i < dma_dom->aperture_size;
1476 i += PAGE_SIZE) {
Joerg Roedel24cd7722010-01-19 17:27:39 +01001477 u64 *pte = fetch_pte(&dma_dom->domain, i);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001478 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1479 continue;
1480
Joerg Roedelfcd08612011-10-11 17:41:32 +02001481 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001482 }
1483
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001484 update_domain(&dma_dom->domain);
1485
Joerg Roedel9cabe892009-05-18 16:38:55 +02001486 return 0;
1487
1488out_free:
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001489 update_domain(&dma_dom->domain);
1490
Joerg Roedel9cabe892009-05-18 16:38:55 +02001491 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1492
1493 kfree(dma_dom->aperture[index]);
1494 dma_dom->aperture[index] = NULL;
1495
1496 return -ENOMEM;
1497}
1498
Joerg Roedel384de722009-05-15 12:30:05 +02001499static unsigned long dma_ops_area_alloc(struct device *dev,
1500 struct dma_ops_domain *dom,
1501 unsigned int pages,
1502 unsigned long align_mask,
1503 u64 dma_mask,
1504 unsigned long start)
1505{
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001506 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
Joerg Roedel384de722009-05-15 12:30:05 +02001507 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1508 int i = start >> APERTURE_RANGE_SHIFT;
1509 unsigned long boundary_size;
1510 unsigned long address = -1;
1511 unsigned long limit;
1512
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001513 next_bit >>= PAGE_SHIFT;
1514
Joerg Roedel384de722009-05-15 12:30:05 +02001515 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1516 PAGE_SIZE) >> PAGE_SHIFT;
1517
1518 for (;i < max_index; ++i) {
1519 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1520
1521 if (dom->aperture[i]->offset >= dma_mask)
1522 break;
1523
1524 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1525 dma_mask >> PAGE_SHIFT);
1526
1527 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1528 limit, next_bit, pages, 0,
1529 boundary_size, align_mask);
1530 if (address != -1) {
1531 address = dom->aperture[i]->offset +
1532 (address << PAGE_SHIFT);
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001533 dom->next_address = address + (pages << PAGE_SHIFT);
Joerg Roedel384de722009-05-15 12:30:05 +02001534 break;
1535 }
1536
1537 next_bit = 0;
1538 }
1539
1540 return address;
1541}
1542
Joerg Roedeld3086442008-06-26 21:27:57 +02001543static unsigned long dma_ops_alloc_addresses(struct device *dev,
1544 struct dma_ops_domain *dom,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02001545 unsigned int pages,
Joerg Roedel832a90c2008-09-18 15:54:23 +02001546 unsigned long align_mask,
1547 u64 dma_mask)
Joerg Roedeld3086442008-06-26 21:27:57 +02001548{
Joerg Roedeld3086442008-06-26 21:27:57 +02001549 unsigned long address;
Joerg Roedeld3086442008-06-26 21:27:57 +02001550
Joerg Roedelfe16f082009-05-22 12:27:53 +02001551#ifdef CONFIG_IOMMU_STRESS
1552 dom->next_address = 0;
1553 dom->need_flush = true;
1554#endif
Joerg Roedeld3086442008-06-26 21:27:57 +02001555
Joerg Roedel384de722009-05-15 12:30:05 +02001556 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001557 dma_mask, dom->next_address);
Joerg Roedeld3086442008-06-26 21:27:57 +02001558
Joerg Roedel1c655772008-09-04 18:40:05 +02001559 if (address == -1) {
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001560 dom->next_address = 0;
Joerg Roedel384de722009-05-15 12:30:05 +02001561 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1562 dma_mask, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001563 dom->need_flush = true;
1564 }
Joerg Roedeld3086442008-06-26 21:27:57 +02001565
Joerg Roedel384de722009-05-15 12:30:05 +02001566 if (unlikely(address == -1))
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09001567 address = DMA_ERROR_CODE;
Joerg Roedeld3086442008-06-26 21:27:57 +02001568
1569 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1570
1571 return address;
1572}
1573
Joerg Roedel431b2a22008-07-11 17:14:22 +02001574/*
1575 * The address free function.
1576 *
1577 * called with domain->lock held
1578 */
Joerg Roedeld3086442008-06-26 21:27:57 +02001579static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1580 unsigned long address,
1581 unsigned int pages)
1582{
Joerg Roedel384de722009-05-15 12:30:05 +02001583 unsigned i = address >> APERTURE_RANGE_SHIFT;
1584 struct aperture_range *range = dom->aperture[i];
Joerg Roedel80be3082008-11-06 14:59:05 +01001585
Joerg Roedel384de722009-05-15 12:30:05 +02001586 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1587
Joerg Roedel47bccd62009-05-22 12:40:54 +02001588#ifdef CONFIG_IOMMU_STRESS
1589 if (i < 4)
1590 return;
1591#endif
1592
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001593 if (address >= dom->next_address)
Joerg Roedel80be3082008-11-06 14:59:05 +01001594 dom->need_flush = true;
Joerg Roedel384de722009-05-15 12:30:05 +02001595
1596 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001597
Akinobu Mitaa66022c2009-12-15 16:48:28 -08001598 bitmap_clear(range->bitmap, address, pages);
Joerg Roedel384de722009-05-15 12:30:05 +02001599
Joerg Roedeld3086442008-06-26 21:27:57 +02001600}
1601
Joerg Roedel431b2a22008-07-11 17:14:22 +02001602/****************************************************************************
1603 *
1604 * The next functions belong to the domain allocation. A domain is
1605 * allocated for every IOMMU as the default domain. If device isolation
1606 * is enabled, every device get its own domain. The most important thing
1607 * about domains is the page table mapping the DMA address space they
1608 * contain.
1609 *
1610 ****************************************************************************/
1611
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001612/*
1613 * This function adds a protection domain to the global protection domain list
1614 */
1615static void add_domain_to_list(struct protection_domain *domain)
1616{
1617 unsigned long flags;
1618
1619 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1620 list_add(&domain->list, &amd_iommu_pd_list);
1621 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1622}
1623
1624/*
1625 * This function removes a protection domain to the global
1626 * protection domain list
1627 */
1628static void del_domain_from_list(struct protection_domain *domain)
1629{
1630 unsigned long flags;
1631
1632 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1633 list_del(&domain->list);
1634 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1635}
1636
Joerg Roedelec487d12008-06-26 21:27:58 +02001637static u16 domain_id_alloc(void)
1638{
1639 unsigned long flags;
1640 int id;
1641
1642 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1643 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1644 BUG_ON(id == 0);
1645 if (id > 0 && id < MAX_DOMAIN_ID)
1646 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1647 else
1648 id = 0;
1649 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1650
1651 return id;
1652}
1653
Joerg Roedela2acfb72008-12-02 18:28:53 +01001654static void domain_id_free(int id)
1655{
1656 unsigned long flags;
1657
1658 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1659 if (id > 0 && id < MAX_DOMAIN_ID)
1660 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1661 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1662}
Joerg Roedela2acfb72008-12-02 18:28:53 +01001663
Joerg Roedel86db2e52008-12-02 18:20:21 +01001664static void free_pagetable(struct protection_domain *domain)
Joerg Roedelec487d12008-06-26 21:27:58 +02001665{
1666 int i, j;
1667 u64 *p1, *p2, *p3;
1668
Joerg Roedel86db2e52008-12-02 18:20:21 +01001669 p1 = domain->pt_root;
Joerg Roedelec487d12008-06-26 21:27:58 +02001670
1671 if (!p1)
1672 return;
1673
1674 for (i = 0; i < 512; ++i) {
1675 if (!IOMMU_PTE_PRESENT(p1[i]))
1676 continue;
1677
1678 p2 = IOMMU_PTE_PAGE(p1[i]);
Joerg Roedel3cc3d842008-12-04 16:44:31 +01001679 for (j = 0; j < 512; ++j) {
Joerg Roedelec487d12008-06-26 21:27:58 +02001680 if (!IOMMU_PTE_PRESENT(p2[j]))
1681 continue;
1682 p3 = IOMMU_PTE_PAGE(p2[j]);
1683 free_page((unsigned long)p3);
1684 }
1685
1686 free_page((unsigned long)p2);
1687 }
1688
1689 free_page((unsigned long)p1);
Joerg Roedel86db2e52008-12-02 18:20:21 +01001690
1691 domain->pt_root = NULL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001692}
1693
Joerg Roedelb16137b2011-11-21 16:50:23 +01001694static void free_gcr3_tbl_level1(u64 *tbl)
1695{
1696 u64 *ptr;
1697 int i;
1698
1699 for (i = 0; i < 512; ++i) {
1700 if (!(tbl[i] & GCR3_VALID))
1701 continue;
1702
1703 ptr = __va(tbl[i] & PAGE_MASK);
1704
1705 free_page((unsigned long)ptr);
1706 }
1707}
1708
1709static void free_gcr3_tbl_level2(u64 *tbl)
1710{
1711 u64 *ptr;
1712 int i;
1713
1714 for (i = 0; i < 512; ++i) {
1715 if (!(tbl[i] & GCR3_VALID))
1716 continue;
1717
1718 ptr = __va(tbl[i] & PAGE_MASK);
1719
1720 free_gcr3_tbl_level1(ptr);
1721 }
1722}
1723
Joerg Roedel52815b72011-11-17 17:24:28 +01001724static void free_gcr3_table(struct protection_domain *domain)
1725{
Joerg Roedelb16137b2011-11-21 16:50:23 +01001726 if (domain->glx == 2)
1727 free_gcr3_tbl_level2(domain->gcr3_tbl);
1728 else if (domain->glx == 1)
1729 free_gcr3_tbl_level1(domain->gcr3_tbl);
1730 else if (domain->glx != 0)
1731 BUG();
1732
Joerg Roedel52815b72011-11-17 17:24:28 +01001733 free_page((unsigned long)domain->gcr3_tbl);
1734}
1735
Joerg Roedel431b2a22008-07-11 17:14:22 +02001736/*
1737 * Free a domain, only used if something went wrong in the
1738 * allocation path and we need to free an already allocated page table
1739 */
Joerg Roedelec487d12008-06-26 21:27:58 +02001740static void dma_ops_domain_free(struct dma_ops_domain *dom)
1741{
Joerg Roedel384de722009-05-15 12:30:05 +02001742 int i;
1743
Joerg Roedelec487d12008-06-26 21:27:58 +02001744 if (!dom)
1745 return;
1746
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001747 del_domain_from_list(&dom->domain);
1748
Joerg Roedel86db2e52008-12-02 18:20:21 +01001749 free_pagetable(&dom->domain);
Joerg Roedelec487d12008-06-26 21:27:58 +02001750
Joerg Roedel384de722009-05-15 12:30:05 +02001751 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1752 if (!dom->aperture[i])
1753 continue;
1754 free_page((unsigned long)dom->aperture[i]->bitmap);
1755 kfree(dom->aperture[i]);
1756 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001757
1758 kfree(dom);
1759}
1760
Joerg Roedel431b2a22008-07-11 17:14:22 +02001761/*
1762 * Allocates a new protection domain usable for the dma_ops functions.
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001763 * It also initializes the page table and the address allocator data
Joerg Roedel431b2a22008-07-11 17:14:22 +02001764 * structures required for the dma_ops interface
1765 */
Joerg Roedel87a64d52009-11-24 17:26:43 +01001766static struct dma_ops_domain *dma_ops_domain_alloc(void)
Joerg Roedelec487d12008-06-26 21:27:58 +02001767{
1768 struct dma_ops_domain *dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001769
1770 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1771 if (!dma_dom)
1772 return NULL;
1773
1774 spin_lock_init(&dma_dom->domain.lock);
1775
1776 dma_dom->domain.id = domain_id_alloc();
1777 if (dma_dom->domain.id == 0)
1778 goto free_dma_dom;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01001779 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
Joerg Roedel8f7a0172009-09-02 16:55:24 +02001780 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001781 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
Joerg Roedel9fdb19d2008-12-02 17:46:25 +01001782 dma_dom->domain.flags = PD_DMA_OPS_MASK;
Joerg Roedelec487d12008-06-26 21:27:58 +02001783 dma_dom->domain.priv = dma_dom;
1784 if (!dma_dom->domain.pt_root)
1785 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001786
Joerg Roedel1c655772008-09-04 18:40:05 +02001787 dma_dom->need_flush = false;
Joerg Roedelbd60b732008-09-11 10:24:48 +02001788 dma_dom->target_dev = 0xffff;
Joerg Roedel1c655772008-09-04 18:40:05 +02001789
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001790 add_domain_to_list(&dma_dom->domain);
1791
Joerg Roedel576175c2009-11-23 19:08:46 +01001792 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
Joerg Roedelec487d12008-06-26 21:27:58 +02001793 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001794
Joerg Roedel431b2a22008-07-11 17:14:22 +02001795 /*
Joerg Roedelec487d12008-06-26 21:27:58 +02001796 * mark the first page as allocated so we never return 0 as
1797 * a valid dma-address. So we can use 0 as error value
Joerg Roedel431b2a22008-07-11 17:14:22 +02001798 */
Joerg Roedel384de722009-05-15 12:30:05 +02001799 dma_dom->aperture[0]->bitmap[0] = 1;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001800 dma_dom->next_address = 0;
Joerg Roedelec487d12008-06-26 21:27:58 +02001801
Joerg Roedelec487d12008-06-26 21:27:58 +02001802
1803 return dma_dom;
1804
1805free_dma_dom:
1806 dma_ops_domain_free(dma_dom);
1807
1808 return NULL;
1809}
1810
Joerg Roedel431b2a22008-07-11 17:14:22 +02001811/*
Joerg Roedel5b28df62008-12-02 17:49:42 +01001812 * little helper function to check whether a given protection domain is a
1813 * dma_ops domain
1814 */
1815static bool dma_ops_domain(struct protection_domain *domain)
1816{
1817 return domain->flags & PD_DMA_OPS_MASK;
1818}
1819
Joerg Roedelfd7b5532011-04-05 15:31:08 +02001820static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001821{
Joerg Roedel132bd682011-11-17 14:18:46 +01001822 u64 pte_root = 0;
Joerg Roedelee6c2862011-11-09 12:06:03 +01001823 u64 flags = 0;
Joerg Roedel863c74e2008-12-02 17:56:36 +01001824
Joerg Roedel132bd682011-11-17 14:18:46 +01001825 if (domain->mode != PAGE_MODE_NONE)
1826 pte_root = virt_to_phys(domain->pt_root);
1827
Joerg Roedel38ddf412008-09-11 10:38:32 +02001828 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1829 << DEV_ENTRY_MODE_SHIFT;
1830 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001831
Joerg Roedelee6c2862011-11-09 12:06:03 +01001832 flags = amd_iommu_dev_table[devid].data[1];
1833
Joerg Roedelfd7b5532011-04-05 15:31:08 +02001834 if (ats)
1835 flags |= DTE_FLAG_IOTLB;
1836
Joerg Roedel52815b72011-11-17 17:24:28 +01001837 if (domain->flags & PD_IOMMUV2_MASK) {
1838 u64 gcr3 = __pa(domain->gcr3_tbl);
1839 u64 glx = domain->glx;
1840 u64 tmp;
1841
1842 pte_root |= DTE_FLAG_GV;
1843 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1844
1845 /* First mask out possible old values for GCR3 table */
1846 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1847 flags &= ~tmp;
1848
1849 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1850 flags &= ~tmp;
1851
1852 /* Encode GCR3 table into DTE */
1853 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1854 pte_root |= tmp;
1855
1856 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1857 flags |= tmp;
1858
1859 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1860 flags |= tmp;
1861 }
1862
Joerg Roedelee6c2862011-11-09 12:06:03 +01001863 flags &= ~(0xffffUL);
1864 flags |= domain->id;
1865
1866 amd_iommu_dev_table[devid].data[1] = flags;
1867 amd_iommu_dev_table[devid].data[0] = pte_root;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001868}
1869
Joerg Roedel15898bb2009-11-24 15:39:42 +01001870static void clear_dte_entry(u16 devid)
Joerg Roedel355bf552008-12-08 12:02:41 +01001871{
Joerg Roedel355bf552008-12-08 12:02:41 +01001872 /* remove entry from the device table seen by the hardware */
1873 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1874 amd_iommu_dev_table[devid].data[1] = 0;
Joerg Roedel355bf552008-12-08 12:02:41 +01001875
Joerg Roedelc5cca142009-10-09 18:31:20 +02001876 amd_iommu_apply_erratum_63(devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001877}
1878
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001879static void do_attach(struct iommu_dev_data *dev_data,
1880 struct protection_domain *domain)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001881{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001882 struct amd_iommu *iommu;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001883 bool ats;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001884
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001885 iommu = amd_iommu_rlookup_table[dev_data->devid];
1886 ats = dev_data->ats.enabled;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001887
1888 /* Update data structures */
1889 dev_data->domain = domain;
1890 list_add(&dev_data->list, &domain->dev_list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02001891 set_dte_entry(dev_data->devid, domain, ats);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001892
1893 /* Do reference counting */
1894 domain->dev_iommu[iommu->index] += 1;
1895 domain->dev_cnt += 1;
1896
1897 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02001898 device_flush_dte(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001899}
1900
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001901static void do_detach(struct iommu_dev_data *dev_data)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001902{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001903 struct amd_iommu *iommu;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001904
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001905 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelc5cca142009-10-09 18:31:20 +02001906
Joerg Roedelc4596112009-11-20 14:57:32 +01001907 /* decrease reference counters */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001908 dev_data->domain->dev_iommu[iommu->index] -= 1;
1909 dev_data->domain->dev_cnt -= 1;
Joerg Roedel355bf552008-12-08 12:02:41 +01001910
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001911 /* Update data structures */
1912 dev_data->domain = NULL;
1913 list_del(&dev_data->list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02001914 clear_dte_entry(dev_data->devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001915
1916 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02001917 device_flush_dte(dev_data);
Joerg Roedel15898bb2009-11-24 15:39:42 +01001918}
1919
1920/*
1921 * If a device is not yet associated with a domain, this function does
1922 * assigns it visible for the hardware
1923 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001924static int __attach_device(struct iommu_dev_data *dev_data,
Joerg Roedel15898bb2009-11-24 15:39:42 +01001925 struct protection_domain *domain)
1926{
Julia Lawall84fe6c12010-05-27 12:31:51 +02001927 int ret;
Joerg Roedel657cbb62009-11-23 15:26:46 +01001928
Joerg Roedel15898bb2009-11-24 15:39:42 +01001929 /* lock domain */
1930 spin_lock(&domain->lock);
1931
Joerg Roedel71f77582011-06-09 19:03:15 +02001932 if (dev_data->alias_data != NULL) {
1933 struct iommu_dev_data *alias_data = dev_data->alias_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01001934
Joerg Roedel2b02b092011-06-09 17:48:39 +02001935 /* Some sanity checks */
1936 ret = -EBUSY;
1937 if (alias_data->domain != NULL &&
1938 alias_data->domain != domain)
1939 goto out_unlock;
Joerg Roedel15898bb2009-11-24 15:39:42 +01001940
Joerg Roedel2b02b092011-06-09 17:48:39 +02001941 if (dev_data->domain != NULL &&
1942 dev_data->domain != domain)
1943 goto out_unlock;
1944
1945 /* Do real assignment */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001946 if (alias_data->domain == NULL)
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001947 do_attach(alias_data, domain);
Joerg Roedel24100052009-11-25 15:59:57 +01001948
1949 atomic_inc(&alias_data->bind);
Joerg Roedel657cbb62009-11-23 15:26:46 +01001950 }
Joerg Roedel15898bb2009-11-24 15:39:42 +01001951
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001952 if (dev_data->domain == NULL)
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001953 do_attach(dev_data, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01001954
Joerg Roedel24100052009-11-25 15:59:57 +01001955 atomic_inc(&dev_data->bind);
1956
Julia Lawall84fe6c12010-05-27 12:31:51 +02001957 ret = 0;
1958
1959out_unlock:
1960
Joerg Roedel355bf552008-12-08 12:02:41 +01001961 /* ready */
1962 spin_unlock(&domain->lock);
Joerg Roedel21129f72009-09-01 11:59:42 +02001963
Julia Lawall84fe6c12010-05-27 12:31:51 +02001964 return ret;
Joerg Roedel15898bb2009-11-24 15:39:42 +01001965}
1966
Joerg Roedel52815b72011-11-17 17:24:28 +01001967
1968static void pdev_iommuv2_disable(struct pci_dev *pdev)
1969{
1970 pci_disable_ats(pdev);
1971 pci_disable_pri(pdev);
1972 pci_disable_pasid(pdev);
1973}
1974
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001975/* FIXME: Change generic reset-function to do the same */
1976static int pri_reset_while_enabled(struct pci_dev *pdev)
1977{
1978 u16 control;
1979 int pos;
1980
Joerg Roedel46277b72011-12-07 14:34:02 +01001981 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001982 if (!pos)
1983 return -EINVAL;
1984
Joerg Roedel46277b72011-12-07 14:34:02 +01001985 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1986 control |= PCI_PRI_CTRL_RESET;
1987 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001988
1989 return 0;
1990}
1991
Joerg Roedel52815b72011-11-17 17:24:28 +01001992static int pdev_iommuv2_enable(struct pci_dev *pdev)
1993{
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001994 bool reset_enable;
1995 int reqs, ret;
1996
1997 /* FIXME: Hardcode number of outstanding requests for now */
1998 reqs = 32;
1999 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2000 reqs = 1;
2001 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
Joerg Roedel52815b72011-11-17 17:24:28 +01002002
2003 /* Only allow access to user-accessible pages */
2004 ret = pci_enable_pasid(pdev, 0);
2005 if (ret)
2006 goto out_err;
2007
2008 /* First reset the PRI state of the device */
2009 ret = pci_reset_pri(pdev);
2010 if (ret)
2011 goto out_err;
2012
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002013 /* Enable PRI */
2014 ret = pci_enable_pri(pdev, reqs);
Joerg Roedel52815b72011-11-17 17:24:28 +01002015 if (ret)
2016 goto out_err;
2017
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002018 if (reset_enable) {
2019 ret = pri_reset_while_enabled(pdev);
2020 if (ret)
2021 goto out_err;
2022 }
2023
Joerg Roedel52815b72011-11-17 17:24:28 +01002024 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2025 if (ret)
2026 goto out_err;
2027
2028 return 0;
2029
2030out_err:
2031 pci_disable_pri(pdev);
2032 pci_disable_pasid(pdev);
2033
2034 return ret;
2035}
2036
Joerg Roedelc99afa22011-11-21 18:19:25 +01002037/* FIXME: Move this to PCI code */
2038#define PCI_PRI_TLP_OFF (1 << 2)
2039
2040bool pci_pri_tlp_required(struct pci_dev *pdev)
2041{
2042 u16 control;
2043 int pos;
2044
Joerg Roedel46277b72011-12-07 14:34:02 +01002045 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002046 if (!pos)
2047 return false;
2048
Joerg Roedel46277b72011-12-07 14:34:02 +01002049 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002050
2051 return (control & PCI_PRI_TLP_OFF) ? true : false;
2052}
2053
Joerg Roedel15898bb2009-11-24 15:39:42 +01002054/*
2055 * If a device is not yet associated with a domain, this function does
2056 * assigns it visible for the hardware
2057 */
2058static int attach_device(struct device *dev,
2059 struct protection_domain *domain)
2060{
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002061 struct pci_dev *pdev = to_pci_dev(dev);
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002062 struct iommu_dev_data *dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002063 unsigned long flags;
2064 int ret;
2065
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002066 dev_data = get_dev_data(dev);
2067
Joerg Roedel52815b72011-11-17 17:24:28 +01002068 if (domain->flags & PD_IOMMUV2_MASK) {
2069 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2070 return -EINVAL;
2071
2072 if (pdev_iommuv2_enable(pdev) != 0)
2073 return -EINVAL;
2074
2075 dev_data->ats.enabled = true;
2076 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002077 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002078 } else if (amd_iommu_iotlb_sup &&
2079 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002080 dev_data->ats.enabled = true;
2081 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2082 }
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002083
Joerg Roedel15898bb2009-11-24 15:39:42 +01002084 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002085 ret = __attach_device(dev_data, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002086 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2087
2088 /*
2089 * We might boot into a crash-kernel here. The crashed kernel
2090 * left the caches in the IOMMU dirty. So we have to flush
2091 * here to evict all dirty stuff.
2092 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02002093 domain_flush_tlb_pde(domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002094
2095 return ret;
2096}
2097
2098/*
2099 * Removes a device from a protection domain (unlocked)
2100 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002101static void __detach_device(struct iommu_dev_data *dev_data)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002102{
Joerg Roedel2ca76272010-01-22 16:45:31 +01002103 struct protection_domain *domain;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01002104 unsigned long flags;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002105
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002106 BUG_ON(!dev_data->domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002107
Joerg Roedel2ca76272010-01-22 16:45:31 +01002108 domain = dev_data->domain;
2109
2110 spin_lock_irqsave(&domain->lock, flags);
Joerg Roedel24100052009-11-25 15:59:57 +01002111
Joerg Roedel71f77582011-06-09 19:03:15 +02002112 if (dev_data->alias_data != NULL) {
2113 struct iommu_dev_data *alias_data = dev_data->alias_data;
2114
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002115 if (atomic_dec_and_test(&alias_data->bind))
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002116 do_detach(alias_data);
Joerg Roedel24100052009-11-25 15:59:57 +01002117 }
2118
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002119 if (atomic_dec_and_test(&dev_data->bind))
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002120 do_detach(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002121
Joerg Roedel2ca76272010-01-22 16:45:31 +01002122 spin_unlock_irqrestore(&domain->lock, flags);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002123
Joerg Roedel21129f72009-09-01 11:59:42 +02002124 /*
2125 * If we run in passthrough mode the device must be assigned to the
Joerg Roedeld3ad9372010-01-22 17:55:27 +01002126 * passthrough domain if it is detached from any other domain.
2127 * Make sure we can deassign from the pt_domain itself.
Joerg Roedel21129f72009-09-01 11:59:42 +02002128 */
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002129 if (dev_data->passthrough &&
Joerg Roedeld3ad9372010-01-22 17:55:27 +01002130 (dev_data->domain == NULL && domain != pt_domain))
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002131 __attach_device(dev_data, pt_domain);
Joerg Roedel355bf552008-12-08 12:02:41 +01002132}
2133
2134/*
2135 * Removes a device from a protection domain (with devtable_lock held)
2136 */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002137static void detach_device(struct device *dev)
Joerg Roedel355bf552008-12-08 12:02:41 +01002138{
Joerg Roedel52815b72011-11-17 17:24:28 +01002139 struct protection_domain *domain;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002140 struct iommu_dev_data *dev_data;
Joerg Roedel355bf552008-12-08 12:02:41 +01002141 unsigned long flags;
2142
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002143 dev_data = get_dev_data(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002144 domain = dev_data->domain;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002145
Joerg Roedel355bf552008-12-08 12:02:41 +01002146 /* lock device table */
2147 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002148 __detach_device(dev_data);
Joerg Roedel355bf552008-12-08 12:02:41 +01002149 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002150
Joerg Roedel52815b72011-11-17 17:24:28 +01002151 if (domain->flags & PD_IOMMUV2_MASK)
2152 pdev_iommuv2_disable(to_pci_dev(dev));
2153 else if (dev_data->ats.enabled)
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002154 pci_disable_ats(to_pci_dev(dev));
Joerg Roedel52815b72011-11-17 17:24:28 +01002155
2156 dev_data->ats.enabled = false;
Joerg Roedel355bf552008-12-08 12:02:41 +01002157}
Joerg Roedele275a2a2008-12-10 18:27:25 +01002158
Joerg Roedel15898bb2009-11-24 15:39:42 +01002159/*
2160 * Find out the protection domain structure for a given PCI device. This
2161 * will give us the pointer to the page table root for example.
2162 */
2163static struct protection_domain *domain_for_device(struct device *dev)
2164{
Joerg Roedel71f77582011-06-09 19:03:15 +02002165 struct iommu_dev_data *dev_data;
Joerg Roedel2b02b092011-06-09 17:48:39 +02002166 struct protection_domain *dom = NULL;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002167 unsigned long flags;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002168
Joerg Roedel657cbb62009-11-23 15:26:46 +01002169 dev_data = get_dev_data(dev);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002170
Joerg Roedel2b02b092011-06-09 17:48:39 +02002171 if (dev_data->domain)
2172 return dev_data->domain;
2173
Joerg Roedel71f77582011-06-09 19:03:15 +02002174 if (dev_data->alias_data != NULL) {
2175 struct iommu_dev_data *alias_data = dev_data->alias_data;
Joerg Roedel2b02b092011-06-09 17:48:39 +02002176
2177 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2178 if (alias_data->domain != NULL) {
2179 __attach_device(dev_data, alias_data->domain);
2180 dom = alias_data->domain;
2181 }
2182 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002183 }
2184
Joerg Roedel15898bb2009-11-24 15:39:42 +01002185 return dom;
2186}
2187
Joerg Roedele275a2a2008-12-10 18:27:25 +01002188static int device_change_notifier(struct notifier_block *nb,
2189 unsigned long action, void *data)
2190{
Joerg Roedele275a2a2008-12-10 18:27:25 +01002191 struct dma_ops_domain *dma_domain;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002192 struct protection_domain *domain;
2193 struct iommu_dev_data *dev_data;
2194 struct device *dev = data;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002195 struct amd_iommu *iommu;
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002196 unsigned long flags;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002197 u16 devid;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002198
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002199 if (!check_device(dev))
2200 return 0;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002201
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002202 devid = get_device_id(dev);
2203 iommu = amd_iommu_rlookup_table[devid];
2204 dev_data = get_dev_data(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002205
2206 switch (action) {
Chris Wrightc1eee672009-05-21 00:56:58 -07002207 case BUS_NOTIFY_UNBOUND_DRIVER:
Joerg Roedel657cbb62009-11-23 15:26:46 +01002208
2209 domain = domain_for_device(dev);
2210
Joerg Roedele275a2a2008-12-10 18:27:25 +01002211 if (!domain)
2212 goto out;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002213 if (dev_data->passthrough)
Joerg Roedela1ca3312009-09-01 12:22:22 +02002214 break;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002215 detach_device(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002216 break;
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002217 case BUS_NOTIFY_ADD_DEVICE:
Joerg Roedel657cbb62009-11-23 15:26:46 +01002218
2219 iommu_init_device(dev);
2220
2221 domain = domain_for_device(dev);
2222
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002223 /* allocate a protection domain if a device is added */
2224 dma_domain = find_protection_domain(devid);
2225 if (dma_domain)
2226 goto out;
Joerg Roedel87a64d52009-11-24 17:26:43 +01002227 dma_domain = dma_ops_domain_alloc();
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002228 if (!dma_domain)
2229 goto out;
2230 dma_domain->target_dev = devid;
2231
2232 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2233 list_add_tail(&dma_domain->list, &iommu_pd_list);
2234 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2235
2236 break;
Joerg Roedel657cbb62009-11-23 15:26:46 +01002237 case BUS_NOTIFY_DEL_DEVICE:
2238
2239 iommu_uninit_device(dev);
2240
Joerg Roedele275a2a2008-12-10 18:27:25 +01002241 default:
2242 goto out;
2243 }
2244
Joerg Roedele275a2a2008-12-10 18:27:25 +01002245 iommu_completion_wait(iommu);
2246
2247out:
2248 return 0;
2249}
2250
Jaswinder Singh Rajputb25ae672009-07-01 19:53:14 +05302251static struct notifier_block device_nb = {
Joerg Roedele275a2a2008-12-10 18:27:25 +01002252 .notifier_call = device_change_notifier,
2253};
Joerg Roedel355bf552008-12-08 12:02:41 +01002254
Joerg Roedel8638c492009-12-10 11:12:25 +01002255void amd_iommu_init_notifier(void)
2256{
2257 bus_register_notifier(&pci_bus_type, &device_nb);
2258}
2259
Joerg Roedel431b2a22008-07-11 17:14:22 +02002260/*****************************************************************************
2261 *
2262 * The next functions belong to the dma_ops mapping/unmapping code.
2263 *
2264 *****************************************************************************/
2265
2266/*
2267 * In the dma_ops path we only have the struct device. This function
2268 * finds the corresponding IOMMU, the protection domain and the
2269 * requestor id for a given device.
2270 * If the device is not yet associated with a domain this is also done
2271 * in this function.
2272 */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002273static struct protection_domain *get_domain(struct device *dev)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002274{
Joerg Roedel94f6d192009-11-24 16:40:02 +01002275 struct protection_domain *domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002276 struct dma_ops_domain *dma_dom;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002277 u16 devid = get_device_id(dev);
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002278
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002279 if (!check_device(dev))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002280 return ERR_PTR(-EINVAL);
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002281
Joerg Roedel94f6d192009-11-24 16:40:02 +01002282 domain = domain_for_device(dev);
2283 if (domain != NULL && !dma_ops_domain(domain))
2284 return ERR_PTR(-EBUSY);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002285
Joerg Roedel94f6d192009-11-24 16:40:02 +01002286 if (domain != NULL)
2287 return domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002288
Joerg Roedel15898bb2009-11-24 15:39:42 +01002289 /* Device not bount yet - bind it */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002290 dma_dom = find_protection_domain(devid);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002291 if (!dma_dom)
Joerg Roedel94f6d192009-11-24 16:40:02 +01002292 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2293 attach_device(dev, &dma_dom->domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002294 DUMP_printk("Using protection domain %d for device %s\n",
Joerg Roedel94f6d192009-11-24 16:40:02 +01002295 dma_dom->domain.id, dev_name(dev));
Joerg Roedelf91ba192008-11-25 12:56:12 +01002296
Joerg Roedel94f6d192009-11-24 16:40:02 +01002297 return &dma_dom->domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002298}
2299
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002300static void update_device_table(struct protection_domain *domain)
2301{
Joerg Roedel492667d2009-11-27 13:25:47 +01002302 struct iommu_dev_data *dev_data;
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002303
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002304 list_for_each_entry(dev_data, &domain->dev_list, list)
2305 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002306}
2307
2308static void update_domain(struct protection_domain *domain)
2309{
2310 if (!domain->updated)
2311 return;
2312
2313 update_device_table(domain);
Joerg Roedel17b124b2011-04-06 18:01:35 +02002314
2315 domain_flush_devices(domain);
2316 domain_flush_tlb_pde(domain);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002317
2318 domain->updated = false;
2319}
2320
Joerg Roedel431b2a22008-07-11 17:14:22 +02002321/*
Joerg Roedel8bda3092009-05-12 12:02:46 +02002322 * This function fetches the PTE for a given address in the aperture
2323 */
2324static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2325 unsigned long address)
2326{
Joerg Roedel384de722009-05-15 12:30:05 +02002327 struct aperture_range *aperture;
Joerg Roedel8bda3092009-05-12 12:02:46 +02002328 u64 *pte, *pte_page;
2329
Joerg Roedel384de722009-05-15 12:30:05 +02002330 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2331 if (!aperture)
2332 return NULL;
2333
2334 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
Joerg Roedel8bda3092009-05-12 12:02:46 +02002335 if (!pte) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01002336 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02002337 GFP_ATOMIC);
Joerg Roedel384de722009-05-15 12:30:05 +02002338 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2339 } else
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002340 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002341
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002342 update_domain(&dom->domain);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002343
2344 return pte;
2345}
2346
2347/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002348 * This is the generic map function. It maps one 4kb page at paddr to
2349 * the given address in the DMA address space for the domain.
2350 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002351static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002352 unsigned long address,
2353 phys_addr_t paddr,
2354 int direction)
2355{
2356 u64 *pte, __pte;
2357
2358 WARN_ON(address > dom->aperture_size);
2359
2360 paddr &= PAGE_MASK;
2361
Joerg Roedel8bda3092009-05-12 12:02:46 +02002362 pte = dma_ops_get_pte(dom, address);
Joerg Roedel53812c12009-05-12 12:17:38 +02002363 if (!pte)
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002364 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002365
2366 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2367
2368 if (direction == DMA_TO_DEVICE)
2369 __pte |= IOMMU_PTE_IR;
2370 else if (direction == DMA_FROM_DEVICE)
2371 __pte |= IOMMU_PTE_IW;
2372 else if (direction == DMA_BIDIRECTIONAL)
2373 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2374
2375 WARN_ON(*pte);
2376
2377 *pte = __pte;
2378
2379 return (dma_addr_t)address;
2380}
2381
Joerg Roedel431b2a22008-07-11 17:14:22 +02002382/*
2383 * The generic unmapping function for on page in the DMA address space.
2384 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002385static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002386 unsigned long address)
2387{
Joerg Roedel384de722009-05-15 12:30:05 +02002388 struct aperture_range *aperture;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002389 u64 *pte;
2390
2391 if (address >= dom->aperture_size)
2392 return;
2393
Joerg Roedel384de722009-05-15 12:30:05 +02002394 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2395 if (!aperture)
2396 return;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002397
Joerg Roedel384de722009-05-15 12:30:05 +02002398 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2399 if (!pte)
2400 return;
2401
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002402 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002403
2404 WARN_ON(!*pte);
2405
2406 *pte = 0ULL;
2407}
2408
Joerg Roedel431b2a22008-07-11 17:14:22 +02002409/*
2410 * This function contains common code for mapping of a physically
Joerg Roedel24f81162008-12-08 14:25:39 +01002411 * contiguous memory region into DMA address space. It is used by all
2412 * mapping functions provided with this IOMMU driver.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002413 * Must be called with the domain lock held.
2414 */
Joerg Roedelcb76c322008-06-26 21:28:00 +02002415static dma_addr_t __map_single(struct device *dev,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002416 struct dma_ops_domain *dma_dom,
2417 phys_addr_t paddr,
2418 size_t size,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002419 int dir,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002420 bool align,
2421 u64 dma_mask)
Joerg Roedelcb76c322008-06-26 21:28:00 +02002422{
2423 dma_addr_t offset = paddr & ~PAGE_MASK;
Joerg Roedel53812c12009-05-12 12:17:38 +02002424 dma_addr_t address, start, ret;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002425 unsigned int pages;
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002426 unsigned long align_mask = 0;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002427 int i;
2428
Joerg Roedele3c449f2008-10-15 22:02:11 -07002429 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002430 paddr &= PAGE_MASK;
2431
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +01002432 INC_STATS_COUNTER(total_map_requests);
2433
Joerg Roedelc1858972008-12-12 15:42:39 +01002434 if (pages > 1)
2435 INC_STATS_COUNTER(cross_page);
2436
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002437 if (align)
2438 align_mask = (1UL << get_order(size)) - 1;
2439
Joerg Roedel11b83882009-05-19 10:23:15 +02002440retry:
Joerg Roedel832a90c2008-09-18 15:54:23 +02002441 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2442 dma_mask);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002443 if (unlikely(address == DMA_ERROR_CODE)) {
Joerg Roedel11b83882009-05-19 10:23:15 +02002444 /*
2445 * setting next_address here will let the address
2446 * allocator only scan the new allocated range in the
2447 * first run. This is a small optimization.
2448 */
2449 dma_dom->next_address = dma_dom->aperture_size;
2450
Joerg Roedel576175c2009-11-23 19:08:46 +01002451 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
Joerg Roedel11b83882009-05-19 10:23:15 +02002452 goto out;
2453
2454 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02002455 * aperture was successfully enlarged by 128 MB, try
Joerg Roedel11b83882009-05-19 10:23:15 +02002456 * allocation again
2457 */
2458 goto retry;
2459 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002460
2461 start = address;
2462 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002463 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002464 if (ret == DMA_ERROR_CODE)
Joerg Roedel53812c12009-05-12 12:17:38 +02002465 goto out_unmap;
2466
Joerg Roedelcb76c322008-06-26 21:28:00 +02002467 paddr += PAGE_SIZE;
2468 start += PAGE_SIZE;
2469 }
2470 address += offset;
2471
Joerg Roedel5774f7c2008-12-12 15:57:30 +01002472 ADD_STATS_COUNTER(alloced_io_mem, size);
2473
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09002474 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002475 domain_flush_tlb(&dma_dom->domain);
Joerg Roedel1c655772008-09-04 18:40:05 +02002476 dma_dom->need_flush = false;
Joerg Roedel318afd42009-11-23 18:32:38 +01002477 } else if (unlikely(amd_iommu_np_cache))
Joerg Roedel17b124b2011-04-06 18:01:35 +02002478 domain_flush_pages(&dma_dom->domain, address, size);
Joerg Roedel270cab242008-09-04 15:49:46 +02002479
Joerg Roedelcb76c322008-06-26 21:28:00 +02002480out:
2481 return address;
Joerg Roedel53812c12009-05-12 12:17:38 +02002482
2483out_unmap:
2484
2485 for (--i; i >= 0; --i) {
2486 start -= PAGE_SIZE;
Joerg Roedel680525e2009-11-23 18:44:42 +01002487 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedel53812c12009-05-12 12:17:38 +02002488 }
2489
2490 dma_ops_free_addresses(dma_dom, address, pages);
2491
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002492 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002493}
2494
Joerg Roedel431b2a22008-07-11 17:14:22 +02002495/*
2496 * Does the reverse of the __map_single function. Must be called with
2497 * the domain lock held too
2498 */
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002499static void __unmap_single(struct dma_ops_domain *dma_dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002500 dma_addr_t dma_addr,
2501 size_t size,
2502 int dir)
2503{
Joerg Roedel04e04632010-09-23 16:12:48 +02002504 dma_addr_t flush_addr;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002505 dma_addr_t i, start;
2506 unsigned int pages;
2507
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002508 if ((dma_addr == DMA_ERROR_CODE) ||
Joerg Roedelb8d99052008-12-08 14:40:26 +01002509 (dma_addr + size > dma_dom->aperture_size))
Joerg Roedelcb76c322008-06-26 21:28:00 +02002510 return;
2511
Joerg Roedel04e04632010-09-23 16:12:48 +02002512 flush_addr = dma_addr;
Joerg Roedele3c449f2008-10-15 22:02:11 -07002513 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002514 dma_addr &= PAGE_MASK;
2515 start = dma_addr;
2516
2517 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002518 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002519 start += PAGE_SIZE;
2520 }
2521
Joerg Roedel5774f7c2008-12-12 15:57:30 +01002522 SUB_STATS_COUNTER(alloced_io_mem, size);
2523
Joerg Roedelcb76c322008-06-26 21:28:00 +02002524 dma_ops_free_addresses(dma_dom, dma_addr, pages);
Joerg Roedel270cab242008-09-04 15:49:46 +02002525
Joerg Roedel80be3082008-11-06 14:59:05 +01002526 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002527 domain_flush_pages(&dma_dom->domain, flush_addr, size);
Joerg Roedel80be3082008-11-06 14:59:05 +01002528 dma_dom->need_flush = false;
2529 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002530}
2531
Joerg Roedel431b2a22008-07-11 17:14:22 +02002532/*
2533 * The exported map_single function for dma_ops.
2534 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002535static dma_addr_t map_page(struct device *dev, struct page *page,
2536 unsigned long offset, size_t size,
2537 enum dma_data_direction dir,
2538 struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002539{
2540 unsigned long flags;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002541 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002542 dma_addr_t addr;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002543 u64 dma_mask;
FUJITA Tomonori51491362009-01-05 23:47:25 +09002544 phys_addr_t paddr = page_to_phys(page) + offset;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002545
Joerg Roedel0f2a86f2008-12-12 15:05:16 +01002546 INC_STATS_COUNTER(cnt_map_single);
2547
Joerg Roedel94f6d192009-11-24 16:40:02 +01002548 domain = get_domain(dev);
2549 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002550 return (dma_addr_t)paddr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002551 else if (IS_ERR(domain))
2552 return DMA_ERROR_CODE;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002553
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002554 dma_mask = *dev->dma_mask;
2555
Joerg Roedel4da70b92008-06-26 21:28:01 +02002556 spin_lock_irqsave(&domain->lock, flags);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002557
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002558 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002559 dma_mask);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002560 if (addr == DMA_ERROR_CODE)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002561 goto out;
2562
Joerg Roedel17b124b2011-04-06 18:01:35 +02002563 domain_flush_complete(domain);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002564
2565out:
2566 spin_unlock_irqrestore(&domain->lock, flags);
2567
2568 return addr;
2569}
2570
Joerg Roedel431b2a22008-07-11 17:14:22 +02002571/*
2572 * The exported unmap_single function for dma_ops.
2573 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002574static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2575 enum dma_data_direction dir, struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002576{
2577 unsigned long flags;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002578 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002579
Joerg Roedel146a6912008-12-12 15:07:12 +01002580 INC_STATS_COUNTER(cnt_unmap_single);
2581
Joerg Roedel94f6d192009-11-24 16:40:02 +01002582 domain = get_domain(dev);
2583 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002584 return;
2585
Joerg Roedel4da70b92008-06-26 21:28:01 +02002586 spin_lock_irqsave(&domain->lock, flags);
2587
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002588 __unmap_single(domain->priv, dma_addr, size, dir);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002589
Joerg Roedel17b124b2011-04-06 18:01:35 +02002590 domain_flush_complete(domain);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002591
2592 spin_unlock_irqrestore(&domain->lock, flags);
2593}
2594
Joerg Roedel431b2a22008-07-11 17:14:22 +02002595/*
2596 * This is a special map_sg function which is used if we should map a
2597 * device which is not handled by an AMD IOMMU in the system.
2598 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002599static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2600 int nelems, int dir)
2601{
2602 struct scatterlist *s;
2603 int i;
2604
2605 for_each_sg(sglist, s, nelems, i) {
2606 s->dma_address = (dma_addr_t)sg_phys(s);
2607 s->dma_length = s->length;
2608 }
2609
2610 return nelems;
2611}
2612
Joerg Roedel431b2a22008-07-11 17:14:22 +02002613/*
2614 * The exported map_sg function for dma_ops (handles scatter-gather
2615 * lists).
2616 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002617static int map_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002618 int nelems, enum dma_data_direction dir,
2619 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002620{
2621 unsigned long flags;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002622 struct protection_domain *domain;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002623 int i;
2624 struct scatterlist *s;
2625 phys_addr_t paddr;
2626 int mapped_elems = 0;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002627 u64 dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002628
Joerg Roedeld03f0672008-12-12 15:09:48 +01002629 INC_STATS_COUNTER(cnt_map_sg);
2630
Joerg Roedel94f6d192009-11-24 16:40:02 +01002631 domain = get_domain(dev);
2632 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002633 return map_sg_no_iommu(dev, sglist, nelems, dir);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002634 else if (IS_ERR(domain))
2635 return 0;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002636
Joerg Roedel832a90c2008-09-18 15:54:23 +02002637 dma_mask = *dev->dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002638
Joerg Roedel65b050a2008-06-26 21:28:02 +02002639 spin_lock_irqsave(&domain->lock, flags);
2640
2641 for_each_sg(sglist, s, nelems, i) {
2642 paddr = sg_phys(s);
2643
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002644 s->dma_address = __map_single(dev, domain->priv,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002645 paddr, s->length, dir, false,
2646 dma_mask);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002647
2648 if (s->dma_address) {
2649 s->dma_length = s->length;
2650 mapped_elems++;
2651 } else
2652 goto unmap;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002653 }
2654
Joerg Roedel17b124b2011-04-06 18:01:35 +02002655 domain_flush_complete(domain);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002656
2657out:
2658 spin_unlock_irqrestore(&domain->lock, flags);
2659
2660 return mapped_elems;
2661unmap:
2662 for_each_sg(sglist, s, mapped_elems, i) {
2663 if (s->dma_address)
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002664 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002665 s->dma_length, dir);
2666 s->dma_address = s->dma_length = 0;
2667 }
2668
2669 mapped_elems = 0;
2670
2671 goto out;
2672}
2673
Joerg Roedel431b2a22008-07-11 17:14:22 +02002674/*
2675 * The exported map_sg function for dma_ops (handles scatter-gather
2676 * lists).
2677 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002678static void unmap_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002679 int nelems, enum dma_data_direction dir,
2680 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002681{
2682 unsigned long flags;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002683 struct protection_domain *domain;
2684 struct scatterlist *s;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002685 int i;
2686
Joerg Roedel55877a62008-12-12 15:12:14 +01002687 INC_STATS_COUNTER(cnt_unmap_sg);
2688
Joerg Roedel94f6d192009-11-24 16:40:02 +01002689 domain = get_domain(dev);
2690 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002691 return;
2692
Joerg Roedel65b050a2008-06-26 21:28:02 +02002693 spin_lock_irqsave(&domain->lock, flags);
2694
2695 for_each_sg(sglist, s, nelems, i) {
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002696 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002697 s->dma_length, dir);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002698 s->dma_address = s->dma_length = 0;
2699 }
2700
Joerg Roedel17b124b2011-04-06 18:01:35 +02002701 domain_flush_complete(domain);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002702
2703 spin_unlock_irqrestore(&domain->lock, flags);
2704}
2705
Joerg Roedel431b2a22008-07-11 17:14:22 +02002706/*
2707 * The exported alloc_coherent function for dma_ops.
2708 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002709static void *alloc_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002710 dma_addr_t *dma_addr, gfp_t flag,
2711 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002712{
2713 unsigned long flags;
2714 void *virt_addr;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002715 struct protection_domain *domain;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002716 phys_addr_t paddr;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002717 u64 dma_mask = dev->coherent_dma_mask;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002718
Joerg Roedelc8f0fb32008-12-12 15:14:21 +01002719 INC_STATS_COUNTER(cnt_alloc_coherent);
2720
Joerg Roedel94f6d192009-11-24 16:40:02 +01002721 domain = get_domain(dev);
2722 if (PTR_ERR(domain) == -EINVAL) {
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002723 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2724 *dma_addr = __pa(virt_addr);
2725 return virt_addr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002726 } else if (IS_ERR(domain))
2727 return NULL;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002728
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002729 dma_mask = dev->coherent_dma_mask;
2730 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2731 flag |= __GFP_ZERO;
FUJITA Tomonori13d9fea2008-09-10 20:19:40 +09002732
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002733 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2734 if (!virt_addr)
Jaswinder Singh Rajputb25ae672009-07-01 19:53:14 +05302735 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002736
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002737 paddr = virt_to_phys(virt_addr);
2738
Joerg Roedel832a90c2008-09-18 15:54:23 +02002739 if (!dma_mask)
2740 dma_mask = *dev->dma_mask;
2741
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002742 spin_lock_irqsave(&domain->lock, flags);
2743
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002744 *dma_addr = __map_single(dev, domain->priv, paddr,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002745 size, DMA_BIDIRECTIONAL, true, dma_mask);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002746
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002747 if (*dma_addr == DMA_ERROR_CODE) {
Jiri Slaby367d04c2009-05-28 09:54:48 +02002748 spin_unlock_irqrestore(&domain->lock, flags);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002749 goto out_free;
Jiri Slaby367d04c2009-05-28 09:54:48 +02002750 }
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002751
Joerg Roedel17b124b2011-04-06 18:01:35 +02002752 domain_flush_complete(domain);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002753
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002754 spin_unlock_irqrestore(&domain->lock, flags);
2755
2756 return virt_addr;
Joerg Roedel5b28df62008-12-02 17:49:42 +01002757
2758out_free:
2759
2760 free_pages((unsigned long)virt_addr, get_order(size));
2761
2762 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002763}
2764
Joerg Roedel431b2a22008-07-11 17:14:22 +02002765/*
2766 * The exported free_coherent function for dma_ops.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002767 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002768static void free_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002769 void *virt_addr, dma_addr_t dma_addr,
2770 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002771{
2772 unsigned long flags;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002773 struct protection_domain *domain;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002774
Joerg Roedel5d31ee72008-12-12 15:16:38 +01002775 INC_STATS_COUNTER(cnt_free_coherent);
2776
Joerg Roedel94f6d192009-11-24 16:40:02 +01002777 domain = get_domain(dev);
2778 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002779 goto free_mem;
2780
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002781 spin_lock_irqsave(&domain->lock, flags);
2782
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002783 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002784
Joerg Roedel17b124b2011-04-06 18:01:35 +02002785 domain_flush_complete(domain);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002786
2787 spin_unlock_irqrestore(&domain->lock, flags);
2788
2789free_mem:
2790 free_pages((unsigned long)virt_addr, get_order(size));
2791}
2792
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002793/*
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002794 * This function is called by the DMA layer to find out if we can handle a
2795 * particular device. It is part of the dma_ops.
2796 */
2797static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2798{
Joerg Roedel420aef82009-11-23 16:14:57 +01002799 return check_device(dev);
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002800}
2801
2802/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002803 * The function for pre-allocating protection domains.
2804 *
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002805 * If the driver core informs the DMA layer if a driver grabs a device
2806 * we don't need to preallocate the protection domains anymore.
2807 * For now we have to.
2808 */
Steffen Persvold943bc7e2012-03-15 12:16:28 +01002809static void __init prealloc_protection_domains(void)
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002810{
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002811 struct iommu_dev_data *dev_data;
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002812 struct dma_ops_domain *dma_dom;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002813 struct pci_dev *dev = NULL;
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002814 u16 devid;
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002815
Chris Wrightd18c69d2010-04-02 18:27:55 -07002816 for_each_pci_dev(dev) {
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002817
2818 /* Do we handle this device? */
2819 if (!check_device(&dev->dev))
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002820 continue;
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002821
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002822 dev_data = get_dev_data(&dev->dev);
2823 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2824 /* Make sure passthrough domain is allocated */
2825 alloc_passthrough_domain();
2826 dev_data->passthrough = true;
2827 attach_device(&dev->dev, pt_domain);
2828 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2829 dev_name(&dev->dev));
2830 }
2831
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002832 /* Is there already any domain for it? */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002833 if (domain_for_device(&dev->dev))
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002834 continue;
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002835
2836 devid = get_device_id(&dev->dev);
2837
Joerg Roedel87a64d52009-11-24 17:26:43 +01002838 dma_dom = dma_ops_domain_alloc();
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002839 if (!dma_dom)
2840 continue;
2841 init_unity_mappings_for_device(dma_dom, devid);
Joerg Roedelbd60b732008-09-11 10:24:48 +02002842 dma_dom->target_dev = devid;
2843
Joerg Roedel15898bb2009-11-24 15:39:42 +01002844 attach_device(&dev->dev, &dma_dom->domain);
Joerg Roedelbe831292009-11-23 12:50:00 +01002845
Joerg Roedelbd60b732008-09-11 10:24:48 +02002846 list_add_tail(&dma_dom->list, &iommu_pd_list);
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002847 }
2848}
2849
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002850static struct dma_map_ops amd_iommu_dma_ops = {
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002851 .alloc = alloc_coherent,
2852 .free = free_coherent,
FUJITA Tomonori51491362009-01-05 23:47:25 +09002853 .map_page = map_page,
2854 .unmap_page = unmap_page,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002855 .map_sg = map_sg,
2856 .unmap_sg = unmap_sg,
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002857 .dma_supported = amd_iommu_dma_supported,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002858};
2859
Joerg Roedel27c21272011-05-30 15:56:24 +02002860static unsigned device_dma_ops_init(void)
2861{
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002862 struct iommu_dev_data *dev_data;
Joerg Roedel27c21272011-05-30 15:56:24 +02002863 struct pci_dev *pdev = NULL;
2864 unsigned unhandled = 0;
2865
2866 for_each_pci_dev(pdev) {
2867 if (!check_device(&pdev->dev)) {
Joerg Roedelaf1be042012-01-18 14:03:11 +01002868
2869 iommu_ignore_device(&pdev->dev);
2870
Joerg Roedel27c21272011-05-30 15:56:24 +02002871 unhandled += 1;
2872 continue;
2873 }
2874
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002875 dev_data = get_dev_data(&pdev->dev);
2876
2877 if (!dev_data->passthrough)
2878 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2879 else
2880 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
Joerg Roedel27c21272011-05-30 15:56:24 +02002881 }
2882
2883 return unhandled;
2884}
2885
Joerg Roedel431b2a22008-07-11 17:14:22 +02002886/*
2887 * The function which clues the AMD IOMMU driver into dma_ops.
2888 */
Joerg Roedelf5325092010-01-22 17:44:35 +01002889
2890void __init amd_iommu_init_api(void)
2891{
Joerg Roedel2cc21c42011-09-06 17:56:07 +02002892 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
Joerg Roedelf5325092010-01-22 17:44:35 +01002893}
2894
Joerg Roedel6631ee92008-06-26 21:28:05 +02002895int __init amd_iommu_init_dma_ops(void)
2896{
2897 struct amd_iommu *iommu;
Joerg Roedel27c21272011-05-30 15:56:24 +02002898 int ret, unhandled;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002899
Joerg Roedel431b2a22008-07-11 17:14:22 +02002900 /*
2901 * first allocate a default protection domain for every IOMMU we
2902 * found in the system. Devices not assigned to any other
2903 * protection domain will be assigned to the default one.
2904 */
Joerg Roedel3bd22172009-05-04 15:06:20 +02002905 for_each_iommu(iommu) {
Joerg Roedel87a64d52009-11-24 17:26:43 +01002906 iommu->default_dom = dma_ops_domain_alloc();
Joerg Roedel6631ee92008-06-26 21:28:05 +02002907 if (iommu->default_dom == NULL)
2908 return -ENOMEM;
Joerg Roedele2dc14a2008-12-10 18:48:59 +01002909 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002910 ret = iommu_init_unity_mappings(iommu);
2911 if (ret)
2912 goto free_domains;
2913 }
2914
Joerg Roedel431b2a22008-07-11 17:14:22 +02002915 /*
Joerg Roedel8793abe2009-11-27 11:40:33 +01002916 * Pre-allocate the protection domains for each device.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002917 */
Joerg Roedel8793abe2009-11-27 11:40:33 +01002918 prealloc_protection_domains();
Joerg Roedel6631ee92008-06-26 21:28:05 +02002919
2920 iommu_detected = 1;
FUJITA Tomonori75f1cdf2009-11-10 19:46:20 +09002921 swiotlb = 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002922
Joerg Roedel431b2a22008-07-11 17:14:22 +02002923 /* Make the driver finally visible to the drivers */
Joerg Roedel27c21272011-05-30 15:56:24 +02002924 unhandled = device_dma_ops_init();
2925 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2926 /* There are unhandled devices - initialize swiotlb for them */
2927 swiotlb = 1;
2928 }
Joerg Roedel6631ee92008-06-26 21:28:05 +02002929
Joerg Roedel7f265082008-12-12 13:50:21 +01002930 amd_iommu_stats_init();
2931
Joerg Roedel6631ee92008-06-26 21:28:05 +02002932 return 0;
2933
2934free_domains:
2935
Joerg Roedel3bd22172009-05-04 15:06:20 +02002936 for_each_iommu(iommu) {
Joerg Roedel6631ee92008-06-26 21:28:05 +02002937 if (iommu->default_dom)
2938 dma_ops_domain_free(iommu->default_dom);
2939 }
2940
2941 return ret;
2942}
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002943
2944/*****************************************************************************
2945 *
2946 * The following functions belong to the exported interface of AMD IOMMU
2947 *
2948 * This interface allows access to lower level functions of the IOMMU
2949 * like protection domain handling and assignement of devices to domains
2950 * which is not possible with the dma_ops interface.
2951 *
2952 *****************************************************************************/
2953
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002954static void cleanup_domain(struct protection_domain *domain)
2955{
Joerg Roedel492667d2009-11-27 13:25:47 +01002956 struct iommu_dev_data *dev_data, *next;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002957 unsigned long flags;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002958
2959 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2960
Joerg Roedel492667d2009-11-27 13:25:47 +01002961 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002962 __detach_device(dev_data);
Joerg Roedel492667d2009-11-27 13:25:47 +01002963 atomic_set(&dev_data->bind, 0);
2964 }
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002965
2966 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2967}
2968
Joerg Roedel26508152009-08-26 16:52:40 +02002969static void protection_domain_free(struct protection_domain *domain)
2970{
2971 if (!domain)
2972 return;
2973
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002974 del_domain_from_list(domain);
2975
Joerg Roedel26508152009-08-26 16:52:40 +02002976 if (domain->id)
2977 domain_id_free(domain->id);
2978
2979 kfree(domain);
2980}
2981
2982static struct protection_domain *protection_domain_alloc(void)
Joerg Roedelc156e342008-12-02 18:13:27 +01002983{
2984 struct protection_domain *domain;
2985
2986 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2987 if (!domain)
Joerg Roedel26508152009-08-26 16:52:40 +02002988 return NULL;
Joerg Roedelc156e342008-12-02 18:13:27 +01002989
2990 spin_lock_init(&domain->lock);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01002991 mutex_init(&domain->api_lock);
Joerg Roedelc156e342008-12-02 18:13:27 +01002992 domain->id = domain_id_alloc();
2993 if (!domain->id)
Joerg Roedel26508152009-08-26 16:52:40 +02002994 goto out_err;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01002995 INIT_LIST_HEAD(&domain->dev_list);
Joerg Roedel26508152009-08-26 16:52:40 +02002996
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002997 add_domain_to_list(domain);
2998
Joerg Roedel26508152009-08-26 16:52:40 +02002999 return domain;
3000
3001out_err:
3002 kfree(domain);
3003
3004 return NULL;
3005}
3006
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003007static int __init alloc_passthrough_domain(void)
3008{
3009 if (pt_domain != NULL)
3010 return 0;
3011
3012 /* allocate passthrough domain */
3013 pt_domain = protection_domain_alloc();
3014 if (!pt_domain)
3015 return -ENOMEM;
3016
3017 pt_domain->mode = PAGE_MODE_NONE;
3018
3019 return 0;
3020}
Joerg Roedel26508152009-08-26 16:52:40 +02003021static int amd_iommu_domain_init(struct iommu_domain *dom)
3022{
3023 struct protection_domain *domain;
3024
3025 domain = protection_domain_alloc();
3026 if (!domain)
Joerg Roedelc156e342008-12-02 18:13:27 +01003027 goto out_free;
Joerg Roedel26508152009-08-26 16:52:40 +02003028
3029 domain->mode = PAGE_MODE_3_LEVEL;
Joerg Roedelc156e342008-12-02 18:13:27 +01003030 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3031 if (!domain->pt_root)
3032 goto out_free;
3033
Joerg Roedelf3572db2011-11-23 12:36:25 +01003034 domain->iommu_domain = dom;
3035
Joerg Roedelc156e342008-12-02 18:13:27 +01003036 dom->priv = domain;
3037
3038 return 0;
3039
3040out_free:
Joerg Roedel26508152009-08-26 16:52:40 +02003041 protection_domain_free(domain);
Joerg Roedelc156e342008-12-02 18:13:27 +01003042
3043 return -ENOMEM;
3044}
3045
Joerg Roedel98383fc2008-12-02 18:34:12 +01003046static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3047{
3048 struct protection_domain *domain = dom->priv;
3049
3050 if (!domain)
3051 return;
3052
3053 if (domain->dev_cnt > 0)
3054 cleanup_domain(domain);
3055
3056 BUG_ON(domain->dev_cnt != 0);
3057
Joerg Roedel132bd682011-11-17 14:18:46 +01003058 if (domain->mode != PAGE_MODE_NONE)
3059 free_pagetable(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003060
Joerg Roedel52815b72011-11-17 17:24:28 +01003061 if (domain->flags & PD_IOMMUV2_MASK)
3062 free_gcr3_table(domain);
3063
Joerg Roedel8b408fe2010-03-08 14:20:07 +01003064 protection_domain_free(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003065
3066 dom->priv = NULL;
3067}
3068
Joerg Roedel684f2882008-12-08 12:07:44 +01003069static void amd_iommu_detach_device(struct iommu_domain *dom,
3070 struct device *dev)
3071{
Joerg Roedel657cbb62009-11-23 15:26:46 +01003072 struct iommu_dev_data *dev_data = dev->archdata.iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003073 struct amd_iommu *iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003074 u16 devid;
3075
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003076 if (!check_device(dev))
Joerg Roedel684f2882008-12-08 12:07:44 +01003077 return;
3078
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003079 devid = get_device_id(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003080
Joerg Roedel657cbb62009-11-23 15:26:46 +01003081 if (dev_data->domain != NULL)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003082 detach_device(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003083
3084 iommu = amd_iommu_rlookup_table[devid];
3085 if (!iommu)
3086 return;
3087
Joerg Roedel684f2882008-12-08 12:07:44 +01003088 iommu_completion_wait(iommu);
3089}
3090
Joerg Roedel01106062008-12-02 19:34:11 +01003091static int amd_iommu_attach_device(struct iommu_domain *dom,
3092 struct device *dev)
3093{
3094 struct protection_domain *domain = dom->priv;
Joerg Roedel657cbb62009-11-23 15:26:46 +01003095 struct iommu_dev_data *dev_data;
Joerg Roedel01106062008-12-02 19:34:11 +01003096 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01003097 int ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003098
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003099 if (!check_device(dev))
Joerg Roedel01106062008-12-02 19:34:11 +01003100 return -EINVAL;
3101
Joerg Roedel657cbb62009-11-23 15:26:46 +01003102 dev_data = dev->archdata.iommu;
3103
Joerg Roedelf62dda62011-06-09 12:55:35 +02003104 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel01106062008-12-02 19:34:11 +01003105 if (!iommu)
3106 return -EINVAL;
3107
Joerg Roedel657cbb62009-11-23 15:26:46 +01003108 if (dev_data->domain)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003109 detach_device(dev);
Joerg Roedel01106062008-12-02 19:34:11 +01003110
Joerg Roedel15898bb2009-11-24 15:39:42 +01003111 ret = attach_device(dev, domain);
Joerg Roedel01106062008-12-02 19:34:11 +01003112
3113 iommu_completion_wait(iommu);
3114
Joerg Roedel15898bb2009-11-24 15:39:42 +01003115 return ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003116}
3117
Joerg Roedel468e2362010-01-21 16:37:36 +01003118static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003119 phys_addr_t paddr, size_t page_size, int iommu_prot)
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003120{
3121 struct protection_domain *domain = dom->priv;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003122 int prot = 0;
3123 int ret;
3124
Joerg Roedel132bd682011-11-17 14:18:46 +01003125 if (domain->mode == PAGE_MODE_NONE)
3126 return -EINVAL;
3127
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003128 if (iommu_prot & IOMMU_READ)
3129 prot |= IOMMU_PROT_IR;
3130 if (iommu_prot & IOMMU_WRITE)
3131 prot |= IOMMU_PROT_IW;
3132
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003133 mutex_lock(&domain->api_lock);
Joerg Roedel795e74f2010-05-11 17:40:57 +02003134 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003135 mutex_unlock(&domain->api_lock);
3136
Joerg Roedel795e74f2010-05-11 17:40:57 +02003137 return ret;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003138}
3139
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003140static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3141 size_t page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003142{
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003143 struct protection_domain *domain = dom->priv;
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003144 size_t unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003145
Joerg Roedel132bd682011-11-17 14:18:46 +01003146 if (domain->mode == PAGE_MODE_NONE)
3147 return -EINVAL;
3148
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003149 mutex_lock(&domain->api_lock);
Joerg Roedel468e2362010-01-21 16:37:36 +01003150 unmap_size = iommu_unmap_page(domain, iova, page_size);
Joerg Roedel795e74f2010-05-11 17:40:57 +02003151 mutex_unlock(&domain->api_lock);
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003152
Joerg Roedel17b124b2011-04-06 18:01:35 +02003153 domain_flush_tlb_pde(domain);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003154
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003155 return unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003156}
3157
Joerg Roedel645c4c82008-12-02 20:05:50 +01003158static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3159 unsigned long iova)
3160{
3161 struct protection_domain *domain = dom->priv;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003162 unsigned long offset_mask;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003163 phys_addr_t paddr;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003164 u64 *pte, __pte;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003165
Joerg Roedel132bd682011-11-17 14:18:46 +01003166 if (domain->mode == PAGE_MODE_NONE)
3167 return iova;
3168
Joerg Roedel24cd7722010-01-19 17:27:39 +01003169 pte = fetch_pte(domain, iova);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003170
Joerg Roedela6d41a42009-09-02 17:08:55 +02003171 if (!pte || !IOMMU_PTE_PRESENT(*pte))
Joerg Roedel645c4c82008-12-02 20:05:50 +01003172 return 0;
3173
Joerg Roedelf03152b2010-01-21 16:15:24 +01003174 if (PM_PTE_LEVEL(*pte) == 0)
3175 offset_mask = PAGE_SIZE - 1;
3176 else
3177 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3178
3179 __pte = *pte & PM_ADDR_MASK;
3180 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003181
3182 return paddr;
3183}
3184
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003185static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3186 unsigned long cap)
3187{
Joerg Roedel80a506b2010-07-27 17:14:24 +02003188 switch (cap) {
3189 case IOMMU_CAP_CACHE_COHERENCY:
3190 return 1;
3191 }
3192
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003193 return 0;
3194}
3195
Joerg Roedel26961ef2008-12-03 17:00:17 +01003196static struct iommu_ops amd_iommu_ops = {
3197 .domain_init = amd_iommu_domain_init,
3198 .domain_destroy = amd_iommu_domain_destroy,
3199 .attach_dev = amd_iommu_attach_device,
3200 .detach_dev = amd_iommu_detach_device,
Joerg Roedel468e2362010-01-21 16:37:36 +01003201 .map = amd_iommu_map,
3202 .unmap = amd_iommu_unmap,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003203 .iova_to_phys = amd_iommu_iova_to_phys,
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003204 .domain_has_cap = amd_iommu_domain_has_cap,
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +02003205 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003206};
3207
Joerg Roedel0feae532009-08-26 15:26:30 +02003208/*****************************************************************************
3209 *
3210 * The next functions do a basic initialization of IOMMU for pass through
3211 * mode
3212 *
3213 * In passthrough mode the IOMMU is initialized and enabled but not used for
3214 * DMA-API translation.
3215 *
3216 *****************************************************************************/
3217
3218int __init amd_iommu_init_passthrough(void)
3219{
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003220 struct iommu_dev_data *dev_data;
Joerg Roedel0feae532009-08-26 15:26:30 +02003221 struct pci_dev *dev = NULL;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003222 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01003223 u16 devid;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003224 int ret;
Joerg Roedel0feae532009-08-26 15:26:30 +02003225
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003226 ret = alloc_passthrough_domain();
3227 if (ret)
3228 return ret;
Joerg Roedel0feae532009-08-26 15:26:30 +02003229
Kulikov Vasiliy6c54aab2010-07-03 12:03:51 -04003230 for_each_pci_dev(dev) {
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003231 if (!check_device(&dev->dev))
Joerg Roedel0feae532009-08-26 15:26:30 +02003232 continue;
3233
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003234 dev_data = get_dev_data(&dev->dev);
3235 dev_data->passthrough = true;
3236
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003237 devid = get_device_id(&dev->dev);
3238
Joerg Roedel15898bb2009-11-24 15:39:42 +01003239 iommu = amd_iommu_rlookup_table[devid];
Joerg Roedel0feae532009-08-26 15:26:30 +02003240 if (!iommu)
3241 continue;
3242
Joerg Roedel15898bb2009-11-24 15:39:42 +01003243 attach_device(&dev->dev, pt_domain);
Joerg Roedel0feae532009-08-26 15:26:30 +02003244 }
3245
Joerg Roedel2655d7a2011-12-22 12:35:38 +01003246 amd_iommu_stats_init();
3247
Joerg Roedel0feae532009-08-26 15:26:30 +02003248 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3249
3250 return 0;
3251}
Joerg Roedel72e1dcc2011-11-10 19:13:51 +01003252
3253/* IOMMUv2 specific functions */
3254int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3255{
3256 return atomic_notifier_chain_register(&ppr_notifier, nb);
3257}
3258EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3259
3260int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3261{
3262 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3263}
3264EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
Joerg Roedel132bd682011-11-17 14:18:46 +01003265
3266void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3267{
3268 struct protection_domain *domain = dom->priv;
3269 unsigned long flags;
3270
3271 spin_lock_irqsave(&domain->lock, flags);
3272
3273 /* Update data structure */
3274 domain->mode = PAGE_MODE_NONE;
3275 domain->updated = true;
3276
3277 /* Make changes visible to IOMMUs */
3278 update_domain(domain);
3279
3280 /* Page-table is not visible to IOMMU anymore, so free it */
3281 free_pagetable(domain);
3282
3283 spin_unlock_irqrestore(&domain->lock, flags);
3284}
3285EXPORT_SYMBOL(amd_iommu_domain_direct_map);
Joerg Roedel52815b72011-11-17 17:24:28 +01003286
3287int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3288{
3289 struct protection_domain *domain = dom->priv;
3290 unsigned long flags;
3291 int levels, ret;
3292
3293 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3294 return -EINVAL;
3295
3296 /* Number of GCR3 table levels required */
3297 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3298 levels += 1;
3299
3300 if (levels > amd_iommu_max_glx_val)
3301 return -EINVAL;
3302
3303 spin_lock_irqsave(&domain->lock, flags);
3304
3305 /*
3306 * Save us all sanity checks whether devices already in the
3307 * domain support IOMMUv2. Just force that the domain has no
3308 * devices attached when it is switched into IOMMUv2 mode.
3309 */
3310 ret = -EBUSY;
3311 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3312 goto out;
3313
3314 ret = -ENOMEM;
3315 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3316 if (domain->gcr3_tbl == NULL)
3317 goto out;
3318
3319 domain->glx = levels;
3320 domain->flags |= PD_IOMMUV2_MASK;
3321 domain->updated = true;
3322
3323 update_domain(domain);
3324
3325 ret = 0;
3326
3327out:
3328 spin_unlock_irqrestore(&domain->lock, flags);
3329
3330 return ret;
3331}
3332EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003333
3334static int __flush_pasid(struct protection_domain *domain, int pasid,
3335 u64 address, bool size)
3336{
3337 struct iommu_dev_data *dev_data;
3338 struct iommu_cmd cmd;
3339 int i, ret;
3340
3341 if (!(domain->flags & PD_IOMMUV2_MASK))
3342 return -EINVAL;
3343
3344 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3345
3346 /*
3347 * IOMMU TLB needs to be flushed before Device TLB to
3348 * prevent device TLB refill from IOMMU TLB
3349 */
3350 for (i = 0; i < amd_iommus_present; ++i) {
3351 if (domain->dev_iommu[i] == 0)
3352 continue;
3353
3354 ret = iommu_queue_command(amd_iommus[i], &cmd);
3355 if (ret != 0)
3356 goto out;
3357 }
3358
3359 /* Wait until IOMMU TLB flushes are complete */
3360 domain_flush_complete(domain);
3361
3362 /* Now flush device TLBs */
3363 list_for_each_entry(dev_data, &domain->dev_list, list) {
3364 struct amd_iommu *iommu;
3365 int qdep;
3366
3367 BUG_ON(!dev_data->ats.enabled);
3368
3369 qdep = dev_data->ats.qdep;
3370 iommu = amd_iommu_rlookup_table[dev_data->devid];
3371
3372 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3373 qdep, address, size);
3374
3375 ret = iommu_queue_command(iommu, &cmd);
3376 if (ret != 0)
3377 goto out;
3378 }
3379
3380 /* Wait until all device TLBs are flushed */
3381 domain_flush_complete(domain);
3382
3383 ret = 0;
3384
3385out:
3386
3387 return ret;
3388}
3389
3390static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3391 u64 address)
3392{
Joerg Roedel399be2f2011-12-01 16:53:47 +01003393 INC_STATS_COUNTER(invalidate_iotlb);
3394
Joerg Roedel22e266c2011-11-21 15:59:08 +01003395 return __flush_pasid(domain, pasid, address, false);
3396}
3397
3398int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3399 u64 address)
3400{
3401 struct protection_domain *domain = dom->priv;
3402 unsigned long flags;
3403 int ret;
3404
3405 spin_lock_irqsave(&domain->lock, flags);
3406 ret = __amd_iommu_flush_page(domain, pasid, address);
3407 spin_unlock_irqrestore(&domain->lock, flags);
3408
3409 return ret;
3410}
3411EXPORT_SYMBOL(amd_iommu_flush_page);
3412
3413static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3414{
Joerg Roedel399be2f2011-12-01 16:53:47 +01003415 INC_STATS_COUNTER(invalidate_iotlb_all);
3416
Joerg Roedel22e266c2011-11-21 15:59:08 +01003417 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3418 true);
3419}
3420
3421int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3422{
3423 struct protection_domain *domain = dom->priv;
3424 unsigned long flags;
3425 int ret;
3426
3427 spin_lock_irqsave(&domain->lock, flags);
3428 ret = __amd_iommu_flush_tlb(domain, pasid);
3429 spin_unlock_irqrestore(&domain->lock, flags);
3430
3431 return ret;
3432}
3433EXPORT_SYMBOL(amd_iommu_flush_tlb);
3434
Joerg Roedelb16137b2011-11-21 16:50:23 +01003435static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3436{
3437 int index;
3438 u64 *pte;
3439
3440 while (true) {
3441
3442 index = (pasid >> (9 * level)) & 0x1ff;
3443 pte = &root[index];
3444
3445 if (level == 0)
3446 break;
3447
3448 if (!(*pte & GCR3_VALID)) {
3449 if (!alloc)
3450 return NULL;
3451
3452 root = (void *)get_zeroed_page(GFP_ATOMIC);
3453 if (root == NULL)
3454 return NULL;
3455
3456 *pte = __pa(root) | GCR3_VALID;
3457 }
3458
3459 root = __va(*pte & PAGE_MASK);
3460
3461 level -= 1;
3462 }
3463
3464 return pte;
3465}
3466
3467static int __set_gcr3(struct protection_domain *domain, int pasid,
3468 unsigned long cr3)
3469{
3470 u64 *pte;
3471
3472 if (domain->mode != PAGE_MODE_NONE)
3473 return -EINVAL;
3474
3475 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3476 if (pte == NULL)
3477 return -ENOMEM;
3478
3479 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3480
3481 return __amd_iommu_flush_tlb(domain, pasid);
3482}
3483
3484static int __clear_gcr3(struct protection_domain *domain, int pasid)
3485{
3486 u64 *pte;
3487
3488 if (domain->mode != PAGE_MODE_NONE)
3489 return -EINVAL;
3490
3491 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3492 if (pte == NULL)
3493 return 0;
3494
3495 *pte = 0;
3496
3497 return __amd_iommu_flush_tlb(domain, pasid);
3498}
3499
3500int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3501 unsigned long cr3)
3502{
3503 struct protection_domain *domain = dom->priv;
3504 unsigned long flags;
3505 int ret;
3506
3507 spin_lock_irqsave(&domain->lock, flags);
3508 ret = __set_gcr3(domain, pasid, cr3);
3509 spin_unlock_irqrestore(&domain->lock, flags);
3510
3511 return ret;
3512}
3513EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3514
3515int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3516{
3517 struct protection_domain *domain = dom->priv;
3518 unsigned long flags;
3519 int ret;
3520
3521 spin_lock_irqsave(&domain->lock, flags);
3522 ret = __clear_gcr3(domain, pasid);
3523 spin_unlock_irqrestore(&domain->lock, flags);
3524
3525 return ret;
3526}
3527EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
Joerg Roedelc99afa22011-11-21 18:19:25 +01003528
3529int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3530 int status, int tag)
3531{
3532 struct iommu_dev_data *dev_data;
3533 struct amd_iommu *iommu;
3534 struct iommu_cmd cmd;
3535
Joerg Roedel399be2f2011-12-01 16:53:47 +01003536 INC_STATS_COUNTER(complete_ppr);
3537
Joerg Roedelc99afa22011-11-21 18:19:25 +01003538 dev_data = get_dev_data(&pdev->dev);
3539 iommu = amd_iommu_rlookup_table[dev_data->devid];
3540
3541 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3542 tag, dev_data->pri_tlp);
3543
3544 return iommu_queue_command(iommu, &cmd);
3545}
3546EXPORT_SYMBOL(amd_iommu_complete_ppr);
Joerg Roedelf3572db2011-11-23 12:36:25 +01003547
3548struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3549{
3550 struct protection_domain *domain;
3551
3552 domain = get_domain(&pdev->dev);
3553 if (IS_ERR(domain))
3554 return NULL;
3555
3556 /* Only return IOMMUv2 domains */
3557 if (!(domain->flags & PD_IOMMUV2_MASK))
3558 return NULL;
3559
3560 return domain->iommu_domain;
3561}
3562EXPORT_SYMBOL(amd_iommu_get_v2_domain);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01003563
3564void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3565{
3566 struct iommu_dev_data *dev_data;
3567
3568 if (!amd_iommu_v2_supported())
3569 return;
3570
3571 dev_data = get_dev_data(&pdev->dev);
3572 dev_data->errata |= (1 << erratum);
3573}
3574EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
Joerg Roedel52efdb82011-12-07 12:01:36 +01003575
3576int amd_iommu_device_info(struct pci_dev *pdev,
3577 struct amd_iommu_device_info *info)
3578{
3579 int max_pasids;
3580 int pos;
3581
3582 if (pdev == NULL || info == NULL)
3583 return -EINVAL;
3584
3585 if (!amd_iommu_v2_supported())
3586 return -EINVAL;
3587
3588 memset(info, 0, sizeof(*info));
3589
3590 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3591 if (pos)
3592 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3593
3594 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3595 if (pos)
3596 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3597
3598 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3599 if (pos) {
3600 int features;
3601
3602 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3603 max_pasids = min(max_pasids, (1 << 20));
3604
3605 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3606 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3607
3608 features = pci_pasid_features(pdev);
3609 if (features & PCI_PASID_CAP_EXEC)
3610 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3611 if (features & PCI_PASID_CAP_PRIV)
3612 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3613 }
3614
3615 return 0;
3616}
3617EXPORT_SYMBOL(amd_iommu_device_info);