blob: 64f0f697c958ad399317fe7cc628bf93d9f73018 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
8 *
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries.
12 *
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 *
33 * Changelog:
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * irq mask updated
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * open.
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * the tx length.
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * on close.
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities.
Manfred Spraul22c6d142005-04-19 21:17:09 +020084 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
Manfred Spraul8f767fc2005-06-18 16:27:19 +020085 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
Manfred Spraulf49d16e2005-06-26 11:36:52 +020087 * 0.35: 26 Jun 2005: Support for MCP55 added.
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 *
89 * Known bugs:
90 * We suspect that on some hardware no TX done interrupts are generated.
91 * This means recovery from netif_stop_queue only happens if the hw timer
92 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
93 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
94 * If your hardware reliably generates tx done interrupts, then you can remove
95 * DEV_NEED_TIMERIRQ from the driver_data flags.
96 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
97 * superfluous timer interrupts from the nic.
98 */
Manfred Spraulf49d16e2005-06-26 11:36:52 +020099#define FORCEDETH_VERSION "0.35"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100#define DRV_NAME "forcedeth"
101
102#include <linux/module.h>
103#include <linux/types.h>
104#include <linux/pci.h>
105#include <linux/interrupt.h>
106#include <linux/netdevice.h>
107#include <linux/etherdevice.h>
108#include <linux/delay.h>
109#include <linux/spinlock.h>
110#include <linux/ethtool.h>
111#include <linux/timer.h>
112#include <linux/skbuff.h>
113#include <linux/mii.h>
114#include <linux/random.h>
115#include <linux/init.h>
Manfred Spraul22c6d142005-04-19 21:17:09 +0200116#include <linux/if_vlan.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
118#include <asm/irq.h>
119#include <asm/io.h>
120#include <asm/uaccess.h>
121#include <asm/system.h>
122
123#if 0
124#define dprintk printk
125#else
126#define dprintk(x...) do { } while (0)
127#endif
128
129
130/*
131 * Hardware access:
132 */
133
134#define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
135#define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
136#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
137#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
138#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
139
140enum {
141 NvRegIrqStatus = 0x000,
142#define NVREG_IRQSTAT_MIIEVENT 0x040
143#define NVREG_IRQSTAT_MASK 0x1ff
144 NvRegIrqMask = 0x004,
145#define NVREG_IRQ_RX_ERROR 0x0001
146#define NVREG_IRQ_RX 0x0002
147#define NVREG_IRQ_RX_NOBUF 0x0004
148#define NVREG_IRQ_TX_ERR 0x0008
149#define NVREG_IRQ_TX2 0x0010
150#define NVREG_IRQ_TIMER 0x0020
151#define NVREG_IRQ_LINK 0x0040
152#define NVREG_IRQ_TX1 0x0100
153#define NVREG_IRQMASK_WANTED_1 0x005f
154#define NVREG_IRQMASK_WANTED_2 0x0147
155#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
156
157 NvRegUnknownSetupReg6 = 0x008,
158#define NVREG_UNKSETUP6_VAL 3
159
160/*
161 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
162 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
163 */
164 NvRegPollingInterval = 0x00c,
165#define NVREG_POLL_DEFAULT 970
166 NvRegMisc1 = 0x080,
167#define NVREG_MISC1_HD 0x02
168#define NVREG_MISC1_FORCE 0x3b0f3c
169
170 NvRegTransmitterControl = 0x084,
171#define NVREG_XMITCTL_START 0x01
172 NvRegTransmitterStatus = 0x088,
173#define NVREG_XMITSTAT_BUSY 0x01
174
175 NvRegPacketFilterFlags = 0x8c,
176#define NVREG_PFF_ALWAYS 0x7F0008
177#define NVREG_PFF_PROMISC 0x80
178#define NVREG_PFF_MYADDR 0x20
179
180 NvRegOffloadConfig = 0x90,
181#define NVREG_OFFLOAD_HOMEPHY 0x601
182#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
183 NvRegReceiverControl = 0x094,
184#define NVREG_RCVCTL_START 0x01
185 NvRegReceiverStatus = 0x98,
186#define NVREG_RCVSTAT_BUSY 0x01
187
188 NvRegRandomSeed = 0x9c,
189#define NVREG_RNDSEED_MASK 0x00ff
190#define NVREG_RNDSEED_FORCE 0x7f00
191#define NVREG_RNDSEED_FORCE2 0x2d00
192#define NVREG_RNDSEED_FORCE3 0x7400
193
194 NvRegUnknownSetupReg1 = 0xA0,
195#define NVREG_UNKSETUP1_VAL 0x16070f
196 NvRegUnknownSetupReg2 = 0xA4,
197#define NVREG_UNKSETUP2_VAL 0x16
198 NvRegMacAddrA = 0xA8,
199 NvRegMacAddrB = 0xAC,
200 NvRegMulticastAddrA = 0xB0,
201#define NVREG_MCASTADDRA_FORCE 0x01
202 NvRegMulticastAddrB = 0xB4,
203 NvRegMulticastMaskA = 0xB8,
204 NvRegMulticastMaskB = 0xBC,
205
206 NvRegPhyInterface = 0xC0,
207#define PHY_RGMII 0x10000000
208
209 NvRegTxRingPhysAddr = 0x100,
210 NvRegRxRingPhysAddr = 0x104,
211 NvRegRingSizes = 0x108,
212#define NVREG_RINGSZ_TXSHIFT 0
213#define NVREG_RINGSZ_RXSHIFT 16
214 NvRegUnknownTransmitterReg = 0x10c,
215 NvRegLinkSpeed = 0x110,
216#define NVREG_LINKSPEED_FORCE 0x10000
217#define NVREG_LINKSPEED_10 1000
218#define NVREG_LINKSPEED_100 100
219#define NVREG_LINKSPEED_1000 50
220#define NVREG_LINKSPEED_MASK (0xFFF)
221 NvRegUnknownSetupReg5 = 0x130,
222#define NVREG_UNKSETUP5_BIT31 (1<<31)
223 NvRegUnknownSetupReg3 = 0x13c,
224#define NVREG_UNKSETUP3_VAL1 0x200010
225 NvRegTxRxControl = 0x144,
226#define NVREG_TXRXCTL_KICK 0x0001
227#define NVREG_TXRXCTL_BIT1 0x0002
228#define NVREG_TXRXCTL_BIT2 0x0004
229#define NVREG_TXRXCTL_IDLE 0x0008
230#define NVREG_TXRXCTL_RESET 0x0010
231#define NVREG_TXRXCTL_RXCHECK 0x0400
232 NvRegMIIStatus = 0x180,
233#define NVREG_MIISTAT_ERROR 0x0001
234#define NVREG_MIISTAT_LINKCHANGE 0x0008
235#define NVREG_MIISTAT_MASK 0x000f
236#define NVREG_MIISTAT_MASK2 0x000f
237 NvRegUnknownSetupReg4 = 0x184,
238#define NVREG_UNKSETUP4_VAL 8
239
240 NvRegAdapterControl = 0x188,
241#define NVREG_ADAPTCTL_START 0x02
242#define NVREG_ADAPTCTL_LINKUP 0x04
243#define NVREG_ADAPTCTL_PHYVALID 0x40000
244#define NVREG_ADAPTCTL_RUNNING 0x100000
245#define NVREG_ADAPTCTL_PHYSHIFT 24
246 NvRegMIISpeed = 0x18c,
247#define NVREG_MIISPEED_BIT8 (1<<8)
248#define NVREG_MIIDELAY 5
249 NvRegMIIControl = 0x190,
250#define NVREG_MIICTL_INUSE 0x08000
251#define NVREG_MIICTL_WRITE 0x00400
252#define NVREG_MIICTL_ADDRSHIFT 5
253 NvRegMIIData = 0x194,
254 NvRegWakeUpFlags = 0x200,
255#define NVREG_WAKEUPFLAGS_VAL 0x7770
256#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
257#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
258#define NVREG_WAKEUPFLAGS_D3SHIFT 12
259#define NVREG_WAKEUPFLAGS_D2SHIFT 8
260#define NVREG_WAKEUPFLAGS_D1SHIFT 4
261#define NVREG_WAKEUPFLAGS_D0SHIFT 0
262#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
263#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
264#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
265#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
266
267 NvRegPatternCRC = 0x204,
268 NvRegPatternMask = 0x208,
269 NvRegPowerCap = 0x268,
270#define NVREG_POWERCAP_D3SUPP (1<<30)
271#define NVREG_POWERCAP_D2SUPP (1<<26)
272#define NVREG_POWERCAP_D1SUPP (1<<25)
273 NvRegPowerState = 0x26c,
274#define NVREG_POWERSTATE_POWEREDUP 0x8000
275#define NVREG_POWERSTATE_VALID 0x0100
276#define NVREG_POWERSTATE_MASK 0x0003
277#define NVREG_POWERSTATE_D0 0x0000
278#define NVREG_POWERSTATE_D1 0x0001
279#define NVREG_POWERSTATE_D2 0x0002
280#define NVREG_POWERSTATE_D3 0x0003
281};
282
283/* Big endian: should work, but is untested */
284struct ring_desc {
285 u32 PacketBuffer;
286 u32 FlagLen;
287};
288
289#define FLAG_MASK_V1 0xffff0000
290#define FLAG_MASK_V2 0xffffc000
291#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
292#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
293
294#define NV_TX_LASTPACKET (1<<16)
295#define NV_TX_RETRYERROR (1<<19)
296#define NV_TX_LASTPACKET1 (1<<24)
297#define NV_TX_DEFERRED (1<<26)
298#define NV_TX_CARRIERLOST (1<<27)
299#define NV_TX_LATECOLLISION (1<<28)
300#define NV_TX_UNDERFLOW (1<<29)
301#define NV_TX_ERROR (1<<30)
302#define NV_TX_VALID (1<<31)
303
304#define NV_TX2_LASTPACKET (1<<29)
305#define NV_TX2_RETRYERROR (1<<18)
306#define NV_TX2_LASTPACKET1 (1<<23)
307#define NV_TX2_DEFERRED (1<<25)
308#define NV_TX2_CARRIERLOST (1<<26)
309#define NV_TX2_LATECOLLISION (1<<27)
310#define NV_TX2_UNDERFLOW (1<<28)
311/* error and valid are the same for both */
312#define NV_TX2_ERROR (1<<30)
313#define NV_TX2_VALID (1<<31)
314
315#define NV_RX_DESCRIPTORVALID (1<<16)
316#define NV_RX_MISSEDFRAME (1<<17)
317#define NV_RX_SUBSTRACT1 (1<<18)
318#define NV_RX_ERROR1 (1<<23)
319#define NV_RX_ERROR2 (1<<24)
320#define NV_RX_ERROR3 (1<<25)
321#define NV_RX_ERROR4 (1<<26)
322#define NV_RX_CRCERR (1<<27)
323#define NV_RX_OVERFLOW (1<<28)
324#define NV_RX_FRAMINGERR (1<<29)
325#define NV_RX_ERROR (1<<30)
326#define NV_RX_AVAIL (1<<31)
327
328#define NV_RX2_CHECKSUMMASK (0x1C000000)
329#define NV_RX2_CHECKSUMOK1 (0x10000000)
330#define NV_RX2_CHECKSUMOK2 (0x14000000)
331#define NV_RX2_CHECKSUMOK3 (0x18000000)
332#define NV_RX2_DESCRIPTORVALID (1<<29)
333#define NV_RX2_SUBSTRACT1 (1<<25)
334#define NV_RX2_ERROR1 (1<<18)
335#define NV_RX2_ERROR2 (1<<19)
336#define NV_RX2_ERROR3 (1<<20)
337#define NV_RX2_ERROR4 (1<<21)
338#define NV_RX2_CRCERR (1<<22)
339#define NV_RX2_OVERFLOW (1<<23)
340#define NV_RX2_FRAMINGERR (1<<24)
341/* error and avail are the same for both */
342#define NV_RX2_ERROR (1<<30)
343#define NV_RX2_AVAIL (1<<31)
344
345/* Miscelaneous hardware related defines: */
346#define NV_PCI_REGSZ 0x270
347
348/* various timeout delays: all in usec */
349#define NV_TXRX_RESET_DELAY 4
350#define NV_TXSTOP_DELAY1 10
351#define NV_TXSTOP_DELAY1MAX 500000
352#define NV_TXSTOP_DELAY2 100
353#define NV_RXSTOP_DELAY1 10
354#define NV_RXSTOP_DELAY1MAX 500000
355#define NV_RXSTOP_DELAY2 100
356#define NV_SETUP5_DELAY 5
357#define NV_SETUP5_DELAYMAX 50000
358#define NV_POWERUP_DELAY 5
359#define NV_POWERUP_DELAYMAX 5000
360#define NV_MIIBUSY_DELAY 50
361#define NV_MIIPHY_DELAY 10
362#define NV_MIIPHY_DELAYMAX 10000
363
364#define NV_WAKEUPPATTERNS 5
365#define NV_WAKEUPMASKENTRIES 4
366
367/* General driver defaults */
368#define NV_WATCHDOG_TIMEO (5*HZ)
369
370#define RX_RING 128
371#define TX_RING 64
372/*
373 * If your nic mysteriously hangs then try to reduce the limits
374 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
375 * last valid ring entry. But this would be impossible to
376 * implement - probably a disassembly error.
377 */
378#define TX_LIMIT_STOP 63
379#define TX_LIMIT_START 62
380
381/* rx/tx mac addr + type + vlan + align + slack*/
382#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
383/* even more slack */
384#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
385
386#define OOM_REFILL (1+HZ/20)
387#define POLL_WAIT (1+HZ/100)
388#define LINK_TIMEOUT (3*HZ)
389
390/*
391 * desc_ver values:
392 * This field has two purposes:
393 * - Newer nics uses a different ring layout. The layout is selected by
394 * comparing np->desc_ver with DESC_VER_xy.
395 * - It contains bits that are forced on when writing to NvRegTxRxControl.
396 */
397#define DESC_VER_1 0x0
398#define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
399
400/* PHY defines */
401#define PHY_OUI_MARVELL 0x5043
402#define PHY_OUI_CICADA 0x03f1
403#define PHYID1_OUI_MASK 0x03ff
404#define PHYID1_OUI_SHFT 6
405#define PHYID2_OUI_MASK 0xfc00
406#define PHYID2_OUI_SHFT 10
407#define PHY_INIT1 0x0f000
408#define PHY_INIT2 0x0e00
409#define PHY_INIT3 0x01000
410#define PHY_INIT4 0x0200
411#define PHY_INIT5 0x0004
412#define PHY_INIT6 0x02000
413#define PHY_GIGABIT 0x0100
414
415#define PHY_TIMEOUT 0x1
416#define PHY_ERROR 0x2
417
418#define PHY_100 0x1
419#define PHY_1000 0x2
420#define PHY_HALF 0x100
421
422/* FIXME: MII defines that should be added to <linux/mii.h> */
423#define MII_1000BT_CR 0x09
424#define MII_1000BT_SR 0x0a
425#define ADVERTISE_1000FULL 0x0200
426#define ADVERTISE_1000HALF 0x0100
427#define LPA_1000FULL 0x0800
428#define LPA_1000HALF 0x0400
429
430
431/*
432 * SMP locking:
433 * All hardware access under dev->priv->lock, except the performance
434 * critical parts:
435 * - rx is (pseudo-) lockless: it relies on the single-threading provided
436 * by the arch code for interrupts.
437 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
438 * needs dev->priv->lock :-(
439 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
440 */
441
442/* in dev: base, irq */
443struct fe_priv {
444 spinlock_t lock;
445
446 /* General data:
447 * Locking: spin_lock(&np->lock); */
448 struct net_device_stats stats;
449 int in_shutdown;
450 u32 linkspeed;
451 int duplex;
452 int autoneg;
453 int fixed_mode;
454 int phyaddr;
455 int wolenabled;
456 unsigned int phy_oui;
457 u16 gigabit;
458
459 /* General data: RO fields */
460 dma_addr_t ring_addr;
461 struct pci_dev *pci_dev;
462 u32 orig_mac[2];
463 u32 irqmask;
464 u32 desc_ver;
465
466 void __iomem *base;
467
468 /* rx specific fields.
469 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
470 */
471 struct ring_desc *rx_ring;
472 unsigned int cur_rx, refill_rx;
473 struct sk_buff *rx_skbuff[RX_RING];
474 dma_addr_t rx_dma[RX_RING];
475 unsigned int rx_buf_sz;
476 struct timer_list oom_kick;
477 struct timer_list nic_poll;
478
479 /* media detection workaround.
480 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
481 */
482 int need_linktimer;
483 unsigned long link_timeout;
484 /*
485 * tx specific fields.
486 */
487 struct ring_desc *tx_ring;
488 unsigned int next_tx, nic_tx;
489 struct sk_buff *tx_skbuff[TX_RING];
490 dma_addr_t tx_dma[TX_RING];
491 u32 tx_flags;
492};
493
494/*
495 * Maximum number of loops until we assume that a bit in the irq mask
496 * is stuck. Overridable with module param.
497 */
498static int max_interrupt_work = 5;
499
500static inline struct fe_priv *get_nvpriv(struct net_device *dev)
501{
502 return netdev_priv(dev);
503}
504
505static inline u8 __iomem *get_hwbase(struct net_device *dev)
506{
507 return get_nvpriv(dev)->base;
508}
509
510static inline void pci_push(u8 __iomem *base)
511{
512 /* force out pending posted writes */
513 readl(base);
514}
515
516static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
517{
518 return le32_to_cpu(prd->FlagLen)
519 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
520}
521
522static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
523 int delay, int delaymax, const char *msg)
524{
525 u8 __iomem *base = get_hwbase(dev);
526
527 pci_push(base);
528 do {
529 udelay(delay);
530 delaymax -= delay;
531 if (delaymax < 0) {
532 if (msg)
533 printk(msg);
534 return 1;
535 }
536 } while ((readl(base + offset) & mask) != target);
537 return 0;
538}
539
540#define MII_READ (-1)
541/* mii_rw: read/write a register on the PHY.
542 *
543 * Caller must guarantee serialization
544 */
545static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
546{
547 u8 __iomem *base = get_hwbase(dev);
548 u32 reg;
549 int retval;
550
551 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
552
553 reg = readl(base + NvRegMIIControl);
554 if (reg & NVREG_MIICTL_INUSE) {
555 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
556 udelay(NV_MIIBUSY_DELAY);
557 }
558
559 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
560 if (value != MII_READ) {
561 writel(value, base + NvRegMIIData);
562 reg |= NVREG_MIICTL_WRITE;
563 }
564 writel(reg, base + NvRegMIIControl);
565
566 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
567 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
568 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
569 dev->name, miireg, addr);
570 retval = -1;
571 } else if (value != MII_READ) {
572 /* it was a write operation - fewer failures are detectable */
573 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
574 dev->name, value, miireg, addr);
575 retval = 0;
576 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
577 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
578 dev->name, miireg, addr);
579 retval = -1;
580 } else {
581 retval = readl(base + NvRegMIIData);
582 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
583 dev->name, miireg, addr, retval);
584 }
585
586 return retval;
587}
588
589static int phy_reset(struct net_device *dev)
590{
591 struct fe_priv *np = get_nvpriv(dev);
592 u32 miicontrol;
593 unsigned int tries = 0;
594
595 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
596 miicontrol |= BMCR_RESET;
597 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
598 return -1;
599 }
600
601 /* wait for 500ms */
602 msleep(500);
603
604 /* must wait till reset is deasserted */
605 while (miicontrol & BMCR_RESET) {
606 msleep(10);
607 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
608 /* FIXME: 100 tries seem excessive */
609 if (tries++ > 100)
610 return -1;
611 }
612 return 0;
613}
614
615static int phy_init(struct net_device *dev)
616{
617 struct fe_priv *np = get_nvpriv(dev);
618 u8 __iomem *base = get_hwbase(dev);
619 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
620
621 /* set advertise register */
622 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
623 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
624 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
625 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
626 return PHY_ERROR;
627 }
628
629 /* get phy interface type */
630 phyinterface = readl(base + NvRegPhyInterface);
631
632 /* see if gigabit phy */
633 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
634 if (mii_status & PHY_GIGABIT) {
635 np->gigabit = PHY_GIGABIT;
636 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
637 mii_control_1000 &= ~ADVERTISE_1000HALF;
638 if (phyinterface & PHY_RGMII)
639 mii_control_1000 |= ADVERTISE_1000FULL;
640 else
641 mii_control_1000 &= ~ADVERTISE_1000FULL;
642
643 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
644 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
645 return PHY_ERROR;
646 }
647 }
648 else
649 np->gigabit = 0;
650
651 /* reset the phy */
652 if (phy_reset(dev)) {
653 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
654 return PHY_ERROR;
655 }
656
657 /* phy vendor specific configuration */
658 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
659 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
660 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
661 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
662 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
663 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
664 return PHY_ERROR;
665 }
666 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
667 phy_reserved |= PHY_INIT5;
668 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
669 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
670 return PHY_ERROR;
671 }
672 }
673 if (np->phy_oui == PHY_OUI_CICADA) {
674 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
675 phy_reserved |= PHY_INIT6;
676 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
677 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
678 return PHY_ERROR;
679 }
680 }
681
682 /* restart auto negotiation */
683 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
684 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
685 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
686 return PHY_ERROR;
687 }
688
689 return 0;
690}
691
692static void nv_start_rx(struct net_device *dev)
693{
694 struct fe_priv *np = get_nvpriv(dev);
695 u8 __iomem *base = get_hwbase(dev);
696
697 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
698 /* Already running? Stop it. */
699 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
700 writel(0, base + NvRegReceiverControl);
701 pci_push(base);
702 }
703 writel(np->linkspeed, base + NvRegLinkSpeed);
704 pci_push(base);
705 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
706 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
707 dev->name, np->duplex, np->linkspeed);
708 pci_push(base);
709}
710
711static void nv_stop_rx(struct net_device *dev)
712{
713 u8 __iomem *base = get_hwbase(dev);
714
715 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
716 writel(0, base + NvRegReceiverControl);
717 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
718 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
719 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
720
721 udelay(NV_RXSTOP_DELAY2);
722 writel(0, base + NvRegLinkSpeed);
723}
724
725static void nv_start_tx(struct net_device *dev)
726{
727 u8 __iomem *base = get_hwbase(dev);
728
729 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
730 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
731 pci_push(base);
732}
733
734static void nv_stop_tx(struct net_device *dev)
735{
736 u8 __iomem *base = get_hwbase(dev);
737
738 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
739 writel(0, base + NvRegTransmitterControl);
740 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
741 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
742 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
743
744 udelay(NV_TXSTOP_DELAY2);
745 writel(0, base + NvRegUnknownTransmitterReg);
746}
747
748static void nv_txrx_reset(struct net_device *dev)
749{
750 struct fe_priv *np = get_nvpriv(dev);
751 u8 __iomem *base = get_hwbase(dev);
752
753 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
754 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
755 pci_push(base);
756 udelay(NV_TXRX_RESET_DELAY);
757 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
758 pci_push(base);
759}
760
761/*
762 * nv_get_stats: dev->get_stats function
763 * Get latest stats value from the nic.
764 * Called with read_lock(&dev_base_lock) held for read -
765 * only synchronized against unregister_netdevice.
766 */
767static struct net_device_stats *nv_get_stats(struct net_device *dev)
768{
769 struct fe_priv *np = get_nvpriv(dev);
770
771 /* It seems that the nic always generates interrupts and doesn't
772 * accumulate errors internally. Thus the current values in np->stats
773 * are already up to date.
774 */
775 return &np->stats;
776}
777
778/*
779 * nv_alloc_rx: fill rx ring entries.
780 * Return 1 if the allocations for the skbs failed and the
781 * rx engine is without Available descriptors
782 */
783static int nv_alloc_rx(struct net_device *dev)
784{
785 struct fe_priv *np = get_nvpriv(dev);
786 unsigned int refill_rx = np->refill_rx;
787 int nr;
788
789 while (np->cur_rx != refill_rx) {
790 struct sk_buff *skb;
791
792 nr = refill_rx % RX_RING;
793 if (np->rx_skbuff[nr] == NULL) {
794
795 skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
796 if (!skb)
797 break;
798
799 skb->dev = dev;
800 np->rx_skbuff[nr] = skb;
801 } else {
802 skb = np->rx_skbuff[nr];
803 }
804 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
805 PCI_DMA_FROMDEVICE);
806 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
807 wmb();
808 np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
809 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
810 dev->name, refill_rx);
811 refill_rx++;
812 }
813 np->refill_rx = refill_rx;
814 if (np->cur_rx - refill_rx == RX_RING)
815 return 1;
816 return 0;
817}
818
819static void nv_do_rx_refill(unsigned long data)
820{
821 struct net_device *dev = (struct net_device *) data;
822 struct fe_priv *np = get_nvpriv(dev);
823
824 disable_irq(dev->irq);
825 if (nv_alloc_rx(dev)) {
826 spin_lock(&np->lock);
827 if (!np->in_shutdown)
828 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
829 spin_unlock(&np->lock);
830 }
831 enable_irq(dev->irq);
832}
833
834static int nv_init_ring(struct net_device *dev)
835{
836 struct fe_priv *np = get_nvpriv(dev);
837 int i;
838
839 np->next_tx = np->nic_tx = 0;
840 for (i = 0; i < TX_RING; i++)
841 np->tx_ring[i].FlagLen = 0;
842
843 np->cur_rx = RX_RING;
844 np->refill_rx = 0;
845 for (i = 0; i < RX_RING; i++)
846 np->rx_ring[i].FlagLen = 0;
847 return nv_alloc_rx(dev);
848}
849
850static void nv_drain_tx(struct net_device *dev)
851{
852 struct fe_priv *np = get_nvpriv(dev);
853 int i;
854 for (i = 0; i < TX_RING; i++) {
855 np->tx_ring[i].FlagLen = 0;
856 if (np->tx_skbuff[i]) {
857 pci_unmap_single(np->pci_dev, np->tx_dma[i],
858 np->tx_skbuff[i]->len,
859 PCI_DMA_TODEVICE);
860 dev_kfree_skb(np->tx_skbuff[i]);
861 np->tx_skbuff[i] = NULL;
862 np->stats.tx_dropped++;
863 }
864 }
865}
866
867static void nv_drain_rx(struct net_device *dev)
868{
869 struct fe_priv *np = get_nvpriv(dev);
870 int i;
871 for (i = 0; i < RX_RING; i++) {
872 np->rx_ring[i].FlagLen = 0;
873 wmb();
874 if (np->rx_skbuff[i]) {
875 pci_unmap_single(np->pci_dev, np->rx_dma[i],
876 np->rx_skbuff[i]->len,
877 PCI_DMA_FROMDEVICE);
878 dev_kfree_skb(np->rx_skbuff[i]);
879 np->rx_skbuff[i] = NULL;
880 }
881 }
882}
883
884static void drain_ring(struct net_device *dev)
885{
886 nv_drain_tx(dev);
887 nv_drain_rx(dev);
888}
889
890/*
891 * nv_start_xmit: dev->hard_start_xmit function
892 * Called with dev->xmit_lock held.
893 */
894static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
895{
896 struct fe_priv *np = get_nvpriv(dev);
897 int nr = np->next_tx % TX_RING;
898
899 np->tx_skbuff[nr] = skb;
900 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
901 PCI_DMA_TODEVICE);
902
903 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
904
905 spin_lock_irq(&np->lock);
906 wmb();
907 np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
908 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
909 dev->name, np->next_tx);
910 {
911 int j;
912 for (j=0; j<64; j++) {
913 if ((j%16) == 0)
914 dprintk("\n%03x:", j);
915 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
916 }
917 dprintk("\n");
918 }
919
920 np->next_tx++;
921
922 dev->trans_start = jiffies;
923 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
924 netif_stop_queue(dev);
925 spin_unlock_irq(&np->lock);
926 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
927 pci_push(get_hwbase(dev));
928 return 0;
929}
930
931/*
932 * nv_tx_done: check for completed packets, release the skbs.
933 *
934 * Caller must own np->lock.
935 */
936static void nv_tx_done(struct net_device *dev)
937{
938 struct fe_priv *np = get_nvpriv(dev);
939 u32 Flags;
940 int i;
941
942 while (np->nic_tx != np->next_tx) {
943 i = np->nic_tx % TX_RING;
944
945 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
946
947 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
948 dev->name, np->nic_tx, Flags);
949 if (Flags & NV_TX_VALID)
950 break;
951 if (np->desc_ver == DESC_VER_1) {
952 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
953 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
954 if (Flags & NV_TX_UNDERFLOW)
955 np->stats.tx_fifo_errors++;
956 if (Flags & NV_TX_CARRIERLOST)
957 np->stats.tx_carrier_errors++;
958 np->stats.tx_errors++;
959 } else {
960 np->stats.tx_packets++;
961 np->stats.tx_bytes += np->tx_skbuff[i]->len;
962 }
963 } else {
964 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
965 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
966 if (Flags & NV_TX2_UNDERFLOW)
967 np->stats.tx_fifo_errors++;
968 if (Flags & NV_TX2_CARRIERLOST)
969 np->stats.tx_carrier_errors++;
970 np->stats.tx_errors++;
971 } else {
972 np->stats.tx_packets++;
973 np->stats.tx_bytes += np->tx_skbuff[i]->len;
974 }
975 }
976 pci_unmap_single(np->pci_dev, np->tx_dma[i],
977 np->tx_skbuff[i]->len,
978 PCI_DMA_TODEVICE);
979 dev_kfree_skb_irq(np->tx_skbuff[i]);
980 np->tx_skbuff[i] = NULL;
981 np->nic_tx++;
982 }
983 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
984 netif_wake_queue(dev);
985}
986
987/*
988 * nv_tx_timeout: dev->tx_timeout function
989 * Called with dev->xmit_lock held.
990 */
991static void nv_tx_timeout(struct net_device *dev)
992{
993 struct fe_priv *np = get_nvpriv(dev);
994 u8 __iomem *base = get_hwbase(dev);
995
996 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
997 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
998
999 spin_lock_irq(&np->lock);
1000
1001 /* 1) stop tx engine */
1002 nv_stop_tx(dev);
1003
1004 /* 2) check that the packets were not sent already: */
1005 nv_tx_done(dev);
1006
1007 /* 3) if there are dead entries: clear everything */
1008 if (np->next_tx != np->nic_tx) {
1009 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1010 nv_drain_tx(dev);
1011 np->next_tx = np->nic_tx = 0;
1012 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1013 netif_wake_queue(dev);
1014 }
1015
1016 /* 4) restart tx engine */
1017 nv_start_tx(dev);
1018 spin_unlock_irq(&np->lock);
1019}
1020
Manfred Spraul22c6d142005-04-19 21:17:09 +02001021/*
1022 * Called when the nic notices a mismatch between the actual data len on the
1023 * wire and the len indicated in the 802 header
1024 */
1025static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1026{
1027 int hdrlen; /* length of the 802 header */
1028 int protolen; /* length as stored in the proto field */
1029
1030 /* 1) calculate len according to header */
1031 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1032 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1033 hdrlen = VLAN_HLEN;
1034 } else {
1035 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1036 hdrlen = ETH_HLEN;
1037 }
1038 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1039 dev->name, datalen, protolen, hdrlen);
1040 if (protolen > ETH_DATA_LEN)
1041 return datalen; /* Value in proto field not a len, no checks possible */
1042
1043 protolen += hdrlen;
1044 /* consistency checks: */
1045 if (datalen > ETH_ZLEN) {
1046 if (datalen >= protolen) {
1047 /* more data on wire than in 802 header, trim of
1048 * additional data.
1049 */
1050 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1051 dev->name, protolen);
1052 return protolen;
1053 } else {
1054 /* less data on wire than mentioned in header.
1055 * Discard the packet.
1056 */
1057 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1058 dev->name);
1059 return -1;
1060 }
1061 } else {
1062 /* short packet. Accept only if 802 values are also short */
1063 if (protolen > ETH_ZLEN) {
1064 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1065 dev->name);
1066 return -1;
1067 }
1068 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1069 dev->name, datalen);
1070 return datalen;
1071 }
1072}
1073
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074static void nv_rx_process(struct net_device *dev)
1075{
1076 struct fe_priv *np = get_nvpriv(dev);
1077 u32 Flags;
1078
1079 for (;;) {
1080 struct sk_buff *skb;
1081 int len;
1082 int i;
1083 if (np->cur_rx - np->refill_rx >= RX_RING)
1084 break; /* we scanned the whole ring - do not continue */
1085
1086 i = np->cur_rx % RX_RING;
1087 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1088 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1089
1090 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1091 dev->name, np->cur_rx, Flags);
1092
1093 if (Flags & NV_RX_AVAIL)
1094 break; /* still owned by hardware, */
1095
1096 /*
1097 * the packet is for us - immediately tear down the pci mapping.
1098 * TODO: check if a prefetch of the first cacheline improves
1099 * the performance.
1100 */
1101 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1102 np->rx_skbuff[i]->len,
1103 PCI_DMA_FROMDEVICE);
1104
1105 {
1106 int j;
1107 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1108 for (j=0; j<64; j++) {
1109 if ((j%16) == 0)
1110 dprintk("\n%03x:", j);
1111 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1112 }
1113 dprintk("\n");
1114 }
1115 /* look at what we actually got: */
1116 if (np->desc_ver == DESC_VER_1) {
1117 if (!(Flags & NV_RX_DESCRIPTORVALID))
1118 goto next_pkt;
1119
1120 if (Flags & NV_RX_MISSEDFRAME) {
1121 np->stats.rx_missed_errors++;
1122 np->stats.rx_errors++;
1123 goto next_pkt;
1124 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001125 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126 np->stats.rx_errors++;
1127 goto next_pkt;
1128 }
1129 if (Flags & NV_RX_CRCERR) {
1130 np->stats.rx_crc_errors++;
1131 np->stats.rx_errors++;
1132 goto next_pkt;
1133 }
1134 if (Flags & NV_RX_OVERFLOW) {
1135 np->stats.rx_over_errors++;
1136 np->stats.rx_errors++;
1137 goto next_pkt;
1138 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001139 if (Flags & NV_RX_ERROR4) {
1140 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1141 if (len < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142 np->stats.rx_errors++;
1143 goto next_pkt;
1144 }
1145 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001146 /* framing errors are soft errors. */
1147 if (Flags & NV_RX_FRAMINGERR) {
1148 if (Flags & NV_RX_SUBSTRACT1) {
1149 len--;
1150 }
1151 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152 } else {
1153 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1154 goto next_pkt;
1155
Manfred Spraul22c6d142005-04-19 21:17:09 +02001156 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 np->stats.rx_errors++;
1158 goto next_pkt;
1159 }
1160 if (Flags & NV_RX2_CRCERR) {
1161 np->stats.rx_crc_errors++;
1162 np->stats.rx_errors++;
1163 goto next_pkt;
1164 }
1165 if (Flags & NV_RX2_OVERFLOW) {
1166 np->stats.rx_over_errors++;
1167 np->stats.rx_errors++;
1168 goto next_pkt;
1169 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001170 if (Flags & NV_RX2_ERROR4) {
1171 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1172 if (len < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 np->stats.rx_errors++;
1174 goto next_pkt;
1175 }
1176 }
Manfred Spraul22c6d142005-04-19 21:17:09 +02001177 /* framing errors are soft errors */
1178 if (Flags & NV_RX2_FRAMINGERR) {
1179 if (Flags & NV_RX2_SUBSTRACT1) {
1180 len--;
1181 }
1182 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 Flags &= NV_RX2_CHECKSUMMASK;
1184 if (Flags == NV_RX2_CHECKSUMOK1 ||
1185 Flags == NV_RX2_CHECKSUMOK2 ||
1186 Flags == NV_RX2_CHECKSUMOK3) {
1187 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1188 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1189 } else {
1190 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1191 }
1192 }
1193 /* got a valid packet - forward it to the network core */
1194 skb = np->rx_skbuff[i];
1195 np->rx_skbuff[i] = NULL;
1196
1197 skb_put(skb, len);
1198 skb->protocol = eth_type_trans(skb, dev);
1199 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1200 dev->name, np->cur_rx, len, skb->protocol);
1201 netif_rx(skb);
1202 dev->last_rx = jiffies;
1203 np->stats.rx_packets++;
1204 np->stats.rx_bytes += len;
1205next_pkt:
1206 np->cur_rx++;
1207 }
1208}
1209
1210/*
1211 * nv_change_mtu: dev->change_mtu function
1212 * Called with dev_base_lock held for read.
1213 */
1214static int nv_change_mtu(struct net_device *dev, int new_mtu)
1215{
1216 if (new_mtu > ETH_DATA_LEN)
1217 return -EINVAL;
1218 dev->mtu = new_mtu;
1219 return 0;
1220}
1221
1222/*
1223 * nv_set_multicast: dev->set_multicast function
1224 * Called with dev->xmit_lock held.
1225 */
1226static void nv_set_multicast(struct net_device *dev)
1227{
1228 struct fe_priv *np = get_nvpriv(dev);
1229 u8 __iomem *base = get_hwbase(dev);
1230 u32 addr[2];
1231 u32 mask[2];
1232 u32 pff;
1233
1234 memset(addr, 0, sizeof(addr));
1235 memset(mask, 0, sizeof(mask));
1236
1237 if (dev->flags & IFF_PROMISC) {
1238 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1239 pff = NVREG_PFF_PROMISC;
1240 } else {
1241 pff = NVREG_PFF_MYADDR;
1242
1243 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1244 u32 alwaysOff[2];
1245 u32 alwaysOn[2];
1246
1247 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1248 if (dev->flags & IFF_ALLMULTI) {
1249 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1250 } else {
1251 struct dev_mc_list *walk;
1252
1253 walk = dev->mc_list;
1254 while (walk != NULL) {
1255 u32 a, b;
1256 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1257 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1258 alwaysOn[0] &= a;
1259 alwaysOff[0] &= ~a;
1260 alwaysOn[1] &= b;
1261 alwaysOff[1] &= ~b;
1262 walk = walk->next;
1263 }
1264 }
1265 addr[0] = alwaysOn[0];
1266 addr[1] = alwaysOn[1];
1267 mask[0] = alwaysOn[0] | alwaysOff[0];
1268 mask[1] = alwaysOn[1] | alwaysOff[1];
1269 }
1270 }
1271 addr[0] |= NVREG_MCASTADDRA_FORCE;
1272 pff |= NVREG_PFF_ALWAYS;
1273 spin_lock_irq(&np->lock);
1274 nv_stop_rx(dev);
1275 writel(addr[0], base + NvRegMulticastAddrA);
1276 writel(addr[1], base + NvRegMulticastAddrB);
1277 writel(mask[0], base + NvRegMulticastMaskA);
1278 writel(mask[1], base + NvRegMulticastMaskB);
1279 writel(pff, base + NvRegPacketFilterFlags);
1280 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1281 dev->name);
1282 nv_start_rx(dev);
1283 spin_unlock_irq(&np->lock);
1284}
1285
1286static int nv_update_linkspeed(struct net_device *dev)
1287{
1288 struct fe_priv *np = get_nvpriv(dev);
1289 u8 __iomem *base = get_hwbase(dev);
1290 int adv, lpa;
1291 int newls = np->linkspeed;
1292 int newdup = np->duplex;
1293 int mii_status;
1294 int retval = 0;
1295 u32 control_1000, status_1000, phyreg;
1296
1297 /* BMSR_LSTATUS is latched, read it twice:
1298 * we want the current value.
1299 */
1300 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1301 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1302
1303 if (!(mii_status & BMSR_LSTATUS)) {
1304 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1305 dev->name);
1306 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1307 newdup = 0;
1308 retval = 0;
1309 goto set_speed;
1310 }
1311
1312 if (np->autoneg == 0) {
1313 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1314 dev->name, np->fixed_mode);
1315 if (np->fixed_mode & LPA_100FULL) {
1316 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1317 newdup = 1;
1318 } else if (np->fixed_mode & LPA_100HALF) {
1319 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1320 newdup = 0;
1321 } else if (np->fixed_mode & LPA_10FULL) {
1322 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1323 newdup = 1;
1324 } else {
1325 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1326 newdup = 0;
1327 }
1328 retval = 1;
1329 goto set_speed;
1330 }
1331 /* check auto negotiation is complete */
1332 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1333 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1334 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1335 newdup = 0;
1336 retval = 0;
1337 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1338 goto set_speed;
1339 }
1340
1341 retval = 1;
1342 if (np->gigabit == PHY_GIGABIT) {
1343 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1344 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1345
1346 if ((control_1000 & ADVERTISE_1000FULL) &&
1347 (status_1000 & LPA_1000FULL)) {
1348 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1349 dev->name);
1350 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1351 newdup = 1;
1352 goto set_speed;
1353 }
1354 }
1355
1356 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1357 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1358 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1359 dev->name, adv, lpa);
1360
1361 /* FIXME: handle parallel detection properly */
1362 lpa = lpa & adv;
1363 if (lpa & LPA_100FULL) {
1364 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1365 newdup = 1;
1366 } else if (lpa & LPA_100HALF) {
1367 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1368 newdup = 0;
1369 } else if (lpa & LPA_10FULL) {
1370 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1371 newdup = 1;
1372 } else if (lpa & LPA_10HALF) {
1373 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1374 newdup = 0;
1375 } else {
1376 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1377 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1378 newdup = 0;
1379 }
1380
1381set_speed:
1382 if (np->duplex == newdup && np->linkspeed == newls)
1383 return retval;
1384
1385 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1386 dev->name, np->linkspeed, np->duplex, newls, newdup);
1387
1388 np->duplex = newdup;
1389 np->linkspeed = newls;
1390
1391 if (np->gigabit == PHY_GIGABIT) {
1392 phyreg = readl(base + NvRegRandomSeed);
1393 phyreg &= ~(0x3FF00);
1394 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1395 phyreg |= NVREG_RNDSEED_FORCE3;
1396 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1397 phyreg |= NVREG_RNDSEED_FORCE2;
1398 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1399 phyreg |= NVREG_RNDSEED_FORCE;
1400 writel(phyreg, base + NvRegRandomSeed);
1401 }
1402
1403 phyreg = readl(base + NvRegPhyInterface);
1404 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1405 if (np->duplex == 0)
1406 phyreg |= PHY_HALF;
1407 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1408 phyreg |= PHY_100;
1409 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1410 phyreg |= PHY_1000;
1411 writel(phyreg, base + NvRegPhyInterface);
1412
1413 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1414 base + NvRegMisc1);
1415 pci_push(base);
1416 writel(np->linkspeed, base + NvRegLinkSpeed);
1417 pci_push(base);
1418
1419 return retval;
1420}
1421
1422static void nv_linkchange(struct net_device *dev)
1423{
1424 if (nv_update_linkspeed(dev)) {
1425 if (netif_carrier_ok(dev)) {
1426 nv_stop_rx(dev);
1427 } else {
1428 netif_carrier_on(dev);
1429 printk(KERN_INFO "%s: link up.\n", dev->name);
1430 }
1431 nv_start_rx(dev);
1432 } else {
1433 if (netif_carrier_ok(dev)) {
1434 netif_carrier_off(dev);
1435 printk(KERN_INFO "%s: link down.\n", dev->name);
1436 nv_stop_rx(dev);
1437 }
1438 }
1439}
1440
1441static void nv_link_irq(struct net_device *dev)
1442{
1443 u8 __iomem *base = get_hwbase(dev);
1444 u32 miistat;
1445
1446 miistat = readl(base + NvRegMIIStatus);
1447 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1448 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1449
1450 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1451 nv_linkchange(dev);
1452 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1453}
1454
1455static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1456{
1457 struct net_device *dev = (struct net_device *) data;
1458 struct fe_priv *np = get_nvpriv(dev);
1459 u8 __iomem *base = get_hwbase(dev);
1460 u32 events;
1461 int i;
1462
1463 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1464
1465 for (i=0; ; i++) {
1466 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1467 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1468 pci_push(base);
1469 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1470 if (!(events & np->irqmask))
1471 break;
1472
1473 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1474 spin_lock(&np->lock);
1475 nv_tx_done(dev);
1476 spin_unlock(&np->lock);
1477 }
1478
1479 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1480 nv_rx_process(dev);
1481 if (nv_alloc_rx(dev)) {
1482 spin_lock(&np->lock);
1483 if (!np->in_shutdown)
1484 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1485 spin_unlock(&np->lock);
1486 }
1487 }
1488
1489 if (events & NVREG_IRQ_LINK) {
1490 spin_lock(&np->lock);
1491 nv_link_irq(dev);
1492 spin_unlock(&np->lock);
1493 }
1494 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1495 spin_lock(&np->lock);
1496 nv_linkchange(dev);
1497 spin_unlock(&np->lock);
1498 np->link_timeout = jiffies + LINK_TIMEOUT;
1499 }
1500 if (events & (NVREG_IRQ_TX_ERR)) {
1501 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1502 dev->name, events);
1503 }
1504 if (events & (NVREG_IRQ_UNKNOWN)) {
1505 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1506 dev->name, events);
1507 }
1508 if (i > max_interrupt_work) {
1509 spin_lock(&np->lock);
1510 /* disable interrupts on the nic */
1511 writel(0, base + NvRegIrqMask);
1512 pci_push(base);
1513
1514 if (!np->in_shutdown)
1515 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1516 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1517 spin_unlock(&np->lock);
1518 break;
1519 }
1520
1521 }
1522 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1523
1524 return IRQ_RETVAL(i);
1525}
1526
1527static void nv_do_nic_poll(unsigned long data)
1528{
1529 struct net_device *dev = (struct net_device *) data;
1530 struct fe_priv *np = get_nvpriv(dev);
1531 u8 __iomem *base = get_hwbase(dev);
1532
1533 disable_irq(dev->irq);
1534 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1535 /*
1536 * reenable interrupts on the nic, we have to do this before calling
1537 * nv_nic_irq because that may decide to do otherwise
1538 */
1539 writel(np->irqmask, base + NvRegIrqMask);
1540 pci_push(base);
1541 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1542 enable_irq(dev->irq);
1543}
1544
Michal Schmidt2918c352005-05-12 19:42:06 -04001545#ifdef CONFIG_NET_POLL_CONTROLLER
1546static void nv_poll_controller(struct net_device *dev)
1547{
1548 nv_do_nic_poll((unsigned long) dev);
1549}
1550#endif
1551
Linus Torvalds1da177e2005-04-16 15:20:36 -07001552static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1553{
1554 struct fe_priv *np = get_nvpriv(dev);
1555 strcpy(info->driver, "forcedeth");
1556 strcpy(info->version, FORCEDETH_VERSION);
1557 strcpy(info->bus_info, pci_name(np->pci_dev));
1558}
1559
1560static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1561{
1562 struct fe_priv *np = get_nvpriv(dev);
1563 wolinfo->supported = WAKE_MAGIC;
1564
1565 spin_lock_irq(&np->lock);
1566 if (np->wolenabled)
1567 wolinfo->wolopts = WAKE_MAGIC;
1568 spin_unlock_irq(&np->lock);
1569}
1570
1571static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1572{
1573 struct fe_priv *np = get_nvpriv(dev);
1574 u8 __iomem *base = get_hwbase(dev);
1575
1576 spin_lock_irq(&np->lock);
1577 if (wolinfo->wolopts == 0) {
1578 writel(0, base + NvRegWakeUpFlags);
1579 np->wolenabled = 0;
1580 }
1581 if (wolinfo->wolopts & WAKE_MAGIC) {
1582 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1583 np->wolenabled = 1;
1584 }
1585 spin_unlock_irq(&np->lock);
1586 return 0;
1587}
1588
1589static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1590{
1591 struct fe_priv *np = netdev_priv(dev);
1592 int adv;
1593
1594 spin_lock_irq(&np->lock);
1595 ecmd->port = PORT_MII;
1596 if (!netif_running(dev)) {
1597 /* We do not track link speed / duplex setting if the
1598 * interface is disabled. Force a link check */
1599 nv_update_linkspeed(dev);
1600 }
1601 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1602 case NVREG_LINKSPEED_10:
1603 ecmd->speed = SPEED_10;
1604 break;
1605 case NVREG_LINKSPEED_100:
1606 ecmd->speed = SPEED_100;
1607 break;
1608 case NVREG_LINKSPEED_1000:
1609 ecmd->speed = SPEED_1000;
1610 break;
1611 }
1612 ecmd->duplex = DUPLEX_HALF;
1613 if (np->duplex)
1614 ecmd->duplex = DUPLEX_FULL;
1615
1616 ecmd->autoneg = np->autoneg;
1617
1618 ecmd->advertising = ADVERTISED_MII;
1619 if (np->autoneg) {
1620 ecmd->advertising |= ADVERTISED_Autoneg;
1621 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1622 } else {
1623 adv = np->fixed_mode;
1624 }
1625 if (adv & ADVERTISE_10HALF)
1626 ecmd->advertising |= ADVERTISED_10baseT_Half;
1627 if (adv & ADVERTISE_10FULL)
1628 ecmd->advertising |= ADVERTISED_10baseT_Full;
1629 if (adv & ADVERTISE_100HALF)
1630 ecmd->advertising |= ADVERTISED_100baseT_Half;
1631 if (adv & ADVERTISE_100FULL)
1632 ecmd->advertising |= ADVERTISED_100baseT_Full;
1633 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1634 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1635 if (adv & ADVERTISE_1000FULL)
1636 ecmd->advertising |= ADVERTISED_1000baseT_Full;
1637 }
1638
1639 ecmd->supported = (SUPPORTED_Autoneg |
1640 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1641 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1642 SUPPORTED_MII);
1643 if (np->gigabit == PHY_GIGABIT)
1644 ecmd->supported |= SUPPORTED_1000baseT_Full;
1645
1646 ecmd->phy_address = np->phyaddr;
1647 ecmd->transceiver = XCVR_EXTERNAL;
1648
1649 /* ignore maxtxpkt, maxrxpkt for now */
1650 spin_unlock_irq(&np->lock);
1651 return 0;
1652}
1653
1654static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1655{
1656 struct fe_priv *np = netdev_priv(dev);
1657
1658 if (ecmd->port != PORT_MII)
1659 return -EINVAL;
1660 if (ecmd->transceiver != XCVR_EXTERNAL)
1661 return -EINVAL;
1662 if (ecmd->phy_address != np->phyaddr) {
1663 /* TODO: support switching between multiple phys. Should be
1664 * trivial, but not enabled due to lack of test hardware. */
1665 return -EINVAL;
1666 }
1667 if (ecmd->autoneg == AUTONEG_ENABLE) {
1668 u32 mask;
1669
1670 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1671 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1672 if (np->gigabit == PHY_GIGABIT)
1673 mask |= ADVERTISED_1000baseT_Full;
1674
1675 if ((ecmd->advertising & mask) == 0)
1676 return -EINVAL;
1677
1678 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1679 /* Note: autonegotiation disable, speed 1000 intentionally
1680 * forbidden - noone should need that. */
1681
1682 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1683 return -EINVAL;
1684 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1685 return -EINVAL;
1686 } else {
1687 return -EINVAL;
1688 }
1689
1690 spin_lock_irq(&np->lock);
1691 if (ecmd->autoneg == AUTONEG_ENABLE) {
1692 int adv, bmcr;
1693
1694 np->autoneg = 1;
1695
1696 /* advertise only what has been requested */
1697 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1698 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1699 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1700 adv |= ADVERTISE_10HALF;
1701 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1702 adv |= ADVERTISE_10FULL;
1703 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1704 adv |= ADVERTISE_100HALF;
1705 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1706 adv |= ADVERTISE_100FULL;
1707 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1708
1709 if (np->gigabit == PHY_GIGABIT) {
1710 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1711 adv &= ~ADVERTISE_1000FULL;
1712 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1713 adv |= ADVERTISE_1000FULL;
1714 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1715 }
1716
1717 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1718 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1719 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1720
1721 } else {
1722 int adv, bmcr;
1723
1724 np->autoneg = 0;
1725
1726 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1727 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1728 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1729 adv |= ADVERTISE_10HALF;
1730 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1731 adv |= ADVERTISE_10FULL;
1732 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1733 adv |= ADVERTISE_100HALF;
1734 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1735 adv |= ADVERTISE_100FULL;
1736 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1737 np->fixed_mode = adv;
1738
1739 if (np->gigabit == PHY_GIGABIT) {
1740 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1741 adv &= ~ADVERTISE_1000FULL;
1742 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1743 }
1744
1745 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1746 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1747 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1748 bmcr |= BMCR_FULLDPLX;
1749 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1750 bmcr |= BMCR_SPEED100;
1751 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1752
1753 if (netif_running(dev)) {
1754 /* Wait a bit and then reconfigure the nic. */
1755 udelay(10);
1756 nv_linkchange(dev);
1757 }
1758 }
1759 spin_unlock_irq(&np->lock);
1760
1761 return 0;
1762}
1763
1764static struct ethtool_ops ops = {
1765 .get_drvinfo = nv_get_drvinfo,
1766 .get_link = ethtool_op_get_link,
1767 .get_wol = nv_get_wol,
1768 .set_wol = nv_set_wol,
1769 .get_settings = nv_get_settings,
1770 .set_settings = nv_set_settings,
1771};
1772
1773static int nv_open(struct net_device *dev)
1774{
1775 struct fe_priv *np = get_nvpriv(dev);
1776 u8 __iomem *base = get_hwbase(dev);
1777 int ret, oom, i;
1778
1779 dprintk(KERN_DEBUG "nv_open: begin\n");
1780
1781 /* 1) erase previous misconfiguration */
1782 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1783 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1784 writel(0, base + NvRegMulticastAddrB);
1785 writel(0, base + NvRegMulticastMaskA);
1786 writel(0, base + NvRegMulticastMaskB);
1787 writel(0, base + NvRegPacketFilterFlags);
1788
1789 writel(0, base + NvRegTransmitterControl);
1790 writel(0, base + NvRegReceiverControl);
1791
1792 writel(0, base + NvRegAdapterControl);
1793
1794 /* 2) initialize descriptor rings */
1795 oom = nv_init_ring(dev);
1796
1797 writel(0, base + NvRegLinkSpeed);
1798 writel(0, base + NvRegUnknownTransmitterReg);
1799 nv_txrx_reset(dev);
1800 writel(0, base + NvRegUnknownSetupReg6);
1801
1802 np->in_shutdown = 0;
1803
1804 /* 3) set mac address */
1805 {
1806 u32 mac[2];
1807
1808 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1809 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1810 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1811
1812 writel(mac[0], base + NvRegMacAddrA);
1813 writel(mac[1], base + NvRegMacAddrB);
1814 }
1815
1816 /* 4) give hw rings */
1817 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1818 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1819 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1820 base + NvRegRingSizes);
1821
1822 /* 5) continue setup */
1823 writel(np->linkspeed, base + NvRegLinkSpeed);
1824 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1825 writel(np->desc_ver, base + NvRegTxRxControl);
1826 pci_push(base);
1827 writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1828 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1829 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1830 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1831
1832 writel(0, base + NvRegUnknownSetupReg4);
1833 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1834 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1835
1836 /* 6) continue setup */
1837 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1838 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1839 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1840 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1841
1842 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1843 get_random_bytes(&i, sizeof(i));
1844 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1845 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1846 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1847 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1848 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1849 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
1850 base + NvRegAdapterControl);
1851 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1852 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1853 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1854
1855 i = readl(base + NvRegPowerState);
1856 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1857 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1858
1859 pci_push(base);
1860 udelay(10);
1861 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1862
1863 writel(0, base + NvRegIrqMask);
1864 pci_push(base);
1865 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1866 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1867 pci_push(base);
1868
1869 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1870 if (ret)
1871 goto out_drain;
1872
1873 /* ask for interrupts */
1874 writel(np->irqmask, base + NvRegIrqMask);
1875
1876 spin_lock_irq(&np->lock);
1877 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1878 writel(0, base + NvRegMulticastAddrB);
1879 writel(0, base + NvRegMulticastMaskA);
1880 writel(0, base + NvRegMulticastMaskB);
1881 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1882 /* One manual link speed update: Interrupts are enabled, future link
1883 * speed changes cause interrupts and are handled by nv_link_irq().
1884 */
1885 {
1886 u32 miistat;
1887 miistat = readl(base + NvRegMIIStatus);
1888 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1889 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
1890 }
1891 ret = nv_update_linkspeed(dev);
1892 nv_start_rx(dev);
1893 nv_start_tx(dev);
1894 netif_start_queue(dev);
1895 if (ret) {
1896 netif_carrier_on(dev);
1897 } else {
1898 printk("%s: no link during initialization.\n", dev->name);
1899 netif_carrier_off(dev);
1900 }
1901 if (oom)
1902 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1903 spin_unlock_irq(&np->lock);
1904
1905 return 0;
1906out_drain:
1907 drain_ring(dev);
1908 return ret;
1909}
1910
1911static int nv_close(struct net_device *dev)
1912{
1913 struct fe_priv *np = get_nvpriv(dev);
1914 u8 __iomem *base;
1915
1916 spin_lock_irq(&np->lock);
1917 np->in_shutdown = 1;
1918 spin_unlock_irq(&np->lock);
1919 synchronize_irq(dev->irq);
1920
1921 del_timer_sync(&np->oom_kick);
1922 del_timer_sync(&np->nic_poll);
1923
1924 netif_stop_queue(dev);
1925 spin_lock_irq(&np->lock);
1926 nv_stop_tx(dev);
1927 nv_stop_rx(dev);
1928 nv_txrx_reset(dev);
1929
1930 /* disable interrupts on the nic or we will lock up */
1931 base = get_hwbase(dev);
1932 writel(0, base + NvRegIrqMask);
1933 pci_push(base);
1934 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1935
1936 spin_unlock_irq(&np->lock);
1937
1938 free_irq(dev->irq, dev);
1939
1940 drain_ring(dev);
1941
1942 if (np->wolenabled)
1943 nv_start_rx(dev);
1944
1945 /* FIXME: power down nic */
1946
1947 return 0;
1948}
1949
1950static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1951{
1952 struct net_device *dev;
1953 struct fe_priv *np;
1954 unsigned long addr;
1955 u8 __iomem *base;
1956 int err, i;
1957
1958 dev = alloc_etherdev(sizeof(struct fe_priv));
1959 err = -ENOMEM;
1960 if (!dev)
1961 goto out;
1962
1963 np = get_nvpriv(dev);
1964 np->pci_dev = pci_dev;
1965 spin_lock_init(&np->lock);
1966 SET_MODULE_OWNER(dev);
1967 SET_NETDEV_DEV(dev, &pci_dev->dev);
1968
1969 init_timer(&np->oom_kick);
1970 np->oom_kick.data = (unsigned long) dev;
1971 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
1972 init_timer(&np->nic_poll);
1973 np->nic_poll.data = (unsigned long) dev;
1974 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
1975
1976 err = pci_enable_device(pci_dev);
1977 if (err) {
1978 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1979 err, pci_name(pci_dev));
1980 goto out_free;
1981 }
1982
1983 pci_set_master(pci_dev);
1984
1985 err = pci_request_regions(pci_dev, DRV_NAME);
1986 if (err < 0)
1987 goto out_disable;
1988
1989 err = -EINVAL;
1990 addr = 0;
1991 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1992 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1993 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1994 pci_resource_len(pci_dev, i),
1995 pci_resource_flags(pci_dev, i));
1996 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1997 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1998 addr = pci_resource_start(pci_dev, i);
1999 break;
2000 }
2001 }
2002 if (i == DEVICE_COUNT_RESOURCE) {
2003 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2004 pci_name(pci_dev));
2005 goto out_relreg;
2006 }
2007
2008 /* handle different descriptor versions */
2009 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
2010 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
Manfred Spraul9992d4a2005-06-05 17:36:11 +02002011 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3 ||
2012 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
2013 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_13)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014 np->desc_ver = DESC_VER_1;
2015 else
2016 np->desc_ver = DESC_VER_2;
2017
2018 err = -ENOMEM;
2019 np->base = ioremap(addr, NV_PCI_REGSZ);
2020 if (!np->base)
2021 goto out_relreg;
2022 dev->base_addr = (unsigned long)np->base;
2023 dev->irq = pci_dev->irq;
2024 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2025 &np->ring_addr);
2026 if (!np->rx_ring)
2027 goto out_unmap;
2028 np->tx_ring = &np->rx_ring[RX_RING];
2029
2030 dev->open = nv_open;
2031 dev->stop = nv_close;
2032 dev->hard_start_xmit = nv_start_xmit;
2033 dev->get_stats = nv_get_stats;
2034 dev->change_mtu = nv_change_mtu;
2035 dev->set_multicast_list = nv_set_multicast;
Michal Schmidt2918c352005-05-12 19:42:06 -04002036#ifdef CONFIG_NET_POLL_CONTROLLER
2037 dev->poll_controller = nv_poll_controller;
2038#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002039 SET_ETHTOOL_OPS(dev, &ops);
2040 dev->tx_timeout = nv_tx_timeout;
2041 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2042
2043 pci_set_drvdata(pci_dev, dev);
2044
2045 /* read the mac address */
2046 base = get_hwbase(dev);
2047 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2048 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2049
2050 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2051 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2052 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2053 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2054 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2055 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
2056
2057 if (!is_valid_ether_addr(dev->dev_addr)) {
2058 /*
2059 * Bad mac address. At least one bios sets the mac address
2060 * to 01:23:45:67:89:ab
2061 */
2062 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2063 pci_name(pci_dev),
2064 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2065 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2066 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2067 dev->dev_addr[0] = 0x00;
2068 dev->dev_addr[1] = 0x00;
2069 dev->dev_addr[2] = 0x6c;
2070 get_random_bytes(&dev->dev_addr[3], 3);
2071 }
2072
2073 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2074 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2075 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2076
2077 /* disable WOL */
2078 writel(0, base + NvRegWakeUpFlags);
2079 np->wolenabled = 0;
2080
2081 if (np->desc_ver == DESC_VER_1) {
2082 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2083 if (id->driver_data & DEV_NEED_LASTPACKET1)
2084 np->tx_flags |= NV_TX_LASTPACKET1;
2085 } else {
2086 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2087 if (id->driver_data & DEV_NEED_LASTPACKET1)
2088 np->tx_flags |= NV_TX2_LASTPACKET1;
2089 }
2090 if (id->driver_data & DEV_IRQMASK_1)
2091 np->irqmask = NVREG_IRQMASK_WANTED_1;
2092 if (id->driver_data & DEV_IRQMASK_2)
2093 np->irqmask = NVREG_IRQMASK_WANTED_2;
2094 if (id->driver_data & DEV_NEED_TIMERIRQ)
2095 np->irqmask |= NVREG_IRQ_TIMER;
2096 if (id->driver_data & DEV_NEED_LINKTIMER) {
2097 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2098 np->need_linktimer = 1;
2099 np->link_timeout = jiffies + LINK_TIMEOUT;
2100 } else {
2101 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2102 np->need_linktimer = 0;
2103 }
2104
2105 /* find a suitable phy */
2106 for (i = 1; i < 32; i++) {
2107 int id1, id2;
2108
2109 spin_lock_irq(&np->lock);
2110 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2111 spin_unlock_irq(&np->lock);
2112 if (id1 < 0 || id1 == 0xffff)
2113 continue;
2114 spin_lock_irq(&np->lock);
2115 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2116 spin_unlock_irq(&np->lock);
2117 if (id2 < 0 || id2 == 0xffff)
2118 continue;
2119
2120 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2121 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2122 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2123 pci_name(pci_dev), id1, id2, i);
2124 np->phyaddr = i;
2125 np->phy_oui = id1 | id2;
2126 break;
2127 }
2128 if (i == 32) {
2129 /* PHY in isolate mode? No phy attached and user wants to
2130 * test loopback? Very odd, but can be correct.
2131 */
2132 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2133 pci_name(pci_dev));
2134 }
2135
2136 if (i != 32) {
2137 /* reset it */
2138 phy_init(dev);
2139 }
2140
2141 /* set default link speed settings */
2142 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2143 np->duplex = 0;
2144 np->autoneg = 1;
2145
2146 err = register_netdev(dev);
2147 if (err) {
2148 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2149 goto out_freering;
2150 }
2151 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2152 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2153 pci_name(pci_dev));
2154
2155 return 0;
2156
2157out_freering:
2158 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2159 np->rx_ring, np->ring_addr);
2160 pci_set_drvdata(pci_dev, NULL);
2161out_unmap:
2162 iounmap(get_hwbase(dev));
2163out_relreg:
2164 pci_release_regions(pci_dev);
2165out_disable:
2166 pci_disable_device(pci_dev);
2167out_free:
2168 free_netdev(dev);
2169out:
2170 return err;
2171}
2172
2173static void __devexit nv_remove(struct pci_dev *pci_dev)
2174{
2175 struct net_device *dev = pci_get_drvdata(pci_dev);
2176 struct fe_priv *np = get_nvpriv(dev);
2177 u8 __iomem *base = get_hwbase(dev);
2178
2179 unregister_netdev(dev);
2180
2181 /* special op: write back the misordered MAC address - otherwise
2182 * the next nv_probe would see a wrong address.
2183 */
2184 writel(np->orig_mac[0], base + NvRegMacAddrA);
2185 writel(np->orig_mac[1], base + NvRegMacAddrB);
2186
2187 /* free all structures */
2188 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
2189 iounmap(get_hwbase(dev));
2190 pci_release_regions(pci_dev);
2191 pci_disable_device(pci_dev);
2192 free_netdev(dev);
2193 pci_set_drvdata(pci_dev, NULL);
2194}
2195
2196static struct pci_device_id pci_tbl[] = {
2197 { /* nForce Ethernet Controller */
2198 .vendor = PCI_VENDOR_ID_NVIDIA,
2199 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
2200 .subvendor = PCI_ANY_ID,
2201 .subdevice = PCI_ANY_ID,
2202 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2203 },
2204 { /* nForce2 Ethernet Controller */
2205 .vendor = PCI_VENDOR_ID_NVIDIA,
2206 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
2207 .subvendor = PCI_ANY_ID,
2208 .subdevice = PCI_ANY_ID,
2209 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2210 },
2211 { /* nForce3 Ethernet Controller */
2212 .vendor = PCI_VENDOR_ID_NVIDIA,
2213 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
2214 .subvendor = PCI_ANY_ID,
2215 .subdevice = PCI_ANY_ID,
2216 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2217 },
2218 { /* nForce3 Ethernet Controller */
2219 .vendor = PCI_VENDOR_ID_NVIDIA,
2220 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002223 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224 },
2225 { /* nForce3 Ethernet Controller */
2226 .vendor = PCI_VENDOR_ID_NVIDIA,
2227 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002230 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231 },
2232 { /* nForce3 Ethernet Controller */
2233 .vendor = PCI_VENDOR_ID_NVIDIA,
2234 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
2235 .subvendor = PCI_ANY_ID,
2236 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002237 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002238 },
2239 { /* nForce3 Ethernet Controller */
2240 .vendor = PCI_VENDOR_ID_NVIDIA,
2241 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
2242 .subvendor = PCI_ANY_ID,
2243 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002244 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245 },
2246 { /* CK804 Ethernet Controller */
2247 .vendor = PCI_VENDOR_ID_NVIDIA,
2248 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
2249 .subvendor = PCI_ANY_ID,
2250 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002251 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002252 },
2253 { /* CK804 Ethernet Controller */
2254 .vendor = PCI_VENDOR_ID_NVIDIA,
2255 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
2256 .subvendor = PCI_ANY_ID,
2257 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002258 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002259 },
2260 { /* MCP04 Ethernet Controller */
2261 .vendor = PCI_VENDOR_ID_NVIDIA,
2262 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
2263 .subvendor = PCI_ANY_ID,
2264 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002265 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266 },
2267 { /* MCP04 Ethernet Controller */
2268 .vendor = PCI_VENDOR_ID_NVIDIA,
2269 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
2270 .subvendor = PCI_ANY_ID,
2271 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002272 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002273 },
Manfred Spraul9992d4a2005-06-05 17:36:11 +02002274 { /* MCP51 Ethernet Controller */
2275 .vendor = PCI_VENDOR_ID_NVIDIA,
2276 .device = PCI_DEVICE_ID_NVIDIA_NVENET_12,
2277 .subvendor = PCI_ANY_ID,
2278 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002279 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02002280 },
2281 { /* MCP51 Ethernet Controller */
2282 .vendor = PCI_VENDOR_ID_NVIDIA,
2283 .device = PCI_DEVICE_ID_NVIDIA_NVENET_13,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
Manfred Spraul8f767fc2005-06-18 16:27:19 +02002286 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
Manfred Spraul9992d4a2005-06-05 17:36:11 +02002287 },
Manfred Spraulf49d16e2005-06-26 11:36:52 +02002288 { /* MCP55 Ethernet Controller */
2289 .vendor = PCI_VENDOR_ID_NVIDIA,
2290 .device = PCI_DEVICE_ID_NVIDIA_NVENET_14,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2294 },
2295 { /* MCP55 Ethernet Controller */
2296 .vendor = PCI_VENDOR_ID_NVIDIA,
2297 .device = PCI_DEVICE_ID_NVIDIA_NVENET_15,
2298 .subvendor = PCI_ANY_ID,
2299 .subdevice = PCI_ANY_ID,
2300 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2301 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002302 {0,},
2303};
2304
2305static struct pci_driver driver = {
2306 .name = "forcedeth",
2307 .id_table = pci_tbl,
2308 .probe = nv_probe,
2309 .remove = __devexit_p(nv_remove),
2310};
2311
2312
2313static int __init init_nic(void)
2314{
2315 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2316 return pci_module_init(&driver);
2317}
2318
2319static void __exit exit_nic(void)
2320{
2321 pci_unregister_driver(&driver);
2322}
2323
2324module_param(max_interrupt_work, int, 0);
2325MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2326
2327MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2328MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2329MODULE_LICENSE("GPL");
2330
2331MODULE_DEVICE_TABLE(pci, pci_tbl);
2332
2333module_init(init_nic);
2334module_exit(exit_nic);