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gerrit-public.fairphone.software / kernel / msm / d1fd56643015ed35d853a42f5a04055e104fdbb9 / . / arch / arm / mach-msm / clock-pcom-lookup.c
blob: 2a2cc01bd6052ca77cdf2980f6d304c218894d48 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]1/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "clock.h"
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]14#include "clock-pll.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]15#include "clock-pcom.h"
16#include "clock-voter.h"
Steve Mucklef132c6c2012-06-06 18:30:57 -0700[diff] [blame]17#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]18
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]19#include <mach/msm_iomap.h>
20#include <mach/socinfo.h>
21
22#define PLLn_MODE(n) (MSM_CLK_CTL_BASE + 0x300 + 28 * (n))
23#define PLL4_MODE (MSM_CLK_CTL_BASE + 0x374)
24
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]25static DEFINE_CLK_PCOM(adm_clk, ADM_CLK, 0);
26static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, 0);
27static DEFINE_CLK_PCOM(ahb_m_clk, AHB_M_CLK, 0);
28static DEFINE_CLK_PCOM(ahb_s_clk, AHB_S_CLK, 0);
29static DEFINE_CLK_PCOM(cam_m_clk, CAM_M_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]30static DEFINE_CLK_PCOM(axi_rotator_clk, AXI_ROTATOR_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]31static DEFINE_CLK_PCOM(ce_clk, CE_CLK, 0);
32static DEFINE_CLK_PCOM(csi0_clk, CSI0_CLK, 0);
33static DEFINE_CLK_PCOM(csi0_p_clk, CSI0_P_CLK, 0);
34static DEFINE_CLK_PCOM(csi0_vfe_clk, CSI0_VFE_CLK, 0);
35static DEFINE_CLK_PCOM(csi1_clk, CSI1_CLK, 0);
36static DEFINE_CLK_PCOM(csi1_p_clk, CSI1_P_CLK, 0);
37static DEFINE_CLK_PCOM(csi1_vfe_clk, CSI1_VFE_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]38
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]39static struct pll_shared_clk pll0_clk = {
40 .id = PLL_0,
41 .mode_reg = PLLn_MODE(0),
42 .c = {
Matt Wagantallae053222012-05-14 19:42:07 -0700[diff] [blame]43 .ops = &clk_ops_pll,
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]44 .dbg_name = "pll0_clk",
45 CLK_INIT(pll0_clk.c),
46 },
47};
48
49static struct pll_shared_clk pll1_clk = {
50 .id = PLL_1,
51 .mode_reg = PLLn_MODE(1),
52 .c = {
Matt Wagantallae053222012-05-14 19:42:07 -0700[diff] [blame]53 .ops = &clk_ops_pll,
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]54 .dbg_name = "pll1_clk",
55 CLK_INIT(pll1_clk.c),
56 },
57};
58
59static struct pll_shared_clk pll2_clk = {
60 .id = PLL_2,
61 .mode_reg = PLLn_MODE(2),
62 .c = {
Matt Wagantallae053222012-05-14 19:42:07 -0700[diff] [blame]63 .ops = &clk_ops_pll,
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]64 .dbg_name = "pll2_clk",
65 CLK_INIT(pll2_clk.c),
66 },
67};
68
69static struct pll_shared_clk pll4_clk = {
70 .id = PLL_4,
71 .mode_reg = PLL4_MODE,
72 .c = {
Matt Wagantallae053222012-05-14 19:42:07 -0700[diff] [blame]73 .ops = &clk_ops_pll,
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]74 .dbg_name = "pll4_clk",
75 CLK_INIT(pll4_clk.c),
76 },
77};
78
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]79static struct pcom_clk dsi_byte_clk = {
80 .id = P_DSI_BYTE_CLK,
81 .c = {
82 .ops = &clk_ops_pcom_ext_config,
83 .dbg_name = "dsi_byte_clk",
84 CLK_INIT(dsi_byte_clk.c),
85 },
86};
87
88static struct pcom_clk dsi_clk = {
89 .id = P_DSI_CLK,
90 .c = {
91 .ops = &clk_ops_pcom_ext_config,
92 .dbg_name = "dsi_clk",
93 CLK_INIT(dsi_clk.c),
94 },
95};
96
97static struct pcom_clk dsi_esc_clk = {
98 .id = P_DSI_ESC_CLK,
99 .c = {
100 .ops = &clk_ops_pcom_ext_config,
101 .dbg_name = "dsi_esc_clk",
102 CLK_INIT(dsi_esc_clk.c),
103 },
104};
105
106static struct pcom_clk dsi_pixel_clk = {
107 .id = P_DSI_PIXEL_CLK,
108 .c = {
109 .ops = &clk_ops_pcom_ext_config,
110 .dbg_name = "dsi_pixel_clk",
111 CLK_INIT(dsi_pixel_clk.c),
112 },
113};
114
115static DEFINE_CLK_PCOM(dsi_ref_clk, DSI_REF_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]116static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLKFLAG_MIN);
117static DEFINE_CLK_PCOM(ebi2_clk, EBI2_CLK, 0);
118static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]119static DEFINE_CLK_PCOM(emdh_clk, EMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]120static DEFINE_CLK_PCOM(gp_clk, GP_CLK, 0);
121static DEFINE_CLK_PCOM(grp_2d_clk, GRP_2D_CLK, 0);
122static DEFINE_CLK_PCOM(grp_2d_p_clk, GRP_2D_P_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]123static DEFINE_CLK_PCOM(grp_3d_clk, GRP_3D_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]124static DEFINE_CLK_PCOM(grp_3d_p_clk, GRP_3D_P_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]125static DEFINE_CLK_PCOM(gsbi1_qup_clk, GSBI1_QUP_CLK, 0);
126static DEFINE_CLK_PCOM(gsbi1_qup_p_clk, GSBI1_QUP_P_CLK, 0);
127static DEFINE_CLK_PCOM(gsbi2_qup_clk, GSBI2_QUP_CLK, 0);
128static DEFINE_CLK_PCOM(gsbi2_qup_p_clk, GSBI2_QUP_P_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]129static DEFINE_CLK_PCOM(gsbi_clk, GSBI_CLK, 0);
130static DEFINE_CLK_PCOM(gsbi_p_clk, GSBI_P_CLK, 0);
131static DEFINE_CLK_PCOM(hdmi_clk, HDMI_CLK, 0);
132static DEFINE_CLK_PCOM(i2c_clk, I2C_CLK, 0);
133static DEFINE_CLK_PCOM(icodec_rx_clk, ICODEC_RX_CLK, 0);
134static DEFINE_CLK_PCOM(icodec_tx_clk, ICODEC_TX_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]135static DEFINE_CLK_PCOM(imem_clk, IMEM_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]136static DEFINE_CLK_PCOM(mdc_clk, MDC_CLK, 0);
Matt Wagantalla12cc952011-11-08 18:14:50 -0800[diff] [blame]137static DEFINE_CLK_PCOM(mdp_clk, MDP_CLK, CLKFLAG_MIN);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]138static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK,
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]139 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]140static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK,
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]141 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]142static DEFINE_CLK_PCOM(mdp_vsync_clk, MDP_VSYNC_CLK, 0);
143static DEFINE_CLK_PCOM(mdp_dsi_p_clk, MDP_DSI_P_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]144static DEFINE_CLK_PCOM(pbus_clk, PBUS_CLK, CLKFLAG_MIN);
145static DEFINE_CLK_PCOM(pcm_clk, PCM_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]146static DEFINE_CLK_PCOM(pmdh_clk, PMDH_CLK, CLKFLAG_MIN | CLKFLAG_MAX);
147static DEFINE_CLK_PCOM(sdac_clk, SDAC_CLK, 0);
148static DEFINE_CLK_PCOM(sdc1_clk, SDC1_CLK, 0);
149static DEFINE_CLK_PCOM(sdc1_p_clk, SDC1_P_CLK, 0);
150static DEFINE_CLK_PCOM(sdc2_clk, SDC2_CLK, 0);
151static DEFINE_CLK_PCOM(sdc2_p_clk, SDC2_P_CLK, 0);
152static DEFINE_CLK_PCOM(sdc3_clk, SDC3_CLK, 0);
153static DEFINE_CLK_PCOM(sdc3_p_clk, SDC3_P_CLK, 0);
154static DEFINE_CLK_PCOM(sdc4_clk, SDC4_CLK, 0);
155static DEFINE_CLK_PCOM(sdc4_p_clk, SDC4_P_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]156static DEFINE_CLK_PCOM(spi_clk, SPI_CLK, 0);
157static DEFINE_CLK_PCOM(tsif_clk, TSIF_CLK, 0);
158static DEFINE_CLK_PCOM(tsif_p_clk, TSIF_P_CLK, 0);
159static DEFINE_CLK_PCOM(tsif_ref_clk, TSIF_REF_CLK, 0);
160static DEFINE_CLK_PCOM(tv_dac_clk, TV_DAC_CLK, 0);
161static DEFINE_CLK_PCOM(tv_enc_clk, TV_ENC_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]162static DEFINE_CLK_PCOM(uart1_clk, UART1_CLK, 0);
163static DEFINE_CLK_PCOM(uart1dm_clk, UART1DM_CLK, 0);
164static DEFINE_CLK_PCOM(uart2_clk, UART2_CLK, 0);
165static DEFINE_CLK_PCOM(uart2dm_clk, UART2DM_CLK, 0);
166static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, 0);
167static DEFINE_CLK_PCOM(usb_hs2_clk, USB_HS2_CLK, 0);
168static DEFINE_CLK_PCOM(usb_hs2_p_clk, USB_HS2_P_CLK, 0);
169static DEFINE_CLK_PCOM(usb_hs3_clk, USB_HS3_CLK, 0);
170static DEFINE_CLK_PCOM(usb_hs3_p_clk, USB_HS3_P_CLK, 0);
171static DEFINE_CLK_PCOM(usb_hs_clk, USB_HS_CLK, 0);
172static DEFINE_CLK_PCOM(usb_hs_core_clk, USB_HS_CORE_CLK, 0);
173static DEFINE_CLK_PCOM(usb_hs_p_clk, USB_HS_P_CLK, 0);
Matt Wagantall647d1c12012-05-16 14:32:14 -0700[diff] [blame]174static DEFINE_CLK_PCOM(usb_otg_clk, USB_OTG_CLK, 0);
175static DEFINE_CLK_PCOM(usb_phy_clk, USB_PHY_CLK, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]176static DEFINE_CLK_PCOM(vdc_clk, VDC_CLK, CLKFLAG_MIN);
177static DEFINE_CLK_PCOM(vfe_axi_clk, VFE_AXI_CLK, 0);
178static DEFINE_CLK_PCOM(vfe_clk, VFE_CLK, 0);
179static DEFINE_CLK_PCOM(vfe_mdc_clk, VFE_MDC_CLK, 0);
180
Matt Wagantall35e78fc2012-04-05 14:18:44 -0700[diff] [blame]181static DEFINE_CLK_VOTER(ebi_acpu_clk, &ebi1_clk.c, 0);
182static DEFINE_CLK_VOTER(ebi_grp_3d_clk, &ebi1_clk.c, 0);
183static DEFINE_CLK_VOTER(ebi_grp_2d_clk, &ebi1_clk.c, 0);
184static DEFINE_CLK_VOTER(ebi_lcdc_clk, &ebi1_clk.c, 0);
185static DEFINE_CLK_VOTER(ebi_mddi_clk, &ebi1_clk.c, 0);
186static DEFINE_CLK_VOTER(ebi_tv_clk, &ebi1_clk.c, 0);
187static DEFINE_CLK_VOTER(ebi_usb_clk, &ebi1_clk.c, 0);
188static DEFINE_CLK_VOTER(ebi_vfe_clk, &ebi1_clk.c, 0);
189static DEFINE_CLK_VOTER(ebi_adm_clk, &ebi1_clk.c, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]190
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]191static struct clk_lookup msm_clocks_7x01a[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]192 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]193 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
194 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
195 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
196 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]197 CLK_LOOKUP("core_clk", emdh_clk.c, "msm_mddi.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -0800[diff] [blame]198 CLK_LOOKUP("core_clk", gp_clk.c, ""),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]199 CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]200 CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]201 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
202 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]203 CLK_LOOKUP("mem_clk", imem_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]204 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]205 CLK_LOOKUP("core_clk", pmdh_clk.c, "mddi.0"),
206 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]207 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
208 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
209 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]210 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
211 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
212 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
213 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
214 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
215 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
216 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
217 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -0700[diff] [blame]218 CLK_LOOKUP("core_clk", tsif_clk.c, "msm_tsif.0"),
219 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]220 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
221 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]222 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
223 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
224 CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2"),
225 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
226 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]227 CLK_LOOKUP("alt_core_clk", usb_hs_clk.c, "msm_otg"),
228 CLK_LOOKUP("iface_clk", usb_hs_p_clk.c, "msm_otg"),
229 CLK_LOOKUP("alt_core_clk", usb_hs_clk.c, "msm_hsusb_otg"),
230 CLK_LOOKUP("iface_clk", usb_hs_p_clk.c, "msm_hsusb_otg"),
231 CLK_LOOKUP("alt_core_clk", usb_hs_clk.c, "msm_hsusb_peripheral"),
232 CLK_LOOKUP("iface_clk", usb_hs_p_clk.c, "msm_hsusb_peripheral"),
233 CLK_LOOKUP("alt_core_clk", usb_otg_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]234 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
235 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
236 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
237};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]238
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]239struct clock_init_data msm7x01a_clock_init_data __initdata = {
240 .table = msm_clocks_7x01a,
241 .size = ARRAY_SIZE(msm_clocks_7x01a),
242};
243
244static struct clk_lookup msm_clocks_7x27[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]245 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]246 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
247 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
248 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
249 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -0800[diff] [blame]250 CLK_LOOKUP("core_clk", gp_clk.c, ""),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]251 CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]252 CLK_LOOKUP("core_clk", grp_3d_clk.c, "footswitch-pcom.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]253 CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]254 CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]255 CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "footswitch-pcom.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]256 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
257 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]258 CLK_LOOKUP("mem_clk", imem_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]259 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]260 CLK_LOOKUP("core_clk", pmdh_clk.c, "mddi.0"),
261 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
262 CLK_LOOKUP("mdp_clk", mdp_lcdc_pclk_clk.c, "lcdc.0"),
263 CLK_LOOKUP("lcdc_clk", mdp_lcdc_pad_pclk_clk.c, "lcdc.0"),
264 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]265 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
266 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
267 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]268 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
269 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
270 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
271 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
272 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
273 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
274 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
275 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -0700[diff] [blame]276 CLK_LOOKUP("core_clk", tsif_clk.c, "msm_tsif.0"),
277 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
278 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.0"),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]279 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
280 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
281 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
282 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]283 CLK_LOOKUP("alt_core_clk", usb_hs_clk.c, "msm_otg"),
284 CLK_LOOKUP("iface_clk", usb_hs_p_clk.c, "msm_otg"),
285 CLK_LOOKUP("alt_core_clk", usb_otg_clk.c, NULL),
286 CLK_LOOKUP("phy_clk", usb_phy_clk.c, "msm_otg"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]287 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]288 CLK_LOOKUP("core_clk", vdc_clk.c, "footswitch-pcom.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]289 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]290 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-pcom.8"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]291 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
292
293 CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]294 CLK_LOOKUP("bus_clk", ebi_grp_3d_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]295 CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "lcdc.0"),
296 CLK_LOOKUP("mem_clk", ebi_mddi_clk.c, "mddi.0"),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]297 CLK_LOOKUP("core_clk", ebi_usb_clk.c, "msm_otg"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]298 CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]299 CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]300
301 CLK_LOOKUP("pll0_clk", pll0_clk.c, "acpu"),
302 CLK_LOOKUP("pll1_clk", pll1_clk.c, "acpu"),
303 CLK_LOOKUP("pll2_clk", pll2_clk.c, "acpu"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]304};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]305
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]306struct clock_init_data msm7x27_clock_init_data __initdata = {
307 .table = msm_clocks_7x27,
308 .size = ARRAY_SIZE(msm_clocks_7x27),
Matt Wagantallb64888f2012-04-02 21:35:07 -0700[diff] [blame]309 .pre_init = msm_shared_pll_control_init,
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]310};
311
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]312/* Clock table for common clocks between 7627a and 7625a */
313static struct clk_lookup msm_cmn_clk_7625a_7627a[] __initdata = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]314 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]315 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]316 CLK_LOOKUP("master_iface_clk", ahb_m_clk.c, "mipi_dsi.1"),
317 CLK_LOOKUP("slave_iface_clk", ahb_s_clk.c, "mipi_dsi.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]318 CLK_LOOKUP("cam_m_clk", cam_m_clk.c, NULL),
Sandeep Kodimelac6f78672012-03-07 10:44:04 +0530[diff] [blame]319 CLK_LOOKUP("cam_clk", cam_m_clk.c, "0-0036"),
320 CLK_LOOKUP("cam_clk", cam_m_clk.c, "0-001b"),
321 CLK_LOOKUP("cam_clk", cam_m_clk.c, "0-0010"),
Raju P.L.S.S.S.Ncc400972012-03-13 10:09:59 +0530[diff] [blame]322 CLK_LOOKUP("cam_clk", cam_m_clk.c, "0-0078"),
323 CLK_LOOKUP("cam_clk", cam_m_clk.c, "0-006c"),
Katta Santhisindhu16746f62012-06-08 13:35:07 +0530[diff] [blame]324 CLK_LOOKUP("cam_clk", cam_m_clk.c, "0-000d"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]325 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_ov9726.0"),
326 CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_camera_ov9726.0"),
327 CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_camera_ov9726.0"),
Taniya Das7a22cdd2011-09-08 14:57:00 +0530[diff] [blame]328 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_camera_ov7692.0"),
329 CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_camera_ov7692.0"),
330 CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_camera_ov7692.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]331 CLK_LOOKUP("csi_clk", csi1_clk.c, NULL),
332 CLK_LOOKUP("csi_pclk", csi1_p_clk.c, NULL),
333 CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, NULL),
Suresh Vankadara4d4d5c52012-01-18 00:45:49 +0530[diff] [blame]334 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csic.0"),
335 CLK_LOOKUP("csi_pclk", csi0_p_clk.c, "msm_csic.0"),
336 CLK_LOOKUP("csi_vfe_clk", csi0_vfe_clk.c, "msm_csic.0"),
337 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csic.1"),
338 CLK_LOOKUP("csi_pclk", csi1_p_clk.c, "msm_csic.1"),
339 CLK_LOOKUP("csi_vfe_clk", csi1_vfe_clk.c, "msm_csic.1"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]340 CLK_LOOKUP("byte_clk", dsi_byte_clk.c, "mipi_dsi.1"),
341 CLK_LOOKUP("core_clk", dsi_clk.c, "mipi_dsi.1"),
342 CLK_LOOKUP("esc_clk", dsi_esc_clk.c, "mipi_dsi.1"),
343 CLK_LOOKUP("pixel_clk", dsi_pixel_clk.c, "mipi_dsi.1"),
344 CLK_LOOKUP("ref_clk", dsi_ref_clk.c, "mipi_dsi.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]345 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
346 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
347 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -0800[diff] [blame]348 CLK_LOOKUP("core_clk", gp_clk.c, ""),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]349 CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]350 CLK_LOOKUP("core_clk", grp_3d_clk.c, "footswitch-pcom.2"),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]351 CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]352 CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "footswitch-pcom.2"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]353 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
354 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, "qup_i2c.1"),
355 CLK_LOOKUP("iface_clk", gsbi1_qup_p_clk.c, "qup_i2c.0"),
356 CLK_LOOKUP("iface_clk", gsbi2_qup_p_clk.c, "qup_i2c.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]357 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
358 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]359 CLK_LOOKUP("mem_clk", imem_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]360 CLK_LOOKUP("core_clk", pmdh_clk.c, "mddi.0"),
361 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
362 CLK_LOOKUP("mdp_clk", mdp_lcdc_pclk_clk.c, "lcdc.0"),
363 CLK_LOOKUP("lcdc_clk", mdp_lcdc_pad_pclk_clk.c, "lcdc.0"),
364 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
365 CLK_LOOKUP("mdp_clk", mdp_dsi_p_clk.c, "mipi_dsi.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]366 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
367 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
368 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]369 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
370 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
371 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
372 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
373 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
374 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
375 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
376 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantall640e5fd2011-08-17 16:08:53 -0700[diff] [blame]377 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
378 CLK_LOOKUP("iface_clk", tsif_p_clk.c, "msm_tsif.0"),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]379 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
380 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
381 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
382 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hsl.0"),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]383 CLK_LOOKUP("core_clk", usb_hs_core_clk.c, "msm_otg"),
384 CLK_LOOKUP("alt_core_clk", usb_hs_clk.c, "msm_otg"),
385 CLK_LOOKUP("iface_clk", usb_hs_p_clk.c, "msm_otg"),
386 CLK_LOOKUP("phy_clk", usb_phy_clk.c, "msm_otg"),
387 CLK_LOOKUP("alt_core_clk", usb_hs2_clk.c, "msm_hsusb_host.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]388 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]389 CLK_LOOKUP("core_clk", vdc_clk.c, "footswitch-pcom.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]390 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
Suresh Vankadara4d4d5c52012-01-18 00:45:49 +0530[diff] [blame]391 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -0700[diff] [blame]392 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-pcom.8"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]393 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
394
395 CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]396 CLK_LOOKUP("bus_clk", ebi_grp_3d_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]397 CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "lcdc.0"),
Padmanabhan Komanduru0769dbd2012-04-19 16:54:09 +0530[diff] [blame]398 CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "mipi_dsi.1"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]399 CLK_LOOKUP("mem_clk", ebi_mddi_clk.c, "mddi.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]400 CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]401 CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]402
403 CLK_LOOKUP("pll0_clk", pll0_clk.c, "acpu"),
404 CLK_LOOKUP("pll1_clk", pll1_clk.c, "acpu"),
405 CLK_LOOKUP("pll2_clk", pll2_clk.c, "acpu"),
406
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]407};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]408
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]409/* PLL 4 clock is available for 7627a target. */
410static struct clk_lookup msm_clk_7627a[] __initdata = {
411 CLK_LOOKUP("pll4_clk", pll4_clk.c, "acpu"),
412};
413
414static struct clk_lookup msm_clk_7627a_7625a[ARRAY_SIZE(msm_cmn_clk_7625a_7627a)
415 + ARRAY_SIZE(msm_clk_7627a)];
416
Matt Wagantallb64888f2012-04-02 21:35:07 -0700[diff] [blame]417static void __init msm7627a_clock_pre_init(void)
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]418{
419 int size = ARRAY_SIZE(msm_cmn_clk_7625a_7627a);
420
421 /* Intialize shared PLL control structure */
422 msm_shared_pll_control_init();
423
424 memcpy(&msm_clk_7627a_7625a, &msm_cmn_clk_7625a_7627a,
425 sizeof(msm_cmn_clk_7625a_7627a));
426 if (!cpu_is_msm7x25a()) {
427 memcpy(&msm_clk_7627a_7625a[size],
428 &msm_clk_7627a, sizeof(msm_clk_7627a));
429 size += ARRAY_SIZE(msm_clk_7627a);
430 }
431 msm7x27a_clock_init_data.size = size;
432}
433
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]434struct clock_init_data msm7x27a_clock_init_data __initdata = {
Pankaj Kumar3912c982011-12-07 16:59:03 +0530[diff] [blame]435 .table = msm_clk_7627a_7625a,
Matt Wagantallb64888f2012-04-02 21:35:07 -0700[diff] [blame]436 .pre_init = msm7627a_clock_pre_init,
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]437};
438
439static struct clk_lookup msm_clocks_8x50[] = {
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]440 CLK_LOOKUP("core_clk", adm_clk.c, "msm_dmov"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -0700[diff] [blame]441 CLK_LOOKUP("core_clk", ce_clk.c, "qce.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]442 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
443 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
444 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]445 CLK_LOOKUP("core_clk", emdh_clk.c, "msm_mddi.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -0800[diff] [blame]446 CLK_LOOKUP("core_clk", gp_clk.c, ""),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]447 CLK_LOOKUP("core_clk", grp_3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]448 CLK_LOOKUP("core_clk", i2c_clk.c, "msm_i2c.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]449 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
450 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]451 CLK_LOOKUP("mem_clk", imem_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]452 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]453 CLK_LOOKUP("core_clk", pmdh_clk.c, "mddi.0"),
454 CLK_LOOKUP("core_clk", mdp_clk.c, "mdp.0"),
455 CLK_LOOKUP("mdp_clk", mdp_lcdc_pclk_clk.c, "lcdc.0"),
456 CLK_LOOKUP("lcdc_clk", mdp_lcdc_pad_pclk_clk.c, "lcdc.0"),
457 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "mdp.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]458 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
459 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
460 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
Matt Wagantall37ce3842011-08-17 16:00:36 -0700[diff] [blame]461 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
462 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
463 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
464 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
465 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
466 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
467 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
468 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]469 CLK_LOOKUP("core_clk", spi_clk.c, "spi_qsd.0"),
470 CLK_DUMMY("iface_clk", SPI_P_CLK, "spi_qsd.0", 0),
Matt Wagantall640e5fd2011-08-17 16:08:53 -0700[diff] [blame]471 CLK_LOOKUP("core_clk", tsif_clk.c, "msm_tsif.0"),
472 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, "msm_tsif.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]473 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
474 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
Matt Wagantalle2522372011-08-17 14:52:21 -0700[diff] [blame]475 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
476 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
477 CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2"),
478 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
479 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]480 CLK_LOOKUP("alt_core_clk", usb_hs_clk.c, "msm_otg"),
481 CLK_LOOKUP("iface_clk", usb_hs_p_clk.c, "msm_otg"),
482 CLK_LOOKUP("alt_core_clk", usb_otg_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]483 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
484 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
485 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
486 CLK_LOOKUP("vfe_axi_clk", vfe_axi_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]487 CLK_LOOKUP("alt_core_clk", usb_hs2_clk.c, "msm_hsusb_host.0"),
488 CLK_LOOKUP("iface_clk", usb_hs2_p_clk.c, "msm_hsusb_host.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -0800[diff] [blame]489 CLK_LOOKUP("alt_core_clk", usb_hs3_clk.c, ""),
490 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]491 CLK_LOOKUP("phy_clk", usb_phy_clk.c, "msm_otg"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]492
493 CLK_LOOKUP("ebi1_acpu_clk", ebi_acpu_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]494 CLK_LOOKUP("bus_clk", ebi_grp_3d_clk.c, "kgsl-3d0.0"),
495 CLK_LOOKUP("bus_clk", ebi_grp_2d_clk.c, "kgsl-2d0.0"),
Ravishangar Kalyanam1b064f52012-03-15 18:17:54 -0700[diff] [blame]496 CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "lcdc.0"),
497 CLK_LOOKUP("mem_clk", ebi_lcdc_clk.c, "mipi_dsi.1"),
498 CLK_LOOKUP("mem_clk", ebi_mddi_clk.c, "mddi.0"),
499 CLK_LOOKUP("mem_clk", ebi_tv_clk.c, "tvenc.0"),
Manu Gautam5143b252012-01-05 19:25:23 -0800[diff] [blame]500 CLK_LOOKUP("core_clk", ebi_usb_clk.c, "msm_otg"),
501 CLK_LOOKUP("core_clk", ebi_usb_clk.c, "msm_hsusb_host.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]502 CLK_LOOKUP("ebi1_vfe_clk", ebi_vfe_clk.c, NULL),
Matt Wagantalle1a86062011-08-18 17:46:10 -0700[diff] [blame]503 CLK_LOOKUP("mem_clk", ebi_adm_clk.c, "msm_dmov"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]504
Matt Wagantall9dc01632011-08-17 18:55:04 -0700[diff] [blame]505 CLK_LOOKUP("iface_clk", grp_3d_p_clk.c, "kgsl-3d0.0"),
506 CLK_LOOKUP("core_clk", grp_2d_clk.c, "kgsl-2d0.0"),
507 CLK_LOOKUP("iface_clk", grp_2d_p_clk.c, "kgsl-2d0.0"),
Matt Wagantallac294852011-08-17 15:44:58 -0700[diff] [blame]508 CLK_LOOKUP("core_clk", gsbi_clk.c, "qup_i2c.4"),
509 CLK_LOOKUP("iface_clk", gsbi_p_clk.c, "qup_i2c.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]510};
Stephen Boydbb600ae2011-08-02 20:11:40 -0700[diff] [blame]511
512struct clock_init_data qds8x50_clock_init_data __initdata = {
513 .table = msm_clocks_8x50,
514 .size = ARRAY_SIZE(msm_clocks_8x50),
515};