| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2001 MontaVista Software Inc. |
| 3 | * Author: jsun@mvista.com or jsun@junsun.net |
| 4 | * |
| 5 | * First-level interrupt dispatcher for ddb5476 |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | */ |
| 12 | #include <asm/asm.h> |
| 13 | #include <asm/mipsregs.h> |
| 14 | #include <asm/addrspace.h> |
| 15 | #include <asm/regdef.h> |
| 16 | #include <asm/stackframe.h> |
| 17 | |
| 18 | #include <asm/ddb5xxx/ddb5476.h> |
| 19 | |
| 20 | /* |
| 21 | * first level interrupt dispatcher for ocelot board - |
| 22 | * We check for the timer first, then check PCI ints A and D. |
| 23 | * Then check for serial IRQ and fall through. |
| 24 | */ |
| 25 | .align 5 |
| 26 | NESTED(ddb5476_handle_int, PT_SIZE, sp) |
| 27 | SAVE_ALL |
| 28 | CLI |
| 29 | .set at |
| 30 | .set noreorder |
| 31 | mfc0 t0, CP0_CAUSE |
| 32 | mfc0 t2, CP0_STATUS |
| 33 | |
| 34 | and t0, t2 |
| 35 | |
| 36 | andi t1, t0, STATUSF_IP7 /* cpu timer */ |
| 37 | bnez t1, ll_cpu_ip7 |
| 38 | andi t1, t0, STATUSF_IP2 /* vrc5476 & i8259 */ |
| 39 | bnez t1, ll_cpu_ip2 |
| 40 | andi t1, t0, STATUSF_IP3 |
| 41 | bnez t1, ll_cpu_ip3 |
| 42 | andi t1, t0, STATUSF_IP4 |
| 43 | bnez t1, ll_cpu_ip4 |
| 44 | andi t1, t0, STATUSF_IP5 |
| 45 | bnez t1, ll_cpu_ip5 |
| 46 | andi t1, t0, STATUSF_IP6 |
| 47 | bnez t1, ll_cpu_ip6 |
| 48 | andi t1, t0, STATUSF_IP0 /* software int 0 */ |
| 49 | bnez t1, ll_cpu_ip0 |
| 50 | andi t1, t0, STATUSF_IP1 /* software int 1 */ |
| 51 | bnez t1, ll_cpu_ip1 |
| 52 | nop |
| 53 | |
| 54 | .set reorder |
| 55 | |
| 56 | /* wrong alarm or masked ... */ |
| Ralf Baechle | 93373ed | 2006-04-01 21:17:45 +0100 | [diff] [blame] | 57 | // jal spurious_interrupt |
| 58 | // j ret_from_irq |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | move a0, sp |
| 60 | jal vrc5476_irq_dispatch |
| 61 | j ret_from_irq |
| 62 | nop |
| 63 | |
| 64 | .align 5 |
| 65 | |
| 66 | ll_cpu_ip0: |
| 67 | li a0, CPU_IRQ_BASE + 0 |
| 68 | move a1, sp |
| 69 | jal do_IRQ |
| 70 | j ret_from_irq |
| 71 | |
| 72 | ll_cpu_ip1: |
| 73 | li a0, CPU_IRQ_BASE + 1 |
| 74 | move a1, sp |
| 75 | jal do_IRQ |
| 76 | j ret_from_irq |
| 77 | |
| 78 | ll_cpu_ip2: /* jump to second-level dispatching */ |
| 79 | move a0, sp |
| 80 | jal vrc5476_irq_dispatch |
| 81 | j ret_from_irq |
| 82 | |
| 83 | ll_cpu_ip3: |
| 84 | li a0, CPU_IRQ_BASE + 3 |
| 85 | move a1, sp |
| 86 | jal do_IRQ |
| 87 | j ret_from_irq |
| 88 | |
| 89 | ll_cpu_ip4: |
| 90 | li a0, CPU_IRQ_BASE + 4 |
| 91 | move a1, sp |
| 92 | jal do_IRQ |
| 93 | j ret_from_irq |
| 94 | |
| 95 | ll_cpu_ip5: |
| 96 | li a0, CPU_IRQ_BASE + 5 |
| 97 | move a1, sp |
| 98 | jal do_IRQ |
| 99 | j ret_from_irq |
| 100 | |
| 101 | ll_cpu_ip6: |
| 102 | li a0, CPU_IRQ_BASE + 6 |
| 103 | move a1, sp |
| 104 | jal do_IRQ |
| 105 | j ret_from_irq |
| 106 | |
| 107 | ll_cpu_ip7: |
| 108 | li a0, CPU_IRQ_BASE + 7 |
| 109 | move a1, sp |
| 110 | jal do_IRQ |
| 111 | j ret_from_irq |
| 112 | |
| 113 | END(ddb5476_handle_int) |