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gerrit-public.fairphone.software / kernel / msm / d53d9e67b55f6a9fc3f836c5c392eb41ce5676f4 / . / drivers / net / wireless / rt2x00 / rt2800usb.h
blob: 8e4291d280b3d194e469cc17166e25eee5885012 [file] [log] [blame]
Ivo van Doornd53d9e62009-04-26 15:47:48 +0200[diff] [blame^]1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800usb
23 Abstract: Data structures and registers for the rt2800usb module.
24 Supported chipsets: RT2800U.
25 */
26
27#ifndef RT2800USB_H
28#define RT2800USB_H
29
30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 */
40#define RF2820 0x0001
41#define RF2850 0x0002
42#define RF2720 0x0003
43#define RF2750 0x0004
44#define RF3020 0x0005
45#define RF2020 0x0006
46
47/*
48 * RT2870 version
49 */
50#define RT2860C_VERSION 0x28600100
51#define RT2860D_VERSION 0x28600101
52#define RT2880E_VERSION 0x28720200
53#define RT2883_VERSION 0x28830300
54#define RT3070_VERSION 0x30700200
55
56/*
57 * Signal information.
58 * Defaul offset is required for RSSI <-> dBm conversion.
59 */
60#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
61
62/*
63 * Register layout information.
64 */
65#define CSR_REG_BASE 0x1000
66#define CSR_REG_SIZE 0x0800
67#define EEPROM_BASE 0x0000
68#define EEPROM_SIZE 0x0110
69#define BBP_BASE 0x0000
70#define BBP_SIZE 0x0080
71#define RF_BASE 0x0004
72#define RF_SIZE 0x0010
73
74/*
75 * Number of TX queues.
76 */
77#define NUM_TX_QUEUES 4
78
79/*
80 * USB registers.
81 */
82
83/*
84 * HOST-MCU shared memory
85 */
86#define HOST_CMD_CSR 0x0404
87#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
88
89/*
90 * INT_SOURCE_CSR: Interrupt source register.
91 * Write one to clear corresponding bit.
92 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
93 */
94#define INT_SOURCE_CSR 0x0200
95#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
96#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
97#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
98#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
99#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
100#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
101#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
102#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
103#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
104#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
105#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
106#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
107#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
108#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
109#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
110#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
111#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
112#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
113
114/*
115 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
116 */
117#define INT_MASK_CSR 0x0204
118#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
119#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
120#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
121#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
122#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
123#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
124#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
125#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
126#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
127#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
128#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
129#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
130#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
131#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
132#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
133#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
134#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
135#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
136
137/*
138 * WPDMA_GLO_CFG
139 */
140#define WPDMA_GLO_CFG 0x0208
141#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
142#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
143#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
144#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
145#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
146#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
147#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
148#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
149#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
150
151/*
152 * WPDMA_RST_IDX
153 */
154#define WPDMA_RST_IDX 0x020c
155#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
156#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
157#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
158#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
159#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
160#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
161#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
162
163/*
164 * DELAY_INT_CFG
165 */
166#define DELAY_INT_CFG 0x0210
167#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
168#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
169#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
170#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
171#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
172#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
173
174/*
175 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
176 * AIFSN0: AC_BE
177 * AIFSN1: AC_BK
178 * AIFSN1: AC_VI
179 * AIFSN1: AC_VO
180 */
181#define WMM_AIFSN_CFG 0x0214
182#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
183#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
184#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
185#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
186
187/*
188 * WMM_CWMIN_CSR: CWmin for each EDCA AC
189 * CWMIN0: AC_BE
190 * CWMIN1: AC_BK
191 * CWMIN1: AC_VI
192 * CWMIN1: AC_VO
193 */
194#define WMM_CWMIN_CFG 0x0218
195#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
196#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
197#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
198#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
199
200/*
201 * WMM_CWMAX_CSR: CWmax for each EDCA AC
202 * CWMAX0: AC_BE
203 * CWMAX1: AC_BK
204 * CWMAX1: AC_VI
205 * CWMAX1: AC_VO
206 */
207#define WMM_CWMAX_CFG 0x021c
208#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
209#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
210#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
211#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
212
213/*
214 * AC_TXOP0: AC_BK/AC_BE TXOP register
215 * AC0TXOP: AC_BK in unit of 32us
216 * AC1TXOP: AC_BE in unit of 32us
217 */
218#define WMM_TXOP0_CFG 0x0220
219#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
220#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
221
222/*
223 * AC_TXOP1: AC_VO/AC_VI TXOP register
224 * AC2TXOP: AC_VI in unit of 32us
225 * AC3TXOP: AC_VO in unit of 32us
226 */
227#define WMM_TXOP1_CFG 0x0224
228#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
229#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
230
231/*
232 * GPIO_CTRL_CFG:
233 */
234#define GPIO_CTRL_CFG 0x0228
235#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
236#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
237#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
238#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
239#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
240#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
241#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
242#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
243#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
244
245/*
246 * MCU_CMD_CFG
247 */
248#define MCU_CMD_CFG 0x022c
249
250/*
251 * AC_BK register offsets
252 */
253#define TX_BASE_PTR0 0x0230
254#define TX_MAX_CNT0 0x0234
255#define TX_CTX_IDX0 0x0238
256#define TX_DTX_IDX0 0x023c
257
258/*
259 * AC_BE register offsets
260 */
261#define TX_BASE_PTR1 0x0240
262#define TX_MAX_CNT1 0x0244
263#define TX_CTX_IDX1 0x0248
264#define TX_DTX_IDX1 0x024c
265
266/*
267 * AC_VI register offsets
268 */
269#define TX_BASE_PTR2 0x0250
270#define TX_MAX_CNT2 0x0254
271#define TX_CTX_IDX2 0x0258
272#define TX_DTX_IDX2 0x025c
273
274/*
275 * AC_VO register offsets
276 */
277#define TX_BASE_PTR3 0x0260
278#define TX_MAX_CNT3 0x0264
279#define TX_CTX_IDX3 0x0268
280#define TX_DTX_IDX3 0x026c
281
282/*
283 * HCCA register offsets
284 */
285#define TX_BASE_PTR4 0x0270
286#define TX_MAX_CNT4 0x0274
287#define TX_CTX_IDX4 0x0278
288#define TX_DTX_IDX4 0x027c
289
290/*
291 * MGMT register offsets
292 */
293#define TX_BASE_PTR5 0x0280
294#define TX_MAX_CNT5 0x0284
295#define TX_CTX_IDX5 0x0288
296#define TX_DTX_IDX5 0x028c
297
298/*
299 * RX register offsets
300 */
301#define RX_BASE_PTR 0x0290
302#define RX_MAX_CNT 0x0294
303#define RX_CRX_IDX 0x0298
304#define RX_DRX_IDX 0x029c
305
306/*
307 * USB_DMA_CFG
308 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
309 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
310 * PHY_CLEAR: phy watch dog enable.
311 * TX_CLEAR: Clear USB DMA TX path.
312 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
313 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
314 * RX_BULK_EN: Enable USB DMA Rx.
315 * TX_BULK_EN: Enable USB DMA Tx.
316 * EP_OUT_VALID: OUT endpoint data valid.
317 * RX_BUSY: USB DMA RX FSM busy.
318 * TX_BUSY: USB DMA TX FSM busy.
319 */
320#define USB_DMA_CFG 0x02a0
321#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
322#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
323#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
324#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
325#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
326#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
327#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
328#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
329#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
330#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
331#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
332
333/*
334 * USB_CYC_CFG
335 */
336#define USB_CYC_CFG 0x02a4
337#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
338
339/*
340 * PBF_SYS_CTRL
341 * HOST_RAM_WRITE: enable Host program ram write selection
342 */
343#define PBF_SYS_CTRL 0x0400
344#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
345#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
346
347/*
348 * PBF registers
349 * Most are for debug. Driver doesn't touch PBF register.
350 */
351#define PBF_CFG 0x0408
352#define PBF_MAX_PCNT 0x040c
353#define PBF_CTRL 0x0410
354#define PBF_INT_STA 0x0414
355#define PBF_INT_ENA 0x0418
356
357/*
358 * BCN_OFFSET0:
359 */
360#define BCN_OFFSET0 0x042c
361#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
362#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
363#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
364#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
365
366/*
367 * BCN_OFFSET1:
368 */
369#define BCN_OFFSET1 0x0430
370#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
371#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
372#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
373#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
374
375/*
376 * PBF registers
377 * Most are for debug. Driver doesn't touch PBF register.
378 */
379#define TXRXQ_PCNT 0x0438
380#define PBF_DBG 0x043c
381
382/*
383 * RF registers
384 */
385#define RF_CSR_CFG 0x0500
386#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
387#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
388#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
389#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
390
391/*
392 * MAC Control/Status Registers(CSR).
393 * Some values are set in TU, whereas 1 TU == 1024 us.
394 */
395
396/*
397 * MAC_CSR0: ASIC revision number.
398 * ASIC_REV: 0
399 * ASIC_VER: 2870
400 */
401#define MAC_CSR0 0x1000
402#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
403#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
404
405/*
406 * MAC_SYS_CTRL:
407 */
408#define MAC_SYS_CTRL 0x1004
409#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
410#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
411#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
412#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
413#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
414#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
415#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
416#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
417
418/*
419 * MAC_ADDR_DW0: STA MAC register 0
420 */
421#define MAC_ADDR_DW0 0x1008
422#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
423#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
424#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
425#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
426
427/*
428 * MAC_ADDR_DW1: STA MAC register 1
429 * UNICAST_TO_ME_MASK:
430 * Used to mask off bits from byte 5 of the MAC address
431 * to determine the UNICAST_TO_ME bit for RX frames.
432 * The full mask is complemented by BSS_ID_MASK:
433 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
434 */
435#define MAC_ADDR_DW1 0x100c
436#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
437#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
438#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
439
440/*
441 * MAC_BSSID_DW0: BSSID register 0
442 */
443#define MAC_BSSID_DW0 0x1010
444#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
445#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
446#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
447#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
448
449/*
450 * MAC_BSSID_DW1: BSSID register 1
451 * BSS_ID_MASK:
452 * 0: 1-BSSID mode (BSS index = 0)
453 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
454 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
455 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
456 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
457 * BSSID. This will make sure that those bits will be ignored
458 * when determining the MY_BSS of RX frames.
459 */
460#define MAC_BSSID_DW1 0x1014
461#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
462#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
463#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
464#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
465
466/*
467 * MAX_LEN_CFG: Maximum frame length register.
468 * MAX_MPDU: rt2860b max 16k bytes
469 * MAX_PSDU: Maximum PSDU length
470 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
471 */
472#define MAX_LEN_CFG 0x1018
473#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
474#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
475#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
476#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
477
478/*
479 * BBP_CSR_CFG: BBP serial control register
480 * VALUE: Register value to program into BBP
481 * REG_NUM: Selected BBP register
482 * READ_CONTROL: 0 write BBP, 1 read BBP
483 * BUSY: ASIC is busy executing BBP commands
484 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
485 * BBP_RW_MODE: 0 serial, 1 paralell
486 */
487#define BBP_CSR_CFG 0x101c
488#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
489#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
490#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
491#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
492#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
493#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
494
495/*
496 * RF_CSR_CFG0: RF control register
497 * REGID_AND_VALUE: Register value to program into RF
498 * BITWIDTH: Selected RF register
499 * STANDBYMODE: 0 high when standby, 1 low when standby
500 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
501 * BUSY: ASIC is busy executing RF commands
502 */
503#define RF_CSR_CFG0 0x1020
504#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
505#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
506#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
507#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
508#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
509#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
510
511/*
512 * RF_CSR_CFG1: RF control register
513 * REGID_AND_VALUE: Register value to program into RF
514 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
515 * 0: 3 system clock cycle (37.5usec)
516 * 1: 5 system clock cycle (62.5usec)
517 */
518#define RF_CSR_CFG1 0x1024
519#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
520#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
521
522/*
523 * RF_CSR_CFG2: RF control register
524 * VALUE: Register value to program into RF
525 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
526 * 0: 3 system clock cycle (37.5usec)
527 * 1: 5 system clock cycle (62.5usec)
528 */
529#define RF_CSR_CFG2 0x1028
530#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
531
532/*
533 * LED_CFG: LED control
534 * color LED's:
535 * 0: off
536 * 1: blinking upon TX2
537 * 2: periodic slow blinking
538 * 3: always on
539 * LED polarity:
540 * 0: active low
541 * 1: active high
542 */
543#define LED_CFG 0x102c
544#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
545#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
546#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
547#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
548#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
549#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
550#define LED_CFG_LED_POLAR FIELD32(0x40000000)
551
552/*
553 * XIFS_TIME_CFG: MAC timing
554 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
555 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
556 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
557 * when MAC doesn't reference BBP signal BBRXEND
558 * EIFS: unit 1us
559 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
560 *
561 */
562#define XIFS_TIME_CFG 0x1100
563#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
564#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
565#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
566#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
567#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
568
569/*
570 * BKOFF_SLOT_CFG:
571 */
572#define BKOFF_SLOT_CFG 0x1104
573#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
574#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
575
576/*
577 * NAV_TIME_CFG:
578 */
579#define NAV_TIME_CFG 0x1108
580#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
581#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
582#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
583#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
584
585/*
586 * CH_TIME_CFG: count as channel busy
587 */
588#define CH_TIME_CFG 0x110c
589
590/*
591 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
592 */
593#define PBF_LIFE_TIMER 0x1110
594
595/*
596 * BCN_TIME_CFG:
597 * BEACON_INTERVAL: in unit of 1/16 TU
598 * TSF_TICKING: Enable TSF auto counting
599 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
600 * BEACON_GEN: Enable beacon generator
601 */
602#define BCN_TIME_CFG 0x1114
603#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
604#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
605#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
606#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
607#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
608#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
609
610/*
611 * TBTT_SYNC_CFG:
612 */
613#define TBTT_SYNC_CFG 0x1118
614
615/*
616 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
617 */
618#define TSF_TIMER_DW0 0x111c
619#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
620
621/*
622 * TSF_TIMER_DW1: Local msb TSF timer, read-only
623 */
624#define TSF_TIMER_DW1 0x1120
625#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
626
627/*
628 * TBTT_TIMER: TImer remains till next TBTT, read-only
629 */
630#define TBTT_TIMER 0x1124
631
632/*
633 * INT_TIMER_CFG:
634 */
635#define INT_TIMER_CFG 0x1128
636
637/*
638 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
639 */
640#define INT_TIMER_EN 0x112c
641
642/*
643 * CH_IDLE_STA: channel idle time
644 */
645#define CH_IDLE_STA 0x1130
646
647/*
648 * CH_BUSY_STA: channel busy time
649 */
650#define CH_BUSY_STA 0x1134
651
652/*
653 * MAC_STATUS_CFG:
654 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
655 * if 1 or higher one of the 2 registers is busy.
656 */
657#define MAC_STATUS_CFG 0x1200
658#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
659
660/*
661 * PWR_PIN_CFG:
662 */
663#define PWR_PIN_CFG 0x1204
664
665/*
666 * AUTOWAKEUP_CFG: Manual power control / status register
667 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
668 * AUTOWAKE: 0:sleep, 1:awake
669 */
670#define AUTOWAKEUP_CFG 0x1208
671#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
672#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
673#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
674
675/*
676 * EDCA_AC0_CFG:
677 */
678#define EDCA_AC0_CFG 0x1300
679#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
680#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
681#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
682#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
683
684/*
685 * EDCA_AC1_CFG:
686 */
687#define EDCA_AC1_CFG 0x1304
688#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
689#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
690#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
691#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
692
693/*
694 * EDCA_AC2_CFG:
695 */
696#define EDCA_AC2_CFG 0x1308
697#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
698#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
699#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
700#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
701
702/*
703 * EDCA_AC3_CFG:
704 */
705#define EDCA_AC3_CFG 0x130c
706#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
707#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
708#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
709#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
710
711/*
712 * EDCA_TID_AC_MAP:
713 */
714#define EDCA_TID_AC_MAP 0x1310
715
716/*
717 * TX_PWR_CFG_0:
718 */
719#define TX_PWR_CFG_0 0x1314
720#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
721#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
722#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
723#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
724#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
725#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
726#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
727#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
728
729/*
730 * TX_PWR_CFG_1:
731 */
732#define TX_PWR_CFG_1 0x1318
733#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
734#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
735#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
736#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
737#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
738#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
739#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
740#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
741
742/*
743 * TX_PWR_CFG_2:
744 */
745#define TX_PWR_CFG_2 0x131c
746#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
747#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
748#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
749#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
750#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
751#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
752#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
753#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
754
755/*
756 * TX_PWR_CFG_3:
757 */
758#define TX_PWR_CFG_3 0x1320
759#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
760#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
761#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
762#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
763#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
764#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
765#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
766#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
767
768/*
769 * TX_PWR_CFG_4:
770 */
771#define TX_PWR_CFG_4 0x1324
772#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
773#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
774#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
775#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
776
777/*
778 * TX_PIN_CFG:
779 */
780#define TX_PIN_CFG 0x1328
781#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
782#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
783#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
784#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
785#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
786#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
787#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
788#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
789#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
790#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
791#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
792#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
793#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
794#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
795#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
796#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
797#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
798#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
799#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
800#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
801
802/*
803 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
804 */
805#define TX_BAND_CFG 0x132c
806#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
807#define TX_BAND_CFG_A FIELD32(0x00000002)
808#define TX_BAND_CFG_BG FIELD32(0x00000004)
809
810/*
811 * TX_SW_CFG0:
812 */
813#define TX_SW_CFG0 0x1330
814
815/*
816 * TX_SW_CFG1:
817 */
818#define TX_SW_CFG1 0x1334
819
820/*
821 * TX_SW_CFG2:
822 */
823#define TX_SW_CFG2 0x1338
824
825/*
826 * TXOP_THRES_CFG:
827 */
828#define TXOP_THRES_CFG 0x133c
829
830/*
831 * TXOP_CTRL_CFG:
832 */
833#define TXOP_CTRL_CFG 0x1340
834
835/*
836 * TX_RTS_CFG:
837 * RTS_THRES: unit:byte
838 * RTS_FBK_EN: enable rts rate fallback
839 */
840#define TX_RTS_CFG 0x1344
841#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
842#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
843#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
844
845/*
846 * TX_TIMEOUT_CFG:
847 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
848 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
849 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
850 * it is recommended that:
851 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
852 */
853#define TX_TIMEOUT_CFG 0x1348
854#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
855#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
856#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
857
858/*
859 * TX_RTY_CFG:
860 * SHORT_RTY_LIMIT: short retry limit
861 * LONG_RTY_LIMIT: long retry limit
862 * LONG_RTY_THRE: Long retry threshoold
863 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
864 * 0:expired by retry limit, 1: expired by mpdu life timer
865 * AGG_RTY_MODE: Aggregate MPDU retry mode
866 * 0:expired by retry limit, 1: expired by mpdu life timer
867 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
868 */
869#define TX_RTY_CFG 0x134c
870#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
871#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
872#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
873#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
874#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
875#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
876
877/*
878 * TX_LINK_CFG:
879 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
880 * MFB_ENABLE: TX apply remote MFB 1:enable
881 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
882 * 0: not apply remote remote unsolicit (MFS=7)
883 * TX_MRQ_EN: MCS request TX enable
884 * TX_RDG_EN: RDG TX enable
885 * TX_CF_ACK_EN: Piggyback CF-ACK enable
886 * REMOTE_MFB: remote MCS feedback
887 * REMOTE_MFS: remote MCS feedback sequence number
888 */
889#define TX_LINK_CFG 0x1350
890#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
891#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
892#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
893#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
894#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
895#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
896#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
897#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
898
899/*
900 * HT_FBK_CFG0:
901 */
902#define HT_FBK_CFG0 0x1354
903#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
904#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
905#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
906#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
907#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
908#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
909#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
910#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
911
912/*
913 * HT_FBK_CFG1:
914 */
915#define HT_FBK_CFG1 0x1358
916#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
917#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
918#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
919#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
920#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
921#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
922#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
923#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
924
925/*
926 * LG_FBK_CFG0:
927 */
928#define LG_FBK_CFG0 0x135c
929#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
930#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
931#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
932#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
933#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
934#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
935#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
936#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
937
938/*
939 * LG_FBK_CFG1:
940 */
941#define LG_FBK_CFG1 0x1360
942#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
943#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
944#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
945#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
946
947/*
948 * CCK_PROT_CFG: CCK Protection
949 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
950 * PROTECT_CTRL: Protection control frame type for CCK TX
951 * 0:none, 1:RTS/CTS, 2:CTS-to-self
952 * PROTECT_NAV: TXOP protection type for CCK TX
953 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
954 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
955 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
956 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
957 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
958 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
959 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
960 * RTS_TH_EN: RTS threshold enable on CCK TX
961 */
962#define CCK_PROT_CFG 0x1364
963#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
964#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
965#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
966#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
967#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
968#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
969#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
970#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
971#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
972#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
973
974/*
975 * OFDM_PROT_CFG: OFDM Protection
976 */
977#define OFDM_PROT_CFG 0x1368
978#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
979#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
980#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
981#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
982#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
983#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
984#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
985#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
986#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
987#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
988
989/*
990 * MM20_PROT_CFG: MM20 Protection
991 */
992#define MM20_PROT_CFG 0x136c
993#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
994#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
995#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
996#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
997#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
998#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
999#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1000#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1001#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1002#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1003
1004/*
1005 * MM40_PROT_CFG: MM40 Protection
1006 */
1007#define MM40_PROT_CFG 0x1370
1008#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1009#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1010#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1011#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1012#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1013#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1014#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1015#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1016#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1017#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1018
1019/*
1020 * GF20_PROT_CFG: GF20 Protection
1021 */
1022#define GF20_PROT_CFG 0x1374
1023#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1024#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1025#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1026#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1027#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1028#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1029#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1030#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1031#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1032#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1033
1034/*
1035 * GF40_PROT_CFG: GF40 Protection
1036 */
1037#define GF40_PROT_CFG 0x1378
1038#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1039#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1040#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1041#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1042#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1043#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1044#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1045#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1046#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1047#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1048
1049/*
1050 * EXP_CTS_TIME:
1051 */
1052#define EXP_CTS_TIME 0x137c
1053
1054/*
1055 * EXP_ACK_TIME:
1056 */
1057#define EXP_ACK_TIME 0x1380
1058
1059/*
1060 * RX_FILTER_CFG: RX configuration register.
1061 */
1062#define RX_FILTER_CFG 0x1400
1063#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1064#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1065#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1066#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1067#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1068#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1069#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1070#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1071#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1072#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1073#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1074#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1075#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1076#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1077#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1078#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1079#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1080
1081/*
1082 * AUTO_RSP_CFG:
1083 * AUTORESPONDER: 0: disable, 1: enable
1084 * BAC_ACK_POLICY: 0:long, 1:short preamble
1085 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1086 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1087 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1088 * DUAL_CTS_EN: Power bit value in control frame
1089 * ACK_CTS_PSM_BIT:Power bit value in control frame
1090 */
1091#define AUTO_RSP_CFG 0x1404
1092#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1093#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1094#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1095#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1096#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1097#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1098#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1099
1100/*
1101 * LEGACY_BASIC_RATE:
1102 */
1103#define LEGACY_BASIC_RATE 0x1408
1104
1105/*
1106 * HT_BASIC_RATE:
1107 */
1108#define HT_BASIC_RATE 0x140c
1109
1110/*
1111 * HT_CTRL_CFG:
1112 */
1113#define HT_CTRL_CFG 0x1410
1114
1115/*
1116 * SIFS_COST_CFG:
1117 */
1118#define SIFS_COST_CFG 0x1414
1119
1120/*
1121 * RX_PARSER_CFG:
1122 * Set NAV for all received frames
1123 */
1124#define RX_PARSER_CFG 0x1418
1125
1126/*
1127 * TX_SEC_CNT0:
1128 */
1129#define TX_SEC_CNT0 0x1500
1130
1131/*
1132 * RX_SEC_CNT0:
1133 */
1134#define RX_SEC_CNT0 0x1504
1135
1136/*
1137 * CCMP_FC_MUTE:
1138 */
1139#define CCMP_FC_MUTE 0x1508
1140
1141/*
1142 * TXOP_HLDR_ADDR0:
1143 */
1144#define TXOP_HLDR_ADDR0 0x1600
1145
1146/*
1147 * TXOP_HLDR_ADDR1:
1148 */
1149#define TXOP_HLDR_ADDR1 0x1604
1150
1151/*
1152 * TXOP_HLDR_ET:
1153 */
1154#define TXOP_HLDR_ET 0x1608
1155
1156/*
1157 * QOS_CFPOLL_RA_DW0:
1158 */
1159#define QOS_CFPOLL_RA_DW0 0x160c
1160
1161/*
1162 * QOS_CFPOLL_RA_DW1:
1163 */
1164#define QOS_CFPOLL_RA_DW1 0x1610
1165
1166/*
1167 * QOS_CFPOLL_QC:
1168 */
1169#define QOS_CFPOLL_QC 0x1614
1170
1171/*
1172 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1173 */
1174#define RX_STA_CNT0 0x1700
1175#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1176#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1177
1178/*
1179 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1180 */
1181#define RX_STA_CNT1 0x1704
1182#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1183#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1184
1185/*
1186 * RX_STA_CNT2:
1187 */
1188#define RX_STA_CNT2 0x1708
1189#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1190#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1191
1192/*
1193 * TX_STA_CNT0: TX Beacon count
1194 */
1195#define TX_STA_CNT0 0x170c
1196#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1197#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1198
1199/*
1200 * TX_STA_CNT1: TX tx count
1201 */
1202#define TX_STA_CNT1 0x1710
1203#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1204#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1205
1206/*
1207 * TX_STA_CNT2: TX tx count
1208 */
1209#define TX_STA_CNT2 0x1714
1210#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1211#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1212
1213/*
1214 * TX_STA_FIFO: TX Result for specific PID status fifo register
1215 */
1216#define TX_STA_FIFO 0x1718
1217#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1218#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1219#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1220#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1221#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1222#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1223#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1224
1225/*
1226 * TX_AGG_CNT: Debug counter
1227 */
1228#define TX_AGG_CNT 0x171c
1229#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1230#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1231
1232/*
1233 * TX_AGG_CNT0:
1234 */
1235#define TX_AGG_CNT0 0x1720
1236#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1237#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1238
1239/*
1240 * TX_AGG_CNT1:
1241 */
1242#define TX_AGG_CNT1 0x1724
1243#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1244#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1245
1246/*
1247 * TX_AGG_CNT2:
1248 */
1249#define TX_AGG_CNT2 0x1728
1250#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1251#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1252
1253/*
1254 * TX_AGG_CNT3:
1255 */
1256#define TX_AGG_CNT3 0x172c
1257#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1258#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1259
1260/*
1261 * TX_AGG_CNT4:
1262 */
1263#define TX_AGG_CNT4 0x1730
1264#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1265#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1266
1267/*
1268 * TX_AGG_CNT5:
1269 */
1270#define TX_AGG_CNT5 0x1734
1271#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1272#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1273
1274/*
1275 * TX_AGG_CNT6:
1276 */
1277#define TX_AGG_CNT6 0x1738
1278#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1279#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1280
1281/*
1282 * TX_AGG_CNT7:
1283 */
1284#define TX_AGG_CNT7 0x173c
1285#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1286#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1287
1288/*
1289 * MPDU_DENSITY_CNT:
1290 * TX_ZERO_DEL: TX zero length delimiter count
1291 * RX_ZERO_DEL: RX zero length delimiter count
1292 */
1293#define MPDU_DENSITY_CNT 0x1740
1294#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1295#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1296
1297/*
1298 * Security key table memory.
1299 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1300 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1301 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1302 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1303 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1304 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1305 */
1306#define MAC_WCID_BASE 0x1800
1307#define PAIRWISE_KEY_TABLE_BASE 0x4000
1308#define MAC_IVEIV_TABLE_BASE 0x6000
1309#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1310#define SHARED_KEY_TABLE_BASE 0x6c00
1311#define SHARED_KEY_MODE_BASE 0x7000
1312
1313#define MAC_WCID_ENTRY(__idx) \
1314 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1315#define PAIRWISE_KEY_ENTRY(__idx) \
1316 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1317#define MAC_IVEIV_ENTRY(__idx) \
1318 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1319#define MAC_WCID_ATTR_ENTRY(__idx) \
1320 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1321#define SHARED_KEY_ENTRY(__idx) \
1322 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1323#define SHARED_KEY_MODE_ENTRY(__idx) \
1324 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1325
1326struct mac_wcid_entry {
1327 u8 mac[6];
1328 u8 reserved[2];
1329} __attribute__ ((packed));
1330
1331struct hw_key_entry {
1332 u8 key[16];
1333 u8 tx_mic[8];
1334 u8 rx_mic[8];
1335} __attribute__ ((packed));
1336
1337struct mac_iveiv_entry {
1338 u8 iv[8];
1339} __attribute__ ((packed));
1340
1341/*
1342 * MAC_WCID_ATTRIBUTE:
1343 */
1344#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1345#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1346#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1347#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1348
1349/*
1350 * SHARED_KEY_MODE:
1351 */
1352#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1353#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1354#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1355#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1356#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1357#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1358#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1359#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1360
1361/*
1362 * HOST-MCU communication
1363 */
1364
1365/*
1366 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1367 */
1368#define H2M_MAILBOX_CSR 0x7010
1369#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1370#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1371#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1372#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1373
1374/*
1375 * H2M_MAILBOX_CID:
1376 */
1377#define H2M_MAILBOX_CID 0x7014
1378
1379/*
1380 * H2M_MAILBOX_STATUS:
1381 */
1382#define H2M_MAILBOX_STATUS 0x701c
1383
1384/*
1385 * H2M_INT_SRC:
1386 */
1387#define H2M_INT_SRC 0x7024
1388
1389/*
1390 * H2M_BBP_AGENT:
1391 */
1392#define H2M_BBP_AGENT 0x7028
1393
1394/*
1395 * MCU_LEDCS: LED control for MCU Mailbox.
1396 */
1397#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1398#define MCU_LEDCS_POLARITY FIELD8(0x01)
1399
1400/*
1401 * HW_CS_CTS_BASE:
1402 * Carrier-sense CTS frame base address.
1403 * It's where mac stores carrier-sense frame for carrier-sense function.
1404 */
1405#define HW_CS_CTS_BASE 0x7700
1406
1407/*
1408 * HW_DFS_CTS_BASE:
1409 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1410 */
1411#define HW_DFS_CTS_BASE 0x7780
1412
1413/*
1414 * TXRX control registers - base address 0x3000
1415 */
1416
1417/*
1418 * TXRX_CSR1:
1419 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1420 */
1421#define TXRX_CSR1 0x77d0
1422
1423/*
1424 * HW_DEBUG_SETTING_BASE:
1425 * since NULL frame won't be that long (256 byte)
1426 * We steal 16 tail bytes to save debugging settings
1427 */
1428#define HW_DEBUG_SETTING_BASE 0x77f0
1429#define HW_DEBUG_SETTING_BASE2 0x7770
1430
1431/*
1432 * HW_BEACON_BASE
1433 * In order to support maximum 8 MBSS and its maximum length
1434 * is 512 bytes for each beacon
1435 * Three section discontinue memory segments will be used.
1436 * 1. The original region for BCN 0~3
1437 * 2. Extract memory from FCE table for BCN 4~5
1438 * 3. Extract memory from Pair-wise key table for BCN 6~7
1439 * It occupied those memory of wcid 238~253 for BCN 6
1440 * and wcid 222~237 for BCN 7
1441 *
1442 * IMPORTANT NOTE: Not sure why legacy driver does this,
1443 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1444 */
1445#define HW_BEACON_BASE0 0x7800
1446#define HW_BEACON_BASE1 0x7a00
1447#define HW_BEACON_BASE2 0x7c00
1448#define HW_BEACON_BASE3 0x7e00
1449#define HW_BEACON_BASE4 0x7200
1450#define HW_BEACON_BASE5 0x7400
1451#define HW_BEACON_BASE6 0x5dc0
1452#define HW_BEACON_BASE7 0x5bc0
1453
1454#define HW_BEACON_OFFSET(__index) \
1455 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1456 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1457 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1458
1459/*
1460 * 8051 firmware image.
1461 */
1462#define FIRMWARE_RT2870 "rt2870.bin"
1463#define FIRMWARE_IMAGE_BASE 0x3000
1464
1465/*
1466 * BBP registers.
1467 * The wordsize of the BBP is 8 bits.
1468 */
1469
1470/*
1471 * BBP 1: TX Antenna
1472 */
1473#define BBP1_TX_POWER FIELD8(0x07)
1474#define BBP1_TX_ANTENNA FIELD8(0x18)
1475
1476/*
1477 * BBP 3: RX Antenna
1478 */
1479#define BBP3_RX_ANTENNA FIELD8(0x18)
1480#define BBP3_HT40_PLUS FIELD8(0x20)
1481
1482/*
1483 * BBP 4: Bandwidth
1484 */
1485#define BBP4_TX_BF FIELD8(0x01)
1486#define BBP4_BANDWIDTH FIELD8(0x18)
1487
1488/*
1489 * RFCSR registers
1490 * The wordsize of the RFCSR is 8 bits.
1491 */
1492
1493/*
1494 * RFCSR 6:
1495 */
1496#define RFCSR6_R FIELD8(0x03)
1497
1498/*
1499 * RFCSR 7:
1500 */
1501#define RFCSR7_RF_TUNING FIELD8(0x01)
1502
1503/*
1504 * RFCSR 12:
1505 */
1506#define RFCSR12_TX_POWER FIELD8(0x1f)
1507
1508/*
1509 * RFCSR 22:
1510 */
1511#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1512
1513/*
1514 * RFCSR 23:
1515 */
1516#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1517
1518/*
1519 * RFCSR 30:
1520 */
1521#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1522
1523/*
1524 * RF registers
1525 */
1526
1527/*
1528 * RF 2
1529 */
1530#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1531#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1532#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1533
1534/*
1535 * RF 3
1536 */
1537#define RF3_TXPOWER_G FIELD32(0x00003e00)
1538#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1539#define RF3_TXPOWER_A FIELD32(0x00003c00)
1540
1541/*
1542 * RF 4
1543 */
1544#define RF4_TXPOWER_G FIELD32(0x000007c0)
1545#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1546#define RF4_TXPOWER_A FIELD32(0x00000780)
1547#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1548#define RF4_HT40 FIELD32(0x00200000)
1549
1550/*
1551 * EEPROM content.
1552 * The wordsize of the EEPROM is 16 bits.
1553 */
1554
1555/*
1556 * EEPROM Version
1557 */
1558#define EEPROM_VERSION 0x0001
1559#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1560#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1561
1562/*
1563 * HW MAC address.
1564 */
1565#define EEPROM_MAC_ADDR_0 0x0002
1566#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1567#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1568#define EEPROM_MAC_ADDR_1 0x0003
1569#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1570#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1571#define EEPROM_MAC_ADDR_2 0x0004
1572#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1573#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1574
1575/*
1576 * EEPROM ANTENNA config
1577 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1578 * TXPATH: 1: 1T, 2: 2T
1579 */
1580#define EEPROM_ANTENNA 0x001a
1581#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1582#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1583#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1584
1585/*
1586 * EEPROM NIC config
1587 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1588 */
1589#define EEPROM_NIC 0x001b
1590#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1591#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1592#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1593#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1594#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1595#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1596#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1597#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1598#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1599#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1600
1601/*
1602 * EEPROM frequency
1603 */
1604#define EEPROM_FREQ 0x001d
1605#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1606#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1607#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1608
1609/*
1610 * EEPROM LED
1611 * POLARITY_RDY_G: Polarity RDY_G setting.
1612 * POLARITY_RDY_A: Polarity RDY_A setting.
1613 * POLARITY_ACT: Polarity ACT setting.
1614 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1615 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1616 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1617 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1618 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1619 * LED_MODE: Led mode.
1620 */
1621#define EEPROM_LED1 0x001e
1622#define EEPROM_LED2 0x001f
1623#define EEPROM_LED3 0x0020
1624#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1625#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1626#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1627#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1628#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1629#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1630#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1631#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1632#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1633
1634/*
1635 * EEPROM LNA
1636 */
1637#define EEPROM_LNA 0x0022
1638#define EEPROM_LNA_BG FIELD16(0x00ff)
1639#define EEPROM_LNA_A0 FIELD16(0xff00)
1640
1641/*
1642 * EEPROM RSSI BG offset
1643 */
1644#define EEPROM_RSSI_BG 0x0023
1645#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1646#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1647
1648/*
1649 * EEPROM RSSI BG2 offset
1650 */
1651#define EEPROM_RSSI_BG2 0x0024
1652#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1653#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1654
1655/*
1656 * EEPROM RSSI A offset
1657 */
1658#define EEPROM_RSSI_A 0x0025
1659#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1660#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1661
1662/*
1663 * EEPROM RSSI A2 offset
1664 */
1665#define EEPROM_RSSI_A2 0x0026
1666#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1667#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1668
1669/*
1670 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1671 * This is delta in 40MHZ.
1672 * VALUE: Tx Power dalta value (MAX=4)
1673 * TYPE: 1: Plus the delta value, 0: minus the delta value
1674 * TXPOWER: Enable:
1675 */
1676#define EEPROM_TXPOWER_DELTA 0x0028
1677#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1678#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1679#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1680
1681/*
1682 * EEPROM TXPOWER 802.11BG
1683 */
1684#define EEPROM_TXPOWER_BG1 0x0029
1685#define EEPROM_TXPOWER_BG2 0x0030
1686#define EEPROM_TXPOWER_BG_SIZE 7
1687#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1688#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1689
1690/*
1691 * EEPROM TXPOWER 802.11A
1692 */
1693#define EEPROM_TXPOWER_A1 0x003c
1694#define EEPROM_TXPOWER_A2 0x0053
1695#define EEPROM_TXPOWER_A_SIZE 6
1696#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1697#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1698
1699/*
1700 * EEPROM TXpower byrate: 20MHZ power
1701 */
1702#define EEPROM_TXPOWER_BYRATE 0x006f
1703
1704/*
1705 * EEPROM BBP.
1706 */
1707#define EEPROM_BBP_START 0x0078
1708#define EEPROM_BBP_SIZE 16
1709#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1710#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1711
1712/*
1713 * MCU mailbox commands.
1714 */
1715#define MCU_SLEEP 0x30
1716#define MCU_WAKEUP 0x31
1717#define MCU_RADIO_OFF 0x35
1718#define MCU_LED 0x50
1719#define MCU_LED_STRENGTH 0x51
1720#define MCU_LED_1 0x52
1721#define MCU_LED_2 0x53
1722#define MCU_LED_3 0x54
1723#define MCU_RADAR 0x60
1724#define MCU_BOOT_SIGNAL 0x72
1725#define MCU_BBP_SIGNAL 0x80
1726
1727/*
1728 * DMA descriptor defines.
1729 */
1730#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1731#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1732#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1733#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1734#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1735
1736/*
1737 * TX descriptor format for TX, PRIO and Beacon Ring.
1738 */
1739
1740/*
1741 * Word0
1742 */
1743#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
1744
1745/*
1746 * Word1
1747 */
1748#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
1749#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
1750#define TXD_W1_BURST FIELD32(0x00008000)
1751#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
1752#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
1753#define TXD_W1_DMA_DONE FIELD32(0x80000000)
1754
1755/*
1756 * Word2
1757 */
1758#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
1759
1760/*
1761 * Word3
1762 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1763 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1764 * 0:MGMT, 1:HCCA 2:EDCA
1765 */
1766#define TXD_W3_WIV FIELD32(0x01000000)
1767#define TXD_W3_QSEL FIELD32(0x06000000)
1768#define TXD_W3_TCO FIELD32(0x20000000)
1769#define TXD_W3_UCO FIELD32(0x40000000)
1770#define TXD_W3_ICO FIELD32(0x80000000)
1771
1772/*
1773 * TX Info structure
1774 */
1775
1776/*
1777 * Word0
1778 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1779 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1780 * 0:MGMT, 1:HCCA 2:EDCA
1781 * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
1782 * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
1783 * Force USB DMA transmit frame from current selected endpoint
1784 */
1785#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
1786#define TXINFO_W0_WIV FIELD32(0x01000000)
1787#define TXINFO_W0_QSEL FIELD32(0x06000000)
1788#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
1789#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
1790#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
1791
1792/*
1793 * TX WI structure
1794 */
1795
1796/*
1797 * Word0
1798 * FRAG: 1 To inform TKIP engine this is a fragment.
1799 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1800 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1801 * BW: Channel bandwidth 20MHz or 40 MHz
1802 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1803 */
1804#define TXWI_W0_FRAG FIELD32(0x00000001)
1805#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1806#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1807#define TXWI_W0_TS FIELD32(0x00000008)
1808#define TXWI_W0_AMPDU FIELD32(0x00000010)
1809#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1810#define TXWI_W0_TX_OP FIELD32(0x00000300)
1811#define TXWI_W0_MCS FIELD32(0x007f0000)
1812#define TXWI_W0_BW FIELD32(0x00800000)
1813#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1814#define TXWI_W0_STBC FIELD32(0x06000000)
1815#define TXWI_W0_IFS FIELD32(0x08000000)
1816#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1817
1818/*
1819 * Word1
1820 */
1821#define TXWI_W1_ACK FIELD32(0x00000001)
1822#define TXWI_W1_NSEQ FIELD32(0x00000002)
1823#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1824#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1825#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1826#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1827
1828/*
1829 * Word2
1830 */
1831#define TXWI_W2_IV FIELD32(0xffffffff)
1832
1833/*
1834 * Word3
1835 */
1836#define TXWI_W3_EIV FIELD32(0xffffffff)
1837
1838/*
1839 * RX descriptor format for RX Ring.
1840 */
1841
1842/*
1843 * Word0
1844 * UNICAST_TO_ME: This RX frame is unicast to me.
1845 * MULTICAST: This is a multicast frame.
1846 * BROADCAST: This is a broadcast frame.
1847 * MY_BSS: this frame belongs to the same BSSID.
1848 * CRC_ERROR: CRC error.
1849 * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
1850 * AMSDU: rx with 802.3 header, not 802.11 header.
1851 */
1852
1853#define RXD_W0_BA FIELD32(0x00000001)
1854#define RXD_W0_DATA FIELD32(0x00000002)
1855#define RXD_W0_NULLDATA FIELD32(0x00000004)
1856#define RXD_W0_FRAG FIELD32(0x00000008)
1857#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
1858#define RXD_W0_MULTICAST FIELD32(0x00000020)
1859#define RXD_W0_BROADCAST FIELD32(0x00000040)
1860#define RXD_W0_MY_BSS FIELD32(0x00000080)
1861#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
1862#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
1863#define RXD_W0_AMSDU FIELD32(0x00000800)
1864#define RXD_W0_HTC FIELD32(0x00001000)
1865#define RXD_W0_RSSI FIELD32(0x00002000)
1866#define RXD_W0_L2PAD FIELD32(0x00004000)
1867#define RXD_W0_AMPDU FIELD32(0x00008000)
1868#define RXD_W0_DECRYPTED FIELD32(0x00010000)
1869#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
1870#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
1871#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
1872#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
1873
1874/*
1875 * RX WI structure
1876 */
1877
1878/*
1879 * Word0
1880 */
1881#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1882#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1883#define RXWI_W0_BSSID FIELD32(0x00001c00)
1884#define RXWI_W0_UDF FIELD32(0x0000e000)
1885#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1886#define RXWI_W0_TID FIELD32(0xf0000000)
1887
1888/*
1889 * Word1
1890 */
1891#define RXWI_W1_FRAG FIELD32(0x0000000f)
1892#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1893#define RXWI_W1_MCS FIELD32(0x007f0000)
1894#define RXWI_W1_BW FIELD32(0x00800000)
1895#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1896#define RXWI_W1_STBC FIELD32(0x06000000)
1897#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1898
1899/*
1900 * Word2
1901 */
1902#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1903#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1904#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1905
1906/*
1907 * Word3
1908 */
1909#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1910#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1911
1912/*
1913 * Macro's for converting txpower from EEPROM to mac80211 value
1914 * and from mac80211 value to register value.
1915 */
1916#define MIN_G_TXPOWER 0
1917#define MIN_A_TXPOWER -7
1918#define MAX_G_TXPOWER 31
1919#define MAX_A_TXPOWER 15
1920#define DEFAULT_TXPOWER 5
1921
1922#define TXPOWER_G_FROM_DEV(__txpower) \
1923 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1924
1925#define TXPOWER_G_TO_DEV(__txpower) \
1926 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1927
1928#define TXPOWER_A_FROM_DEV(__txpower) \
1929 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1930
1931#define TXPOWER_A_TO_DEV(__txpower) \
1932 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1933
1934#endif /* RT2800USB_H */