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gerrit-public.fairphone.software / kernel / msm / d59fc755a3ef8947237a28f566bdef9d178c38c5 / . / sound / soc / codecs / wcd9306-tables.c
blob: 21c563602781610f07d1b7218503d833b045b543 [file] [log] [blame]
Bhalchandra Gajaredcf09f82012-11-09 11:58:26 -0800[diff] [blame]1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
2*
3* This program is free software; you can redistribute it and/or modify
4* it under the terms of the GNU General Public License version 2 and
5* only version 2 as published by the Free Software Foundation.
6*
7* This program is distributed in the hope that it will be useful,
8* but WITHOUT ANY WARRANTY; without even the implied warranty of
9* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10* GNU General Public License for more details.
11*/
12
13#include <linux/mfd/wcd9xxx/wcd9306_registers.h>
14#include "wcd9306.h"
15
16const u8 tapan_reg_readable[TAPAN_CACHE_SIZE] = {
17 [TAPAN_A_CHIP_CTL] = 1,
18 [TAPAN_A_CHIP_STATUS] = 1,
19 [TAPAN_A_CHIP_ID_BYTE_0] = 1,
20 [TAPAN_A_CHIP_ID_BYTE_1] = 1,
21 [TAPAN_A_CHIP_ID_BYTE_2] = 1,
22 [TAPAN_A_CHIP_ID_BYTE_3] = 1,
23 [TAPAN_A_CHIP_VERSION] = 1,
24 [TAPAN_A_CHIP_DEBUG_CTL] = 1,
25 [TAPAN_A_SLAVE_ID_1] = 1,
26 [TAPAN_A_SLAVE_ID_2] = 1,
27 [TAPAN_A_SLAVE_ID_3] = 1,
28 [TAPAN_A_PIN_CTL_OE0] = 1,
29 [TAPAN_A_PIN_CTL_DATA0] = 1,
30 [TAPAN_A_HDRIVE_GENERIC] = 1,
31 [TAPAN_A_HDRIVE_OVERRIDE] = 1,
32 [TAPAN_A_ANA_CSR_WAIT_STATE] = 1,
33 [TAPAN_A_PROCESS_MONITOR_CTL0] = 1,
34 [TAPAN_A_PROCESS_MONITOR_CTL1] = 1,
35 [TAPAN_A_PROCESS_MONITOR_CTL2] = 1,
36 [TAPAN_A_PROCESS_MONITOR_CTL3] = 1,
37 [TAPAN_A_QFUSE_CTL] = 1,
38 [TAPAN_A_QFUSE_STATUS] = 1,
39 [TAPAN_A_QFUSE_DATA_OUT0] = 1,
40 [TAPAN_A_QFUSE_DATA_OUT1] = 1,
41 [TAPAN_A_QFUSE_DATA_OUT2] = 1,
42 [TAPAN_A_QFUSE_DATA_OUT3] = 1,
43 [TAPAN_A_QFUSE_DATA_OUT4] = 1,
44 [TAPAN_A_QFUSE_DATA_OUT5] = 1,
45 [TAPAN_A_QFUSE_DATA_OUT6] = 1,
46 [TAPAN_A_QFUSE_DATA_OUT7] = 1,
47 [TAPAN_A_CDC_CTL] = 1,
48 [TAPAN_A_LEAKAGE_CTL] = 1,
49 [TAPAN_A_INTR_MODE] = 1,
50 [TAPAN_A_INTR_MASK0] = 1,
51 [TAPAN_A_INTR_MASK1] = 1,
52 [TAPAN_A_INTR_MASK2] = 1,
53 [TAPAN_A_INTR_MASK3] = 1,
54 [TAPAN_A_INTR_STATUS0] = 1,
55 [TAPAN_A_INTR_STATUS1] = 1,
56 [TAPAN_A_INTR_STATUS2] = 1,
57 [TAPAN_A_INTR_STATUS3] = 1,
58 [TAPAN_A_INTR_CLEAR0] = 0,
59 [TAPAN_A_INTR_CLEAR1] = 0,
60 [TAPAN_A_INTR_CLEAR2] = 0,
61 [TAPAN_A_INTR_CLEAR3] = 0,
62 [TAPAN_A_INTR_LEVEL0] = 1,
63 [TAPAN_A_INTR_LEVEL1] = 1,
64 [TAPAN_A_INTR_LEVEL2] = 1,
65 [TAPAN_A_INTR_LEVEL3] = 1,
66 [TAPAN_A_INTR_TEST0] = 1,
67 [TAPAN_A_INTR_TEST1] = 1,
68 [TAPAN_A_INTR_TEST2] = 1,
69 [TAPAN_A_INTR_TEST3] = 1,
70 [TAPAN_A_INTR_SET0] = 1,
71 [TAPAN_A_INTR_SET1] = 1,
72 [TAPAN_A_INTR_SET2] = 1,
73 [TAPAN_A_INTR_SET3] = 1,
74 [TAPAN_A_INTR_DESTN0] = 1,
75 [TAPAN_A_INTR_DESTN1] = 1,
76 [TAPAN_A_INTR_DESTN2] = 1,
77 [TAPAN_A_INTR_DESTN3] = 1,
78 [TAPAN_A_CDC_DMIC_DATA0_MODE] = 1,
79 [TAPAN_A_CDC_DMIC_CLK0_MODE] = 1,
80 [TAPAN_A_CDC_DMIC_DATA1_MODE] = 1,
81 [TAPAN_A_CDC_DMIC_CLK1_MODE] = 1,
82 [TAPAN_A_CDC_INTR_MODE] = 1,
83 [TAPAN_A_BIAS_REF_CTL] = 1,
84 [TAPAN_A_BIAS_CENTRAL_BG_CTL] = 1,
85 [TAPAN_A_BIAS_PRECHRG_CTL] = 1,
86 [TAPAN_A_BIAS_CURR_CTL_1] = 1,
87 [TAPAN_A_BIAS_CURR_CTL_2] = 1,
88 [TAPAN_A_BIAS_OSC_BG_CTL] = 1,
89 [TAPAN_A_CLK_BUFF_EN1] = 1,
90 [TAPAN_A_CLK_BUFF_EN2] = 1,
91 [TAPAN_A_LDO_H_MODE_1] = 1,
92 [TAPAN_A_LDO_H_MODE_2] = 1,
93 [TAPAN_A_LDO_H_LOOP_CTL] = 1,
94 [TAPAN_A_LDO_H_COMP_1] = 1,
95 [TAPAN_A_LDO_H_COMP_2] = 1,
96 [TAPAN_A_LDO_H_BIAS_1] = 1,
97 [TAPAN_A_LDO_H_BIAS_2] = 1,
98 [TAPAN_A_LDO_H_BIAS_3] = 1,
99 [TAPAN_A_MICB_CFILT_1_CTL] = 1,
100 [TAPAN_A_MICB_CFILT_1_VAL] = 1,
101 [TAPAN_A_MICB_CFILT_1_PRECHRG] = 1,
102 [TAPAN_A_MICB_1_CTL] = 1,
103 [TAPAN_A_MICB_1_INT_RBIAS] = 1,
104 [TAPAN_A_MICB_1_MBHC] = 1,
105 [TAPAN_A_MICB_CFILT_2_CTL] = 1,
106 [TAPAN_A_MICB_CFILT_2_VAL] = 1,
107 [TAPAN_A_MICB_CFILT_2_PRECHRG] = 1,
108 [TAPAN_A_MICB_2_CTL] = 1,
109 [TAPAN_A_MICB_2_INT_RBIAS] = 1,
110 [TAPAN_A_MICB_2_MBHC] = 1,
111 [TAPAN_A_MICB_CFILT_3_CTL] = 1,
112 [TAPAN_A_MICB_CFILT_3_VAL] = 1,
113 [TAPAN_A_MICB_CFILT_3_PRECHRG] = 1,
114 [TAPAN_A_MICB_3_CTL] = 1,
115 [TAPAN_A_MICB_3_INT_RBIAS] = 1,
116 [TAPAN_A_MICB_3_MBHC] = 1,
117 [TAPAN_A_MBHC_INSERT_DETECT] = 1,
118 [TAPAN_A_MBHC_INSERT_DET_STATUS] = 1,
119 [TAPAN_A_TX_COM_BIAS] = 1,
120 [TAPAN_A_MBHC_SCALING_MUX_1] = 1,
121 [TAPAN_A_MBHC_SCALING_MUX_2] = 1,
122 [TAPAN_A_RESERVED_MAD_ANA_CTRL] = 1,
123 [TAPAN_A_TX_SUP_SWITCH_CTRL_1] = 1,
124 [TAPAN_A_TX_SUP_SWITCH_CTRL_2] = 1,
125 [TAPAN_A_TX_1_EN] = 1,
126 [TAPAN_A_TX_2_EN] = 1,
127 [TAPAN_A_TX_1_2_ADC_CH1] = 1,
128 [TAPAN_A_TX_1_2_ADC_CH2] = 1,
129 [TAPAN_A_TX_1_2_ATEST_REFCTRL] = 1,
130 [TAPAN_A_TX_1_2_TEST_CTL] = 1,
131 [TAPAN_A_TX_1_2_TEST_BLOCK_EN] = 1,
132 [TAPAN_A_TX_1_2_TXFE_CLKDIV] = 1,
133 [TAPAN_A_TX_1_2_SAR_ERR_CH1] = 1,
134 [TAPAN_A_TX_1_2_SAR_ERR_CH2] = 1,
135 [TAPAN_A_TX_3_EN] = 1,
136 [TAPAN_A_TX_1_2_TEST_EN] = 1,
137 [TAPAN_A_TX_4_5_TXFE_SC_CTL] = 1,
138 [TAPAN_A_TX_4_5_TEST_EN] = 1,
139 [TAPAN_A_TX_4_EN] = 1,
140 [TAPAN_A_TX_5_EN] = 1,
141 [TAPAN_A_TX_4_5_ADC_CH4] = 1,
142 [TAPAN_A_TX_4_5_ADC_CH5] = 1,
143 [TAPAN_A_TX_4_5_ATEST_REFCTRL] = 1,
144 [TAPAN_A_TX_4_5_TEST_CTL] = 1,
145 [TAPAN_A_TX_4_5_TEST_BLOCK_EN] = 1,
146 [TAPAN_A_TX_4_5_TXFE_CKDIV] = 1,
147 [TAPAN_A_TX_4_5_SAR_ERR_CH4] = 1,
148 [TAPAN_A_TX_4_5_SAR_ERR_CH5] = 1,
149 [TAPAN_A_TX_7_MBHC_EN] = 1,
150 [TAPAN_A_TX_7_MBHC_ATEST_REFCTRL] = 1,
151 [TAPAN_A_TX_7_MBHC_ADC] = 1,
152 [TAPAN_A_TX_7_MBHC_TEST_CTL] = 1,
153 [TAPAN_A_TX_7_MBHC_SAR_ERR] = 1,
154 [TAPAN_A_TX_7_TXFE_CLKDIV] = 1,
155 [TAPAN_A_BUCK_MODE_1] = 1,
156 [TAPAN_A_BUCK_MODE_2] = 1,
157 [TAPAN_A_BUCK_MODE_3] = 1,
158 [TAPAN_A_BUCK_MODE_4] = 1,
159 [TAPAN_A_BUCK_MODE_5] = 1,
160 [TAPAN_A_BUCK_CTRL_VCL_1] = 1,
161 [TAPAN_A_BUCK_CTRL_VCL_2] = 1,
162 [TAPAN_A_BUCK_CTRL_VCL_3] = 1,
163 [TAPAN_A_BUCK_CTRL_CCL_1] = 1,
164 [TAPAN_A_BUCK_CTRL_CCL_2] = 1,
165 [TAPAN_A_BUCK_CTRL_CCL_3] = 1,
166 [TAPAN_A_BUCK_CTRL_CCL_4] = 1,
167 [TAPAN_A_BUCK_CTRL_PWM_DRVR_1] = 1,
168 [TAPAN_A_BUCK_CTRL_PWM_DRVR_2] = 1,
169 [TAPAN_A_BUCK_CTRL_PWM_DRVR_3] = 1,
170 [TAPAN_A_BUCK_TMUX_A_D] = 1,
171 [TAPAN_A_NCP_BUCKREF] = 1,
172 [TAPAN_A_NCP_EN] = 1,
173 [TAPAN_A_NCP_CLK] = 1,
174 [TAPAN_A_NCP_STATIC] = 1,
175 [TAPAN_A_NCP_VTH_LOW] = 1,
176 [TAPAN_A_NCP_VTH_HIGH] = 1,
177 [TAPAN_A_NCP_ATEST] = 1,
178 [TAPAN_A_NCP_DTEST] = 1,
179 [TAPAN_A_NCP_DLY1] = 1,
180 [TAPAN_A_NCP_DLY2] = 1,
181 [TAPAN_A_RX_AUX_SW_CTL] = 1,
182 [TAPAN_A_RX_PA_AUX_IN_CONN] = 1,
183 [TAPAN_A_RX_COM_TIMER_DIV] = 1,
184 [TAPAN_A_RX_COM_OCP_CTL] = 1,
185 [TAPAN_A_RX_COM_OCP_COUNT] = 1,
186 [TAPAN_A_RX_COM_DAC_CTL] = 1,
187 [TAPAN_A_RX_COM_BIAS] = 1,
188 [TAPAN_A_RX_HPH_AUTO_CHOP] = 1,
189 [TAPAN_A_RX_HPH_CHOP_CTL] = 1,
190 [TAPAN_A_RX_HPH_BIAS_PA] = 1,
191 [TAPAN_A_RX_HPH_BIAS_LDO] = 1,
192 [TAPAN_A_RX_HPH_BIAS_CNP] = 1,
193 [TAPAN_A_RX_HPH_BIAS_WG_OCP] = 1,
194 [TAPAN_A_RX_HPH_OCP_CTL] = 1,
195 [TAPAN_A_RX_HPH_CNP_EN] = 1,
196 [TAPAN_A_RX_HPH_CNP_WG_CTL] = 1,
197 [TAPAN_A_RX_HPH_CNP_WG_TIME] = 1,
198 [TAPAN_A_RX_HPH_L_GAIN] = 1,
199 [TAPAN_A_RX_HPH_L_TEST] = 1,
200 [TAPAN_A_RX_HPH_L_PA_CTL] = 1,
201 [TAPAN_A_RX_HPH_L_DAC_CTL] = 1,
202 [TAPAN_A_RX_HPH_L_ATEST] = 1,
203 [TAPAN_A_RX_HPH_L_STATUS] = 1,
204 [TAPAN_A_RX_HPH_R_GAIN] = 1,
205 [TAPAN_A_RX_HPH_R_TEST] = 1,
206 [TAPAN_A_RX_HPH_R_PA_CTL] = 1,
207 [TAPAN_A_RX_HPH_R_DAC_CTL] = 1,
208 [TAPAN_A_RX_HPH_R_ATEST] = 1,
209 [TAPAN_A_RX_HPH_R_STATUS] = 1,
210 [TAPAN_A_RX_EAR_BIAS_PA] = 1,
211 [TAPAN_A_RX_EAR_BIAS_CMBUFF] = 1,
212 [TAPAN_A_RX_EAR_EN] = 1,
213 [TAPAN_A_RX_EAR_GAIN] = 1,
214 [TAPAN_A_RX_EAR_CMBUFF] = 1,
215 [TAPAN_A_RX_EAR_ICTL] = 1,
216 [TAPAN_A_RX_EAR_CCOMP] = 1,
217 [TAPAN_A_RX_EAR_VCM] = 1,
218 [TAPAN_A_RX_EAR_CNP] = 1,
219 [TAPAN_A_RX_EAR_DAC_CTL_ATEST] = 1,
220 [TAPAN_A_RX_EAR_STATUS] = 1,
221 [TAPAN_A_RX_LINE_BIAS_PA] = 1,
222 [TAPAN_A_RX_BUCK_BIAS1] = 1,
223 [TAPAN_A_RX_BUCK_BIAS2] = 1,
224 [TAPAN_A_RX_LINE_COM] = 1,
225 [TAPAN_A_RX_LINE_CNP_EN] = 1,
226 [TAPAN_A_RX_LINE_CNP_WG_CTL] = 1,
227 [TAPAN_A_RX_LINE_CNP_WG_TIME] = 1,
228 [TAPAN_A_RX_LINE_1_GAIN] = 1,
229 [TAPAN_A_RX_LINE_1_TEST] = 1,
230 [TAPAN_A_RX_LINE_1_DAC_CTL] = 1,
231 [TAPAN_A_RX_LINE_1_STATUS] = 1,
232 [TAPAN_A_RX_LINE_2_GAIN] = 1,
233 [TAPAN_A_RX_LINE_2_TEST] = 1,
234 [TAPAN_A_RX_LINE_2_DAC_CTL] = 1,
235 [TAPAN_A_RX_LINE_2_STATUS] = 1,
236 [TAPAN_A_RX_LINE_CNP_DBG] = 1,
237 [TAPAN_A_SPKR_DRV_EN] = 1,
238 [TAPAN_A_SPKR_DRV_GAIN] = 1,
239 [TAPAN_A_SPKR_DRV_DAC_CTL] = 1,
240 [TAPAN_A_SPKR_DRV_OCP_CTL] = 1,
241 [TAPAN_A_SPKR_DRV_CLIP_DET] = 1,
242 [TAPAN_A_SPKR_DRV_IEC] = 1,
243 [TAPAN_A_SPKR_DRV_DBG_DAC] = 1,
244 [TAPAN_A_SPKR_DRV_DBG_PA] = 1,
245 [TAPAN_A_SPKR_DRV_DBG_PWRSTG] = 1,
246 [TAPAN_A_SPKR_DRV_BIAS_LDO] = 1,
247 [TAPAN_A_SPKR_DRV_BIAS_INT] = 1,
248 [TAPAN_A_SPKR_DRV_BIAS_PA] = 1,
249 [TAPAN_A_SPKR_DRV_STATUS_OCP] = 1,
250 [TAPAN_A_SPKR_DRV_STATUS_PA] = 1,
251 [TAPAN_A_RC_OSC_FREQ] = 1,
252 [TAPAN_A_RC_OSC_TEST] = 1,
253 [TAPAN_A_RC_OSC_STATUS] = 1,
254 [TAPAN_A_RC_OSC_TUNER] = 1,
255 [TAPAN_A_MBHC_HPH] = 1,
256 [TAPAN_A_CDC_ANC1_B1_CTL] = 1,
257 [TAPAN_A_CDC_ANC2_B1_CTL] = 1,
258 [TAPAN_A_CDC_ANC1_SHIFT] = 1,
259 [TAPAN_A_CDC_ANC2_SHIFT] = 1,
260 [TAPAN_A_CDC_ANC1_IIR_B1_CTL] = 1,
261 [TAPAN_A_CDC_ANC2_IIR_B1_CTL] = 1,
262 [TAPAN_A_CDC_ANC1_IIR_B2_CTL] = 1,
263 [TAPAN_A_CDC_ANC2_IIR_B2_CTL] = 1,
264 [TAPAN_A_CDC_ANC1_IIR_B3_CTL] = 1,
265 [TAPAN_A_CDC_ANC2_IIR_B3_CTL] = 1,
266 [TAPAN_A_CDC_ANC1_LPF_B1_CTL] = 1,
267 [TAPAN_A_CDC_ANC2_LPF_B1_CTL] = 1,
268 [TAPAN_A_CDC_ANC1_LPF_B2_CTL] = 1,
269 [TAPAN_A_CDC_ANC2_LPF_B2_CTL] = 1,
270 [TAPAN_A_CDC_ANC1_SPARE] = 1,
271 [TAPAN_A_CDC_ANC2_SPARE] = 1,
272 [TAPAN_A_CDC_ANC1_SMLPF_CTL] = 1,
273 [TAPAN_A_CDC_ANC2_SMLPF_CTL] = 1,
274 [TAPAN_A_CDC_ANC1_DCFLT_CTL] = 1,
275 [TAPAN_A_CDC_ANC2_DCFLT_CTL] = 1,
276 [TAPAN_A_CDC_ANC1_GAIN_CTL] = 1,
277 [TAPAN_A_CDC_ANC2_GAIN_CTL] = 1,
278 [TAPAN_A_CDC_ANC1_B2_CTL] = 1,
279 [TAPAN_A_CDC_ANC2_B2_CTL] = 1,
280 [TAPAN_A_CDC_TX1_VOL_CTL_TIMER] = 1,
281 [TAPAN_A_CDC_TX2_VOL_CTL_TIMER] = 1,
282 [TAPAN_A_CDC_TX3_VOL_CTL_TIMER] = 1,
283 [TAPAN_A_CDC_TX4_VOL_CTL_TIMER] = 1,
284 [TAPAN_A_CDC_TX1_VOL_CTL_GAIN] = 1,
285 [TAPAN_A_CDC_TX2_VOL_CTL_GAIN] = 1,
286 [TAPAN_A_CDC_TX3_VOL_CTL_GAIN] = 1,
287 [TAPAN_A_CDC_TX4_VOL_CTL_GAIN] = 1,
288 [TAPAN_A_CDC_TX1_VOL_CTL_CFG] = 1,
289 [TAPAN_A_CDC_TX2_VOL_CTL_CFG] = 1,
290 [TAPAN_A_CDC_TX3_VOL_CTL_CFG] = 1,
291 [TAPAN_A_CDC_TX4_VOL_CTL_CFG] = 1,
292 [TAPAN_A_CDC_TX1_MUX_CTL] = 1,
293 [TAPAN_A_CDC_TX2_MUX_CTL] = 1,
294 [TAPAN_A_CDC_TX3_MUX_CTL] = 1,
295 [TAPAN_A_CDC_TX4_MUX_CTL] = 1,
296 [TAPAN_A_CDC_TX1_CLK_FS_CTL] = 1,
297 [TAPAN_A_CDC_TX2_CLK_FS_CTL] = 1,
298 [TAPAN_A_CDC_TX3_CLK_FS_CTL] = 1,
299 [TAPAN_A_CDC_TX4_CLK_FS_CTL] = 1,
300 [TAPAN_A_CDC_TX1_DMIC_CTL] = 1,
301 [TAPAN_A_CDC_TX2_DMIC_CTL] = 1,
302 [TAPAN_A_CDC_TX3_DMIC_CTL] = 1,
303 [TAPAN_A_CDC_TX4_DMIC_CTL] = 1,
304 [TAPAN_A_CDC_DEBUG_B1_CTL] = 1,
305 [TAPAN_A_CDC_DEBUG_B2_CTL] = 1,
306 [TAPAN_A_CDC_DEBUG_B3_CTL] = 1,
307 [TAPAN_A_CDC_DEBUG_B4_CTL] = 1,
308 [TAPAN_A_CDC_DEBUG_B5_CTL] = 1,
309 [TAPAN_A_CDC_DEBUG_B6_CTL] = 1,
310 [TAPAN_A_CDC_DEBUG_B7_CTL] = 1,
311 [TAPAN_A_CDC_SRC1_PDA_CFG] = 1,
312 [TAPAN_A_CDC_SRC2_PDA_CFG] = 1,
313 [TAPAN_A_CDC_SRC1_FS_CTL] = 1,
314 [TAPAN_A_CDC_SRC2_FS_CTL] = 1,
315 [TAPAN_A_CDC_RX1_B1_CTL] = 1,
316 [TAPAN_A_CDC_RX2_B1_CTL] = 1,
317 [TAPAN_A_CDC_RX3_B1_CTL] = 1,
318 [TAPAN_A_CDC_RX4_B1_CTL] = 1,
319 [TAPAN_A_CDC_RX1_B2_CTL] = 1,
320 [TAPAN_A_CDC_RX2_B2_CTL] = 1,
321 [TAPAN_A_CDC_RX3_B2_CTL] = 1,
322 [TAPAN_A_CDC_RX4_B2_CTL] = 1,
323 [TAPAN_A_CDC_RX1_B3_CTL] = 1,
324 [TAPAN_A_CDC_RX2_B3_CTL] = 1,
325 [TAPAN_A_CDC_RX3_B3_CTL] = 1,
326 [TAPAN_A_CDC_RX4_B3_CTL] = 1,
327 [TAPAN_A_CDC_RX1_B4_CTL] = 1,
328 [TAPAN_A_CDC_RX2_B4_CTL] = 1,
329 [TAPAN_A_CDC_RX3_B4_CTL] = 1,
330 [TAPAN_A_CDC_RX4_B4_CTL] = 1,
331 [TAPAN_A_CDC_RX1_B5_CTL] = 1,
332 [TAPAN_A_CDC_RX2_B5_CTL] = 1,
333 [TAPAN_A_CDC_RX3_B5_CTL] = 1,
334 [TAPAN_A_CDC_RX4_B5_CTL] = 1,
335 [TAPAN_A_CDC_RX1_B6_CTL] = 1,
336 [TAPAN_A_CDC_RX2_B6_CTL] = 1,
337 [TAPAN_A_CDC_RX3_B6_CTL] = 1,
338 [TAPAN_A_CDC_RX4_B6_CTL] = 1,
339 [TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
340 [TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL] = 1,
341 [TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL] = 1,
342 [TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL] = 1,
343 [TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
344 [TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL] = 1,
345 [TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL] = 1,
346 [TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL] = 1,
347 [TAPAN_A_CDC_CLK_ANC_RESET_CTL] = 1,
348 [TAPAN_A_CDC_CLK_RX_RESET_CTL] = 1,
349 [TAPAN_A_CDC_CLK_TX_RESET_B1_CTL] = 1,
350 [TAPAN_A_CDC_CLK_TX_RESET_B2_CTL] = 1,
351 [TAPAN_A_CDC_CLK_DMIC_B1_CTL] = 1,
352 [TAPAN_A_CDC_CLK_DMIC_B2_CTL] = 1,
353 [TAPAN_A_CDC_CLK_I2S_CTL] = 1,
354 [TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL] = 1,
355 [TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL] = 1,
356 [TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1,
357 [TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL] = 1,
358 [TAPAN_A_CDC_CLK_OTHR_CTL] = 1,
359 [TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL] = 1,
360 [TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL] = 1,
361 [TAPAN_A_CDC_CLK_RX_B1_CTL] = 1,
362 [TAPAN_A_CDC_CLK_RX_B2_CTL] = 1,
363 [TAPAN_A_CDC_CLK_MCLK_CTL] = 1,
364 [TAPAN_A_CDC_CLK_PDM_CTL] = 1,
365 [TAPAN_A_CDC_CLK_SD_CTL] = 1,
366 [TAPAN_A_CDC_CLK_POWER_CTL] = 1,
367 [TAPAN_A_CDC_CLSH_B1_CTL] = 1,
368 [TAPAN_A_CDC_CLSH_B2_CTL] = 1,
369 [TAPAN_A_CDC_CLSH_B3_CTL] = 1,
370 [TAPAN_A_CDC_CLSH_BUCK_NCP_VARS] = 1,
371 [TAPAN_A_CDC_CLSH_IDLE_HPH_THSD] = 1,
372 [TAPAN_A_CDC_CLSH_IDLE_EAR_THSD] = 1,
373 [TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD] = 1,
374 [TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD] = 1,
375 [TAPAN_A_CDC_CLSH_K_ADDR] = 1,
376 [TAPAN_A_CDC_CLSH_K_DATA] = 1,
377 [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L] = 1,
378 [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U] = 1,
379 [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L] = 1,
380 [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U] = 1,
381 [TAPAN_A_CDC_CLSH_V_PA_HD_EAR] = 1,
382 [TAPAN_A_CDC_CLSH_V_PA_HD_HPH] = 1,
383 [TAPAN_A_CDC_CLSH_V_PA_MIN_EAR] = 1,
384 [TAPAN_A_CDC_CLSH_V_PA_MIN_HPH] = 1,
385 [TAPAN_A_CDC_IIR1_GAIN_B1_CTL] = 1,
386 [TAPAN_A_CDC_IIR2_GAIN_B1_CTL] = 1,
387 [TAPAN_A_CDC_IIR1_GAIN_B2_CTL] = 1,
388 [TAPAN_A_CDC_IIR2_GAIN_B2_CTL] = 1,
389 [TAPAN_A_CDC_IIR1_GAIN_B3_CTL] = 1,
390 [TAPAN_A_CDC_IIR2_GAIN_B3_CTL] = 1,
391 [TAPAN_A_CDC_IIR1_GAIN_B4_CTL] = 1,
392 [TAPAN_A_CDC_IIR2_GAIN_B4_CTL] = 1,
393 [TAPAN_A_CDC_IIR1_GAIN_B5_CTL] = 1,
394 [TAPAN_A_CDC_IIR2_GAIN_B5_CTL] = 1,
395 [TAPAN_A_CDC_IIR1_GAIN_B6_CTL] = 1,
396 [TAPAN_A_CDC_IIR2_GAIN_B6_CTL] = 1,
397 [TAPAN_A_CDC_IIR1_GAIN_B7_CTL] = 1,
398 [TAPAN_A_CDC_IIR2_GAIN_B7_CTL] = 1,
399 [TAPAN_A_CDC_IIR1_GAIN_B8_CTL] = 1,
400 [TAPAN_A_CDC_IIR2_GAIN_B8_CTL] = 1,
401 [TAPAN_A_CDC_IIR1_CTL] = 1,
402 [TAPAN_A_CDC_IIR2_CTL] = 1,
403 [TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL] = 1,
404 [TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL] = 1,
405 [TAPAN_A_CDC_IIR1_COEF_B1_CTL] = 1,
406 [TAPAN_A_CDC_IIR2_COEF_B1_CTL] = 1,
407 [TAPAN_A_CDC_IIR1_COEF_B2_CTL] = 1,
408 [TAPAN_A_CDC_IIR2_COEF_B2_CTL] = 1,
409 [TAPAN_A_CDC_TOP_GAIN_UPDATE] = 1,
410 [TAPAN_A_CDC_COMP0_B1_CTL] = 1,
411 [TAPAN_A_CDC_COMP1_B1_CTL] = 1,
412 [TAPAN_A_CDC_COMP2_B1_CTL] = 1,
413 [TAPAN_A_CDC_COMP0_B2_CTL] = 1,
414 [TAPAN_A_CDC_COMP1_B2_CTL] = 1,
415 [TAPAN_A_CDC_COMP2_B2_CTL] = 1,
416 [TAPAN_A_CDC_COMP0_B3_CTL] = 1,
417 [TAPAN_A_CDC_COMP1_B3_CTL] = 1,
418 [TAPAN_A_CDC_COMP2_B3_CTL] = 1,
419 [TAPAN_A_CDC_COMP0_B4_CTL] = 1,
420 [TAPAN_A_CDC_COMP1_B4_CTL] = 1,
421 [TAPAN_A_CDC_COMP2_B4_CTL] = 1,
422 [TAPAN_A_CDC_COMP0_B5_CTL] = 1,
423 [TAPAN_A_CDC_COMP1_B5_CTL] = 1,
424 [TAPAN_A_CDC_COMP2_B5_CTL] = 1,
425 [TAPAN_A_CDC_COMP0_B6_CTL] = 1,
426 [TAPAN_A_CDC_COMP1_B6_CTL] = 1,
427 [TAPAN_A_CDC_COMP2_B6_CTL] = 1,
428 [TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS] = 1,
429 [TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS] = 1,
430 [TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS] = 1,
431 [TAPAN_A_CDC_COMP0_FS_CFG] = 1,
432 [TAPAN_A_CDC_COMP1_FS_CFG] = 1,
433 [TAPAN_A_CDC_COMP2_FS_CFG] = 1,
434 [TAPAN_A_CDC_CONN_RX1_B1_CTL] = 1,
435 [TAPAN_A_CDC_CONN_RX1_B2_CTL] = 1,
436 [TAPAN_A_CDC_CONN_RX1_B3_CTL] = 1,
437 [TAPAN_A_CDC_CONN_RX2_B1_CTL] = 1,
438 [TAPAN_A_CDC_CONN_RX2_B2_CTL] = 1,
439 [TAPAN_A_CDC_CONN_RX2_B3_CTL] = 1,
440 [TAPAN_A_CDC_CONN_RX3_B1_CTL] = 1,
441 [TAPAN_A_CDC_CONN_RX3_B2_CTL] = 1,
442 [TAPAN_A_CDC_CONN_RX4_B1_CTL] = 1,
443 [TAPAN_A_CDC_CONN_RX4_B2_CTL] = 1,
444 [TAPAN_A_CDC_CONN_RX4_B3_CTL] = 1,
445 [TAPAN_A_CDC_CONN_ANC_B1_CTL] = 1,
446 [TAPAN_A_CDC_CONN_ANC_B2_CTL] = 1,
447 [TAPAN_A_CDC_CONN_TX_B1_CTL] = 1,
448 [TAPAN_A_CDC_CONN_TX_B2_CTL] = 1,
449 [TAPAN_A_CDC_CONN_TX_B3_CTL] = 1,
450 [TAPAN_A_CDC_CONN_TX_B4_CTL] = 1,
451 [TAPAN_A_CDC_CONN_EQ1_B1_CTL] = 1,
452 [TAPAN_A_CDC_CONN_EQ1_B2_CTL] = 1,
453 [TAPAN_A_CDC_CONN_EQ1_B3_CTL] = 1,
454 [TAPAN_A_CDC_CONN_EQ1_B4_CTL] = 1,
455 [TAPAN_A_CDC_CONN_EQ2_B1_CTL] = 1,
456 [TAPAN_A_CDC_CONN_EQ2_B2_CTL] = 1,
457 [TAPAN_A_CDC_CONN_EQ2_B3_CTL] = 1,
458 [TAPAN_A_CDC_CONN_EQ2_B4_CTL] = 1,
459 [TAPAN_A_CDC_CONN_SRC1_B1_CTL] = 1,
460 [TAPAN_A_CDC_CONN_SRC1_B2_CTL] = 1,
461 [TAPAN_A_CDC_CONN_SRC2_B1_CTL] = 1,
462 [TAPAN_A_CDC_CONN_SRC2_B2_CTL] = 1,
463 [TAPAN_A_CDC_CONN_TX_SB_B1_CTL] = 1,
464 [TAPAN_A_CDC_CONN_TX_SB_B2_CTL] = 1,
465 [TAPAN_A_CDC_CONN_TX_SB_B3_CTL] = 1,
466 [TAPAN_A_CDC_CONN_TX_SB_B4_CTL] = 1,
467 [TAPAN_A_CDC_CONN_TX_SB_B5_CTL] = 1,
468 [TAPAN_A_CDC_CONN_TX_SB_B11_CTL] = 1,
469 [TAPAN_A_CDC_CONN_RX_SB_B1_CTL] = 1,
470 [TAPAN_A_CDC_CONN_RX_SB_B2_CTL] = 1,
471 [TAPAN_A_CDC_CONN_CLSH_CTL] = 1,
472 [TAPAN_A_CDC_CONN_MISC] = 1,
473 [TAPAN_A_CDC_MBHC_EN_CTL] = 1,
474 [TAPAN_A_CDC_MBHC_FIR_B1_CFG] = 1,
475 [TAPAN_A_CDC_MBHC_FIR_B2_CFG] = 1,
476 [TAPAN_A_CDC_MBHC_TIMER_B1_CTL] = 1,
477 [TAPAN_A_CDC_MBHC_TIMER_B2_CTL] = 1,
478 [TAPAN_A_CDC_MBHC_TIMER_B3_CTL] = 1,
479 [TAPAN_A_CDC_MBHC_TIMER_B4_CTL] = 1,
480 [TAPAN_A_CDC_MBHC_TIMER_B5_CTL] = 1,
481 [TAPAN_A_CDC_MBHC_TIMER_B6_CTL] = 1,
482 [TAPAN_A_CDC_MBHC_B1_STATUS] = 1,
483 [TAPAN_A_CDC_MBHC_B2_STATUS] = 1,
484 [TAPAN_A_CDC_MBHC_B3_STATUS] = 1,
485 [TAPAN_A_CDC_MBHC_B4_STATUS] = 1,
486 [TAPAN_A_CDC_MBHC_B5_STATUS] = 1,
487 [TAPAN_A_CDC_MBHC_B1_CTL] = 1,
488 [TAPAN_A_CDC_MBHC_B2_CTL] = 1,
489 [TAPAN_A_CDC_MBHC_VOLT_B1_CTL] = 1,
490 [TAPAN_A_CDC_MBHC_VOLT_B2_CTL] = 1,
491 [TAPAN_A_CDC_MBHC_VOLT_B3_CTL] = 1,
492 [TAPAN_A_CDC_MBHC_VOLT_B4_CTL] = 1,
493 [TAPAN_A_CDC_MBHC_VOLT_B5_CTL] = 1,
494 [TAPAN_A_CDC_MBHC_VOLT_B6_CTL] = 1,
495 [TAPAN_A_CDC_MBHC_VOLT_B7_CTL] = 1,
496 [TAPAN_A_CDC_MBHC_VOLT_B8_CTL] = 1,
497 [TAPAN_A_CDC_MBHC_VOLT_B9_CTL] = 1,
498 [TAPAN_A_CDC_MBHC_VOLT_B10_CTL] = 1,
499 [TAPAN_A_CDC_MBHC_VOLT_B11_CTL] = 1,
500 [TAPAN_A_CDC_MBHC_VOLT_B12_CTL] = 1,
501 [TAPAN_A_CDC_MBHC_CLK_CTL] = 1,
502 [TAPAN_A_CDC_MBHC_INT_CTL] = 1,
503 [TAPAN_A_CDC_MBHC_DEBUG_CTL] = 1,
504 [TAPAN_A_CDC_MBHC_SPARE] = 1,
505};
506
507const u8 tapan_reset_reg_defaults[TAPAN_CACHE_SIZE] = {
508 [TAPAN_A_CHIP_CTL] = TAPAN_A_CHIP_CTL__POR,
509 [TAPAN_A_CHIP_STATUS] = TAPAN_A_CHIP_STATUS__POR,
510 [TAPAN_A_CHIP_ID_BYTE_0] = TAPAN_A_CHIP_ID_BYTE_0__POR,
511 [TAPAN_A_CHIP_ID_BYTE_1] = TAPAN_A_CHIP_ID_BYTE_1__POR,
512 [TAPAN_A_CHIP_ID_BYTE_2] = TAPAN_A_CHIP_ID_BYTE_2__POR,
513 [TAPAN_A_CHIP_ID_BYTE_3] = TAPAN_A_CHIP_ID_BYTE_3__POR,
514 [TAPAN_A_CHIP_VERSION] = TAPAN_A_CHIP_VERSION__POR,
515 [TAPAN_A_CHIP_DEBUG_CTL] = TAPAN_A_CHIP_DEBUG_CTL__POR,
516 [TAPAN_A_SLAVE_ID_1] = TAPAN_A_SLAVE_ID_1__POR,
517 [TAPAN_A_SLAVE_ID_2] = TAPAN_A_SLAVE_ID_2__POR,
518 [TAPAN_A_SLAVE_ID_3] = TAPAN_A_SLAVE_ID_3__POR,
519 [TAPAN_A_PIN_CTL_OE0] = TAPAN_A_PIN_CTL_OE0__POR,
520 [TAPAN_A_PIN_CTL_DATA0] = TAPAN_A_PIN_CTL_DATA0__POR,
521 [TAPAN_A_HDRIVE_GENERIC] = TAPAN_A_HDRIVE_GENERIC__POR,
522 [TAPAN_A_HDRIVE_OVERRIDE] = TAPAN_A_HDRIVE_OVERRIDE__POR,
523 [TAPAN_A_ANA_CSR_WAIT_STATE] = TAPAN_A_ANA_CSR_WAIT_STATE__POR,
524 [TAPAN_A_PROCESS_MONITOR_CTL0] = TAPAN_A_PROCESS_MONITOR_CTL0__POR,
525 [TAPAN_A_PROCESS_MONITOR_CTL1] = TAPAN_A_PROCESS_MONITOR_CTL1__POR,
526 [TAPAN_A_PROCESS_MONITOR_CTL2] = TAPAN_A_PROCESS_MONITOR_CTL2__POR,
527 [TAPAN_A_PROCESS_MONITOR_CTL3] = TAPAN_A_PROCESS_MONITOR_CTL3__POR,
528 [TAPAN_A_QFUSE_CTL] = TAPAN_A_QFUSE_CTL__POR,
529 [TAPAN_A_QFUSE_STATUS] = TAPAN_A_QFUSE_STATUS__POR,
530 [TAPAN_A_QFUSE_DATA_OUT0] = TAPAN_A_QFUSE_DATA_OUT0__POR,
531 [TAPAN_A_QFUSE_DATA_OUT1] = TAPAN_A_QFUSE_DATA_OUT1__POR,
532 [TAPAN_A_QFUSE_DATA_OUT2] = TAPAN_A_QFUSE_DATA_OUT2__POR,
533 [TAPAN_A_QFUSE_DATA_OUT3] = TAPAN_A_QFUSE_DATA_OUT3__POR,
534 [TAPAN_A_QFUSE_DATA_OUT4] = TAPAN_A_QFUSE_DATA_OUT4__POR,
535 [TAPAN_A_QFUSE_DATA_OUT5] = TAPAN_A_QFUSE_DATA_OUT5__POR,
536 [TAPAN_A_QFUSE_DATA_OUT6] = TAPAN_A_QFUSE_DATA_OUT6__POR,
537 [TAPAN_A_QFUSE_DATA_OUT7] = TAPAN_A_QFUSE_DATA_OUT7__POR,
538 [TAPAN_A_CDC_CTL] = TAPAN_A_CDC_CTL__POR,
539 [TAPAN_A_LEAKAGE_CTL] = TAPAN_A_LEAKAGE_CTL__POR,
540 [TAPAN_A_INTR_MODE] = TAPAN_A_INTR_MODE__POR,
541 [TAPAN_A_INTR_MASK0] = TAPAN_A_INTR_MASK0__POR,
542 [TAPAN_A_INTR_MASK1] = TAPAN_A_INTR_MASK1__POR,
543 [TAPAN_A_INTR_MASK2] = TAPAN_A_INTR_MASK2__POR,
544 [TAPAN_A_INTR_MASK3] = TAPAN_A_INTR_MASK3__POR,
545 [TAPAN_A_INTR_STATUS0] = TAPAN_A_INTR_STATUS0__POR,
546 [TAPAN_A_INTR_STATUS1] = TAPAN_A_INTR_STATUS1__POR,
547 [TAPAN_A_INTR_STATUS2] = TAPAN_A_INTR_STATUS2__POR,
548 [TAPAN_A_INTR_STATUS3] = TAPAN_A_INTR_STATUS3__POR,
549 [TAPAN_A_INTR_CLEAR0] = TAPAN_A_INTR_CLEAR0__POR,
550 [TAPAN_A_INTR_CLEAR1] = TAPAN_A_INTR_CLEAR1__POR,
551 [TAPAN_A_INTR_CLEAR2] = TAPAN_A_INTR_CLEAR2__POR,
552 [TAPAN_A_INTR_CLEAR3] = TAPAN_A_INTR_CLEAR3__POR,
553 [TAPAN_A_INTR_LEVEL0] = TAPAN_A_INTR_LEVEL0__POR,
554 [TAPAN_A_INTR_LEVEL1] = TAPAN_A_INTR_LEVEL1__POR,
555 [TAPAN_A_INTR_LEVEL2] = TAPAN_A_INTR_LEVEL2__POR,
556 [TAPAN_A_INTR_LEVEL3] = TAPAN_A_INTR_LEVEL3__POR,
557 [TAPAN_A_INTR_TEST0] = TAPAN_A_INTR_TEST0__POR,
558 [TAPAN_A_INTR_TEST1] = TAPAN_A_INTR_TEST1__POR,
559 [TAPAN_A_INTR_TEST2] = TAPAN_A_INTR_TEST2__POR,
560 [TAPAN_A_INTR_TEST3] = TAPAN_A_INTR_TEST3__POR,
561 [TAPAN_A_INTR_SET0] = TAPAN_A_INTR_SET0__POR,
562 [TAPAN_A_INTR_SET1] = TAPAN_A_INTR_SET1__POR,
563 [TAPAN_A_INTR_SET2] = TAPAN_A_INTR_SET2__POR,
564 [TAPAN_A_INTR_SET3] = TAPAN_A_INTR_SET3__POR,
565 [TAPAN_A_INTR_DESTN0] = TAPAN_A_INTR_DESTN0__POR,
566 [TAPAN_A_INTR_DESTN1] = TAPAN_A_INTR_DESTN1__POR,
567 [TAPAN_A_INTR_DESTN2] = TAPAN_A_INTR_DESTN2__POR,
568 [TAPAN_A_INTR_DESTN3] = TAPAN_A_INTR_DESTN3__POR,
569 [TAPAN_A_CDC_DMIC_DATA0_MODE] = TAPAN_A_CDC_DMIC_DATA0_MODE__POR,
570 [TAPAN_A_CDC_DMIC_CLK0_MODE] = TAPAN_A_CDC_DMIC_CLK0_MODE__POR,
571 [TAPAN_A_CDC_DMIC_DATA1_MODE] = TAPAN_A_CDC_DMIC_DATA1_MODE__POR,
572 [TAPAN_A_CDC_DMIC_CLK1_MODE] = TAPAN_A_CDC_DMIC_CLK1_MODE__POR,
573 [TAPAN_A_CDC_INTR_MODE] = TAPAN_A_CDC_INTR_MODE__POR,
574 [TAPAN_A_BIAS_REF_CTL] = TAPAN_A_BIAS_REF_CTL__POR,
575 [TAPAN_A_BIAS_CENTRAL_BG_CTL] = TAPAN_A_BIAS_CENTRAL_BG_CTL__POR,
576 [TAPAN_A_BIAS_PRECHRG_CTL] = TAPAN_A_BIAS_PRECHRG_CTL__POR,
577 [TAPAN_A_BIAS_CURR_CTL_1] = TAPAN_A_BIAS_CURR_CTL_1__POR,
578 [TAPAN_A_BIAS_CURR_CTL_2] = TAPAN_A_BIAS_CURR_CTL_2__POR,
579 [TAPAN_A_BIAS_OSC_BG_CTL] = TAPAN_A_BIAS_OSC_BG_CTL__POR,
580 [TAPAN_A_CLK_BUFF_EN1] = TAPAN_A_CLK_BUFF_EN1__POR,
581 [TAPAN_A_CLK_BUFF_EN2] = TAPAN_A_CLK_BUFF_EN2__POR,
582 [TAPAN_A_LDO_H_MODE_1] = TAPAN_A_LDO_H_MODE_1__POR,
583 [TAPAN_A_LDO_H_MODE_2] = TAPAN_A_LDO_H_MODE_2__POR,
584 [TAPAN_A_LDO_H_LOOP_CTL] = TAPAN_A_LDO_H_LOOP_CTL__POR,
585 [TAPAN_A_LDO_H_COMP_1] = TAPAN_A_LDO_H_COMP_1__POR,
586 [TAPAN_A_LDO_H_COMP_2] = TAPAN_A_LDO_H_COMP_2__POR,
587 [TAPAN_A_LDO_H_BIAS_1] = TAPAN_A_LDO_H_BIAS_1__POR,
588 [TAPAN_A_LDO_H_BIAS_2] = TAPAN_A_LDO_H_BIAS_2__POR,
589 [TAPAN_A_LDO_H_BIAS_3] = TAPAN_A_LDO_H_BIAS_3__POR,
590 [TAPAN_A_MICB_CFILT_1_CTL] = TAPAN_A_MICB_CFILT_1_CTL__POR,
591 [TAPAN_A_MICB_CFILT_1_VAL] = TAPAN_A_MICB_CFILT_1_VAL__POR,
592 [TAPAN_A_MICB_CFILT_1_PRECHRG] = TAPAN_A_MICB_CFILT_1_PRECHRG__POR,
593 [TAPAN_A_MICB_1_CTL] = TAPAN_A_MICB_1_CTL__POR,
594 [TAPAN_A_MICB_1_INT_RBIAS] = TAPAN_A_MICB_1_INT_RBIAS__POR,
595 [TAPAN_A_MICB_1_MBHC] = TAPAN_A_MICB_1_MBHC__POR,
596 [TAPAN_A_MICB_CFILT_2_CTL] = TAPAN_A_MICB_CFILT_2_CTL__POR,
597 [TAPAN_A_MICB_CFILT_2_VAL] = TAPAN_A_MICB_CFILT_2_VAL__POR,
598 [TAPAN_A_MICB_CFILT_2_PRECHRG] = TAPAN_A_MICB_CFILT_2_PRECHRG__POR,
599 [TAPAN_A_MICB_2_CTL] = TAPAN_A_MICB_2_CTL__POR,
600 [TAPAN_A_MICB_2_INT_RBIAS] = TAPAN_A_MICB_2_INT_RBIAS__POR,
601 [TAPAN_A_MICB_2_MBHC] = TAPAN_A_MICB_2_MBHC__POR,
602 [TAPAN_A_MICB_CFILT_3_CTL] = TAPAN_A_MICB_CFILT_3_CTL__POR,
603 [TAPAN_A_MICB_CFILT_3_VAL] = TAPAN_A_MICB_CFILT_3_VAL__POR,
604 [TAPAN_A_MICB_CFILT_3_PRECHRG] = TAPAN_A_MICB_CFILT_3_PRECHRG__POR,
605 [TAPAN_A_MICB_3_CTL] = TAPAN_A_MICB_3_CTL__POR,
606 [TAPAN_A_MICB_3_INT_RBIAS] = TAPAN_A_MICB_3_INT_RBIAS__POR,
607 [TAPAN_A_MICB_3_MBHC] = TAPAN_A_MICB_3_MBHC__POR,
608 [TAPAN_A_MBHC_INSERT_DETECT] = TAPAN_A_MBHC_INSERT_DETECT__POR,
609 [TAPAN_A_MBHC_INSERT_DET_STATUS] = TAPAN_A_MBHC_INSERT_DET_STATUS__POR,
610 [TAPAN_A_TX_COM_BIAS] = TAPAN_A_TX_COM_BIAS__POR,
611 [TAPAN_A_MBHC_SCALING_MUX_1] = TAPAN_A_MBHC_SCALING_MUX_1__POR,
612 [TAPAN_A_MBHC_SCALING_MUX_2] = TAPAN_A_MBHC_SCALING_MUX_2__POR,
613 [TAPAN_A_RESERVED_MAD_ANA_CTRL] = TAPAN_A_RESERVED_MAD_ANA_CTRL__POR,
614 [TAPAN_A_TX_SUP_SWITCH_CTRL_1] = TAPAN_A_TX_SUP_SWITCH_CTRL_1__POR,
615 [TAPAN_A_TX_SUP_SWITCH_CTRL_2] = TAPAN_A_TX_SUP_SWITCH_CTRL_2__POR,
616 [TAPAN_A_TX_1_EN] = TAPAN_A_TX_1_EN__POR,
617 [TAPAN_A_TX_2_EN] = TAPAN_A_TX_2_EN__POR,
618 [TAPAN_A_TX_1_2_ADC_CH1] = TAPAN_A_TX_1_2_ADC_CH1__POR,
619 [TAPAN_A_TX_1_2_ADC_CH2] = TAPAN_A_TX_1_2_ADC_CH2__POR,
620 [TAPAN_A_TX_1_2_ATEST_REFCTRL] = TAPAN_A_TX_1_2_ATEST_REFCTRL__POR,
621 [TAPAN_A_TX_1_2_TEST_CTL] = TAPAN_A_TX_1_2_TEST_CTL__POR,
622 [TAPAN_A_TX_1_2_TEST_BLOCK_EN] = TAPAN_A_TX_1_2_TEST_BLOCK_EN__POR,
623 [TAPAN_A_TX_1_2_TXFE_CLKDIV] = TAPAN_A_TX_1_2_TXFE_CLKDIV__POR,
624 [TAPAN_A_TX_1_2_SAR_ERR_CH1] = TAPAN_A_TX_1_2_SAR_ERR_CH1__POR,
625 [TAPAN_A_TX_1_2_SAR_ERR_CH2] = TAPAN_A_TX_1_2_SAR_ERR_CH2__POR,
626 [TAPAN_A_TX_3_EN] = TAPAN_A_TX_3_EN__POR,
627 [TAPAN_A_TX_1_2_TEST_EN] = TAPAN_A_TX_1_2_TEST_EN__POR,
628 [TAPAN_A_TX_4_5_TXFE_SC_CTL] = TAPAN_A_TX_4_5_TXFE_SC_CTL__POR,
629 [TAPAN_A_TX_4_5_TEST_EN] = TAPAN_A_TX_4_5_TEST_EN__POR,
630 [TAPAN_A_TX_4_EN] = TAPAN_A_TX_4_EN__POR,
631 [TAPAN_A_TX_5_EN] = TAPAN_A_TX_5_EN__POR,
632 [TAPAN_A_TX_4_5_ADC_CH4] = TAPAN_A_TX_4_5_ADC_CH4__POR,
633 [TAPAN_A_TX_4_5_ADC_CH5] = TAPAN_A_TX_4_5_ADC_CH5__POR,
634 [TAPAN_A_TX_4_5_ATEST_REFCTRL] = TAPAN_A_TX_4_5_ATEST_REFCTRL__POR,
635 [TAPAN_A_TX_4_5_TEST_CTL] = TAPAN_A_TX_4_5_TEST_CTL__POR,
636 [TAPAN_A_TX_4_5_TEST_BLOCK_EN] = TAPAN_A_TX_4_5_TEST_BLOCK_EN__POR,
637 [TAPAN_A_TX_4_5_TXFE_CKDIV] = TAPAN_A_TX_4_5_TXFE_CKDIV__POR,
638 [TAPAN_A_TX_4_5_SAR_ERR_CH4] = TAPAN_A_TX_4_5_SAR_ERR_CH4__POR,
639 [TAPAN_A_TX_4_5_SAR_ERR_CH5] = TAPAN_A_TX_4_5_SAR_ERR_CH5__POR,
640 [TAPAN_A_TX_7_MBHC_EN] = TAPAN_A_TX_7_MBHC_EN__POR,
641 [TAPAN_A_TX_7_MBHC_ATEST_REFCTRL] =
642 TAPAN_A_TX_7_MBHC_ATEST_REFCTRL__POR,
643 [TAPAN_A_TX_7_MBHC_ADC] = TAPAN_A_TX_7_MBHC_ADC__POR,
644 [TAPAN_A_TX_7_MBHC_TEST_CTL] = TAPAN_A_TX_7_MBHC_TEST_CTL__POR,
645 [TAPAN_A_TX_7_MBHC_SAR_ERR] = TAPAN_A_TX_7_MBHC_SAR_ERR__POR,
646 [TAPAN_A_TX_7_TXFE_CLKDIV] = TAPAN_A_TX_7_TXFE_CLKDIV__POR,
647 [TAPAN_A_BUCK_MODE_1] = TAPAN_A_BUCK_MODE_1__POR,
648 [TAPAN_A_BUCK_MODE_2] = TAPAN_A_BUCK_MODE_2__POR,
649 [TAPAN_A_BUCK_MODE_3] = TAPAN_A_BUCK_MODE_3__POR,
650 [TAPAN_A_BUCK_MODE_4] = TAPAN_A_BUCK_MODE_4__POR,
651 [TAPAN_A_BUCK_MODE_5] = TAPAN_A_BUCK_MODE_5__POR,
652 [TAPAN_A_BUCK_CTRL_VCL_1] = TAPAN_A_BUCK_CTRL_VCL_1__POR,
653 [TAPAN_A_BUCK_CTRL_VCL_2] = TAPAN_A_BUCK_CTRL_VCL_2__POR,
654 [TAPAN_A_BUCK_CTRL_VCL_3] = TAPAN_A_BUCK_CTRL_VCL_3__POR,
655 [TAPAN_A_BUCK_CTRL_CCL_1] = TAPAN_A_BUCK_CTRL_CCL_1__POR,
656 [TAPAN_A_BUCK_CTRL_CCL_2] = TAPAN_A_BUCK_CTRL_CCL_2__POR,
657 [TAPAN_A_BUCK_CTRL_CCL_3] = TAPAN_A_BUCK_CTRL_CCL_3__POR,
658 [TAPAN_A_BUCK_CTRL_CCL_4] = TAPAN_A_BUCK_CTRL_CCL_4__POR,
659 [TAPAN_A_BUCK_CTRL_PWM_DRVR_1] = TAPAN_A_BUCK_CTRL_PWM_DRVR_1__POR,
660 [TAPAN_A_BUCK_CTRL_PWM_DRVR_2] = TAPAN_A_BUCK_CTRL_PWM_DRVR_2__POR,
661 [TAPAN_A_BUCK_CTRL_PWM_DRVR_3] = TAPAN_A_BUCK_CTRL_PWM_DRVR_3__POR,
662 [TAPAN_A_BUCK_TMUX_A_D] = TAPAN_A_BUCK_TMUX_A_D__POR,
663 [TAPAN_A_NCP_BUCKREF] = TAPAN_A_NCP_BUCKREF__POR,
664 [TAPAN_A_NCP_EN] = TAPAN_A_NCP_EN__POR,
665 [TAPAN_A_NCP_CLK] = TAPAN_A_NCP_CLK__POR,
666 [TAPAN_A_NCP_STATIC] = TAPAN_A_NCP_STATIC__POR,
667 [TAPAN_A_NCP_VTH_LOW] = TAPAN_A_NCP_VTH_LOW__POR,
668 [TAPAN_A_NCP_VTH_HIGH] = TAPAN_A_NCP_VTH_HIGH__POR,
669 [TAPAN_A_NCP_ATEST] = TAPAN_A_NCP_ATEST__POR,
670 [TAPAN_A_NCP_DTEST] = TAPAN_A_NCP_DTEST__POR,
671 [TAPAN_A_NCP_DLY1] = TAPAN_A_NCP_DLY1__POR,
672 [TAPAN_A_NCP_DLY2] = TAPAN_A_NCP_DLY2__POR,
673 [TAPAN_A_RX_AUX_SW_CTL] = TAPAN_A_RX_AUX_SW_CTL__POR,
674 [TAPAN_A_RX_PA_AUX_IN_CONN] = TAPAN_A_RX_PA_AUX_IN_CONN__POR,
675 [TAPAN_A_RX_COM_TIMER_DIV] = TAPAN_A_RX_COM_TIMER_DIV__POR,
676 [TAPAN_A_RX_COM_OCP_CTL] = TAPAN_A_RX_COM_OCP_CTL__POR,
677 [TAPAN_A_RX_COM_OCP_COUNT] = TAPAN_A_RX_COM_OCP_COUNT__POR,
678 [TAPAN_A_RX_COM_DAC_CTL] = TAPAN_A_RX_COM_DAC_CTL__POR,
679 [TAPAN_A_RX_COM_BIAS] = TAPAN_A_RX_COM_BIAS__POR,
680 [TAPAN_A_RX_HPH_AUTO_CHOP] = TAPAN_A_RX_HPH_AUTO_CHOP__POR,
681 [TAPAN_A_RX_HPH_CHOP_CTL] = TAPAN_A_RX_HPH_CHOP_CTL__POR,
682 [TAPAN_A_RX_HPH_BIAS_PA] = TAPAN_A_RX_HPH_BIAS_PA__POR,
683 [TAPAN_A_RX_HPH_BIAS_LDO] = TAPAN_A_RX_HPH_BIAS_LDO__POR,
684 [TAPAN_A_RX_HPH_BIAS_CNP] = TAPAN_A_RX_HPH_BIAS_CNP__POR,
685 [TAPAN_A_RX_HPH_BIAS_WG_OCP] = TAPAN_A_RX_HPH_BIAS_WG_OCP__POR,
686 [TAPAN_A_RX_HPH_OCP_CTL] = TAPAN_A_RX_HPH_OCP_CTL__POR,
687 [TAPAN_A_RX_HPH_CNP_EN] = TAPAN_A_RX_HPH_CNP_EN__POR,
688 [TAPAN_A_RX_HPH_CNP_WG_CTL] = TAPAN_A_RX_HPH_CNP_WG_CTL__POR,
689 [TAPAN_A_RX_HPH_CNP_WG_TIME] = TAPAN_A_RX_HPH_CNP_WG_TIME__POR,
690 [TAPAN_A_RX_HPH_L_GAIN] = TAPAN_A_RX_HPH_L_GAIN__POR,
691 [TAPAN_A_RX_HPH_L_TEST] = TAPAN_A_RX_HPH_L_TEST__POR,
692 [TAPAN_A_RX_HPH_L_PA_CTL] = TAPAN_A_RX_HPH_L_PA_CTL__POR,
693 [TAPAN_A_RX_HPH_L_DAC_CTL] = TAPAN_A_RX_HPH_L_DAC_CTL__POR,
694 [TAPAN_A_RX_HPH_L_ATEST] = TAPAN_A_RX_HPH_L_ATEST__POR,
695 [TAPAN_A_RX_HPH_L_STATUS] = TAPAN_A_RX_HPH_L_STATUS__POR,
696 [TAPAN_A_RX_HPH_R_GAIN] = TAPAN_A_RX_HPH_R_GAIN__POR,
697 [TAPAN_A_RX_HPH_R_TEST] = TAPAN_A_RX_HPH_R_TEST__POR,
698 [TAPAN_A_RX_HPH_R_PA_CTL] = TAPAN_A_RX_HPH_R_PA_CTL__POR,
699 [TAPAN_A_RX_HPH_R_DAC_CTL] = TAPAN_A_RX_HPH_R_DAC_CTL__POR,
700 [TAPAN_A_RX_HPH_R_ATEST] = TAPAN_A_RX_HPH_R_ATEST__POR,
701 [TAPAN_A_RX_HPH_R_STATUS] = TAPAN_A_RX_HPH_R_STATUS__POR,
702 [TAPAN_A_RX_EAR_BIAS_PA] = TAPAN_A_RX_EAR_BIAS_PA__POR,
703 [TAPAN_A_RX_EAR_BIAS_CMBUFF] = TAPAN_A_RX_EAR_BIAS_CMBUFF__POR,
704 [TAPAN_A_RX_EAR_EN] = TAPAN_A_RX_EAR_EN__POR,
705 [TAPAN_A_RX_EAR_GAIN] = TAPAN_A_RX_EAR_GAIN__POR,
706 [TAPAN_A_RX_EAR_CMBUFF] = TAPAN_A_RX_EAR_CMBUFF__POR,
707 [TAPAN_A_RX_EAR_ICTL] = TAPAN_A_RX_EAR_ICTL__POR,
708 [TAPAN_A_RX_EAR_CCOMP] = TAPAN_A_RX_EAR_CCOMP__POR,
709 [TAPAN_A_RX_EAR_VCM] = TAPAN_A_RX_EAR_VCM__POR,
710 [TAPAN_A_RX_EAR_CNP] = TAPAN_A_RX_EAR_CNP__POR,
711 [TAPAN_A_RX_EAR_DAC_CTL_ATEST] = TAPAN_A_RX_EAR_DAC_CTL_ATEST__POR,
712 [TAPAN_A_RX_EAR_STATUS] = TAPAN_A_RX_EAR_STATUS__POR,
713 [TAPAN_A_RX_LINE_BIAS_PA] = TAPAN_A_RX_LINE_BIAS_PA__POR,
714 [TAPAN_A_RX_BUCK_BIAS1] = TAPAN_A_RX_BUCK_BIAS1__POR,
715 [TAPAN_A_RX_BUCK_BIAS2] = TAPAN_A_RX_BUCK_BIAS2__POR,
716 [TAPAN_A_RX_LINE_COM] = TAPAN_A_RX_LINE_COM__POR,
717 [TAPAN_A_RX_LINE_CNP_EN] = TAPAN_A_RX_LINE_CNP_EN__POR,
718 [TAPAN_A_RX_LINE_CNP_WG_CTL] = TAPAN_A_RX_LINE_CNP_WG_CTL__POR,
719 [TAPAN_A_RX_LINE_CNP_WG_TIME] = TAPAN_A_RX_LINE_CNP_WG_TIME__POR,
720 [TAPAN_A_RX_LINE_1_GAIN] = TAPAN_A_RX_LINE_1_GAIN__POR,
721 [TAPAN_A_RX_LINE_1_TEST] = TAPAN_A_RX_LINE_1_TEST__POR,
722 [TAPAN_A_RX_LINE_1_DAC_CTL] = TAPAN_A_RX_LINE_1_DAC_CTL__POR,
723 [TAPAN_A_RX_LINE_1_STATUS] = TAPAN_A_RX_LINE_1_STATUS__POR,
724 [TAPAN_A_RX_LINE_2_GAIN] = TAPAN_A_RX_LINE_2_GAIN__POR,
725 [TAPAN_A_RX_LINE_2_TEST] = TAPAN_A_RX_LINE_2_TEST__POR,
726 [TAPAN_A_RX_LINE_2_DAC_CTL] = TAPAN_A_RX_LINE_2_DAC_CTL__POR,
727 [TAPAN_A_RX_LINE_2_STATUS] = TAPAN_A_RX_LINE_2_STATUS__POR,
728 [TAPAN_A_RX_LINE_CNP_DBG] = TAPAN_A_RX_LINE_CNP_DBG__POR,
729 [TAPAN_A_SPKR_DRV_EN] = TAPAN_A_SPKR_DRV_EN__POR,
730 [TAPAN_A_SPKR_DRV_GAIN] = TAPAN_A_SPKR_DRV_GAIN__POR,
731 [TAPAN_A_SPKR_DRV_DAC_CTL] = TAPAN_A_SPKR_DRV_DAC_CTL__POR,
732 [TAPAN_A_SPKR_DRV_OCP_CTL] = TAPAN_A_SPKR_DRV_OCP_CTL__POR,
733 [TAPAN_A_SPKR_DRV_CLIP_DET] = TAPAN_A_SPKR_DRV_CLIP_DET__POR,
734 [TAPAN_A_SPKR_DRV_IEC] = TAPAN_A_SPKR_DRV_IEC__POR,
735 [TAPAN_A_SPKR_DRV_DBG_DAC] = TAPAN_A_SPKR_DRV_DBG_DAC__POR,
736 [TAPAN_A_SPKR_DRV_DBG_PA] = TAPAN_A_SPKR_DRV_DBG_PA__POR,
737 [TAPAN_A_SPKR_DRV_DBG_PWRSTG] = TAPAN_A_SPKR_DRV_DBG_PWRSTG__POR,
738 [TAPAN_A_SPKR_DRV_BIAS_LDO] = TAPAN_A_SPKR_DRV_BIAS_LDO__POR,
739 [TAPAN_A_SPKR_DRV_BIAS_INT] = TAPAN_A_SPKR_DRV_BIAS_INT__POR,
740 [TAPAN_A_SPKR_DRV_BIAS_PA] = TAPAN_A_SPKR_DRV_BIAS_PA__POR,
741 [TAPAN_A_SPKR_DRV_STATUS_OCP] = TAPAN_A_SPKR_DRV_STATUS_OCP__POR,
742 [TAPAN_A_SPKR_DRV_STATUS_PA] = TAPAN_A_SPKR_DRV_STATUS_PA__POR,
743 [TAPAN_A_RC_OSC_FREQ] = TAPAN_A_RC_OSC_FREQ__POR,
744 [TAPAN_A_RC_OSC_TEST] = TAPAN_A_RC_OSC_TEST__POR,
745 [TAPAN_A_RC_OSC_STATUS] = TAPAN_A_RC_OSC_STATUS__POR,
746 [TAPAN_A_RC_OSC_TUNER] = TAPAN_A_RC_OSC_TUNER__POR,
747 [TAPAN_A_MBHC_HPH] = TAPAN_A_MBHC_HPH__POR,
748 [TAPAN_A_CDC_ANC1_B1_CTL] = TAPAN_A_CDC_ANC1_B1_CTL__POR,
749 [TAPAN_A_CDC_ANC2_B1_CTL] = TAPAN_A_CDC_ANC2_B1_CTL__POR,
750 [TAPAN_A_CDC_ANC1_SHIFT] = TAPAN_A_CDC_ANC1_SHIFT__POR,
751 [TAPAN_A_CDC_ANC2_SHIFT] = TAPAN_A_CDC_ANC2_SHIFT__POR,
752 [TAPAN_A_CDC_ANC1_IIR_B1_CTL] = TAPAN_A_CDC_ANC1_IIR_B1_CTL__POR,
753 [TAPAN_A_CDC_ANC2_IIR_B1_CTL] = TAPAN_A_CDC_ANC2_IIR_B1_CTL__POR,
754 [TAPAN_A_CDC_ANC1_IIR_B2_CTL] = TAPAN_A_CDC_ANC1_IIR_B2_CTL__POR,
755 [TAPAN_A_CDC_ANC2_IIR_B2_CTL] = TAPAN_A_CDC_ANC2_IIR_B2_CTL__POR,
756 [TAPAN_A_CDC_ANC1_IIR_B3_CTL] = TAPAN_A_CDC_ANC1_IIR_B3_CTL__POR,
757 [TAPAN_A_CDC_ANC2_IIR_B3_CTL] = TAPAN_A_CDC_ANC2_IIR_B3_CTL__POR,
758 [TAPAN_A_CDC_ANC1_LPF_B1_CTL] = TAPAN_A_CDC_ANC1_LPF_B1_CTL__POR,
759 [TAPAN_A_CDC_ANC2_LPF_B1_CTL] = TAPAN_A_CDC_ANC2_LPF_B1_CTL__POR,
760 [TAPAN_A_CDC_ANC1_LPF_B2_CTL] = TAPAN_A_CDC_ANC1_LPF_B2_CTL__POR,
761 [TAPAN_A_CDC_ANC2_LPF_B2_CTL] = TAPAN_A_CDC_ANC2_LPF_B2_CTL__POR,
762 [TAPAN_A_CDC_ANC1_SPARE] = TAPAN_A_CDC_ANC1_SPARE__POR,
763 [TAPAN_A_CDC_ANC2_SPARE] = TAPAN_A_CDC_ANC2_SPARE__POR,
764 [TAPAN_A_CDC_ANC1_SMLPF_CTL] = TAPAN_A_CDC_ANC1_SMLPF_CTL__POR,
765 [TAPAN_A_CDC_ANC2_SMLPF_CTL] = TAPAN_A_CDC_ANC2_SMLPF_CTL__POR,
766 [TAPAN_A_CDC_ANC1_DCFLT_CTL] = TAPAN_A_CDC_ANC1_DCFLT_CTL__POR,
767 [TAPAN_A_CDC_ANC2_DCFLT_CTL] = TAPAN_A_CDC_ANC2_DCFLT_CTL__POR,
768 [TAPAN_A_CDC_ANC1_GAIN_CTL] = TAPAN_A_CDC_ANC1_GAIN_CTL__POR,
769 [TAPAN_A_CDC_ANC2_GAIN_CTL] = TAPAN_A_CDC_ANC2_GAIN_CTL__POR,
770 [TAPAN_A_CDC_ANC1_B2_CTL] = TAPAN_A_CDC_ANC1_B2_CTL__POR,
771 [TAPAN_A_CDC_ANC2_B2_CTL] = TAPAN_A_CDC_ANC2_B2_CTL__POR,
772 [TAPAN_A_CDC_TX1_VOL_CTL_TIMER] = TAPAN_A_CDC_TX1_VOL_CTL_TIMER__POR,
773 [TAPAN_A_CDC_TX2_VOL_CTL_TIMER] = TAPAN_A_CDC_TX2_VOL_CTL_TIMER__POR,
774 [TAPAN_A_CDC_TX3_VOL_CTL_TIMER] = TAPAN_A_CDC_TX3_VOL_CTL_TIMER__POR,
775 [TAPAN_A_CDC_TX4_VOL_CTL_TIMER] = TAPAN_A_CDC_TX4_VOL_CTL_TIMER__POR,
776 [TAPAN_A_CDC_TX1_VOL_CTL_GAIN] = TAPAN_A_CDC_TX1_VOL_CTL_GAIN__POR,
777 [TAPAN_A_CDC_TX2_VOL_CTL_GAIN] = TAPAN_A_CDC_TX2_VOL_CTL_GAIN__POR,
778 [TAPAN_A_CDC_TX3_VOL_CTL_GAIN] = TAPAN_A_CDC_TX3_VOL_CTL_GAIN__POR,
779 [TAPAN_A_CDC_TX4_VOL_CTL_GAIN] = TAPAN_A_CDC_TX4_VOL_CTL_GAIN__POR,
780 [TAPAN_A_CDC_TX1_VOL_CTL_CFG] = TAPAN_A_CDC_TX1_VOL_CTL_CFG__POR,
781 [TAPAN_A_CDC_TX2_VOL_CTL_CFG] = TAPAN_A_CDC_TX2_VOL_CTL_CFG__POR,
782 [TAPAN_A_CDC_TX3_VOL_CTL_CFG] = TAPAN_A_CDC_TX3_VOL_CTL_CFG__POR,
783 [TAPAN_A_CDC_TX4_VOL_CTL_CFG] = TAPAN_A_CDC_TX4_VOL_CTL_CFG__POR,
784 [TAPAN_A_CDC_TX1_MUX_CTL] = TAPAN_A_CDC_TX1_MUX_CTL__POR,
785 [TAPAN_A_CDC_TX2_MUX_CTL] = TAPAN_A_CDC_TX2_MUX_CTL__POR,
786 [TAPAN_A_CDC_TX3_MUX_CTL] = TAPAN_A_CDC_TX3_MUX_CTL__POR,
787 [TAPAN_A_CDC_TX4_MUX_CTL] = TAPAN_A_CDC_TX4_MUX_CTL__POR,
788 [TAPAN_A_CDC_TX1_CLK_FS_CTL] = TAPAN_A_CDC_TX1_CLK_FS_CTL__POR,
789 [TAPAN_A_CDC_TX2_CLK_FS_CTL] = TAPAN_A_CDC_TX2_CLK_FS_CTL__POR,
790 [TAPAN_A_CDC_TX3_CLK_FS_CTL] = TAPAN_A_CDC_TX3_CLK_FS_CTL__POR,
791 [TAPAN_A_CDC_TX4_CLK_FS_CTL] = TAPAN_A_CDC_TX4_CLK_FS_CTL__POR,
792 [TAPAN_A_CDC_TX1_DMIC_CTL] = TAPAN_A_CDC_TX1_DMIC_CTL__POR,
793 [TAPAN_A_CDC_TX2_DMIC_CTL] = TAPAN_A_CDC_TX2_DMIC_CTL__POR,
794 [TAPAN_A_CDC_TX3_DMIC_CTL] = TAPAN_A_CDC_TX3_DMIC_CTL__POR,
795 [TAPAN_A_CDC_TX4_DMIC_CTL] = TAPAN_A_CDC_TX4_DMIC_CTL__POR,
796 [TAPAN_A_CDC_DEBUG_B1_CTL] = TAPAN_A_CDC_DEBUG_B1_CTL__POR,
797 [TAPAN_A_CDC_DEBUG_B2_CTL] = TAPAN_A_CDC_DEBUG_B2_CTL__POR,
798 [TAPAN_A_CDC_DEBUG_B3_CTL] = TAPAN_A_CDC_DEBUG_B3_CTL__POR,
799 [TAPAN_A_CDC_DEBUG_B4_CTL] = TAPAN_A_CDC_DEBUG_B4_CTL__POR,
800 [TAPAN_A_CDC_DEBUG_B5_CTL] = TAPAN_A_CDC_DEBUG_B5_CTL__POR,
801 [TAPAN_A_CDC_DEBUG_B6_CTL] = TAPAN_A_CDC_DEBUG_B6_CTL__POR,
802 [TAPAN_A_CDC_DEBUG_B7_CTL] = TAPAN_A_CDC_DEBUG_B7_CTL__POR,
803 [TAPAN_A_CDC_SRC1_PDA_CFG] = TAPAN_A_CDC_SRC1_PDA_CFG__POR,
804 [TAPAN_A_CDC_SRC2_PDA_CFG] = TAPAN_A_CDC_SRC2_PDA_CFG__POR,
805 [TAPAN_A_CDC_SRC1_FS_CTL] = TAPAN_A_CDC_SRC1_FS_CTL__POR,
806 [TAPAN_A_CDC_SRC2_FS_CTL] = TAPAN_A_CDC_SRC2_FS_CTL__POR,
807 [TAPAN_A_CDC_RX1_B1_CTL] = TAPAN_A_CDC_RX1_B1_CTL__POR,
808 [TAPAN_A_CDC_RX2_B1_CTL] = TAPAN_A_CDC_RX2_B1_CTL__POR,
809 [TAPAN_A_CDC_RX3_B1_CTL] = TAPAN_A_CDC_RX3_B1_CTL__POR,
810 [TAPAN_A_CDC_RX4_B1_CTL] = TAPAN_A_CDC_RX4_B1_CTL__POR,
811 [TAPAN_A_CDC_RX1_B2_CTL] = TAPAN_A_CDC_RX1_B2_CTL__POR,
812 [TAPAN_A_CDC_RX2_B2_CTL] = TAPAN_A_CDC_RX2_B2_CTL__POR,
813 [TAPAN_A_CDC_RX3_B2_CTL] = TAPAN_A_CDC_RX3_B2_CTL__POR,
814 [TAPAN_A_CDC_RX4_B2_CTL] = TAPAN_A_CDC_RX4_B2_CTL__POR,
815 [TAPAN_A_CDC_RX1_B3_CTL] = TAPAN_A_CDC_RX1_B3_CTL__POR,
816 [TAPAN_A_CDC_RX2_B3_CTL] = TAPAN_A_CDC_RX2_B3_CTL__POR,
817 [TAPAN_A_CDC_RX3_B3_CTL] = TAPAN_A_CDC_RX3_B3_CTL__POR,
818 [TAPAN_A_CDC_RX4_B3_CTL] = TAPAN_A_CDC_RX4_B3_CTL__POR,
819 [TAPAN_A_CDC_RX1_B4_CTL] = TAPAN_A_CDC_RX1_B4_CTL__POR,
820 [TAPAN_A_CDC_RX2_B4_CTL] = TAPAN_A_CDC_RX2_B4_CTL__POR,
821 [TAPAN_A_CDC_RX3_B4_CTL] = TAPAN_A_CDC_RX3_B4_CTL__POR,
822 [TAPAN_A_CDC_RX4_B4_CTL] = TAPAN_A_CDC_RX4_B4_CTL__POR,
823 [TAPAN_A_CDC_RX1_B5_CTL] = TAPAN_A_CDC_RX1_B5_CTL__POR,
824 [TAPAN_A_CDC_RX2_B5_CTL] = TAPAN_A_CDC_RX2_B5_CTL__POR,
825 [TAPAN_A_CDC_RX3_B5_CTL] = TAPAN_A_CDC_RX3_B5_CTL__POR,
826 [TAPAN_A_CDC_RX4_B5_CTL] = TAPAN_A_CDC_RX4_B5_CTL__POR,
827 [TAPAN_A_CDC_RX1_B6_CTL] = TAPAN_A_CDC_RX1_B6_CTL__POR,
828 [TAPAN_A_CDC_RX2_B6_CTL] = TAPAN_A_CDC_RX2_B6_CTL__POR,
829 [TAPAN_A_CDC_RX3_B6_CTL] = TAPAN_A_CDC_RX3_B6_CTL__POR,
830 [TAPAN_A_CDC_RX4_B6_CTL] = TAPAN_A_CDC_RX4_B6_CTL__POR,
831 [TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX1_VOL_CTL_B1_CTL__POR,
832 [TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX2_VOL_CTL_B1_CTL__POR,
833 [TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX3_VOL_CTL_B1_CTL__POR,
834 [TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL] = TAPAN_A_CDC_RX4_VOL_CTL_B1_CTL__POR,
835 [TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX1_VOL_CTL_B2_CTL__POR,
836 [TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX2_VOL_CTL_B2_CTL__POR,
837 [TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX3_VOL_CTL_B2_CTL__POR,
838 [TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL] = TAPAN_A_CDC_RX4_VOL_CTL_B2_CTL__POR,
839 [TAPAN_A_CDC_CLK_ANC_RESET_CTL] = TAPAN_A_CDC_CLK_ANC_RESET_CTL__POR,
840 [TAPAN_A_CDC_CLK_RX_RESET_CTL] = TAPAN_A_CDC_CLK_RX_RESET_CTL__POR,
841 [TAPAN_A_CDC_CLK_TX_RESET_B1_CTL] =
842 TAPAN_A_CDC_CLK_TX_RESET_B1_CTL__POR,
843 [TAPAN_A_CDC_CLK_TX_RESET_B2_CTL] =
844 TAPAN_A_CDC_CLK_TX_RESET_B2_CTL__POR,
845 [TAPAN_A_CDC_CLK_DMIC_B1_CTL] = TAPAN_A_CDC_CLK_DMIC_B1_CTL__POR,
846 [TAPAN_A_CDC_CLK_DMIC_B2_CTL] = TAPAN_A_CDC_CLK_DMIC_B2_CTL__POR,
847 [TAPAN_A_CDC_CLK_I2S_CTL] = TAPAN_A_CDC_CLK_I2S_CTL__POR,
848 [TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL] =
849 TAPAN_A_CDC_CLK_OTHR_RESET_B1_CTL__POR,
850 [TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL] =
851 TAPAN_A_CDC_CLK_OTHR_RESET_B2_CTL__POR,
852 [TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL] =
853 TAPAN_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR,
854 [TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL] =
855 TAPAN_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR,
856 [TAPAN_A_CDC_CLK_OTHR_CTL] = TAPAN_A_CDC_CLK_OTHR_CTL__POR,
857 [TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL] =
858 TAPAN_A_CDC_CLK_RDAC_CLK_EN_CTL__POR,
859 [TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL] = TAPAN_A_CDC_CLK_ANC_CLK_EN_CTL__POR,
860 [TAPAN_A_CDC_CLK_RX_B1_CTL] = TAPAN_A_CDC_CLK_RX_B1_CTL__POR,
861 [TAPAN_A_CDC_CLK_RX_B2_CTL] = TAPAN_A_CDC_CLK_RX_B2_CTL__POR,
862 [TAPAN_A_CDC_CLK_MCLK_CTL] = TAPAN_A_CDC_CLK_MCLK_CTL__POR,
863 [TAPAN_A_CDC_CLK_PDM_CTL] = TAPAN_A_CDC_CLK_PDM_CTL__POR,
864 [TAPAN_A_CDC_CLK_SD_CTL] = TAPAN_A_CDC_CLK_SD_CTL__POR,
865 [TAPAN_A_CDC_CLK_POWER_CTL] = TAPAN_A_CDC_CLK_POWER_CTL__POR,
866 [TAPAN_A_CDC_CLSH_B1_CTL] = TAPAN_A_CDC_CLSH_B1_CTL__POR,
867 [TAPAN_A_CDC_CLSH_B2_CTL] = TAPAN_A_CDC_CLSH_B2_CTL__POR,
868 [TAPAN_A_CDC_CLSH_B3_CTL] = TAPAN_A_CDC_CLSH_B3_CTL__POR,
869 [TAPAN_A_CDC_CLSH_BUCK_NCP_VARS] = TAPAN_A_CDC_CLSH_BUCK_NCP_VARS__POR,
870 [TAPAN_A_CDC_CLSH_IDLE_HPH_THSD] = TAPAN_A_CDC_CLSH_IDLE_HPH_THSD__POR,
871 [TAPAN_A_CDC_CLSH_IDLE_EAR_THSD] = TAPAN_A_CDC_CLSH_IDLE_EAR_THSD__POR,
872 [TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD] =
873 TAPAN_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR,
874 [TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD] =
875 TAPAN_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR,
876 [TAPAN_A_CDC_CLSH_K_ADDR] = TAPAN_A_CDC_CLSH_K_ADDR__POR,
877 [TAPAN_A_CDC_CLSH_K_DATA] = TAPAN_A_CDC_CLSH_K_DATA__POR,
878 [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L] =
879 TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_L__POR,
880 [TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U] =
881 TAPAN_A_CDC_CLSH_I_PA_FACT_HPH_U__POR,
882 [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L] =
883 TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_L__POR,
884 [TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U] =
885 TAPAN_A_CDC_CLSH_I_PA_FACT_EAR_U__POR,
886 [TAPAN_A_CDC_CLSH_V_PA_HD_EAR] = TAPAN_A_CDC_CLSH_V_PA_HD_EAR__POR,
887 [TAPAN_A_CDC_CLSH_V_PA_HD_HPH] = TAPAN_A_CDC_CLSH_V_PA_HD_HPH__POR,
888 [TAPAN_A_CDC_CLSH_V_PA_MIN_EAR] = TAPAN_A_CDC_CLSH_V_PA_MIN_EAR__POR,
889 [TAPAN_A_CDC_CLSH_V_PA_MIN_HPH] = TAPAN_A_CDC_CLSH_V_PA_MIN_HPH__POR,
890 [TAPAN_A_CDC_IIR1_GAIN_B1_CTL] = TAPAN_A_CDC_IIR1_GAIN_B1_CTL__POR,
891 [TAPAN_A_CDC_IIR2_GAIN_B1_CTL] = TAPAN_A_CDC_IIR2_GAIN_B1_CTL__POR,
892 [TAPAN_A_CDC_IIR1_GAIN_B2_CTL] = TAPAN_A_CDC_IIR1_GAIN_B2_CTL__POR,
893 [TAPAN_A_CDC_IIR2_GAIN_B2_CTL] = TAPAN_A_CDC_IIR2_GAIN_B2_CTL__POR,
894 [TAPAN_A_CDC_IIR1_GAIN_B3_CTL] = TAPAN_A_CDC_IIR1_GAIN_B3_CTL__POR,
895 [TAPAN_A_CDC_IIR2_GAIN_B3_CTL] = TAPAN_A_CDC_IIR2_GAIN_B3_CTL__POR,
896 [TAPAN_A_CDC_IIR1_GAIN_B4_CTL] = TAPAN_A_CDC_IIR1_GAIN_B4_CTL__POR,
897 [TAPAN_A_CDC_IIR2_GAIN_B4_CTL] = TAPAN_A_CDC_IIR2_GAIN_B4_CTL__POR,
898 [TAPAN_A_CDC_IIR1_GAIN_B5_CTL] = TAPAN_A_CDC_IIR1_GAIN_B5_CTL__POR,
899 [TAPAN_A_CDC_IIR2_GAIN_B5_CTL] = TAPAN_A_CDC_IIR2_GAIN_B5_CTL__POR,
900 [TAPAN_A_CDC_IIR1_GAIN_B6_CTL] = TAPAN_A_CDC_IIR1_GAIN_B6_CTL__POR,
901 [TAPAN_A_CDC_IIR2_GAIN_B6_CTL] = TAPAN_A_CDC_IIR2_GAIN_B6_CTL__POR,
902 [TAPAN_A_CDC_IIR1_GAIN_B7_CTL] = TAPAN_A_CDC_IIR1_GAIN_B7_CTL__POR,
903 [TAPAN_A_CDC_IIR2_GAIN_B7_CTL] = TAPAN_A_CDC_IIR2_GAIN_B7_CTL__POR,
904 [TAPAN_A_CDC_IIR1_GAIN_B8_CTL] = TAPAN_A_CDC_IIR1_GAIN_B8_CTL__POR,
905 [TAPAN_A_CDC_IIR2_GAIN_B8_CTL] = TAPAN_A_CDC_IIR2_GAIN_B8_CTL__POR,
906 [TAPAN_A_CDC_IIR1_CTL] = TAPAN_A_CDC_IIR1_CTL__POR,
907 [TAPAN_A_CDC_IIR2_CTL] = TAPAN_A_CDC_IIR2_CTL__POR,
908 [TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL] =
909 TAPAN_A_CDC_IIR1_GAIN_TIMER_CTL__POR,
910 [TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL] =
911 TAPAN_A_CDC_IIR2_GAIN_TIMER_CTL__POR,
912 [TAPAN_A_CDC_IIR1_COEF_B1_CTL] = TAPAN_A_CDC_IIR1_COEF_B1_CTL__POR,
913 [TAPAN_A_CDC_IIR2_COEF_B1_CTL] = TAPAN_A_CDC_IIR2_COEF_B1_CTL__POR,
914 [TAPAN_A_CDC_IIR1_COEF_B2_CTL] = TAPAN_A_CDC_IIR1_COEF_B2_CTL__POR,
915 [TAPAN_A_CDC_IIR2_COEF_B2_CTL] = TAPAN_A_CDC_IIR2_COEF_B2_CTL__POR,
916 [TAPAN_A_CDC_TOP_GAIN_UPDATE] = TAPAN_A_CDC_TOP_GAIN_UPDATE__POR,
917 [TAPAN_A_CDC_COMP0_B1_CTL] = TAPAN_A_CDC_COMP0_B1_CTL__POR,
918 [TAPAN_A_CDC_COMP1_B1_CTL] = TAPAN_A_CDC_COMP1_B1_CTL__POR,
919 [TAPAN_A_CDC_COMP2_B1_CTL] = TAPAN_A_CDC_COMP2_B1_CTL__POR,
920 [TAPAN_A_CDC_COMP0_B2_CTL] = TAPAN_A_CDC_COMP0_B2_CTL__POR,
921 [TAPAN_A_CDC_COMP1_B2_CTL] = TAPAN_A_CDC_COMP1_B2_CTL__POR,
922 [TAPAN_A_CDC_COMP2_B2_CTL] = TAPAN_A_CDC_COMP2_B2_CTL__POR,
923 [TAPAN_A_CDC_COMP0_B3_CTL] = TAPAN_A_CDC_COMP0_B3_CTL__POR,
924 [TAPAN_A_CDC_COMP1_B3_CTL] = TAPAN_A_CDC_COMP1_B3_CTL__POR,
925 [TAPAN_A_CDC_COMP2_B3_CTL] = TAPAN_A_CDC_COMP2_B3_CTL__POR,
926 [TAPAN_A_CDC_COMP0_B4_CTL] = TAPAN_A_CDC_COMP0_B4_CTL__POR,
927 [TAPAN_A_CDC_COMP1_B4_CTL] = TAPAN_A_CDC_COMP1_B4_CTL__POR,
928 [TAPAN_A_CDC_COMP2_B4_CTL] = TAPAN_A_CDC_COMP2_B4_CTL__POR,
929 [TAPAN_A_CDC_COMP0_B5_CTL] = TAPAN_A_CDC_COMP0_B5_CTL__POR,
930 [TAPAN_A_CDC_COMP1_B5_CTL] = TAPAN_A_CDC_COMP1_B5_CTL__POR,
931 [TAPAN_A_CDC_COMP2_B5_CTL] = TAPAN_A_CDC_COMP2_B5_CTL__POR,
932 [TAPAN_A_CDC_COMP0_B6_CTL] = TAPAN_A_CDC_COMP0_B6_CTL__POR,
933 [TAPAN_A_CDC_COMP1_B6_CTL] = TAPAN_A_CDC_COMP1_B6_CTL__POR,
934 [TAPAN_A_CDC_COMP2_B6_CTL] = TAPAN_A_CDC_COMP2_B6_CTL__POR,
935 [TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS] =
936 TAPAN_A_CDC_COMP0_SHUT_DOWN_STATUS__POR,
937 [TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS] =
938 TAPAN_A_CDC_COMP1_SHUT_DOWN_STATUS__POR,
939 [TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS] =
940 TAPAN_A_CDC_COMP2_SHUT_DOWN_STATUS__POR,
941 [TAPAN_A_CDC_COMP0_FS_CFG] = TAPAN_A_CDC_COMP0_FS_CFG__POR,
942 [TAPAN_A_CDC_COMP1_FS_CFG] = TAPAN_A_CDC_COMP1_FS_CFG__POR,
943 [TAPAN_A_CDC_COMP2_FS_CFG] = TAPAN_A_CDC_COMP2_FS_CFG__POR,
944 [TAPAN_A_CDC_CONN_RX1_B1_CTL] = TAPAN_A_CDC_CONN_RX1_B1_CTL__POR,
945 [TAPAN_A_CDC_CONN_RX1_B2_CTL] = TAPAN_A_CDC_CONN_RX1_B2_CTL__POR,
946 [TAPAN_A_CDC_CONN_RX1_B3_CTL] = TAPAN_A_CDC_CONN_RX1_B3_CTL__POR,
947 [TAPAN_A_CDC_CONN_RX2_B1_CTL] = TAPAN_A_CDC_CONN_RX2_B1_CTL__POR,
948 [TAPAN_A_CDC_CONN_RX2_B2_CTL] = TAPAN_A_CDC_CONN_RX2_B2_CTL__POR,
949 [TAPAN_A_CDC_CONN_RX2_B3_CTL] = TAPAN_A_CDC_CONN_RX2_B3_CTL__POR,
950 [TAPAN_A_CDC_CONN_RX3_B1_CTL] = TAPAN_A_CDC_CONN_RX3_B1_CTL__POR,
951 [TAPAN_A_CDC_CONN_RX3_B2_CTL] = TAPAN_A_CDC_CONN_RX3_B2_CTL__POR,
952 [TAPAN_A_CDC_CONN_RX4_B1_CTL] = TAPAN_A_CDC_CONN_RX4_B1_CTL__POR,
953 [TAPAN_A_CDC_CONN_RX4_B2_CTL] = TAPAN_A_CDC_CONN_RX4_B2_CTL__POR,
954 [TAPAN_A_CDC_CONN_RX4_B3_CTL] = TAPAN_A_CDC_CONN_RX4_B3_CTL__POR,
955 [TAPAN_A_CDC_CONN_ANC_B1_CTL] = TAPAN_A_CDC_CONN_ANC_B1_CTL__POR,
956 [TAPAN_A_CDC_CONN_ANC_B2_CTL] = TAPAN_A_CDC_CONN_ANC_B2_CTL__POR,
957 [TAPAN_A_CDC_CONN_TX_B1_CTL] = TAPAN_A_CDC_CONN_TX_B1_CTL__POR,
958 [TAPAN_A_CDC_CONN_TX_B2_CTL] = TAPAN_A_CDC_CONN_TX_B2_CTL__POR,
959 [TAPAN_A_CDC_CONN_TX_B3_CTL] = TAPAN_A_CDC_CONN_TX_B3_CTL__POR,
960 [TAPAN_A_CDC_CONN_TX_B4_CTL] = TAPAN_A_CDC_CONN_TX_B4_CTL__POR,
961 [TAPAN_A_CDC_CONN_EQ1_B1_CTL] = TAPAN_A_CDC_CONN_EQ1_B1_CTL__POR,
962 [TAPAN_A_CDC_CONN_EQ1_B2_CTL] = TAPAN_A_CDC_CONN_EQ1_B2_CTL__POR,
963 [TAPAN_A_CDC_CONN_EQ1_B3_CTL] = TAPAN_A_CDC_CONN_EQ1_B3_CTL__POR,
964 [TAPAN_A_CDC_CONN_EQ1_B4_CTL] = TAPAN_A_CDC_CONN_EQ1_B4_CTL__POR,
965 [TAPAN_A_CDC_CONN_EQ2_B1_CTL] = TAPAN_A_CDC_CONN_EQ2_B1_CTL__POR,
966 [TAPAN_A_CDC_CONN_EQ2_B2_CTL] = TAPAN_A_CDC_CONN_EQ2_B2_CTL__POR,
967 [TAPAN_A_CDC_CONN_EQ2_B3_CTL] = TAPAN_A_CDC_CONN_EQ2_B3_CTL__POR,
968 [TAPAN_A_CDC_CONN_EQ2_B4_CTL] = TAPAN_A_CDC_CONN_EQ2_B4_CTL__POR,
969 [TAPAN_A_CDC_CONN_SRC1_B1_CTL] = TAPAN_A_CDC_CONN_SRC1_B1_CTL__POR,
970 [TAPAN_A_CDC_CONN_SRC1_B2_CTL] = TAPAN_A_CDC_CONN_SRC1_B2_CTL__POR,
971 [TAPAN_A_CDC_CONN_SRC2_B1_CTL] = TAPAN_A_CDC_CONN_SRC2_B1_CTL__POR,
972 [TAPAN_A_CDC_CONN_SRC2_B2_CTL] = TAPAN_A_CDC_CONN_SRC2_B2_CTL__POR,
973 [TAPAN_A_CDC_CONN_TX_SB_B1_CTL] = TAPAN_A_CDC_CONN_TX_SB_B1_CTL__POR,
974 [TAPAN_A_CDC_CONN_TX_SB_B2_CTL] = TAPAN_A_CDC_CONN_TX_SB_B2_CTL__POR,
975 [TAPAN_A_CDC_CONN_TX_SB_B3_CTL] = TAPAN_A_CDC_CONN_TX_SB_B3_CTL__POR,
976 [TAPAN_A_CDC_CONN_TX_SB_B4_CTL] = TAPAN_A_CDC_CONN_TX_SB_B4_CTL__POR,
977 [TAPAN_A_CDC_CONN_TX_SB_B5_CTL] = TAPAN_A_CDC_CONN_TX_SB_B5_CTL__POR,
978 [TAPAN_A_CDC_CONN_TX_SB_B11_CTL] = TAPAN_A_CDC_CONN_TX_SB_B11_CTL__POR,
979 [TAPAN_A_CDC_CONN_RX_SB_B1_CTL] = TAPAN_A_CDC_CONN_RX_SB_B1_CTL__POR,
980 [TAPAN_A_CDC_CONN_RX_SB_B2_CTL] = TAPAN_A_CDC_CONN_RX_SB_B2_CTL__POR,
981 [TAPAN_A_CDC_CONN_CLSH_CTL] = TAPAN_A_CDC_CONN_CLSH_CTL__POR,
982 [TAPAN_A_CDC_CONN_MISC] = TAPAN_A_CDC_CONN_MISC__POR,
983 [TAPAN_A_CDC_MBHC_EN_CTL] = TAPAN_A_CDC_MBHC_EN_CTL__POR,
984 [TAPAN_A_CDC_MBHC_FIR_B1_CFG] = TAPAN_A_CDC_MBHC_FIR_B1_CFG__POR,
985 [TAPAN_A_CDC_MBHC_FIR_B2_CFG] = TAPAN_A_CDC_MBHC_FIR_B2_CFG__POR,
986 [TAPAN_A_CDC_MBHC_TIMER_B1_CTL] = TAPAN_A_CDC_MBHC_TIMER_B1_CTL__POR,
987 [TAPAN_A_CDC_MBHC_TIMER_B2_CTL] = TAPAN_A_CDC_MBHC_TIMER_B2_CTL__POR,
988 [TAPAN_A_CDC_MBHC_TIMER_B3_CTL] = TAPAN_A_CDC_MBHC_TIMER_B3_CTL__POR,
989 [TAPAN_A_CDC_MBHC_TIMER_B4_CTL] = TAPAN_A_CDC_MBHC_TIMER_B4_CTL__POR,
990 [TAPAN_A_CDC_MBHC_TIMER_B5_CTL] = TAPAN_A_CDC_MBHC_TIMER_B5_CTL__POR,
991 [TAPAN_A_CDC_MBHC_TIMER_B6_CTL] = TAPAN_A_CDC_MBHC_TIMER_B6_CTL__POR,
992 [TAPAN_A_CDC_MBHC_B1_STATUS] = TAPAN_A_CDC_MBHC_B1_STATUS__POR,
993 [TAPAN_A_CDC_MBHC_B2_STATUS] = TAPAN_A_CDC_MBHC_B2_STATUS__POR,
994 [TAPAN_A_CDC_MBHC_B3_STATUS] = TAPAN_A_CDC_MBHC_B3_STATUS__POR,
995 [TAPAN_A_CDC_MBHC_B4_STATUS] = TAPAN_A_CDC_MBHC_B4_STATUS__POR,
996 [TAPAN_A_CDC_MBHC_B5_STATUS] = TAPAN_A_CDC_MBHC_B5_STATUS__POR,
997 [TAPAN_A_CDC_MBHC_B1_CTL] = TAPAN_A_CDC_MBHC_B1_CTL__POR,
998 [TAPAN_A_CDC_MBHC_B2_CTL] = TAPAN_A_CDC_MBHC_B2_CTL__POR,
999 [TAPAN_A_CDC_MBHC_VOLT_B1_CTL] = TAPAN_A_CDC_MBHC_VOLT_B1_CTL__POR,
1000 [TAPAN_A_CDC_MBHC_VOLT_B2_CTL] = TAPAN_A_CDC_MBHC_VOLT_B2_CTL__POR,
1001 [TAPAN_A_CDC_MBHC_VOLT_B3_CTL] = TAPAN_A_CDC_MBHC_VOLT_B3_CTL__POR,
1002 [TAPAN_A_CDC_MBHC_VOLT_B4_CTL] = TAPAN_A_CDC_MBHC_VOLT_B4_CTL__POR,
1003 [TAPAN_A_CDC_MBHC_VOLT_B5_CTL] = TAPAN_A_CDC_MBHC_VOLT_B5_CTL__POR,
1004 [TAPAN_A_CDC_MBHC_VOLT_B6_CTL] = TAPAN_A_CDC_MBHC_VOLT_B6_CTL__POR,
1005 [TAPAN_A_CDC_MBHC_VOLT_B7_CTL] = TAPAN_A_CDC_MBHC_VOLT_B7_CTL__POR,
1006 [TAPAN_A_CDC_MBHC_VOLT_B8_CTL] = TAPAN_A_CDC_MBHC_VOLT_B8_CTL__POR,
1007 [TAPAN_A_CDC_MBHC_VOLT_B9_CTL] = TAPAN_A_CDC_MBHC_VOLT_B9_CTL__POR,
1008 [TAPAN_A_CDC_MBHC_VOLT_B10_CTL] = TAPAN_A_CDC_MBHC_VOLT_B10_CTL__POR,
1009 [TAPAN_A_CDC_MBHC_VOLT_B11_CTL] = TAPAN_A_CDC_MBHC_VOLT_B11_CTL__POR,
1010 [TAPAN_A_CDC_MBHC_VOLT_B12_CTL] = TAPAN_A_CDC_MBHC_VOLT_B12_CTL__POR,
1011 [TAPAN_A_CDC_MBHC_CLK_CTL] = TAPAN_A_CDC_MBHC_CLK_CTL__POR,
1012 [TAPAN_A_CDC_MBHC_INT_CTL] = TAPAN_A_CDC_MBHC_INT_CTL__POR,
1013 [TAPAN_A_CDC_MBHC_DEBUG_CTL] = TAPAN_A_CDC_MBHC_DEBUG_CTL__POR,
1014 [TAPAN_A_CDC_MBHC_SPARE] = TAPAN_A_CDC_MBHC_SPARE__POR,
1015};