blob: ec688548c880ef67d1cf568e6f568c678099232f [file] [log] [blame]
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +02001/*
2 * drivers/mtd/ndfc.c
3 *
4 * Overview:
Sean MacLennana808ad32008-12-10 13:16:34 +00005 * Platform independent driver for NDFC (NanD Flash Controller)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +02006 * integrated into EP440 cores
7 *
Sean MacLennana808ad32008-12-10 13:16:34 +00008 * Ported to an OF platform driver by Sean MacLennan
9 *
10 * The NDFC supports multiple chips, but this driver only supports a
11 * single chip since I do not have access to any boards with
12 * multiple chips.
13 *
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020014 * Author: Thomas Gleixner
15 *
16 * Copyright 2006 IBM
Sean MacLennana808ad32008-12-10 13:16:34 +000017 * Copyright 2008 PIKA Technologies
18 * Sean MacLennan <smaclennan@pikatech.com>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020019 *
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
24 *
25 */
26#include <linux/module.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/mtd/partitions.h>
30#include <linux/mtd/ndfc.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090031#include <linux/slab.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020032#include <linux/mtd/mtd.h>
Sean MacLennana808ad32008-12-10 13:16:34 +000033#include <linux/of_platform.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020034#include <asm/io.h>
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020035
Felix Radensky410fe2f2011-04-26 12:36:46 +030036#define NDFC_MAX_CS 4
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020037
38struct ndfc_controller {
Grant Likely2dc11582010-08-06 09:25:50 -060039 struct platform_device *ofdev;
Sean MacLennana808ad32008-12-10 13:16:34 +000040 void __iomem *ndfcbase;
41 struct mtd_info mtd;
42 struct nand_chip chip;
43 int chip_select;
44 struct nand_hw_control ndfc_control;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020045};
46
Felix Radensky410fe2f2011-04-26 12:36:46 +030047static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020048
49static void ndfc_select_chip(struct mtd_info *mtd, int chip)
50{
51 uint32_t ccr;
Felix Radensky410fe2f2011-04-26 12:36:46 +030052 struct nand_chip *nchip = mtd->priv;
53 struct ndfc_controller *ndfc = nchip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020054
Sean MacLennana808ad32008-12-10 13:16:34 +000055 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020056 if (chip >= 0) {
57 ccr &= ~NDFC_CCR_BS_MASK;
Sean MacLennana808ad32008-12-10 13:16:34 +000058 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020059 } else
60 ccr |= NDFC_CCR_RESET_CE;
Sean MacLennana808ad32008-12-10 13:16:34 +000061 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020062}
63
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020064static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020065{
Felix Radensky410fe2f2011-04-26 12:36:46 +030066 struct nand_chip *chip = mtd->priv;
67 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020068
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020069 if (cmd == NAND_CMD_NONE)
70 return;
71
72 if (ctrl & NAND_CLE)
Thomas Gleixner1794c132006-06-22 13:06:43 +020073 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +020074 else
Thomas Gleixner1794c132006-06-22 13:06:43 +020075 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020076}
77
78static int ndfc_ready(struct mtd_info *mtd)
79{
Felix Radensky410fe2f2011-04-26 12:36:46 +030080 struct nand_chip *chip = mtd->priv;
81 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020082
Sean MacLennana808ad32008-12-10 13:16:34 +000083 return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020084}
85
86static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
87{
88 uint32_t ccr;
Felix Radensky410fe2f2011-04-26 12:36:46 +030089 struct nand_chip *chip = mtd->priv;
90 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020091
Sean MacLennana808ad32008-12-10 13:16:34 +000092 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020093 ccr |= NDFC_CCR_RESET_ECC;
Sean MacLennana808ad32008-12-10 13:16:34 +000094 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +020095 wmb();
96}
97
98static int ndfc_calculate_ecc(struct mtd_info *mtd,
99 const u_char *dat, u_char *ecc_code)
100{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300101 struct nand_chip *chip = mtd->priv;
102 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200103 uint32_t ecc;
104 uint8_t *p = (uint8_t *)&ecc;
105
106 wmb();
Sean MacLennana808ad32008-12-10 13:16:34 +0000107 ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
108 /* The NDFC uses Smart Media (SMC) bytes order */
Feng Kan76c23c32009-08-25 11:27:20 -0700109 ecc_code[0] = p[1];
110 ecc_code[1] = p[2];
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200111 ecc_code[2] = p[3];
112
113 return 0;
114}
115
116/*
117 * Speedups for buffer read/write/verify
118 *
119 * NDFC allows 32bit read/write of data. So we can speed up the buffer
120 * functions. No further checking, as nand_base will always read/write
121 * page aligned.
122 */
123static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
124{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300125 struct nand_chip *chip = mtd->priv;
126 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200127 uint32_t *p = (uint32_t *) buf;
128
129 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000130 *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200131}
132
133static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
134{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300135 struct nand_chip *chip = mtd->priv;
136 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200137 uint32_t *p = (uint32_t *) buf;
138
139 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000140 out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200141}
142
143static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
144{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300145 struct nand_chip *chip = mtd->priv;
146 struct ndfc_controller *ndfc = chip->priv;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200147 uint32_t *p = (uint32_t *) buf;
148
149 for(;len > 0; len -= 4)
Sean MacLennana808ad32008-12-10 13:16:34 +0000150 if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200151 return -EFAULT;
152 return 0;
153}
154
155/*
156 * Initialize chip structure
157 */
Sean MacLennana808ad32008-12-10 13:16:34 +0000158static int ndfc_chip_init(struct ndfc_controller *ndfc,
159 struct device_node *node)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200160{
Sean MacLennana808ad32008-12-10 13:16:34 +0000161 struct device_node *flash_np;
162 struct nand_chip *chip = &ndfc->chip;
Dmitry Eremin-Solenikov9d7948c2011-05-30 01:02:25 +0400163 struct mtd_part_parser_data ppdata;
Sean MacLennana808ad32008-12-10 13:16:34 +0000164 int ret;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200165
166 chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
167 chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200168 chip->cmd_ctrl = ndfc_hwcontrol;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200169 chip->dev_ready = ndfc_ready;
170 chip->select_chip = ndfc_select_chip;
171 chip->chip_delay = 50;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200172 chip->controller = &ndfc->ndfc_control;
173 chip->read_buf = ndfc_read_buf;
174 chip->write_buf = ndfc_write_buf;
175 chip->verify_buf = ndfc_verify_buf;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200176 chip->ecc.correct = nand_correct_data;
177 chip->ecc.hwctl = ndfc_enable_hwecc;
178 chip->ecc.calculate = ndfc_calculate_ecc;
179 chip->ecc.mode = NAND_ECC_HW;
180 chip->ecc.size = 256;
181 chip->ecc.bytes = 3;
Felix Radensky410fe2f2011-04-26 12:36:46 +0300182 chip->priv = ndfc;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200183
Sean MacLennana808ad32008-12-10 13:16:34 +0000184 ndfc->mtd.priv = chip;
185 ndfc->mtd.owner = THIS_MODULE;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200186
Sean MacLennana808ad32008-12-10 13:16:34 +0000187 flash_np = of_get_next_child(node, NULL);
188 if (!flash_np)
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200189 return -ENODEV;
Sean MacLennana808ad32008-12-10 13:16:34 +0000190
Tony Breeds629be5f2011-11-22 15:39:11 +1100191 ppdata.of_node = flash_np;
Sean MacLennana808ad32008-12-10 13:16:34 +0000192 ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s",
Kay Sieversc36f1e32009-03-24 16:38:21 -0700193 dev_name(&ndfc->ofdev->dev), flash_np->name);
Sean MacLennana808ad32008-12-10 13:16:34 +0000194 if (!ndfc->mtd.name) {
195 ret = -ENOMEM;
196 goto err;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200197 }
198
Sean MacLennana808ad32008-12-10 13:16:34 +0000199 ret = nand_scan(&ndfc->mtd, 1);
200 if (ret)
201 goto err;
202
Dmitry Eremin-Solenikova9106492011-06-02 18:00:51 +0400203 ret = mtd_device_parse_register(&ndfc->mtd, NULL, &ppdata, NULL, 0);
Sean MacLennana808ad32008-12-10 13:16:34 +0000204
205err:
206 of_node_put(flash_np);
207 if (ret)
208 kfree(ndfc->mtd.name);
209 return ret;
210}
211
Grant Likely1c48a5c2011-02-17 02:43:24 -0700212static int __devinit ndfc_probe(struct platform_device *ofdev)
Sean MacLennana808ad32008-12-10 13:16:34 +0000213{
Felix Radensky410fe2f2011-04-26 12:36:46 +0300214 struct ndfc_controller *ndfc;
Ian Munsie766f2712010-10-01 17:06:08 +1000215 const __be32 *reg;
Sean MacLennana808ad32008-12-10 13:16:34 +0000216 u32 ccr;
Felix Radensky410fe2f2011-04-26 12:36:46 +0300217 int err, len, cs;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200218
Sean MacLennana808ad32008-12-10 13:16:34 +0000219 /* Read the reg property to get the chip select */
Grant Likely61c7a082010-04-13 16:12:29 -0700220 reg = of_get_property(ofdev->dev.of_node, "reg", &len);
Sean MacLennana808ad32008-12-10 13:16:34 +0000221 if (reg == NULL || len != 12) {
222 dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
223 return -ENOENT;
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200224 }
Felix Radensky410fe2f2011-04-26 12:36:46 +0300225
226 cs = be32_to_cpu(reg[0]);
227 if (cs >= NDFC_MAX_CS) {
228 dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
229 return -EINVAL;
230 }
231
232 ndfc = &ndfc_ctrl[cs];
233 ndfc->chip_select = cs;
234
235 spin_lock_init(&ndfc->ndfc_control.lock);
236 init_waitqueue_head(&ndfc->ndfc_control.wq);
237 ndfc->ofdev = ofdev;
238 dev_set_drvdata(&ofdev->dev, ndfc);
Sean MacLennana808ad32008-12-10 13:16:34 +0000239
Grant Likely61c7a082010-04-13 16:12:29 -0700240 ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
Sean MacLennana808ad32008-12-10 13:16:34 +0000241 if (!ndfc->ndfcbase) {
242 dev_err(&ofdev->dev, "failed to get memory\n");
243 return -EIO;
244 }
245
246 ccr = NDFC_CCR_BS(ndfc->chip_select);
247
248 /* It is ok if ccr does not exist - just default to 0 */
Grant Likely61c7a082010-04-13 16:12:29 -0700249 reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
Sean MacLennana808ad32008-12-10 13:16:34 +0000250 if (reg)
Ian Munsie766f2712010-10-01 17:06:08 +1000251 ccr |= be32_to_cpup(reg);
Sean MacLennana808ad32008-12-10 13:16:34 +0000252
253 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
254
255 /* Set the bank settings if given */
Grant Likely61c7a082010-04-13 16:12:29 -0700256 reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
Sean MacLennana808ad32008-12-10 13:16:34 +0000257 if (reg) {
258 int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
Ian Munsie766f2712010-10-01 17:06:08 +1000259 out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
Sean MacLennana808ad32008-12-10 13:16:34 +0000260 }
261
Grant Likely61c7a082010-04-13 16:12:29 -0700262 err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
Sean MacLennana808ad32008-12-10 13:16:34 +0000263 if (err) {
264 iounmap(ndfc->ndfcbase);
265 return err;
266 }
267
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200268 return 0;
269}
270
Grant Likely2dc11582010-08-06 09:25:50 -0600271static int __devexit ndfc_remove(struct platform_device *ofdev)
Sean MacLennana808ad32008-12-10 13:16:34 +0000272{
273 struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200274
Sean MacLennana808ad32008-12-10 13:16:34 +0000275 nand_release(&ndfc->mtd);
Axel Lin96166052011-06-07 22:55:21 +0800276 kfree(ndfc->mtd.name);
Sean MacLennana808ad32008-12-10 13:16:34 +0000277
278 return 0;
279}
280
281static const struct of_device_id ndfc_match[] = {
282 { .compatible = "ibm,ndfc", },
283 {}
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200284};
Sean MacLennana808ad32008-12-10 13:16:34 +0000285MODULE_DEVICE_TABLE(of, ndfc_match);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200286
Grant Likely1c48a5c2011-02-17 02:43:24 -0700287static struct platform_driver ndfc_driver = {
Sean MacLennana808ad32008-12-10 13:16:34 +0000288 .driver = {
Grant Likely40182942010-04-13 16:13:02 -0700289 .name = "ndfc",
290 .owner = THIS_MODULE,
291 .of_match_table = ndfc_match,
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200292 },
Sean MacLennana808ad32008-12-10 13:16:34 +0000293 .probe = ndfc_probe,
294 .remove = __devexit_p(ndfc_remove),
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200295};
296
Axel Linf99640d2011-11-27 20:45:03 +0800297module_platform_driver(ndfc_driver);
Thomas Gleixnerce4c61f2006-05-23 11:43:28 +0200298
299MODULE_LICENSE("GPL");
300MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
Sean MacLennana808ad32008-12-10 13:16:34 +0000301MODULE_DESCRIPTION("OF Platform driver for NDFC");