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Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
Rajendra Nayak2f5939c2008-09-26 17:50:07 +05308 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
Kevin Hilman8bd22942009-05-28 10:56:16 -070011 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
Kevin Hilmanc40552b2009-10-06 14:25:09 -070028#include <linux/clk.h>
Tero Kristodccaad82009-11-17 18:34:53 +020029#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Paul Walmsley0d8e2d02010-11-24 16:49:05 -070031#include <linux/console.h>
Jean Pihet5e7c58d2011-03-03 11:25:43 +010032#include <trace/events/power.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070033
Tony Lindgrence491cf2009-10-20 09:40:47 -070034#include <plat/sram.h>
Paul Walmsley1540f2142010-12-21 21:05:15 -070035#include "clockdomain.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070036#include "powerdomain.h"
Tony Lindgrence491cf2009-10-20 09:40:47 -070037#include <plat/serial.h>
Rajendra Nayak61255ab2008-09-26 17:49:56 +053038#include <plat/sdrc.h>
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053039#include <plat/prcm.h>
40#include <plat/gpmc.h>
Tero Kristof2d11852008-08-28 13:13:31 +000041#include <plat/dma.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070042
Rajendra Nayak57f277b2008-09-26 17:49:34 +053043#include <asm/tlbflush.h>
44
Paul Walmsley59fb6592010-12-21 15:30:55 -070045#include "cm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070046#include "cm-regbits-34xx.h"
47#include "prm-regbits-34xx.h"
48
Paul Walmsley59fb6592010-12-21 15:30:55 -070049#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070050#include "pm.h"
Tero Kristo13a6fe02008-10-13 13:17:06 +030051#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060052#include "control.h"
Tero Kristo13a6fe02008-10-13 13:17:06 +030053
Kevin Hilmane83df172010-12-08 22:40:40 +000054#ifdef CONFIG_SUSPEND
55static suspend_state_t suspend_state = PM_SUSPEND_ON;
56static inline bool is_suspending(void)
57{
58 return (suspend_state != PM_SUSPEND_ON);
59}
60#else
61static inline bool is_suspending(void)
62{
63 return false;
64}
65#endif
66
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053067/* Scratchpad offsets */
Kevin Hilmande658152010-10-08 22:43:45 +000068#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
69#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
70#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053071
Nishanth Menon8cdfd832010-12-20 14:05:05 -060072/* pm34xx errata defined in pm.h */
73u16 pm34xx_errata;
74
Kevin Hilman8bd22942009-05-28 10:56:16 -070075struct power_state {
76 struct powerdomain *pwrdm;
77 u32 next_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070078#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -070079 u32 saved_state;
Kevin Hilman10f90ed2009-06-24 11:39:18 -070080#endif
Kevin Hilman8bd22942009-05-28 10:56:16 -070081 struct list_head node;
82};
83
84static LIST_HEAD(pwrst_list);
85
86static void (*_omap_sram_idle)(u32 *addr, int save_state);
87
Tero Kristo27d59a42008-10-13 13:15:00 +030088static int (*_omap_save_secure_sram)(u32 *addr);
89
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053090static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
91static struct powerdomain *core_pwrdm, *per_pwrdm;
Tero Kristoc16c3f62008-12-11 16:46:57 +020092static struct powerdomain *cam_pwrdm;
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +053093
Rajendra Nayak2f5939c2008-09-26 17:50:07 +053094static inline void omap3_per_save_context(void)
95{
96 omap_gpio_save_context();
97}
98
99static inline void omap3_per_restore_context(void)
100{
101 omap_gpio_restore_context();
102}
103
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200104static void omap3_enable_io_chain(void)
105{
106 int timeout = 0;
107
108 if (omap_rev() >= OMAP3430_REV_ES3_1) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700109 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600110 PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200111 /* Do a readback to assure write has been done */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700112 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200113
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700114 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600115 OMAP3430_ST_IO_CHAIN_MASK)) {
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200116 timeout++;
117 if (timeout > 1000) {
118 printk(KERN_ERR "Wake up daisy chain "
119 "activation failed.\n");
120 return;
121 }
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700122 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
Kevin Hilman0b96a3a2010-06-09 13:53:09 +0300123 WKUP_MOD, PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200124 }
125 }
126}
127
128static void omap3_disable_io_chain(void)
129{
130 if (omap_rev() >= OMAP3430_REV_ES3_1)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700131 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600132 PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200133}
134
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530135static void omap3_core_save_context(void)
136{
Paul Walmsley596efe42010-12-21 21:05:16 -0700137 omap3_ctrl_save_padconf();
Tero Kristodccaad82009-11-17 18:34:53 +0200138
139 /*
140 * Force write last pad into memory, as this can fail in some
Jean Pihet83521292010-12-18 16:44:46 +0100141 * cases according to errata 1.157, 1.185
Tero Kristodccaad82009-11-17 18:34:53 +0200142 */
143 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
144 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
145
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530146 /* Save the Interrupt controller context */
147 omap_intc_save_context();
148 /* Save the GPMC context */
149 omap3_gpmc_save_context();
150 /* Save the system control module context, padconf already save above*/
151 omap3_control_save_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000152 omap_dma_global_context_save();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530153}
154
155static void omap3_core_restore_context(void)
156{
157 /* Restore the control module context, padconf restored by h/w */
158 omap3_control_restore_context();
159 /* Restore the GPMC context */
160 omap3_gpmc_restore_context();
161 /* Restore the interrupt controller context */
162 omap_intc_restore_context();
Tero Kristof2d11852008-08-28 13:13:31 +0000163 omap_dma_global_context_restore();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530164}
165
Tero Kristo9d971402008-12-12 11:20:05 +0200166/*
167 * FIXME: This function should be called before entering off-mode after
168 * OMAP3 secure services have been accessed. Currently it is only called
169 * once during boot sequence, but this works as we are not using secure
170 * services.
171 */
Kevin Hilman617fcc92011-01-25 16:40:01 -0800172static void omap3_save_secure_ram_context(void)
Tero Kristo27d59a42008-10-13 13:15:00 +0300173{
174 u32 ret;
Kevin Hilman617fcc92011-01-25 16:40:01 -0800175 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300176
177 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
Tero Kristo27d59a42008-10-13 13:15:00 +0300178 /*
179 * MPU next state must be set to POWER_ON temporarily,
180 * otherwise the WFI executed inside the ROM code
181 * will hang the system.
182 */
183 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
184 ret = _omap_save_secure_sram((u32 *)
185 __pa(omap3_secure_ram_storage));
Kevin Hilman617fcc92011-01-25 16:40:01 -0800186 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
Tero Kristo27d59a42008-10-13 13:15:00 +0300187 /* Following is for error tracking, it should not happen */
188 if (ret) {
189 printk(KERN_ERR "save_secure_sram() returns %08x\n",
190 ret);
191 while (1)
192 ;
193 }
194 }
195}
196
Jon Hunter77da2d92009-06-27 00:07:25 -0500197/*
198 * PRCM Interrupt Handler Helper Function
199 *
200 * The purpose of this function is to clear any wake-up events latched
201 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
202 * may occur whilst attempting to clear a PM_WKST_x register and thus
203 * set another bit in this register. A while loop is used to ensure
204 * that any peripheral wake-up events occurring while attempting to
205 * clear the PM_WKST_x are detected and cleared.
206 */
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700207static int prcm_clear_mod_irqs(s16 module, u8 regs)
Jon Hunter77da2d92009-06-27 00:07:25 -0500208{
Vikram Pandita71a80772009-07-17 19:33:09 -0500209 u32 wkst, fclk, iclk, clken;
Jon Hunter77da2d92009-06-27 00:07:25 -0500210 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
211 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
212 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
Paul Walmsley5d805972009-07-22 10:18:07 -0700213 u16 grpsel_off = (regs == 3) ?
214 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700215 int c = 0;
Jon Hunter77da2d92009-06-27 00:07:25 -0500216
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700217 wkst = omap2_prm_read_mod_reg(module, wkst_off);
218 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500219 if (wkst) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700220 iclk = omap2_cm_read_mod_reg(module, iclk_off);
221 fclk = omap2_cm_read_mod_reg(module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500222 while (wkst) {
Vikram Pandita71a80772009-07-17 19:33:09 -0500223 clken = wkst;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700224 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
Vikram Pandita71a80772009-07-17 19:33:09 -0500225 /*
226 * For USBHOST, we don't know whether HOST1 or
227 * HOST2 woke us up, so enable both f-clocks
228 */
229 if (module == OMAP3430ES2_USBHOST_MOD)
230 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700231 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
232 omap2_prm_write_mod_reg(wkst, module, wkst_off);
233 wkst = omap2_prm_read_mod_reg(module, wkst_off);
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700234 c++;
Jon Hunter77da2d92009-06-27 00:07:25 -0500235 }
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700236 omap2_cm_write_mod_reg(iclk, module, iclk_off);
237 omap2_cm_write_mod_reg(fclk, module, fclk_off);
Jon Hunter77da2d92009-06-27 00:07:25 -0500238 }
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700239
240 return c;
241}
242
243static int _prcm_int_handle_wakeup(void)
244{
245 int c;
246
247 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
248 c += prcm_clear_mod_irqs(CORE_MOD, 1);
249 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
250 if (omap_rev() > OMAP3430_REV_ES1_0) {
251 c += prcm_clear_mod_irqs(CORE_MOD, 3);
252 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
253 }
254
255 return c;
Jon Hunter77da2d92009-06-27 00:07:25 -0500256}
257
258/*
259 * PRCM Interrupt Handler
260 *
261 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
262 * interrupts from the PRCM for the MPU. These bits must be cleared in
263 * order to clear the PRCM interrupt. The PRCM interrupt handler is
264 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
265 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
266 * register indicates that a wake-up event is pending for the MPU and
267 * this bit can only be cleared if the all the wake-up events latched
268 * in the various PM_WKST_x registers have been cleared. The interrupt
269 * handler is implemented using a do-while loop so that if a wake-up
270 * event occurred during the processing of the prcm interrupt handler
271 * (setting a bit in the corresponding PM_WKST_x register and thus
272 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
273 * this would be handled.
274 */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700275static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
276{
Kevin Hilmand6290a32010-04-26 14:59:09 -0700277 u32 irqenable_mpu, irqstatus_mpu;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700278 int c = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700279
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700280 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
Kevin Hilmand6290a32010-04-26 14:59:09 -0700281 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700282 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
Kevin Hilmand6290a32010-04-26 14:59:09 -0700283 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
284 irqstatus_mpu &= irqenable_mpu;
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700285
Kevin Hilmand6290a32010-04-26 14:59:09 -0700286 do {
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600287 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
288 OMAP3430_IO_ST_MASK)) {
Paul Walmsley8cb0ac92009-07-22 10:29:02 -0700289 c = _prcm_int_handle_wakeup();
290
291 /*
292 * Is the MPU PRCM interrupt handler racing with the
293 * IVA2 PRCM interrupt handler ?
294 */
295 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
296 "but no wakeup sources are marked\n");
297 } else {
298 /* XXX we need to expand our PRCM interrupt handler */
299 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
300 "no code to handle it (%08x)\n", irqstatus_mpu);
301 }
302
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700303 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
Jon Hunter77da2d92009-06-27 00:07:25 -0500304 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700305
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700306 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
Kevin Hilmand6290a32010-04-26 14:59:09 -0700307 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
308 irqstatus_mpu &= irqenable_mpu;
309
310 } while (irqstatus_mpu);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700311
312 return IRQ_HANDLED;
313}
314
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530315/* Function to restore the table entry that was modified for enabling MMU */
316static void restore_table_entry(void)
317{
Manjunath Kondaiah G4d63bc12010-10-08 09:56:11 -0700318 void __iomem *scratchpad_address;
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530319 u32 previous_value, control_reg_value;
320 u32 *address;
321
322 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
323
324 /* Get address of entry that was modified */
325 address = (u32 *)__raw_readl(scratchpad_address +
326 OMAP343X_TABLE_ADDRESS_OFFSET);
327 /* Get the previous value which needs to be restored */
328 previous_value = __raw_readl(scratchpad_address +
329 OMAP343X_TABLE_VALUE_OFFSET);
330 address = __va(address);
331 *address = previous_value;
332 flush_tlb_all();
333 control_reg_value = __raw_readl(scratchpad_address
334 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
335 /* This will enable caches and prediction */
Santosh Shilimkar261bfb22011-02-11 20:42:11 +0530336 set_cr(control_reg_value);
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530337}
338
Rajendra Nayak99e6a4d2008-10-08 17:30:58 +0530339void omap_sram_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700340{
341 /* Variable to tell what needs to be saved and restored
342 * in omap_sram_idle*/
343 /* save_state = 0 => Nothing to save and restored */
344 /* save_state = 1 => Only L1 and logic lost */
345 /* save_state = 2 => Only L2 lost */
346 /* save_state = 3 => L1, L2 and logic lost */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530347 int save_state = 0;
348 int mpu_next_state = PWRDM_POWER_ON;
349 int per_next_state = PWRDM_POWER_ON;
350 int core_next_state = PWRDM_POWER_ON;
Paul Walmsley72e06d02010-12-21 21:05:16 -0700351 int per_going_off;
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530352 int core_prev_state, per_prev_state;
Tero Kristo13a6fe02008-10-13 13:17:06 +0300353 u32 sdrc_pwr = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700354
355 if (!_omap_sram_idle)
356 return;
357
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530358 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
359 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
360 pwrdm_clear_all_prev_pwrst(core_pwrdm);
361 pwrdm_clear_all_prev_pwrst(per_pwrdm);
362
Kevin Hilman8bd22942009-05-28 10:56:16 -0700363 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
364 switch (mpu_next_state) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530365 case PWRDM_POWER_ON:
Kevin Hilman8bd22942009-05-28 10:56:16 -0700366 case PWRDM_POWER_RET:
367 /* No need to save context */
368 save_state = 0;
369 break;
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530370 case PWRDM_POWER_OFF:
371 save_state = 3;
372 break;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700373 default:
374 /* Invalid state */
375 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
376 return;
377 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300378 pwrdm_pre_transition();
379
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530380 /* NEON control */
381 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
Jouni Hogander71391782008-10-28 10:59:05 +0200382 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530383
Mike Chan40742fa2010-05-03 16:04:06 -0700384 /* Enable IO-PAD and IO-CHAIN wakeups */
Kevin Hilman658ce972008-11-04 20:50:52 -0800385 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
Tero Kristoecf157d2008-12-01 13:17:29 +0200386 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
Kevin Hilmand5c47d72010-08-10 16:04:35 -0700387 if (omap3_has_io_wakeup() &&
388 (per_next_state < PWRDM_POWER_ON ||
389 core_next_state < PWRDM_POWER_ON)) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700390 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
Mike Chan40742fa2010-05-03 16:04:06 -0700391 omap3_enable_io_chain();
392 }
393
Paul Walmsley0d8e2d02010-11-24 16:49:05 -0700394 /* Block console output in case it is on one of the OMAP UARTs */
Kevin Hilmane83df172010-12-08 22:40:40 +0000395 if (!is_suspending())
396 if (per_next_state < PWRDM_POWER_ON ||
397 core_next_state < PWRDM_POWER_ON)
Torben Hohnac751ef2011-01-25 15:07:35 -0800398 if (!console_trylock())
Kevin Hilmane83df172010-12-08 22:40:40 +0000399 goto console_still_active;
Paul Walmsley0d8e2d02010-11-24 16:49:05 -0700400
Mike Chan40742fa2010-05-03 16:04:06 -0700401 /* PER */
Kevin Hilman658ce972008-11-04 20:50:52 -0800402 if (per_next_state < PWRDM_POWER_ON) {
Paul Walmsley72e06d02010-12-21 21:05:16 -0700403 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
Kevin Hilman658ce972008-11-04 20:50:52 -0800404 omap_uart_prepare_idle(2);
Govindraj.Rcd4f1fa2010-09-27 20:20:32 +0530405 omap_uart_prepare_idle(3);
Paul Walmsley72e06d02010-12-21 21:05:16 -0700406 omap2_gpio_prepare_for_idle(per_going_off);
Kevin Hilmane7410cf2010-09-08 16:37:42 -0700407 if (per_next_state == PWRDM_POWER_OFF)
Tero Kristoecf157d2008-12-01 13:17:29 +0200408 omap3_per_save_context();
Kevin Hilman658ce972008-11-04 20:50:52 -0800409 }
410
411 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530412 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530413 omap_uart_prepare_idle(0);
414 omap_uart_prepare_idle(1);
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530415 if (core_next_state == PWRDM_POWER_OFF) {
416 omap3_core_save_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700417 omap3_cm_save_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530418 }
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530419 }
Mike Chan40742fa2010-05-03 16:04:06 -0700420
Tero Kristof18cc2f2009-10-23 19:03:50 +0300421 omap3_intc_prepare_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700422
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530423 /*
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530424 * On EMU/HS devices ROM code restores a SRDC value
425 * from scratchpad which has automatic self refresh on timeout
Jean Pihet83521292010-12-18 16:44:46 +0100426 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530427 * Hence store/restore the SDRC_POWER register here.
428 */
Tero Kristo13a6fe02008-10-13 13:17:06 +0300429 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
430 omap_type() != OMAP2_DEVICE_TYPE_GP &&
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530431 core_next_state == PWRDM_POWER_OFF)
Tero Kristo13a6fe02008-10-13 13:17:06 +0300432 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
Tero Kristo13a6fe02008-10-13 13:17:06 +0300433
434 /*
Rajendra Nayak61255ab2008-09-26 17:49:56 +0530435 * omap3_arm_context is the location where ARM registers
436 * get saved. The restore path then reads from this
437 * location and restores them back.
438 */
439 _omap_sram_idle(omap3_arm_context, save_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700440 cpu_init();
441
Rajendra Nayakf265dc42009-06-09 22:30:41 +0530442 /* Restore normal SDRC POWER settings */
Tero Kristo13a6fe02008-10-13 13:17:06 +0300443 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
444 omap_type() != OMAP2_DEVICE_TYPE_GP &&
445 core_next_state == PWRDM_POWER_OFF)
446 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
447
Rajendra Nayak57f277b2008-09-26 17:49:34 +0530448 /* Restore table entry modified during MMU restoration */
449 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
450 restore_table_entry();
451
Kevin Hilman658ce972008-11-04 20:50:52 -0800452 /* CORE */
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530453 if (core_next_state < PWRDM_POWER_ON) {
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530454 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
455 if (core_prev_state == PWRDM_POWER_OFF) {
456 omap3_core_restore_context();
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700457 omap3_cm_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530458 omap3_sram_restore_context();
Kalle Jokiniemi8a917d22009-05-13 13:32:11 +0300459 omap2_sms_restore_context();
Rajendra Nayak2f5939c2008-09-26 17:50:07 +0530460 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800461 omap_uart_resume_idle(0);
462 omap_uart_resume_idle(1);
463 if (core_next_state == PWRDM_POWER_OFF)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700464 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
Kevin Hilman658ce972008-11-04 20:50:52 -0800465 OMAP3430_GR_MOD,
466 OMAP3_PRM_VOLTCTRL_OFFSET);
467 }
Tero Kristof18cc2f2009-10-23 19:03:50 +0300468 omap3_intc_resume_idle();
Kevin Hilman658ce972008-11-04 20:50:52 -0800469
470 /* PER */
471 if (per_next_state < PWRDM_POWER_ON) {
472 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
Kevin Hilman43ffcd92009-01-27 11:09:24 -0800473 omap2_gpio_resume_after_idle();
474 if (per_prev_state == PWRDM_POWER_OFF)
Kevin Hilman658ce972008-11-04 20:50:52 -0800475 omap3_per_restore_context();
Tero Kristoecf157d2008-12-01 13:17:29 +0200476 omap_uart_resume_idle(2);
Govindraj.Rcd4f1fa2010-09-27 20:20:32 +0530477 omap_uart_resume_idle(3);
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530478 }
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300479
Kevin Hilmane83df172010-12-08 22:40:40 +0000480 if (!is_suspending())
Torben Hohnac751ef2011-01-25 15:07:35 -0800481 console_unlock();
Paul Walmsley0d8e2d02010-11-24 16:49:05 -0700482
483console_still_active:
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200484 /* Disable IO-PAD and IO-CHAIN wakeup */
Kevin Hilman58a55592010-08-16 09:21:19 +0300485 if (omap3_has_io_wakeup() &&
486 (per_next_state < PWRDM_POWER_ON ||
487 core_next_state < PWRDM_POWER_ON)) {
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700488 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
489 PM_WKEN);
Kalle Jokiniemi3a7ec262009-03-26 15:59:01 +0200490 omap3_disable_io_chain();
491 }
Kevin Hilman658ce972008-11-04 20:50:52 -0800492
Peter 'p2' De Schrijverfe617af2008-10-15 17:48:44 +0300493 pwrdm_post_transition();
494
Rajendra Nayak5cd19372011-02-25 16:06:48 -0700495 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700496}
497
Rajendra Nayak20b01662008-10-08 17:31:22 +0530498int omap3_can_sleep(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700499{
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700500 if (!sleep_while_idle)
501 return 0;
Kevin Hilman4af40162009-02-04 10:51:40 -0800502 if (!omap_uart_can_sleep())
503 return 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700504 return 1;
505}
506
Kevin Hilman8bd22942009-05-28 10:56:16 -0700507static void omap3_pm_idle(void)
508{
509 local_irq_disable();
510 local_fiq_disable();
511
512 if (!omap3_can_sleep())
513 goto out;
514
Tero Kristocf228542009-03-20 15:21:02 +0200515 if (omap_irq_pending() || need_resched())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700516 goto out;
517
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100518 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
519 trace_cpu_idle(1, smp_processor_id());
520
Kevin Hilman8bd22942009-05-28 10:56:16 -0700521 omap_sram_idle();
522
Jean Pihet5e7c58d2011-03-03 11:25:43 +0100523 trace_power_end(smp_processor_id());
524 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
525
Kevin Hilman8bd22942009-05-28 10:56:16 -0700526out:
527 local_fiq_enable();
528 local_irq_enable();
529}
530
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700531#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700532static int omap3_pm_suspend(void)
533{
534 struct power_state *pwrst;
535 int state, ret = 0;
536
Ari Kauppi8e2efde2010-03-23 09:04:59 +0200537 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
538 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
539 wakeup_timer_milliseconds);
Kevin Hilmand7814e42009-10-06 14:30:23 -0700540
Kevin Hilman8bd22942009-05-28 10:56:16 -0700541 /* Read current next_pwrsts */
542 list_for_each_entry(pwrst, &pwrst_list, node)
543 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
544 /* Set ones wanted by suspend */
545 list_for_each_entry(pwrst, &pwrst_list, node) {
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530546 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700547 goto restore;
548 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
549 goto restore;
550 }
551
Kevin Hilman4af40162009-02-04 10:51:40 -0800552 omap_uart_prepare_suspend();
Tero Kristo2bbe3af2009-10-23 19:03:48 +0300553 omap3_intc_suspend();
554
Kevin Hilman8bd22942009-05-28 10:56:16 -0700555 omap_sram_idle();
556
557restore:
558 /* Restore next_pwrsts */
559 list_for_each_entry(pwrst, &pwrst_list, node) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700560 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
561 if (state > pwrst->next_state) {
562 printk(KERN_INFO "Powerdomain (%s) didn't enter "
563 "target state %d\n",
564 pwrst->pwrdm->name, pwrst->next_state);
565 ret = -1;
566 }
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530567 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700568 }
569 if (ret)
570 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
571 else
572 printk(KERN_INFO "Successfully put all powerdomains "
573 "to target state\n");
574
575 return ret;
576}
577
Tero Kristo24662112009-03-05 16:32:23 +0200578static int omap3_pm_enter(suspend_state_t unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700579{
580 int ret = 0;
581
Tero Kristo24662112009-03-05 16:32:23 +0200582 switch (suspend_state) {
Kevin Hilman8bd22942009-05-28 10:56:16 -0700583 case PM_SUSPEND_STANDBY:
584 case PM_SUSPEND_MEM:
585 ret = omap3_pm_suspend();
586 break;
587 default:
588 ret = -EINVAL;
589 }
590
591 return ret;
592}
593
Tero Kristo24662112009-03-05 16:32:23 +0200594/* Hooks to enable / disable UART interrupts during suspend */
595static int omap3_pm_begin(suspend_state_t state)
596{
Jean Pihetc1663812010-12-09 18:39:58 +0100597 disable_hlt();
Tero Kristo24662112009-03-05 16:32:23 +0200598 suspend_state = state;
599 omap_uart_enable_irqs(0);
600 return 0;
601}
602
603static void omap3_pm_end(void)
604{
605 suspend_state = PM_SUSPEND_ON;
606 omap_uart_enable_irqs(1);
Jean Pihetc1663812010-12-09 18:39:58 +0100607 enable_hlt();
Tero Kristo24662112009-03-05 16:32:23 +0200608 return;
609}
610
Lionel Debroux2f55ac02010-11-16 14:14:02 +0100611static const struct platform_suspend_ops omap_pm_ops = {
Tero Kristo24662112009-03-05 16:32:23 +0200612 .begin = omap3_pm_begin,
613 .end = omap3_pm_end,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700614 .enter = omap3_pm_enter,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700615 .valid = suspend_valid_only_mem,
616};
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700617#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700618
Kevin Hilman1155e422008-11-25 11:48:24 -0800619
620/**
621 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
622 * retention
623 *
624 * In cases where IVA2 is activated by bootcode, it may prevent
625 * full-chip retention or off-mode because it is not idle. This
626 * function forces the IVA2 into idle state so it can go
627 * into retention/off and thus allow full-chip retention/off.
628 *
629 **/
630static void __init omap3_iva_idle(void)
631{
632 /* ensure IVA2 clock is disabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700633 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800634
635 /* if no clock activity, nothing else to do */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700636 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
Kevin Hilman1155e422008-11-25 11:48:24 -0800637 OMAP3430_CLKACTIVITY_IVA2_MASK))
638 return;
639
640 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700641 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600642 OMAP3430_RST2_IVA2_MASK |
643 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700644 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800645
646 /* Enable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700647 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
Kevin Hilman1155e422008-11-25 11:48:24 -0800648 OMAP3430_IVA2_MOD, CM_FCLKEN);
649
650 /* Set IVA2 boot mode to 'idle' */
651 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
652 OMAP343X_CONTROL_IVA2_BOOTMOD);
653
654 /* Un-reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700655 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800656
657 /* Disable IVA2 clock */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700658 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
Kevin Hilman1155e422008-11-25 11:48:24 -0800659
660 /* Reset IVA2 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700661 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600662 OMAP3430_RST2_IVA2_MASK |
663 OMAP3430_RST3_IVA2_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700664 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman1155e422008-11-25 11:48:24 -0800665}
666
Kevin Hilman8111b222009-04-28 15:27:44 -0700667static void __init omap3_d2d_idle(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700668{
Kevin Hilman8111b222009-04-28 15:27:44 -0700669 u16 mask, padconf;
670
671 /* In a stand alone OMAP3430 where there is not a stacked
672 * modem for the D2D Idle Ack and D2D MStandby must be pulled
673 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
674 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
675 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
676 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
677 padconf |= mask;
678 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
679
680 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
681 padconf |= mask;
682 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
683
Kevin Hilman8bd22942009-05-28 10:56:16 -0700684 /* reset modem */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700685 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
Paul Walmsley2bc4ef72010-05-18 18:47:24 -0600686 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700687 CORE_MOD, OMAP2_RM_RSTCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700688 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
Kevin Hilman8111b222009-04-28 15:27:44 -0700689}
Kevin Hilman8bd22942009-05-28 10:56:16 -0700690
Kevin Hilman8111b222009-04-28 15:27:44 -0700691static void __init prcm_setup_regs(void)
692{
Govindraj.Re5863682010-09-27 20:20:25 +0530693 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
694 OMAP3630_EN_UART4_MASK : 0;
695 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
696 OMAP3630_GRPSEL_UART4_MASK : 0;
697
Paul Walmsley4ef70c02011-02-25 15:39:30 -0700698 /* XXX This should be handled by hwmod code or SCM init code */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600699 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
Tero Kristob296c812009-10-23 19:03:49 +0300700
Kevin Hilman8bd22942009-05-28 10:56:16 -0700701 /*
Kevin Hilman8bd22942009-05-28 10:56:16 -0700702 * Enable control of expternal oscillator through
703 * sys_clkreq. In the long run clock framework should
704 * take care of this.
705 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700706 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700707 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
708 OMAP3430_GR_MOD,
709 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
710
711 /* setup wakup source */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700712 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600713 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700714 WKUP_MOD, PM_WKEN);
715 /* No need to write EN_IO, that is always enabled */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700716 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600717 OMAP3430_GRPSEL_GPT1_MASK |
718 OMAP3430_GRPSEL_GPT12_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700719 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
720 /* For some reason IO doesn't generate wakeup event even if
721 * it is selected to mpu wakeup goup */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700722 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700723 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
Kevin Hilman1155e422008-11-25 11:48:24 -0800724
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530725 /* Enable PM_WKEN to support DSS LPR */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700726 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
Subramani Venkateshb92c5722009-12-22 15:07:50 +0530727 OMAP3430_DSS_MOD, PM_WKEN);
728
Kevin Hilmanb427f922009-10-22 14:48:13 -0700729 /* Enable wakeups in PER */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700730 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530731 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600732 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
733 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
734 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
735 OMAP3430_EN_MCBSP4_MASK,
Kevin Hilmanb427f922009-10-22 14:48:13 -0700736 OMAP3430_PER_MOD, PM_WKEN);
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000737 /* and allow them to wake up MPU */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700738 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
Govindraj.Re5863682010-09-27 20:20:25 +0530739 OMAP3430_GRPSEL_GPIO2_MASK |
Paul Walmsley275f6752010-05-18 18:40:23 -0600740 OMAP3430_GRPSEL_GPIO3_MASK |
741 OMAP3430_GRPSEL_GPIO4_MASK |
742 OMAP3430_GRPSEL_GPIO5_MASK |
743 OMAP3430_GRPSEL_GPIO6_MASK |
744 OMAP3430_GRPSEL_UART3_MASK |
745 OMAP3430_GRPSEL_MCBSP2_MASK |
746 OMAP3430_GRPSEL_MCBSP3_MASK |
747 OMAP3430_GRPSEL_MCBSP4_MASK,
Kevin Hilmaneb350f72009-09-10 15:53:08 +0000748 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
749
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700750 /* Don't attach IVA interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700751 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
752 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
753 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
754 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
Kevin Hilmand3fd3292009-05-05 16:34:25 -0700755
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700756 /* Clear any pending 'reset' flags */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700757 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
758 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
759 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
760 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
761 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
762 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
763 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
Kevin Hilmanb1340d12009-04-27 16:14:54 -0700764
Kevin Hilman014c46d2009-04-27 07:50:23 -0700765 /* Clear any pending PRCM interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700766 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman014c46d2009-04-27 07:50:23 -0700767
Kevin Hilman1155e422008-11-25 11:48:24 -0800768 omap3_iva_idle();
Kevin Hilman8111b222009-04-28 15:27:44 -0700769 omap3_d2d_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700770}
771
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700772void omap3_pm_off_mode_enable(int enable)
773{
774 struct power_state *pwrst;
775 u32 state;
776
777 if (enable)
778 state = PWRDM_POWER_OFF;
779 else
780 state = PWRDM_POWER_RET;
781
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530782#ifdef CONFIG_CPU_IDLE
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600783 /*
784 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
785 * enable OFF mode in a stable form for previous revisions, restrict
786 * instead to RET
787 */
788 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
789 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
790 else
791 omap3_cpuidle_update_states(state, state);
Sanjeev Premi6af83b32010-01-28 23:16:43 +0530792#endif
793
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700794 list_for_each_entry(pwrst, &pwrst_list, node) {
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600795 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
796 pwrst->pwrdm == core_pwrdm &&
797 state == PWRDM_POWER_OFF) {
798 pwrst->next_state = PWRDM_POWER_RET;
Ricardo Salveti de Araujoe16b41b2011-01-31 11:35:25 -0200799 pr_warn("%s: Core OFF disabled due to errata i583\n",
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600800 __func__);
801 } else {
802 pwrst->next_state = state;
803 }
804 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilmanc40552b2009-10-06 14:25:09 -0700805 }
806}
807
Tero Kristo68d47782008-11-26 12:26:24 +0200808int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
809{
810 struct power_state *pwrst;
811
812 list_for_each_entry(pwrst, &pwrst_list, node) {
813 if (pwrst->pwrdm == pwrdm)
814 return pwrst->next_state;
815 }
816 return -EINVAL;
817}
818
819int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
820{
821 struct power_state *pwrst;
822
823 list_for_each_entry(pwrst, &pwrst_list, node) {
824 if (pwrst->pwrdm == pwrdm) {
825 pwrst->next_state = state;
826 return 0;
827 }
828 }
829 return -EINVAL;
830}
831
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300832static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700833{
834 struct power_state *pwrst;
835
836 if (!pwrdm->pwrsts)
837 return 0;
838
Ming Leid3d381c2009-08-22 21:20:26 +0800839 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700840 if (!pwrst)
841 return -ENOMEM;
842 pwrst->pwrdm = pwrdm;
843 pwrst->next_state = PWRDM_POWER_RET;
844 list_add(&pwrst->node, &pwrst_list);
845
846 if (pwrdm_has_hdwr_sar(pwrdm))
847 pwrdm_enable_hdwr_sar(pwrdm);
848
Santosh Shilimkareb6a2c72010-09-15 01:04:01 +0530849 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700850}
851
852/*
853 * Enable hw supervised mode for all clockdomains if it's
854 * supported. Initiate sleep transition for other clockdomains, if
855 * they are not used
856 */
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300857static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700858{
859 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
Rajendra Nayak5cd19372011-02-25 16:06:48 -0700860 clkdm_allow_idle(clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700861 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
862 atomic_read(&clkdm->usecount) == 0)
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700863 clkdm_sleep(clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700864 return 0;
865}
866
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530867void omap_push_sram_idle(void)
868{
869 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
870 omap34xx_cpu_suspend_sz);
Tero Kristo27d59a42008-10-13 13:15:00 +0300871 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
872 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
873 save_secure_ram_context_sz);
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530874}
875
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600876static void __init pm_errata_configure(void)
877{
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600878 if (cpu_is_omap3630()) {
Nishanth Menon458e9992010-12-20 14:05:06 -0600879 pm34xx_errata |= PM_RTA_ERRATUM_i608;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600880 /* Enable the l2 cache toggling in sleep logic */
881 enable_omap3630_toggle_l2_on_restore();
Eduardo Valentincc1b6022010-12-20 14:05:09 -0600882 if (omap_rev() < OMAP3630_REV_ES1_2)
883 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
Peter 'p2' De Schrijverc4236d22010-12-20 14:05:07 -0600884 }
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600885}
886
Kevin Hilman7cc515f2009-06-10 09:02:25 -0700887static int __init omap3_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700888{
889 struct power_state *pwrst, *tmp;
Paul Walmsley55ed9692010-01-26 20:12:59 -0700890 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700891 int ret;
892
893 if (!cpu_is_omap34xx())
894 return -ENODEV;
895
Nishanth Menon8cdfd832010-12-20 14:05:05 -0600896 pm_errata_configure();
897
Kevin Hilman8bd22942009-05-28 10:56:16 -0700898 printk(KERN_ERR "Power Management for TI OMAP3.\n");
899
900 /* XXX prcm_setup_regs needs to be before enabling hw
901 * supervised mode for powerdomains */
902 prcm_setup_regs();
903
904 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
905 (irq_handler_t)prcm_interrupt_handler,
906 IRQF_DISABLED, "prcm", NULL);
907 if (ret) {
908 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
909 INT_34XX_PRCM_MPU_IRQ);
910 goto err1;
911 }
912
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300913 ret = pwrdm_for_each(pwrdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700914 if (ret) {
915 printk(KERN_ERR "Failed to setup powerdomains\n");
916 goto err2;
917 }
918
Peter 'p2' De Schrijvera23456e2008-10-15 18:13:47 +0300919 (void) clkdm_for_each(clkdms_setup, NULL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700920
921 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
922 if (mpu_pwrdm == NULL) {
923 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
924 goto err2;
925 }
926
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530927 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
928 per_pwrdm = pwrdm_lookup("per_pwrdm");
929 core_pwrdm = pwrdm_lookup("core_pwrdm");
Tero Kristoc16c3f62008-12-11 16:46:57 +0200930 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
Rajendra Nayakfa3c2a42008-09-26 17:49:22 +0530931
Paul Walmsley55ed9692010-01-26 20:12:59 -0700932 neon_clkdm = clkdm_lookup("neon_clkdm");
933 mpu_clkdm = clkdm_lookup("mpu_clkdm");
934 per_clkdm = clkdm_lookup("per_clkdm");
935 core_clkdm = clkdm_lookup("core_clkdm");
936
Rajendra Nayak3231fc82008-09-26 17:49:14 +0530937 omap_push_sram_idle();
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700938#ifdef CONFIG_SUSPEND
Kevin Hilman8bd22942009-05-28 10:56:16 -0700939 suspend_set_ops(&omap_pm_ops);
Kevin Hilman10f90ed2009-06-24 11:39:18 -0700940#endif /* CONFIG_SUSPEND */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700941
942 pm_idle = omap3_pm_idle;
Kalle Jokiniemi03433712008-09-26 11:04:20 +0300943 omap3_idle_init();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700944
Nishanth Menon458e9992010-12-20 14:05:06 -0600945 /*
946 * RTA is disabled during initialization as per erratum i608
947 * it is safer to disable RTA by the bootloader, but we would like
948 * to be doubly sure here and prevent any mishaps.
949 */
950 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
951 omap3630_ctrl_disable_rta();
952
Paul Walmsley55ed9692010-01-26 20:12:59 -0700953 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
Tero Kristo27d59a42008-10-13 13:15:00 +0300954 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
955 omap3_secure_ram_storage =
956 kmalloc(0x803F, GFP_KERNEL);
957 if (!omap3_secure_ram_storage)
958 printk(KERN_ERR "Memory allocation failed when"
959 "allocating for secure sram context\n");
Tero Kristo27d59a42008-10-13 13:15:00 +0300960
Tero Kristo9d971402008-12-12 11:20:05 +0200961 local_irq_disable();
962 local_fiq_disable();
963
964 omap_dma_global_context_save();
Kevin Hilman617fcc92011-01-25 16:40:01 -0800965 omap3_save_secure_ram_context();
Tero Kristo9d971402008-12-12 11:20:05 +0200966 omap_dma_global_context_restore();
967
968 local_irq_enable();
969 local_fiq_enable();
970 }
971
972 omap3_save_scratchpad_contents();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700973err1:
974 return ret;
975err2:
976 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
977 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
978 list_del(&pwrst->node);
979 kfree(pwrst);
980 }
981 return ret;
982}
983
984late_initcall(omap3_pm_init);