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gerrit-public.fairphone.software / kernel / msm / dca1cdd3b9f78643bf62dba96daf182883b9f54e / . / arch / arm / mach-msm / arch-init-scorpion.S
blob: db0a1e6417db690bdb3783dfbe2490168f7d5afd [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/*
Duy Truong790f06d2013-02-13 16:38:12 -0800[diff] [blame]2 * Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]3 * Copyright (c) 2008-2009, Google Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
14 * distribution.
15 * * Neither the name of Google, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
22 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
23 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
26 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
29 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33
34/* TODO:
35 * - style cleanup
36 * - do we need to do *all* of this at boot?
37 */
38
39.text
40.code 32
41
42#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
43#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
44
45.equ TCSR_SPARE2, 0xA8700060
46
47SET_SA:
48 ldr r0, =TCSR_SPARE2
49 ldr r12, [r0]
50
51 /* pack bits 8,2,0 into 2,1,0 */
52 and r0, r12, #0x001
53 and r1, r12, #0x004
54 and r2, r12, #0x100
55 orr r0, r1, lsr #1
56 orr r0, r2, lsr #6
57
58 adr r1, table_l1_acc
59 mov r0, r0, lsl #2
60 ldr r3, [r1, r0]
61
62 /* write 3800XXXX to PVR0F0 */
63 orr r0, r3, #0x38000000
64 mcr p15, 0, r0, c15, c15, 0
65
66 /* write XXXX0000 to PVR2F0 */
67 mov r1, r3, lsl #16
68 mcr p15, 2, r1, c15, c15, 0
69
70 adr r1, table_l2_acc
71 and r0, r12, #0x008
72 and r2, r12, #0x002
73 orr r0, r0, r2, lsl #1
74 ldr r2, [r1, r0]
75
76 /* write to L2VR3F1 */
77 mcr p15, 3, r2, c15, c15, 1
78
79 bx lr
80
81table_l1_acc:
82 .word 0xFC00
83 .word 0xFC00
84 .word 0x7C00
85 .word 0xFC00
86 .word 0x3C00
87 .word 0x0400
88 .word 0x0C00
89 .word 0x1C00
90
91table_l2_acc:
92 .word 0x010102
93 .word 0x010102
94 .word 0x010101
95 .word 0x212102
96
97.globl __cpu_early_init
98__cpu_early_init:
99 //; Zero out r0 for use throughout this code. All other GPRs
100 //; (r1-r3) are set throughout this code to help establish
101 //; a consistent startup state for any code that follows.
102 //; Users should add code at the end of this routine to establish
103 //; their own stack address (r13), add translation page tables, enable
104 //; the caches, etc.
105 MOV r0, #0x0
106
107
108 //; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
109 //; API to dynamically configure cache for slow/nominal/fast parts
110
111 //; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
112 //; This must be done early in code (prior to enabling the caches)
113 MOV r1, #0x2
114 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
115 ORR r1, r1, #0x00004000
116 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
117 ADD r1, r1, #0x00004000
118 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
119 ADD r1, r1, #0x00004000
120 MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
121
122 //; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
123 //; and have all address bits (AM) participate.
124 //; Different settings can be used to improve performance
125 // MOVW r1, #0x01FF
126.word 0xe30011ff // hardcoded MOVW instruction due to lack of compiler support
127 // MOVT r1, #0x01FF
128.word 0xe34011ff // hardcoded MOVT instruction due to lack of compiler support
129 MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
130
131
132 //; Initialize all I$ Victim Registers to 0 for startup
133 MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
134 MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
135 MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
136 MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
137 MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
138 MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
139 MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
140 MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
141
142 //; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
143 MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
144 MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
145 MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
146 MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
147 MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
148 MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
149 MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
150 MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
151
152 //; Initialize all D$ Victim Registers to 0
153 MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
154 MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
155 MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
156 MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
157 MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
158 MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
159 MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
160 MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
161
162 //; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
163 MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
164 MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
165 MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
166 MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
167 MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
168 MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
169 MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
170 MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
171
172 //; Initialize ASID to zero
173 MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
174
175 //; ICIALL to invalidate entire I-Cache
176 MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
177
178 //; DCIALL to invalidate entire D-Cache
179 MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
180
181
182 //; The VBAR (Vector Base Address Register) should be initialized
183 //; early in your code. We are setting it to zero
184 MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
185
186 //; Ensure the MCR's above have completed their operation before continuing
187 DSB
188 ISB
189
190 //;-------------------------------------------------------------------
191 //; There are a number of registers that must be set prior to enabling
192 //; the MMU. The DCAR is one of these registers. We are setting
193 //; it to zero (no access) to easily detect improper setup in subsequent
194 //; code sequences
195 //;-------------------------------------------------------------------
196 //; Setup DACR (Domain Access Control Register) to zero
197 MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
198
199 //; Setup DCLKCR to allow normal D-Cache line fills
200 MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
201
202 //; Initialize the ADFSR and EFSR registers.
203 MCR p15, 0, r0, c5, c1, 0 //; ADFSR
204 MCR p15, 7, r0, c15, c0, 1 //; EFSR
205
206 //; Setup the TLBLKCR
207 //; Victim = 6'b000000; Floor = 6'b000000;
208 //; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
209 MOV r1, #0x02
210 MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
211
212 //;Make sure TLBLKCR is complete before continuing
213 ISB
214
215 //; Invalidate the UTLB
216 MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
217
218 //; Make sure UTLB request has been presented to macro before continuing
219 ISB
220
221 //; setup L2CR1 to some default Instruction and data prefetching values
222 //; Users may want specific settings for various performance enhancements
223 //; In Halcyon we do not have broadcasting barriers. So we need to turn
224 // ; on bit 8 of L2CR1; which DBB:( Disable barrier broadcast )
225 MOV r2, #0x100
226 MCR p15, 3, r2, c15, c0, 3 //; WCP15_L2CR1 r0
227
228
229 //; Enable Z bit to enable branch prediction (default is off)
230 MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
231 ORR r2, r2, #0x00000800
232 MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
233
234#ifdef CONFIG_ARCH_QSD8X50
235 /* disable predecode repair cache for thumb2 (DPRC, set bit 4 in PVR0F2) */
236 mrc p15, 0, r2, c15, c15, 2
237 orr r2, r2, #0x10
238 mcr p15, 0, r2, c15, c15, 2
239#endif
240
241 mov r1, lr
242 //; Make sure Link stack is initialized with branch and links to sequential addresses
243 //; This aids in creating a predictable startup environment
244 BL SEQ1
245SEQ1: BL SEQ2
246SEQ2: BL SEQ3
247SEQ3: BL SEQ4
248SEQ4: BL SEQ5
249SEQ5: BL SEQ6
250SEQ6: BL SEQ7
251SEQ7: BL SEQ8
252SEQ8:
253 mov lr, r1
254
255 //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
256 //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
257 //; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
258 MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
259
260
261 //; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
262 //; Any read to DBGPRSR clear the STICKYPD bit
263 //; ISB guarantees the read completes before attempting to
264 //; execute a CP14 instruction.
265 MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
266 ISB
267
268 //; Initialize the Watchpoint Control Registers to zero (optional)
269 //;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
270 //;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
271
272
273 //;----------------------------------------------------------------------
274 //; The saved Program Status Registers (SPSRs) should be setup
275 //; prior to any automatic mode switches. The following
276 //; code sets these registers up to a known state. Users will need to
277 //; customize these settings to meet their needs.
278 //;----------------------------------------------------------------------
279 MOV r2, #0x1f
280 MOV r1, #0x17 //;ABT mode
281 msr cpsr_c, r1 //;ABT mode
282 msr spsr_cxfs, r2 //;clear the spsr
283 MOV r1, #0x1b //;UND mode
284 msr cpsr_c, r1 //;UND mode
285 msr spsr_cxfs, r2 //;clear the spsr
286 MOV r1, #0x11 //;FIQ mode
287 msr cpsr_c, r1 //;FIQ mode
288 msr spsr_cxfs, r2 //;clear the spsr
289 MOV r1, #0x12 //;IRQ mode
290 msr cpsr_c, r1 //;IRQ mode
291 msr spsr_cxfs, r2 //;clear the spsr
292 MOV r1, #0x16 //;Monitor mode
293 msr cpsr_c, r1 //;Monitor mode
294 msr spsr_cxfs, r2 //;clear the spsr
295 MOV r1, #0x13 //;SVC mode
296 msr cpsr_c, r1 //;SVC mode
297 msr spsr_cxfs, r2 //;clear the spsr
298
299
300 //;----------------------------------------------------------------------
301 //; Enabling Error reporting is something users may want to do at
302 //; some other point in time. We have chosen some default settings
303 //; that should be reviewed. Most of these registers come up in an
304 //; unpredictable state after reset.
305 //;----------------------------------------------------------------------
306//;Start of error and control setting
307
308 //; setup L2CR0 with various L2/TCM control settings
309 //; enable out of order bus attributes and error reporting
310 //; this register comes up unpredictable after reset
311 // MOVW r1, #0x0F0F
312.word 0xe3001f0f // hardcoded MOVW instruction due to lack of compiler support
313 // MOVT r1, #0xC005
314.word 0xe34c1005 // hardcoded MOVW instruction due to lack of compiler support
315 MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
316
317 //; setup L2CPUCR
318 //; MOV r2, #0xFF
319 //; Enable I and D cache parity
320 //;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
321 //;tag, and data parity errors
322 MOV r2, #0xe0
323 MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
324
325 //; setup SPCR
326 //; enable all error reporting (reset value is unpredicatble for most bits)
327 MOV r3, #0x0F
328 MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
329
330 //; setup DMACHCRs (reset value unpredictable)
331 //; control setting and enable all error reporting
332 MOV r1, #0x0F
333
334 //; DMACHCR0 = 0000000F
335 MOV r2, #0x00 //; channel 0
336 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
337 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
338
339 //; DMACHCR1 = 0000000F
340 MOV r2, #0x01 //; channel 1
341 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
342 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
343
344 //; DMACHCR2 = 0000000F
345 MOV r2, #0x02 //; channel 2
346 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
347 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
348
349 //; DMACHCR3 = 0000000F
350 MOV r2, #0x03 //; channel 3
351 MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
352 MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
353
354 //; Set ACTLR (reset unpredictable)
355 //; Set AVIVT control, error reporting, etc.
356 //; MOV r3, #0x07
357 //; Enable I and D cache parity
358 //;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
359 //;ACTLR[5:4] = 2'h3 - enable parity
360 //;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
361 //;Value to be written #0xC0037
362 // MOVW r3, #0x0037
363.word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
364 // MOVT r3, #0x000C
365.word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
366 //; read the version_id to determine if d-cache should be disabled
367 LDR r2, = 0xa8e00270 //;Read HW_REVISION_NUMBER, HWIO_HW_REVISION_NUMBER_ADDR
368 LDR r2,[r2]
369 AND r2,r2,#0xf0000000 //;hw_revision mask off bits 28-31
370 //;if HW_revision is 1.0 or older, (revision==0)
371 CMP r2,#0
372 //; Disable d-cache on older QSD8650 (Rev 1.0) silicon
373 orreq r3, r3, #0x4000 //;disable dcache
374 MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
375
376//;End of error and control setting
377
378 //;----------------------------------------------------------------------
379 //; Unlock ETM and read StickyPD to halt the ETM clocks from running.
380 //; This is required for power saving whether the ETM is used or not.
381 //;----------------------------------------------------------------------
382
383 //;Clear ETMOSLSR[LOCK] bit
384 MOV r1, #0x00000000
385 MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
386
387 //;Clear ETMPDSR[STICKYPD] bit
388 MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
389
390/*
391#ifdef APPSBL_ETM_ENABLE
392 ;----------------------------------------------------------------------
393 ; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
394 ;----------------------------------------------------------------------
395
396 ; enable ETM clock if disabled
397 MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
398 ORR r1, r1, #0x00000008
399 MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
400 ISB
401
402 ; set trigger event to counter1 being zero
403 MOV r3, #0x00000040
404 MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
405
406 ; clear ETMSR
407 MOV r2, #0x00000000
408 MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
409
410 ; clear trace enable single address comparator usage
411 MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
412
413 ; set trace enable to always
414 MOV r2, #0x0000006F
415 MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
416
417 ; clear trace enable address range comparator usage and exclude nothing
418 MOV r2, #0x01000000
419 MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
420
421 ; set view data to always
422 MOV r2, #0x0000006F
423 MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
424
425 ; clear view data single address comparator usage
426 MOV r2, #0x00000000
427 MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
428
429 ; clear view data address range comparator usage and exclude nothing
430 MOV r2, #0x00010000
431 MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
432
433 ; set counter1 to 194
434 MOV r2, #0x000000C2
435 MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
436
437 ; set counter1 to never reload
438 MOV r2, #0x0000406F
439 MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
440
441 ; set counter1 to decrement every cycle
442 MOV r2, #0x0000006F
443 MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
444
445 ; Set trace synchronization frequency 1024 bytes
446 MOV r2, #0x00000400
447 MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
448
449 ; Program etm control register
450 ; - Set the CPU to ETM clock ratio to 1:1
451 ; - Set the ETM to perform data address tracing
452 MOV r2, #0x00002008
453 MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
454 ISB
455#endif *//* APPSBL_ETM_ENABLE */
456
457/*
458#ifdef APPSBL_VFP_ENABLE
459 ;----------------------------------------------------------------------
460 ; Perform the following operations if you intend to make use of
461 ; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
462 ; indicating the VFP unit is present (i.e.Cortex-A8). .
463 ; Some tools will require full double precision floating point support
464 ; which will become available in Scorpion pass 2
465 ;----------------------------------------------------------------------
466 ; allow full access to CP 10 and 11 space for VFP/NEON use
467 MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
468 ORR r1, r1, #0x00F00000 ; enable full access for p10,11
469 MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
470
471 ;make sure the CPACR is complete before continuing
472 ISB
473
474 ; Enable VFP itself (certain OSes may want to dynamically set/clear
475 ; the enable bit based on the application being executed
476 MOV r1, #0x40000000
477 FMXR FPEXC, r1
478#endif *//* APPSBL_VFP_ENABLE */
479
480 /* we have no stack, so just tail-call into the SET_SA routine... */
481 b SET_SA
482
483.ltorg