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Jeyaprakash Soundrapandian2474e8f2012-01-03 15:59:57 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __ASM__ARCH_CAMERA_H
15#define __ASM__ARCH_CAMERA_H
16
17#include <linux/list.h>
18#include <linux/poll.h>
19#include <linux/cdev.h>
20#include <linux/platform_device.h>
21#include <linux/wakelock.h>
Kevin Chaneb6b6072012-01-17 11:54:54 -080022#include <linux/regulator/consumer.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070023#include "linux/types.h"
24
25#include <mach/board.h>
26#include <media/msm_camera.h>
Ankit Premrajkac6864b82011-07-15 11:43:41 -070027#include <mach/msm_subsystem_map.h>
Ankit Premrajka748a70a2011-11-01 08:22:04 -070028#include <linux/ion.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029
30#define CONFIG_MSM_CAMERA_DEBUG
31#ifdef CONFIG_MSM_CAMERA_DEBUG
32#define CDBG(fmt, args...) pr_debug(fmt, ##args)
33#else
34#define CDBG(fmt, args...) do { } while (0)
35#endif
36
37#define PAD_TO_2K(a, b) ((!b) ? a : (((a)+2047) & ~2047))
38
39#define MSM_CAMERA_MSG 0
40#define MSM_CAMERA_EVT 1
41#define NUM_WB_EXP_NEUTRAL_REGION_LINES 4
42#define NUM_WB_EXP_STAT_OUTPUT_BUFFERS 3
43#define NUM_AUTOFOCUS_MULTI_WINDOW_GRIDS 16
44#define NUM_STAT_OUTPUT_BUFFERS 3
45#define NUM_AF_STAT_OUTPUT_BUFFERS 3
Mingcheng Zhu996be182011-10-16 16:04:23 -070046#define max_control_command_size 512
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047#define CROP_LEN 36
48
49enum vfe_mode_of_operation{
50 VFE_MODE_OF_OPERATION_CONTINUOUS,
51 VFE_MODE_OF_OPERATION_SNAPSHOT,
52 VFE_MODE_OF_OPERATION_VIDEO,
53 VFE_MODE_OF_OPERATION_RAW_SNAPSHOT,
54 VFE_MODE_OF_OPERATION_ZSL,
55 VFE_LAST_MODE_OF_OPERATION_ENUM
56};
57
58enum msm_queue {
59 MSM_CAM_Q_CTRL, /* control command or control command status */
60 MSM_CAM_Q_VFE_EVT, /* adsp event */
61 MSM_CAM_Q_VFE_MSG, /* adsp message */
62 MSM_CAM_Q_V4L2_REQ, /* v4l2 request */
63 MSM_CAM_Q_VPE_MSG, /* vpe message */
64 MSM_CAM_Q_PP_MSG, /* pp message */
65};
66
67enum vfe_resp_msg {
68 VFE_EVENT,
69 VFE_MSG_GENERAL,
70 VFE_MSG_SNAPSHOT,
71 VFE_MSG_OUTPUT_P, /* preview (continuous mode ) */
72 VFE_MSG_OUTPUT_T, /* thumbnail (snapshot mode )*/
73 VFE_MSG_OUTPUT_S, /* main image (snapshot mode )*/
74 VFE_MSG_OUTPUT_V, /* video (continuous mode ) */
75 VFE_MSG_STATS_AEC,
76 VFE_MSG_STATS_AF,
77 VFE_MSG_STATS_AWB,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080078 VFE_MSG_STATS_RS, /* 10 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070079 VFE_MSG_STATS_CS,
80 VFE_MSG_STATS_IHIST,
81 VFE_MSG_STATS_SKIN,
82 VFE_MSG_STATS_WE, /* AEC + AWB */
83 VFE_MSG_SYNC_TIMER0,
84 VFE_MSG_SYNC_TIMER1,
85 VFE_MSG_SYNC_TIMER2,
86 VFE_MSG_COMMON,
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070087 VFE_MSG_V32_START,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080088 VFE_MSG_V32_START_RECORDING, /* 20 */
Kiran Kumar H N0fb9dcf2011-07-17 12:31:53 -070089 VFE_MSG_V32_CAPTURE,
90 VFE_MSG_OUTPUT_IRQ,
Suresh Vankadara055cb8e2012-01-18 00:50:04 +053091 VFE_MSG_V2X_PREVIEW,
92 VFE_MSG_V2X_CAPTURE,
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080093 VFE_MSG_OUTPUT_PRIMARY,
94 VFE_MSG_OUTPUT_SECONDARY,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070095};
96
97enum vpe_resp_msg {
98 VPE_MSG_GENERAL,
99 VPE_MSG_OUTPUT_V, /* video (continuous mode ) */
100 VPE_MSG_OUTPUT_ST_L,
101 VPE_MSG_OUTPUT_ST_R,
102};
103
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104enum msm_stereo_state {
105 STEREO_VIDEO_IDLE,
106 STEREO_VIDEO_ACTIVE,
107 STEREO_SNAP_IDLE,
108 STEREO_SNAP_STARTED,
109 STEREO_SNAP_BUFFER1_PROCESSING,
110 STEREO_SNAP_BUFFER2_PROCESSING,
111 STEREO_RAW_SNAP_IDLE,
112 STEREO_RAW_SNAP_STARTED,
113};
114
115enum msm_ispif_intftype {
116 PIX0,
117 RDI0,
118 PIX1,
119 RDI1,
120 PIX2,
121 RDI2,
122};
123
124enum msm_ispif_vc {
125 VC0,
126 VC1,
127 VC2,
128 VC3,
129};
130
131enum msm_ispif_cid {
132 CID0,
133 CID1,
134 CID2,
135 CID3,
136 CID4,
137 CID5,
138 CID6,
139 CID7,
140 CID8,
141 CID9,
142 CID10,
143 CID11,
144 CID12,
145 CID13,
146 CID14,
147 CID15,
148};
149
150struct msm_ispif_params {
151 uint8_t intftype;
152 uint16_t cid_mask;
153 uint8_t csid;
154};
Shuzhen Wanga3c1a122011-08-04 15:33:27 -0700155
156struct msm_ispif_params_list {
157 uint32_t len;
158 struct msm_ispif_params params[3];
159};
160
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700161struct msm_vpe_phy_info {
162 uint32_t sbuf_phy;
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530163 uint32_t planar0_off;
164 uint32_t planar1_off;
165 uint32_t planar2_off;
166 uint32_t p0_phy;
167 uint32_t p1_phy;
168 uint32_t p2_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700169 uint8_t output_id; /* VFE31_OUTPUT_MODE_PT/S/V */
170 uint32_t frame_id;
171};
172
173struct msm_camera_csid_vc_cfg {
174 uint8_t cid;
175 uint8_t dt;
176 uint8_t decode_format;
177};
178
179struct msm_camera_csid_lut_params {
180 uint8_t num_cid;
181 struct msm_camera_csid_vc_cfg *vc_cfg;
182};
183
184struct msm_camera_csid_params {
185 uint8_t lane_cnt;
186 uint8_t lane_assign;
187 struct msm_camera_csid_lut_params lut_params;
188};
189
190struct msm_camera_csiphy_params {
191 uint8_t lane_cnt;
192 uint8_t settle_cnt;
193};
194
Kevin Chana980f392011-08-01 20:55:00 -0700195struct msm_camera_csi2_params {
196 struct msm_camera_csid_params csid_params;
197 struct msm_camera_csiphy_params csiphy_params;
198};
199
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700200#define VFE31_OUTPUT_MODE_PT (0x1 << 0)
201#define VFE31_OUTPUT_MODE_S (0x1 << 1)
202#define VFE31_OUTPUT_MODE_V (0x1 << 2)
203#define VFE31_OUTPUT_MODE_P (0x1 << 3)
204#define VFE31_OUTPUT_MODE_T (0x1 << 4)
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530205#define VFE31_OUTPUT_MODE_P_ALL_CHNLS (0x1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700206
207#define CSI_EMBED_DATA 0x12
Rajakumar Govindaram6bc004a2011-12-05 20:58:19 -0800208#define CSI_YUV422_8 0x1E
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700209#define CSI_RAW8 0x2A
210#define CSI_RAW10 0x2B
211#define CSI_RAW12 0x2C
212
213#define CSI_DECODE_6BIT 0
214#define CSI_DECODE_8BIT 1
215#define CSI_DECODE_10BIT 2
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700216
217struct msm_vfe_phy_info {
218 uint32_t sbuf_phy;
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530219 uint32_t planar0_off;
220 uint32_t planar1_off;
221 uint32_t planar2_off;
222 uint32_t p0_phy;
223 uint32_t p1_phy;
224 uint32_t p2_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700225 uint8_t output_id; /* VFE31_OUTPUT_MODE_PT/S/V */
226 uint32_t frame_id;
227};
228
229struct msm_vfe_stats_msg {
Lakshmi Narayana Kalavala4ab97a92011-07-26 15:30:14 -0700230 uint8_t awb_ymin;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700231 uint32_t aec_buff;
232 uint32_t awb_buff;
233 uint32_t af_buff;
234 uint32_t ihist_buff;
235 uint32_t rs_buff;
236 uint32_t cs_buff;
237 uint32_t skin_buff;
238 uint32_t status_bits;
239 uint32_t frame_id;
240};
241
242struct video_crop_t{
243 uint32_t in1_w;
244 uint32_t out1_w;
245 uint32_t in1_h;
246 uint32_t out1_h;
247 uint32_t in2_w;
248 uint32_t out2_w;
249 uint32_t in2_h;
250 uint32_t out2_h;
251 uint8_t update_flag;
252};
253
254struct msm_vpe_buf_info {
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530255 uint32_t p0_phy;
256 uint32_t p1_phy;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700257 struct timespec ts;
258 uint32_t frame_id;
259 struct video_crop_t vpe_crop;
260};
261
262struct msm_vfe_resp {
263 enum vfe_resp_msg type;
264 struct msm_cam_evt_msg evt_msg;
265 struct msm_vfe_phy_info phy;
266 struct msm_vfe_stats_msg stats_msg;
267 struct msm_vpe_buf_info vpe_bf;
268 void *extdata;
269 int32_t extlen;
270};
271
272struct msm_vpe_resp {
273 enum vpe_resp_msg type;
274 struct msm_cam_evt_msg evt_msg;
275 struct msm_vpe_phy_info phy;
276 void *extdata;
277 int32_t extlen;
278};
279
280struct msm_vpe_callback {
281 void (*vpe_resp)(struct msm_vpe_resp *,
282 enum msm_queue, void *syncdata,
283 void *time_stamp, gfp_t gfp);
284 void* (*vpe_alloc)(int, void *syncdata, gfp_t gfp);
285 void (*vpe_free)(void *ptr);
286};
287
288struct msm_vfe_callback {
289 void (*vfe_resp)(struct msm_vfe_resp *,
290 enum msm_queue, void *syncdata,
291 gfp_t gfp);
292 void* (*vfe_alloc)(int, void *syncdata, gfp_t gfp);
293 void (*vfe_free)(void *ptr);
294};
295
296struct msm_camvfe_fn {
297 int (*vfe_init)(struct msm_vfe_callback *,
298 struct platform_device *);
299 int (*vfe_enable)(struct camera_enable_cmd *);
300 int (*vfe_config)(struct msm_vfe_cfg_cmd *, void *);
301 int (*vfe_disable)(struct camera_enable_cmd *,
302 struct platform_device *dev);
303 void (*vfe_release)(struct platform_device *);
304 void (*vfe_stop)(void);
305};
306
307struct msm_camvfe_params {
308 struct msm_vfe_cfg_cmd *vfe_cfg;
309 void *data;
310};
311
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700312struct msm_mctl_pp_params {
313 struct msm_mctl_pp_cmd *cmd;
314 void *data;
315};
316
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700317struct msm_camvpe_fn {
318 int (*vpe_reg)(struct msm_vpe_callback *);
319 int (*vpe_cfg_update) (void *);
Alekhya,Monikafc81e102011-12-29 15:17:33 +0530320 void (*send_frame_to_vpe) (uint32_t planar0_off, uint32_t planar1_off,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700321 struct timespec *ts, int output_id);
322 int (*vpe_config)(struct msm_vpe_cfg_cmd *, void *);
323 void (*vpe_cfg_offset)(int frame_pack, uint32_t pyaddr,
324 uint32_t pcbcraddr, struct timespec *ts, int output_id,
325 struct msm_st_half st_half, int frameid);
326 int *dis;
327};
328
329struct msm_sensor_ctrl {
330 int (*s_init)(const struct msm_camera_sensor_info *);
331 int (*s_release)(void);
332 int (*s_config)(void __user *);
333 enum msm_camera_type s_camera_type;
334 uint32_t s_mount_angle;
335 enum msm_st_frame_packing s_video_packing;
336 enum msm_st_frame_packing s_snap_packing;
337};
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700338
339struct msm_actuator_ctrl {
340 int (*a_init_table)(void);
Rajakumar Govindaramdf6af9c2011-12-01 21:26:20 -0800341 int (*a_power_up)(void *);
342 int (*a_power_down)(void *);
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700343 int (*a_create_subdevice)(void *, void *);
344 int (*a_config)(void __user *);
345};
346
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700347struct msm_strobe_flash_ctrl {
348 int (*strobe_flash_init)
349 (struct msm_camera_sensor_strobe_flash_data *);
350 int (*strobe_flash_release)
351 (struct msm_camera_sensor_strobe_flash_data *, int32_t);
352 int (*strobe_flash_charge)(int32_t, int32_t, uint32_t);
353};
354
355/* this structure is used in kernel */
356struct msm_queue_cmd {
357 struct list_head list_config;
358 struct list_head list_control;
359 struct list_head list_frame;
360 struct list_head list_pict;
361 struct list_head list_vpe_frame;
362 enum msm_queue type;
363 void *command;
364 atomic_t on_heap;
365 struct timespec ts;
366 uint32_t error_code;
367};
368
369struct msm_device_queue {
370 struct list_head list;
371 spinlock_t lock;
372 wait_queue_head_t wait;
373 int max;
374 int len;
375 const char *name;
376};
377
378struct msm_sync {
379 /* These two queues are accessed from a process context only
380 * They contain pmem descriptors for the preview frames and the stats
381 * coming from the camera sensor.
382 */
383 struct hlist_head pmem_frames;
384 struct hlist_head pmem_stats;
385
386 /* The message queue is used by the control thread to send commands
387 * to the config thread, and also by the DSP to send messages to the
388 * config thread. Thus it is the only queue that is accessed from
389 * both interrupt and process context.
390 */
391 struct msm_device_queue event_q;
392
393 /* This queue contains preview frames. It is accessed by the DSP (in
394 * in interrupt context, and by the frame thread.
395 */
396 struct msm_device_queue frame_q;
397 int unblock_poll_frame;
398 int unblock_poll_pic_frame;
399
400 /* This queue contains snapshot frames. It is accessed by the DSP (in
401 * interrupt context, and by the control thread.
402 */
403 struct msm_device_queue pict_q;
404 int get_pic_abort;
405 struct msm_device_queue vpe_q;
406
407 struct msm_camera_sensor_info *sdata;
408 struct msm_camvfe_fn vfefn;
409 struct msm_camvpe_fn vpefn;
410 struct msm_sensor_ctrl sctrl;
411 struct msm_strobe_flash_ctrl sfctrl;
Sreesudhan Ramakrish Ramkumara4b5f302011-09-12 16:23:22 -0700412 struct msm_actuator_ctrl actctrl;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700413 struct wake_lock wake_lock;
414 struct platform_device *pdev;
415 int16_t ignore_qcmd_type;
416 uint8_t ignore_qcmd;
417 uint8_t opencnt;
418 void *cropinfo;
419 int croplen;
420 int core_powered_on;
421
422 struct fd_roi_info fdroiinfo;
423
424 atomic_t vpe_enable;
425 uint32_t pp_mask;
426 uint8_t pp_frame_avail;
427 struct msm_queue_cmd *pp_prev;
428 struct msm_queue_cmd *pp_snap;
429 struct msm_queue_cmd *pp_thumb;
430 int video_fd;
431
432 const char *apps_id;
433
434 struct mutex lock;
435 struct list_head list;
436 uint8_t liveshot_enabled;
437 struct msm_cam_v4l2_device *pcam_sync;
438
439 uint8_t stereocam_enabled;
440 struct msm_queue_cmd *pp_stereocam;
441 struct msm_queue_cmd *pp_stereocam2;
442 struct msm_queue_cmd *pp_stereosnap;
443 enum msm_stereo_state stereo_state;
444 int stcam_quality_ind;
445 uint32_t stcam_conv_value;
446
447 spinlock_t pmem_frame_spinlock;
448 spinlock_t pmem_stats_spinlock;
449 spinlock_t abort_pict_lock;
450 int snap_count;
451 int thumb_count;
452};
453
454#define MSM_APPS_ID_V4L2 "msm_v4l2"
455#define MSM_APPS_ID_PROP "msm_qct"
456
457struct msm_cam_device {
458 struct msm_sync *sync; /* most-frequently accessed */
459 struct device *device;
460 struct cdev cdev;
461 /* opened is meaningful only for the config and frame nodes,
462 * which may be opened only once.
463 */
464 atomic_t opened;
465};
466
467struct msm_control_device {
468 struct msm_cam_device *pmsm;
469
470 /* Used for MSM_CAM_IOCTL_CTRL_CMD_DONE responses */
471 uint8_t ctrl_data[max_control_command_size];
472 struct msm_ctrl_cmd ctrl;
473 struct msm_queue_cmd qcmd;
474
475 /* This queue used by the config thread to send responses back to the
476 * control thread. It is accessed only from a process context.
477 */
478 struct msm_device_queue ctrl_q;
479};
480
481struct register_address_value_pair {
482 uint16_t register_address;
483 uint16_t register_value;
484};
485
486struct msm_pmem_region {
487 struct hlist_node list;
488 unsigned long paddr;
489 unsigned long len;
490 struct file *file;
491 struct msm_pmem_info info;
Ankit Premrajkac6864b82011-07-15 11:43:41 -0700492 struct msm_mapped_buffer *msm_buffer;
493 int subsys_id;
Ankit Premrajka748a70a2011-11-01 08:22:04 -0700494 struct ion_handle *handle;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700495};
496
497struct axidata {
498 uint32_t bufnum1;
499 uint32_t bufnum2;
500 uint32_t bufnum3;
501 struct msm_pmem_region *region;
502};
503
504#ifdef CONFIG_MSM_CAMERA_FLASH
505int msm_camera_flash_set_led_state(
506 struct msm_camera_sensor_flash_data *fdata,
507 unsigned led_state);
508int msm_strobe_flash_init(struct msm_sync *sync, uint32_t sftype);
509int msm_flash_ctrl(struct msm_camera_sensor_info *sdata,
510 struct flash_ctrl_data *flash_info);
511#else
512static inline int msm_camera_flash_set_led_state(
513 struct msm_camera_sensor_flash_data *fdata,
514 unsigned led_state)
515{
516 return -ENOTSUPP;
517}
518static inline int msm_strobe_flash_init(
519 struct msm_sync *sync, uint32_t sftype)
520{
521 return -ENOTSUPP;
522}
523static inline int msm_flash_ctrl(
524 struct msm_camera_sensor_info *sdata,
525 struct flash_ctrl_data *flash_info)
526{
527 return -ENOTSUPP;
528}
529#endif
530
531
532
533void msm_camvfe_init(void);
534int msm_camvfe_check(void *);
535void msm_camvfe_fn_init(struct msm_camvfe_fn *, void *);
536void msm_camvpe_fn_init(struct msm_camvpe_fn *, void *);
537int msm_camera_drv_start(struct platform_device *dev,
538 int (*sensor_probe)(const struct msm_camera_sensor_info *,
539 struct msm_sensor_ctrl *));
540
541enum msm_camio_clk_type {
542 CAMIO_VFE_MDC_CLK,
543 CAMIO_MDC_CLK,
544 CAMIO_VFE_CLK,
545 CAMIO_VFE_AXI_CLK,
546
547 CAMIO_VFE_CAMIF_CLK,
548 CAMIO_VFE_PBDG_CLK,
549 CAMIO_CAM_MCLK_CLK,
550 CAMIO_CAMIF_PAD_PBDG_CLK,
551
552 CAMIO_CSI0_VFE_CLK,
553 CAMIO_CSI1_VFE_CLK,
554 CAMIO_VFE_PCLK,
555
556 CAMIO_CSI_SRC_CLK,
557 CAMIO_CSI0_CLK,
558 CAMIO_CSI1_CLK,
559 CAMIO_CSI0_PCLK,
560 CAMIO_CSI1_PCLK,
561
562 CAMIO_CSI1_SRC_CLK,
563 CAMIO_CSI_PIX_CLK,
Sreesudhan Ramakrish Ramkumard6e9cb92011-10-12 17:55:18 -0700564 CAMIO_CSI_PIX1_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700565 CAMIO_CSI_RDI_CLK,
Sreesudhan Ramakrish Ramkumard6e9cb92011-10-12 17:55:18 -0700566 CAMIO_CSI_RDI1_CLK,
567 CAMIO_CSI_RDI2_CLK,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700568 CAMIO_CSIPHY0_TIMER_CLK,
569 CAMIO_CSIPHY1_TIMER_CLK,
570
571 CAMIO_JPEG_CLK,
572 CAMIO_JPEG_PCLK,
573 CAMIO_VPE_CLK,
574 CAMIO_VPE_PCLK,
575
576 CAMIO_CSI0_PHY_CLK,
577 CAMIO_CSI1_PHY_CLK,
578 CAMIO_CSIPHY_TIMER_SRC_CLK,
579
580 CAMIO_MAX_CLK
581};
582
583enum msm_camio_clk_src_type {
584 MSM_CAMIO_CLK_SRC_INTERNAL,
585 MSM_CAMIO_CLK_SRC_EXTERNAL,
586 MSM_CAMIO_CLK_SRC_MAX
587};
588
589enum msm_s_test_mode {
590 S_TEST_OFF,
591 S_TEST_1,
592 S_TEST_2,
593 S_TEST_3
594};
595
596enum msm_s_resolution {
597 S_QTR_SIZE,
598 S_FULL_SIZE,
599 S_INVALID_SIZE
600};
601
602enum msm_s_reg_update {
603 /* Sensor egisters that need to be updated during initialization */
604 S_REG_INIT,
605 /* Sensor egisters that needs periodic I2C writes */
606 S_UPDATE_PERIODIC,
607 /* All the sensor Registers will be updated */
608 S_UPDATE_ALL,
609 /* Not valid update */
610 S_UPDATE_INVALID
611};
612
613enum msm_s_setting {
614 S_RES_PREVIEW,
615 S_RES_CAPTURE
616};
617
618enum msm_bus_perf_setting {
619 S_INIT,
620 S_PREVIEW,
621 S_VIDEO,
622 S_CAPTURE,
623 S_ZSL,
624 S_STEREO_VIDEO,
625 S_STEREO_CAPTURE,
626 S_DEFAULT,
627 S_EXIT
628};
629
Nishant Pandit24153d82011-08-27 16:05:13 +0530630enum msm_cam_mode {
631 MODE_R,
632 MODE_L,
633 MODE_DUAL
634};
635
Kevin Chan85af4552011-10-25 15:07:58 -0700636struct msm_cam_clk_info {
637 const char *clk_name;
638 long clk_rate;
639};
640
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700641int msm_camio_enable(struct platform_device *dev);
642int msm_camio_jpeg_clk_enable(void);
643int msm_camio_jpeg_clk_disable(void);
644int msm_camio_vpe_clk_enable(uint32_t);
645int msm_camio_vpe_clk_disable(void);
646
Nishant Pandit24153d82011-08-27 16:05:13 +0530647void msm_camio_mode_config(enum msm_cam_mode mode);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700648int msm_camio_clk_enable(enum msm_camio_clk_type clk);
649int msm_camio_clk_disable(enum msm_camio_clk_type clk);
650int msm_camio_clk_config(uint32_t freq);
651void msm_camio_clk_rate_set(int rate);
Shuzhen Wange49436a2011-09-28 16:07:27 -0700652int msm_camio_vfe_clk_rate_set(int rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700653void msm_camio_clk_rate_set_2(struct clk *clk, int rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700654void msm_camio_clk_axi_rate_set(int rate);
655void msm_disable_io_gpio_clk(struct platform_device *);
656
657void msm_camio_camif_pad_reg_reset(void);
658void msm_camio_camif_pad_reg_reset_2(void);
659
660void msm_camio_vfe_blk_reset(void);
661
Nishant Pandit24153d82011-08-27 16:05:13 +0530662int32_t msm_camio_3d_enable(const struct msm_camera_sensor_info *sinfo);
663void msm_camio_3d_disable(void);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700664void msm_camio_clk_sel(enum msm_camio_clk_src_type);
665void msm_camio_disable(struct platform_device *);
666int msm_camio_probe_on(struct platform_device *);
667int msm_camio_probe_off(struct platform_device *);
668int msm_camio_sensor_clk_off(struct platform_device *);
669int msm_camio_sensor_clk_on(struct platform_device *);
670int msm_camio_csi_config(struct msm_camera_csi_params *csi_params);
671int msm_camio_csiphy_config(struct msm_camera_csiphy_params *csiphy_params);
672int msm_camio_csid_config(struct msm_camera_csid_params *csid_params);
673void msm_io_read_interrupt(void);
674int add_axi_qos(void);
675int update_axi_qos(uint32_t freq);
676void release_axi_qos(void);
677void msm_io_w(u32 data, void __iomem *addr);
678void msm_io_w_mb(u32 data, void __iomem *addr);
679u32 msm_io_r(void __iomem *addr);
680u32 msm_io_r_mb(void __iomem *addr);
681void msm_io_dump(void __iomem *addr, int size);
682void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len);
683void msm_camio_set_perf_lvl(enum msm_bus_perf_setting);
Kevin Chan09f4e662011-12-16 08:17:02 -0800684void msm_camio_bus_scale_cfg(
685 struct msm_bus_scale_pdata *, enum msm_bus_perf_setting);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700686
Shuzhen Wanga3c1a122011-08-04 15:33:27 -0700687void *msm_isp_sync_alloc(int size, gfp_t gfp);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700688
689void msm_isp_sync_free(void *ptr);
Kevin Chan85af4552011-10-25 15:07:58 -0700690
691int msm_cam_clk_enable(struct device *dev, struct msm_cam_clk_info *clk_info,
692 struct clk **clk_ptr, int num_clk, int enable);
Jeyaprakash Soundrapandian2474e8f2012-01-03 15:59:57 -0800693int msm_cam_core_reset(void);
Kevin Chaneb6b6072012-01-17 11:54:54 -0800694
695int msm_camera_config_vreg(struct device *dev, struct camera_vreg_t *cam_vreg,
696 int num_vreg, struct regulator **reg_ptr, int config);
697int msm_camera_enable_vreg(struct device *dev, struct camera_vreg_t *cam_vreg,
698 int num_vreg, struct regulator **reg_ptr, int enable);
699
700int msm_camera_config_gpio_table
701 (struct msm_camera_sensor_info *sinfo, int gpio_en);
702int msm_camera_request_gpio_table
703 (struct msm_camera_sensor_info *sinfo, int gpio_en);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700704#endif