Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 1 | /* |
| 2 | * MPC8610 HPCD board specific routines |
| 3 | * |
| 4 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
| 5 | * Recode: Jason Jin <jason.jin@freescale.com> |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 6 | * York Sun <yorksun@freescale.com> |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 7 | * |
| 8 | * Rewrite the interrupt routing. remove the 8259PIC support, |
| 9 | * All the integrated device in ULI use sideband interrupt. |
| 10 | * |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 11 | * Copyright 2008 Freescale Semiconductor Inc. |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify it |
| 14 | * under the terms of the GNU General Public License as published by the |
| 15 | * Free Software Foundation; either version 2 of the License, or (at your |
| 16 | * option) any later version. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/stddef.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/pci.h> |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 22 | #include <linux/interrupt.h> |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 23 | #include <linux/kdev_t.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/seq_file.h> |
| 26 | #include <linux/of.h> |
| 27 | |
| 28 | #include <asm/system.h> |
| 29 | #include <asm/time.h> |
| 30 | #include <asm/machdep.h> |
| 31 | #include <asm/pci-bridge.h> |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 32 | #include <asm/prom.h> |
| 33 | #include <mm/mmu_decl.h> |
| 34 | #include <asm/udbg.h> |
| 35 | |
| 36 | #include <asm/mpic.h> |
| 37 | |
Timur Tabi | c7d24a2 | 2008-01-18 09:24:53 -0600 | [diff] [blame] | 38 | #include <linux/of_platform.h> |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 39 | #include <sysdev/fsl_pci.h> |
| 40 | #include <sysdev/fsl_soc.h> |
Anton Vorontsov | d2998c2 | 2009-06-18 16:49:02 -0700 | [diff] [blame] | 41 | #include <sysdev/simple_gpio.h> |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 42 | |
Kumar Gala | 98384c6 | 2008-07-02 11:46:20 -0500 | [diff] [blame] | 43 | #include "mpc86xx.h" |
| 44 | |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 45 | static struct device_node *pixis_node; |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 46 | static unsigned char *pixis_bdcfg0, *pixis_arch; |
| 47 | |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 48 | #ifdef CONFIG_SUSPEND |
| 49 | static irqreturn_t mpc8610_sw9_irq(int irq, void *data) |
| 50 | { |
| 51 | pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__); |
| 52 | return IRQ_HANDLED; |
| 53 | } |
| 54 | |
| 55 | static void __init mpc8610_suspend_init(void) |
| 56 | { |
| 57 | int irq; |
| 58 | int ret; |
| 59 | |
| 60 | if (!pixis_node) |
| 61 | return; |
| 62 | |
| 63 | irq = irq_of_parse_and_map(pixis_node, 0); |
| 64 | if (!irq) { |
| 65 | pr_err("%s: can't map pixis event IRQ.\n", __func__); |
| 66 | return; |
| 67 | } |
| 68 | |
Geert Uytterhoeven | e0be2c2 | 2011-05-04 16:29:31 +0200 | [diff] [blame] | 69 | ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL); |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 70 | if (ret) { |
| 71 | pr_err("%s: can't request pixis event IRQ: %d\n", |
| 72 | __func__, ret); |
| 73 | irq_dispose_mapping(irq); |
| 74 | } |
| 75 | |
| 76 | enable_irq_wake(irq); |
| 77 | } |
| 78 | #else |
| 79 | static inline void mpc8610_suspend_init(void) { } |
| 80 | #endif /* CONFIG_SUSPEND */ |
| 81 | |
Timur Tabi | c7d24a2 | 2008-01-18 09:24:53 -0600 | [diff] [blame] | 82 | static struct of_device_id __initdata mpc8610_ids[] = { |
| 83 | { .compatible = "fsl,mpc8610-immr", }, |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 84 | { .compatible = "fsl,mpc8610-guts", }, |
Anton Vorontsov | 34b4a87 | 2008-05-04 22:46:27 +0400 | [diff] [blame] | 85 | { .compatible = "simple-bus", }, |
Timur Tabi | 4c5ddd5 | 2010-05-03 16:54:15 -0500 | [diff] [blame] | 86 | /* So that the DMA channel nodes can be probed individually: */ |
| 87 | { .compatible = "fsl,eloplus-dma", }, |
Timur Tabi | c7d24a2 | 2008-01-18 09:24:53 -0600 | [diff] [blame] | 88 | {} |
| 89 | }; |
| 90 | |
| 91 | static int __init mpc8610_declare_of_platform_devices(void) |
| 92 | { |
Anton Vorontsov | d2998c2 | 2009-06-18 16:49:02 -0700 | [diff] [blame] | 93 | /* Firstly, register PIXIS GPIOs. */ |
| 94 | simple_gpiochip_init("fsl,fpga-pixis-gpio-bank"); |
| 95 | |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 96 | /* Enable wakeup on PIXIS' event IRQ. */ |
| 97 | mpc8610_suspend_init(); |
| 98 | |
Timur Tabi | c7d24a2 | 2008-01-18 09:24:53 -0600 | [diff] [blame] | 99 | /* Without this call, the SSI device driver won't get probed. */ |
| 100 | of_platform_bus_probe(NULL, mpc8610_ids, NULL); |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices); |
| 105 | |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 106 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) |
| 107 | |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 108 | /* |
| 109 | * DIU Area Descriptor |
| 110 | * |
| 111 | * The MPC8610 reference manual shows the bits of the AD register in |
| 112 | * little-endian order, which causes the BLUE_C field to be split into two |
| 113 | * parts. To simplify the definition of the MAKE_AD() macro, we define the |
| 114 | * fields in big-endian order and byte-swap the result. |
| 115 | * |
| 116 | * So even though the registers don't look like they're in the |
| 117 | * same bit positions as they are on the P1022, the same value is written to |
| 118 | * the AD register on the MPC8610 and on the P1022. |
| 119 | */ |
| 120 | #define AD_BYTE_F 0x10000000 |
| 121 | #define AD_ALPHA_C_MASK 0x0E000000 |
| 122 | #define AD_ALPHA_C_SHIFT 25 |
| 123 | #define AD_BLUE_C_MASK 0x01800000 |
| 124 | #define AD_BLUE_C_SHIFT 23 |
| 125 | #define AD_GREEN_C_MASK 0x00600000 |
| 126 | #define AD_GREEN_C_SHIFT 21 |
| 127 | #define AD_RED_C_MASK 0x00180000 |
| 128 | #define AD_RED_C_SHIFT 19 |
| 129 | #define AD_PALETTE 0x00040000 |
| 130 | #define AD_PIXEL_S_MASK 0x00030000 |
| 131 | #define AD_PIXEL_S_SHIFT 16 |
| 132 | #define AD_COMP_3_MASK 0x0000F000 |
| 133 | #define AD_COMP_3_SHIFT 12 |
| 134 | #define AD_COMP_2_MASK 0x00000F00 |
| 135 | #define AD_COMP_2_SHIFT 8 |
| 136 | #define AD_COMP_1_MASK 0x000000F0 |
| 137 | #define AD_COMP_1_SHIFT 4 |
| 138 | #define AD_COMP_0_MASK 0x0000000F |
| 139 | #define AD_COMP_0_SHIFT 0 |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 140 | |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 141 | #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ |
| 142 | cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ |
| 143 | (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ |
| 144 | (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ |
| 145 | (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ |
| 146 | (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 147 | |
| 148 | unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel, |
| 149 | int monitor_port) |
| 150 | { |
| 151 | static const unsigned long pixelformat[][3] = { |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 152 | { |
| 153 | MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8), |
| 154 | MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0), |
| 155 | MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0) |
| 156 | }, |
| 157 | { |
| 158 | MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8), |
| 159 | MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0), |
| 160 | MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0) |
| 161 | }, |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 162 | }; |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 163 | unsigned int arch_monitor; |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 164 | |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 165 | /* The DVI port is mis-wired on revision 1 of this board. */ |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 166 | arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1; |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 167 | |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 168 | switch (bits_per_pixel) { |
| 169 | case 32: |
| 170 | return pixelformat[arch_monitor][0]; |
| 171 | case 24: |
| 172 | return pixelformat[arch_monitor][1]; |
| 173 | case 16: |
| 174 | return pixelformat[arch_monitor][2]; |
| 175 | default: |
| 176 | pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); |
| 177 | return 0; |
| 178 | } |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base) |
| 182 | { |
| 183 | int i; |
| 184 | if (monitor_port == 2) { /* dual link LVDS */ |
| 185 | for (i = 0; i < 256*3; i++) |
| 186 | gamma_table_base[i] = (gamma_table_base[i] << 2) | |
| 187 | ((gamma_table_base[i] >> 6) & 0x03); |
| 188 | } |
| 189 | } |
| 190 | |
Anton Vorontsov | f637ef8 | 2008-05-12 16:35:33 +0400 | [diff] [blame] | 191 | #define PX_BRDCFG0_DVISEL (1 << 3) |
| 192 | #define PX_BRDCFG0_DLINK (1 << 4) |
| 193 | #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK) |
| 194 | |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 195 | void mpc8610hpcd_set_monitor_port(int monitor_port) |
| 196 | { |
Anton Vorontsov | f637ef8 | 2008-05-12 16:35:33 +0400 | [diff] [blame] | 197 | static const u8 bdcfg[] = { |
| 198 | PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK, |
| 199 | PX_BRDCFG0_DLINK, |
| 200 | 0, |
| 201 | }; |
| 202 | |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 203 | if (monitor_port < 3) |
Anton Vorontsov | f637ef8 | 2008-05-12 16:35:33 +0400 | [diff] [blame] | 204 | clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK, |
| 205 | bdcfg[monitor_port]); |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) |
| 209 | { |
| 210 | u32 __iomem *clkdvdr; |
| 211 | u32 temp; |
| 212 | /* variables for pixel clock calcs */ |
| 213 | ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock; |
| 214 | ulong pixval; |
| 215 | long err; |
| 216 | int i; |
| 217 | |
| 218 | clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32)); |
| 219 | if (!clkdvdr) { |
| 220 | printk(KERN_ERR "Err: can't map clock divider register!\n"); |
| 221 | return; |
| 222 | } |
| 223 | |
| 224 | /* Pixel Clock configuration */ |
Timur Tabi | f46dad2 | 2011-05-09 14:29:40 -0500 | [diff] [blame] | 225 | speed_ccb = fsl_get_sys_freq(); |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 226 | |
| 227 | /* Calculate the pixel clock with the smallest error */ |
| 228 | /* calculate the following in steps to avoid overflow */ |
| 229 | pr_debug("DIU pixclock in ps - %d\n", pixclock); |
| 230 | temp = 1000000000/pixclock; |
| 231 | temp *= 1000; |
| 232 | pixclock = temp; |
| 233 | pr_debug("DIU pixclock freq - %u\n", pixclock); |
| 234 | |
| 235 | temp = pixclock * 5 / 100; |
| 236 | pr_debug("deviation = %d\n", temp); |
| 237 | minpixclock = pixclock - temp; |
| 238 | maxpixclock = pixclock + temp; |
| 239 | pr_debug("DIU minpixclock - %lu\n", minpixclock); |
| 240 | pr_debug("DIU maxpixclock - %lu\n", maxpixclock); |
| 241 | pixval = speed_ccb/pixclock; |
| 242 | pr_debug("DIU pixval = %lu\n", pixval); |
| 243 | |
| 244 | err = 100000000; |
| 245 | bestval = pixval; |
| 246 | pr_debug("DIU bestval = %lu\n", bestval); |
| 247 | |
| 248 | bestfreq = 0; |
| 249 | for (i = -1; i <= 1; i++) { |
| 250 | temp = speed_ccb / ((pixval+i) + 1); |
| 251 | pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n", |
| 252 | i, pixval, temp); |
| 253 | if ((temp < minpixclock) || (temp > maxpixclock)) |
| 254 | pr_debug("DIU exceeds monitor range (%lu to %lu)\n", |
| 255 | minpixclock, maxpixclock); |
| 256 | else if (abs(temp - pixclock) < err) { |
| 257 | pr_debug("Entered the else if block %d\n", i); |
| 258 | err = abs(temp - pixclock); |
| 259 | bestval = pixval+i; |
| 260 | bestfreq = temp; |
| 261 | } |
| 262 | } |
| 263 | |
| 264 | pr_debug("DIU chose = %lx\n", bestval); |
| 265 | pr_debug("DIU error = %ld\n NomPixClk ", err); |
| 266 | pr_debug("DIU: Best Freq = %lx\n", bestfreq); |
| 267 | /* Modify PXCLK in GUTS CLKDVDR */ |
| 268 | pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr)); |
| 269 | temp = (*clkdvdr) & 0x2000FFFF; |
| 270 | *clkdvdr = temp; /* turn off clock */ |
| 271 | *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16); |
| 272 | pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr)); |
| 273 | iounmap(clkdvdr); |
| 274 | } |
| 275 | |
| 276 | ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf) |
| 277 | { |
| 278 | return snprintf(buf, PAGE_SIZE, |
| 279 | "%c0 - DVI\n" |
| 280 | "%c1 - Single link LVDS\n" |
| 281 | "%c2 - Dual link LVDS\n", |
| 282 | monitor_port == 0 ? '*' : ' ', |
| 283 | monitor_port == 1 ? '*' : ' ', |
| 284 | monitor_port == 2 ? '*' : ' '); |
| 285 | } |
| 286 | |
| 287 | int mpc8610hpcd_set_sysfs_monitor_port(int val) |
| 288 | { |
| 289 | return val < 3 ? val : 0; |
| 290 | } |
| 291 | |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 292 | #endif |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 293 | |
| 294 | static void __init mpc86xx_hpcd_setup_arch(void) |
| 295 | { |
| 296 | struct resource r; |
| 297 | struct device_node *np; |
| 298 | unsigned char *pixis; |
| 299 | |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 300 | if (ppc_md.progress) |
| 301 | ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0); |
| 302 | |
| 303 | #ifdef CONFIG_PCI |
| 304 | for_each_node_by_type(np, "pci") { |
| 305 | if (of_device_is_compatible(np, "fsl,mpc8610-pci") |
| 306 | || of_device_is_compatible(np, "fsl,mpc8641-pcie")) { |
| 307 | struct resource rsrc; |
| 308 | of_address_to_resource(np, 0, &rsrc); |
| 309 | if ((rsrc.start & 0xfffff) == 0xa000) |
| 310 | fsl_add_bridge(np, 1); |
| 311 | else |
| 312 | fsl_add_bridge(np, 0); |
| 313 | } |
| 314 | } |
| 315 | #endif |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 316 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 317 | diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format; |
| 318 | diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table; |
| 319 | diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port; |
| 320 | diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock; |
| 321 | diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port; |
| 322 | diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port; |
| 323 | #endif |
| 324 | |
Anton Vorontsov | 8c68e2f | 2009-09-16 01:44:00 +0400 | [diff] [blame] | 325 | pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis"); |
| 326 | if (pixis_node) { |
| 327 | of_address_to_resource(pixis_node, 0, &r); |
| 328 | of_node_put(pixis_node); |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 329 | pixis = ioremap(r.start, 32); |
| 330 | if (!pixis) { |
| 331 | printk(KERN_ERR "Err: can't map FPGA cfg register!\n"); |
| 332 | return; |
| 333 | } |
| 334 | pixis_bdcfg0 = pixis + 8; |
| 335 | pixis_arch = pixis + 1; |
| 336 | } else |
| 337 | printk(KERN_ERR "Err: " |
| 338 | "can't find device node 'fsl,fpga-pixis'\n"); |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 339 | |
| 340 | printk("MPC86xx HPCD board from Freescale Semiconductor\n"); |
| 341 | } |
| 342 | |
| 343 | /* |
| 344 | * Called very early, device-tree isn't unflattened |
| 345 | */ |
| 346 | static int __init mpc86xx_hpcd_probe(void) |
| 347 | { |
| 348 | unsigned long root = of_get_flat_dt_root(); |
| 349 | |
| 350 | if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD")) |
| 351 | return 1; /* Looks good */ |
| 352 | |
| 353 | return 0; |
| 354 | } |
| 355 | |
York Sun | 6f90a8bd | 2008-04-28 02:15:36 -0700 | [diff] [blame] | 356 | static long __init mpc86xx_time_init(void) |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 357 | { |
| 358 | unsigned int temp; |
| 359 | |
| 360 | /* Set the time base to zero */ |
| 361 | mtspr(SPRN_TBWL, 0); |
| 362 | mtspr(SPRN_TBWU, 0); |
| 363 | |
| 364 | temp = mfspr(SPRN_HID0); |
| 365 | temp |= HID0_TBEN; |
| 366 | mtspr(SPRN_HID0, temp); |
| 367 | asm volatile("isync"); |
| 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
| 372 | define_machine(mpc86xx_hpcd) { |
| 373 | .name = "MPC86xx HPCD", |
| 374 | .probe = mpc86xx_hpcd_probe, |
| 375 | .setup_arch = mpc86xx_hpcd_setup_arch, |
Kumar Gala | 98384c6 | 2008-07-02 11:46:20 -0500 | [diff] [blame] | 376 | .init_IRQ = mpc86xx_init_irq, |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 377 | .get_irq = mpic_get_irq, |
Kumar Gala | e1c1575 | 2007-10-04 01:04:57 -0500 | [diff] [blame] | 378 | .restart = fsl_rstcr_restart, |
Xianghua Xiao | 0e65bfe3 | 2007-10-03 15:09:33 -0500 | [diff] [blame] | 379 | .time_init = mpc86xx_time_init, |
| 380 | .calibrate_decr = generic_calibrate_decr, |
| 381 | .progress = udbg_progress, |
| 382 | .pcibios_fixup_bus = fsl_pcibios_fixup_bus, |
| 383 | }; |