blob: 6d4d074738aba9294e94cdd0326b6e95b71ee6bf [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/*
2 * Register/Interrupt access for userspace aDSP library.
3 *
4 * Copyright (C) 2008 Google, Inc.
5 * Copyright (c) 2008-2009,2011 Code Aurora Forum. All rights reserved.
6 * Author: Iliyan Malchev <ibm@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19/* TODO:
20 * - move shareable rpc code outside of adsp.c
21 * - general solution for virt->phys patchup
22 * - queue IDs should be relative to modules
23 * - disallow access to non-associated queues
24 */
25
26#include <linux/clk.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/kernel.h>
30#include <linux/kthread.h>
31#include <linux/module.h>
32#include <linux/uaccess.h>
33#include <linux/wait.h>
34#include <linux/slab.h>
35#include <linux/io.h>
36#include <mach/msm_iomap.h>
37#include <mach/clk.h>
38#include <mach/msm_adsp.h>
39#include "adsp.h"
40#include <mach/debug_mm.h>
41#include <linux/debugfs.h>
42
43#ifdef CONFIG_DEBUG_FS
44static struct dentry *dentry_adsp;
45static struct dentry *dentry_wdata;
46static struct dentry *dentry_rdata;
47static int wdump, rdump;
48#endif /* CONFIG_DEBUG_FS */
49
50#define INT_ADSP INT_ADSP_A9_A11
51
52static struct adsp_info adsp_info;
53static struct msm_adsp_module *adsp_modules;
54static int adsp_open_count;
55
56static DEFINE_MUTEX(adsp_open_lock);
57
58/* protect interactions with the ADSP command/message queue */
59static spinlock_t adsp_cmd_lock;
60static spinlock_t adsp_write_lock;
61
62static uint32_t current_image = -1;
63
64void adsp_set_image(struct adsp_info *info, uint32_t image)
65{
66 current_image = image;
67}
68
69/*
70 * Checks whether the module_id is available in the
71 * module_entries table.If module_id is available returns `0`.
72 * If module_id is not available returns `-ENXIO`.
73 */
74static int32_t adsp_validate_module(uint32_t module_id)
75{
76 uint32_t *ptr;
77 uint32_t module_index;
78 uint32_t num_mod_entries;
79
80 ptr = adsp_info.init_info_ptr->module_entries;
81 num_mod_entries = adsp_info.init_info_ptr->module_table_size;
82
83 for (module_index = 0; module_index < num_mod_entries; module_index++)
84 if (module_id == ptr[module_index])
85 return 0;
86
87 return -ENXIO;
88}
89
90static int32_t adsp_validate_queue(uint32_t mod_id, unsigned q_idx,
91 uint32_t size)
92{
93 int32_t i;
94 struct adsp_rtos_mp_mtoa_init_info_type *sptr;
95
96 sptr = adsp_info.init_info_ptr;
97 for (i = 0; i < sptr->mod_to_q_entries; i++)
98 if (mod_id == sptr->mod_to_q_tbl[i].module)
99 if (q_idx == sptr->mod_to_q_tbl[i].q_type) {
100 if (size <= sptr->mod_to_q_tbl[i].q_max_len)
101 return 0;
102 MM_ERR("q_idx: %d is not a valid queue \
103 for module %x\n", q_idx, mod_id);
104 return -EINVAL;
105 }
106 MM_ERR("cmd_buf size is more than allowed size\n");
107 return -EINVAL;
108}
109
110uint32_t adsp_get_module(struct adsp_info *info, uint32_t task)
111{
112 return info->task_to_module[current_image][task];
113}
114
115uint32_t adsp_get_queue_offset(struct adsp_info *info, uint32_t queue_id)
116{
117 return info->queue_offset[current_image][queue_id];
118}
119
120static int rpc_adsp_rtos_app_to_modem(uint32_t cmd, uint32_t module,
121 struct msm_adsp_module *adsp_module)
122{
123 struct adsp_rtos_atom_cmd adspsvc_cmd;
124 int err;
125
126 adspsvc_cmd.cmd = cmd;
127 adspsvc_cmd.proc_id = RPC_ADSP_RTOS_PROC_APPS;
128 adspsvc_cmd.module = module;
129 adspsvc_cmd.cb_handle = adsp_info.cb_handle;
130
131 err = dalrpc_fcn_5(DALDEVICE_ADSP_CMD_IDX | 0x80000000,
132 adsp_info.handle,
133 &adspsvc_cmd, sizeof(adspsvc_cmd));
134 if (err < 0)
135 MM_ERR("ADSP command send Failed\n");
136
137 return 0;
138}
139
140static int get_module_index(uint32_t id)
141{
142 int mod_idx;
143 for (mod_idx = 0; mod_idx < adsp_info.module_count; mod_idx++)
144 if (adsp_info.module[mod_idx].id == id)
145 return mod_idx;
146
147 return -ENXIO;
148}
149
150static struct msm_adsp_module *find_adsp_module_by_id(
151 struct adsp_info *info, uint32_t id)
152{
153 int mod_idx;
154
155 if (id > info->max_module_id) {
156 return NULL;
157 } else {
158 mod_idx = get_module_index(id);
159 if (mod_idx < 0)
160 return NULL;
161 return info->id_to_module[mod_idx];
162 }
163}
164
165static struct msm_adsp_module *find_adsp_module_by_name(
166 struct adsp_info *info, const char *name)
167{
168 unsigned n;
169 for (n = 0; n < info->module_count; n++)
170 if (!strcmp(name, adsp_modules[n].name))
171 return adsp_modules + n;
172 return NULL;
173}
174
175/*
176 * Send RPC_ADSP_RTOS_CMD_GET_INIT_INFO cmd to ARM9 and get
177 * queue offsets and module entries (init info) as part of the event.
178 */
179static void msm_get_init_info(void)
180{
181 struct adsp_rtos_atom_cmd cmd;
182 int err;
183
184 cmd.cmd = RPC_ADSP_RTOS_CMD_GET_INIT_INFO;
185 cmd.proc_id = RPC_ADSP_RTOS_PROC_APPS;
186 cmd.module = 0;
187 cmd.cb_handle = adsp_info.cb_handle;
188
189 err = dalrpc_fcn_5(DALDEVICE_ADSP_CMD_IDX | 0x80000000,
190 adsp_info.handle,
191 &cmd, sizeof(cmd));
192 if (err < 0)
193 MM_ERR("INIT_INFO command send Failed\n");
194}
195
196int msm_adsp_get(const char *name, struct msm_adsp_module **out,
197 struct msm_adsp_ops *ops, void *driver_data)
198{
199 struct msm_adsp_module *module;
200 int rc = 0;
201
202 module = find_adsp_module_by_name(&adsp_info, name);
203 if (!module)
204 return -ENODEV;
205
206 mutex_lock(&module->lock);
207 MM_DBG("opening module %s\n", module->name);
208
209 if (module->ops) {
210 rc = -EBUSY;
211 mutex_unlock(&module->lock);
212 goto done;
213 }
214
215 module->ops = ops;
216 module->driver_data = driver_data;
217 *out = module;
218 mutex_unlock(&module->lock);
219 rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_REGISTER_APP,
220 module->id, module);
221 if (rc) {
222 mutex_lock(&module->lock);
223 module->ops = NULL;
224 module->driver_data = NULL;
225 *out = NULL;
226 MM_ERR("REGISTER_APP failed\n");
227 mutex_unlock(&module->lock);
228 goto done;
229 }
230
231 MM_INFO("module %s has been registered\n", module->name);
232
233done:
234 return rc;
235}
236EXPORT_SYMBOL(msm_adsp_get);
237
238void msm_adsp_put(struct msm_adsp_module *module)
239{
240 unsigned long flags;
241
242 mutex_lock(&module->lock);
243 if (module->ops) {
244 MM_INFO("closing module %s\n", module->name);
245
246 /* lock to ensure a dsp event cannot be delivered
247 * during or after removal of the ops and driver_data
248 */
249 spin_lock_irqsave(&adsp_cmd_lock, flags);
250 module->ops = NULL;
251 module->driver_data = NULL;
252 spin_unlock_irqrestore(&adsp_cmd_lock, flags);
253
254 if (module->state != ADSP_STATE_DISABLED) {
255 MM_INFO("disabling module %s\n", module->name);
256 mutex_unlock(&module->lock);
257 msm_adsp_disable(module);
258 return;
259 }
260 } else {
261 MM_INFO("module %s is already closed\n", module->name);
262 }
263 mutex_unlock(&module->lock);
264}
265EXPORT_SYMBOL(msm_adsp_put);
266
267int __msm_adsp_write(struct msm_adsp_module *module, unsigned dsp_queue_addr,
268 void *cmd_buf, size_t cmd_size)
269{
270 uint32_t ctrl_word;
271 uint32_t dsp_q_addr;
272 uint32_t dsp_addr;
273 uint32_t cmd_id = 0;
274 int cnt = 0;
275 int ret_status = 0;
276 unsigned long flags;
277 struct adsp_info *info;
278
279 if (!module || !cmd_buf) {
280 MM_ERR("Called with NULL parameters\n");
281 return -EINVAL;
282 }
283 info = module->info;
284 spin_lock_irqsave(&adsp_write_lock, flags);
285
286 if (module->state != ADSP_STATE_ENABLED) {
287 spin_unlock_irqrestore(&adsp_write_lock, flags);
288 MM_ERR("module %s not enabled before write\n", module->name);
289 return -ENODEV;
290 }
291 if (adsp_validate_module(module->id)) {
292 spin_unlock_irqrestore(&adsp_write_lock, flags);
293 MM_ERR("module id validation failed %s %d\n",
294 module->name, module->id);
295 return -ENXIO;
296 }
297 if (dsp_queue_addr >= QDSP_MAX_NUM_QUEUES) {
298 spin_unlock_irqrestore(&adsp_write_lock, flags);
299 MM_ERR("Invalid Queue Index: %d\n", dsp_queue_addr);
300 return -ENXIO;
301 }
302 if (adsp_validate_queue(module->id, dsp_queue_addr, cmd_size)) {
303 spin_unlock_irqrestore(&adsp_write_lock, flags);
304 return -EINVAL;
305 }
306 dsp_q_addr = adsp_get_queue_offset(info, dsp_queue_addr);
307 dsp_q_addr &= ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M;
308
309 /* Poll until the ADSP is ready to accept a command.
310 * Wait for 100us, return error if it's not responding.
311 * If this returns an error, we need to disable ALL modules and
312 * then retry.
313 */
314 while (((ctrl_word = readl(info->write_ctrl)) &
315 ADSP_RTOS_WRITE_CTRL_WORD_READY_M) !=
316 ADSP_RTOS_WRITE_CTRL_WORD_READY_V) {
317 if (cnt > 50) {
318 MM_ERR("timeout waiting for DSP write ready\n");
319 ret_status = -EIO;
320 goto fail;
321 }
322 MM_DBG("waiting for DSP write ready\n");
323 udelay(2);
324 cnt++;
325 }
326
327 /* Set the mutex bits */
328 ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M);
329 ctrl_word |= ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V;
330
331 /* Clear the command bits */
332 ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_CMD_M);
333
334 /* Set the queue address bits */
335 ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M);
336 ctrl_word |= dsp_q_addr;
337
338 writel(ctrl_word, info->write_ctrl);
339
340 /* Generate an interrupt to the DSP. This notifies the DSP that
341 * we are about to send a command on this particular queue. The
342 * DSP will in response change its state.
343 */
344 writel(1, info->send_irq);
345
346 /* Poll until the adsp responds to the interrupt; this does not
347 * generate an interrupt from the adsp. This should happen within
348 * 5ms.
349 */
350 cnt = 0;
351 while ((readl(info->write_ctrl) &
352 ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M) ==
353 ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V) {
354 if (cnt > 2500) {
355 MM_ERR("timeout waiting for adsp ack\n");
356 ret_status = -EIO;
357 goto fail;
358 }
359 udelay(2);
360 cnt++;
361 }
362
363 /* Read the ctrl word */
364 ctrl_word = readl(info->write_ctrl);
365
366 if ((ctrl_word & ADSP_RTOS_WRITE_CTRL_WORD_STATUS_M) !=
367 ADSP_RTOS_WRITE_CTRL_WORD_NO_ERR_V) {
368 ret_status = -EAGAIN;
369 goto fail;
370 } else {
371 /* No error */
372 /* Get the DSP buffer address */
373 dsp_addr = (ctrl_word & ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M) +
374 (uint32_t)MSM_AD5_BASE;
375
376 if (dsp_addr < (uint32_t)(MSM_AD5_BASE + QDSP_RAMC_OFFSET)) {
377 uint16_t *buf_ptr = (uint16_t *) cmd_buf;
378 uint16_t *dsp_addr16 = (uint16_t *)dsp_addr;
379 cmd_size /= sizeof(uint16_t);
380
381 /* Save the command ID */
382 cmd_id = (uint32_t) buf_ptr[0];
383
384 /* Copy the command to DSP memory */
385 cmd_size++;
386 while (--cmd_size)
387 *dsp_addr16++ = *buf_ptr++;
388 } else {
389 uint32_t *buf_ptr = (uint32_t *) cmd_buf;
390 uint32_t *dsp_addr32 = (uint32_t *)dsp_addr;
391 cmd_size /= sizeof(uint32_t);
392
393 /* Save the command ID */
394 cmd_id = buf_ptr[0];
395
396 cmd_size++;
397 while (--cmd_size)
398 *dsp_addr32++ = *buf_ptr++;
399 }
400
401 /* Set the mutex bits */
402 ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_M);
403 ctrl_word |= ADSP_RTOS_WRITE_CTRL_WORD_MUTEX_NAVAIL_V;
404
405 /* Set the command bits to write done */
406 ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_CMD_M);
407 ctrl_word |= ADSP_RTOS_WRITE_CTRL_WORD_CMD_WRITE_DONE_V;
408
409 /* Set the queue address bits */
410 ctrl_word &= ~(ADSP_RTOS_WRITE_CTRL_WORD_DSP_ADDR_M);
411 ctrl_word |= dsp_q_addr;
412
413 writel(ctrl_word, info->write_ctrl);
414
415 /* Generate an interrupt to the DSP. It does not respond with
416 * an interrupt, and we do not need to wait for it to
417 * acknowledge, because it will hold the mutex lock until it's
418 * ready to receive more commands again.
419 */
420 writel(1, info->send_irq);
421
422 module->num_commands++;
423 } /* Ctrl word status bits were 00, no error in the ctrl word */
424
425fail:
426 spin_unlock_irqrestore(&adsp_write_lock, flags);
427 return ret_status;
428}
429EXPORT_SYMBOL(msm_adsp_write);
430
431int msm_adsp_write(struct msm_adsp_module *module, unsigned dsp_queue_addr,
432 void *cmd_buf, size_t cmd_size)
433{
434 int rc, retries = 0;
435#ifdef CONFIG_DEBUG_FS
436 uint16_t *ptr;
437 int ii;
438
439 if (wdump > 0) {
440 ptr = cmd_buf;
441 pr_info("A->D:%x\n", module->id);
442 pr_info("adsp: %x %d\n", dsp_queue_addr, cmd_size);
443 for (ii = 0; ii < cmd_size/2; ii++)
444 pr_info("%x ", ptr[ii]);
445 pr_info("\n");
446 }
447#endif /* CONFIG_DEBUG_FS */
448 do {
449 rc = __msm_adsp_write(module, dsp_queue_addr, cmd_buf,
450 cmd_size);
451 if (rc == -EAGAIN)
452 udelay(50);
453 } while (rc == -EAGAIN && retries++ < 300);
454 if (retries > 20)
455 MM_INFO("%s command took %d attempts: rc %d\n",
456 module->name, retries, rc);
457 return rc;
458}
459
460#ifdef CONFIG_MSM_ADSP_REPORT_EVENTS
461static void *event_addr;
462static void read_event(void *buf, size_t len)
463{
464 uint32_t dptr[3];
465 struct adsp_rtos_mp_mtoa_s_type *sptr;
466 struct adsp_rtos_mp_mtoa_type *pkt_ptr;
467
468 sptr = event_addr;
469 pkt_ptr = &sptr->adsp_rtos_mp_mtoa_data.mp_mtoa_packet;
470
471 dptr[0] = sptr->mp_mtoa_header.event;
472 dptr[1] = pkt_ptr->module;
473 dptr[2] = pkt_ptr->image;
474
475 if (len > EVENT_LEN)
476 len = EVENT_LEN;
477
478 memcpy(buf, dptr, len);
479}
480#endif
481
482static void adsp_rtos_mtoa_cb(void *context, uint32_t param,
483 void *evt_buf, uint32_t len)
484{
485 struct adsp_rtos_mp_mtoa_s_type *args = NULL;
486 uint32_t event = 0;
487 uint32_t proc_id = 0;
488 uint32_t module_id;
489 uint32_t image;
490 struct msm_adsp_module *module;
491 struct adsp_rtos_mp_mtoa_type *pkt_ptr;
492 struct queue_to_offset_type *qptr;
493 struct queue_to_offset_type *qtbl;
494 struct mod_to_queue_offsets *mqptr;
495 struct mod_to_queue_offsets *mqtbl;
496 uint32_t *mptr;
497 uint32_t *mtbl;
498 uint32_t q_idx;
499 uint32_t num_entries;
500 uint32_t entries_per_image;
501 struct adsp_rtos_mp_mtoa_init_info_type *iptr;
502 struct adsp_rtos_mp_mtoa_init_info_type *sptr;
503 int32_t i_no, e_idx;
504 static uint32_t init_info_completed;
505 static uint32_t init_info_len =
506 sizeof(struct adsp_rtos_mp_mtoa_header_type);
507 static uint32_t next_init_info_byte;
508 static uint32_t expected_byte = 1;
509 uint32_t hdr_len = sizeof(struct adsp_rtos_mp_mtoa_header_type);
510
511 if (len) {
512 args = (struct adsp_rtos_mp_mtoa_s_type *) evt_buf;
513 event = args->mp_mtoa_header.event;
514 proc_id = args->mp_mtoa_header.proc_id;
515 }
516
517 if (!init_info_completed && event == RPC_ADSP_RTOS_INIT_INFO) {
518 memcpy(((char *)adsp_info.raw_event) + init_info_len,
519 (char *)evt_buf + hdr_len + 4,
520 len - ((hdr_len + 4)));
521 init_info_len += (len - (hdr_len + 4));
522 evt_buf += hdr_len;
523 next_init_info_byte = *(uint32_t *) evt_buf;
524 expected_byte += len;
525 if (next_init_info_byte &&
526 (expected_byte != next_init_info_byte)) {
527 MM_ERR("INIT_INFO - expecting next byte to be %d\n"
528 "\tbut ADSPSVC indicated next byte to be %d\n",
529 expected_byte, next_init_info_byte);
530 return;
531 }
532 if (!next_init_info_byte) {
533 args = adsp_info.raw_event;
534 args->mp_mtoa_header.event = event;
535 args->mp_mtoa_header.proc_id = proc_id;
536 init_info_completed = 1;
537 } else
538 return;
539 }
540
541 if (event == RPC_ADSP_RTOS_INIT_INFO) {
542 MM_INFO("INIT_INFO Event\n");
543 sptr = &args->adsp_rtos_mp_mtoa_data.mp_mtoa_init_packet;
544
545 iptr = adsp_info.init_info_ptr;
546 iptr->image_count = sptr->image_count;
547 if (iptr->image_count > IMG_MAX)
548 iptr->image_count = IMG_MAX;
549 iptr->num_queue_offsets = sptr->num_queue_offsets;
550 num_entries = iptr->num_queue_offsets;
551 if (num_entries > ENTRIES_MAX) {
552 num_entries = ENTRIES_MAX;
553 iptr->num_queue_offsets = ENTRIES_MAX;
554 }
555 qptr = &sptr->queue_offsets_tbl[0][0];
556 for (i_no = 0; i_no < iptr->image_count; i_no++) {
557 qtbl = &iptr->queue_offsets_tbl[i_no][0];
558 for (e_idx = 0; e_idx < num_entries; e_idx++) {
559 qtbl[e_idx].offset = qptr->offset;
560 qtbl[e_idx].queue = qptr->queue;
561 q_idx = qptr->queue;
562 iptr->queue_offsets[i_no][q_idx] =
563 qtbl[e_idx].offset;
564 qptr++;
565 }
566 }
567
568 num_entries = sptr->num_task_module_entries;
569 if (num_entries > ENTRIES_MAX)
570 num_entries = ENTRIES_MAX;
571 iptr->num_task_module_entries = num_entries;
572 entries_per_image = num_entries / iptr->image_count;
573 mptr = &sptr->task_to_module_tbl[0][0];
574 for (i_no = 0; i_no < iptr->image_count; i_no++) {
575 mtbl = &iptr->task_to_module_tbl[i_no][0];
576 for (e_idx = 0; e_idx < entries_per_image; e_idx++) {
577 mtbl[e_idx] = *mptr;
578 mptr++;
579 }
580 }
581
582 iptr->module_table_size = sptr->module_table_size;
583 if (iptr->module_table_size > MODULES_MAX)
584 iptr->module_table_size = MODULES_MAX;
585 mptr = &sptr->module_entries[0];
586 for (i_no = 0; i_no < iptr->module_table_size; i_no++)
587 iptr->module_entries[i_no] = mptr[i_no];
588
589 mqptr = &sptr->mod_to_q_tbl[0];
590 mqtbl = &iptr->mod_to_q_tbl[0];
591 iptr->mod_to_q_entries = sptr->mod_to_q_entries;
592 if (iptr->mod_to_q_entries > ENTRIES_MAX)
593 iptr->mod_to_q_entries = ENTRIES_MAX;
594 for (e_idx = 0; e_idx < iptr->mod_to_q_entries; e_idx++) {
595 mqtbl[e_idx].module = mqptr->module;
596 mqtbl[e_idx].q_type = mqptr->q_type;
597 mqtbl[e_idx].q_max_len = mqptr->q_max_len;
598 mqptr++;
599 }
600
601 adsp_info.init_info_state = ADSP_STATE_INIT_INFO;
602 kfree(adsp_info.raw_event);
603 wake_up(&adsp_info.init_info_wait);
604 return;
605 }
606 pkt_ptr = &args->adsp_rtos_mp_mtoa_data.mp_mtoa_packet;
607 module_id = pkt_ptr->module;
608 image = pkt_ptr->image;
609
610 MM_INFO("rpc event=%d, proc_id=%d, module=%d, image=%d\n",
611 event, proc_id, module_id, image);
612
613 module = find_adsp_module_by_id(&adsp_info, module_id);
614 if (!module) {
615 MM_ERR("module %d is not supported!\n", module_id);
616 return;
617 }
618
619 mutex_lock(&module->lock);
620 switch (event) {
621 case RPC_ADSP_RTOS_MOD_READY:
622 MM_INFO("module %s: READY\n", module->name);
623 module->state = ADSP_STATE_ENABLED;
624 wake_up(&module->state_wait);
625 adsp_set_image(module->info, image);
626 break;
627 case RPC_ADSP_RTOS_MOD_DISABLE:
628 MM_INFO("module %s: DISABLED\n", module->name);
629 module->state = ADSP_STATE_DISABLED;
630 wake_up(&module->state_wait);
631 break;
632 case RPC_ADSP_RTOS_SERVICE_RESET:
633 MM_INFO("module %s: SERVICE_RESET\n", module->name);
634 module->state = ADSP_STATE_DISABLED;
635 wake_up(&module->state_wait);
636 break;
637 case RPC_ADSP_RTOS_CMD_SUCCESS:
638 MM_INFO("module %s: CMD_SUCCESS\n", module->name);
639 break;
640 case RPC_ADSP_RTOS_CMD_FAIL:
641 MM_INFO("module %s: CMD_FAIL\n", module->name);
642 break;
643 case RPC_ADSP_RTOS_DISABLE_FAIL:
644 MM_INFO("module %s: DISABLE_FAIL\n", module->name);
645 break;
646 default:
647 MM_ERR("unknown event %d\n", event);
648 mutex_unlock(&module->lock);
649 return;
650 }
651#ifdef CONFIG_MSM_ADSP_REPORT_EVENTS
652 event_addr = (uint32_t *)evt_buf;
653 if (module->ops)
654 module->ops->event(module->driver_data,
655 EVENT_MSG_ID,
656 EVENT_LEN,
657 read_event);
658#endif
659 mutex_unlock(&module->lock);
660}
661
662static size_t read_event_size;
663static void *read_event_addr;
664
665static void read_event_16(void *buf, size_t len)
666{
667 uint16_t *dst = buf;
668 uint16_t *src = read_event_addr;
669 len /= 2;
670 if (len > read_event_size)
671 len = read_event_size;
672 while (len--)
673 *dst++ = *src++;
674}
675
676static void read_event_32(void *buf, size_t len)
677{
678 uint32_t *dst = buf;
679 uint32_t *src = read_event_addr;
680 len /= 2;
681 if (len > read_event_size)
682 len = read_event_size;
683 while (len--)
684 *dst++ = *src++;
685}
686
687static int adsp_rtos_read_ctrl_word_cmd_tast_to_h_v(
688 struct adsp_info *info, void *dsp_addr)
689{
690 struct msm_adsp_module *module;
691 unsigned rtos_task_id;
692 unsigned msg_id;
693 unsigned msg_length;
694#ifdef CONFIG_DEBUG_FS
695 uint16_t *ptr;
696 int ii;
697#endif /* CONFIG_DEBUG_FS */
698 void (*func)(void *, size_t);
699
700 if (dsp_addr >= (void *)(MSM_AD5_BASE + QDSP_RAMC_OFFSET)) {
701 uint32_t *dsp_addr32 = dsp_addr;
702 uint32_t tmp = *dsp_addr32++;
703 rtos_task_id = (tmp & ADSP_RTOS_READ_CTRL_WORD_TASK_ID_M) >> 8;
704 msg_id = (tmp & ADSP_RTOS_READ_CTRL_WORD_MSG_ID_M);
705 read_event_size = tmp >> 16;
706 read_event_addr = dsp_addr32;
707 msg_length = read_event_size * sizeof(uint32_t);
708 func = read_event_32;
709 } else {
710 uint16_t *dsp_addr16 = dsp_addr;
711 uint16_t tmp = *dsp_addr16++;
712 rtos_task_id = (tmp & ADSP_RTOS_READ_CTRL_WORD_TASK_ID_M) >> 8;
713 msg_id = tmp & ADSP_RTOS_READ_CTRL_WORD_MSG_ID_M;
714 read_event_size = *dsp_addr16++;
715 read_event_addr = dsp_addr16;
716 msg_length = read_event_size * sizeof(uint16_t);
717 func = read_event_16;
718 }
719
720 if (rtos_task_id > info->max_task_id) {
721 MM_ERR("bogus task id %d\n", rtos_task_id);
722 return 0;
723 }
724 module = find_adsp_module_by_id(info,
725 adsp_get_module(info, rtos_task_id));
726
727 if (!module) {
728 MM_ERR("no module for task id %d\n", rtos_task_id);
729 return 0;
730 }
731
732 module->num_events++;
733
734 if (!module->ops) {
735 MM_ERR("module %s is not open\n", module->name);
736 return 0;
737 }
738#ifdef CONFIG_DEBUG_FS
739 if (rdump > 0) {
740 ptr = read_event_addr;
741 pr_info("D->A\n");
742 pr_info("m_id = %x id = %x\n", module->id, msg_id);
743 for (ii = 0; ii < msg_length/2; ii++)
744 pr_info("%x ", ptr[ii]);
745 pr_info("\n");
746 }
747#endif /* CONFIG_DEBUG_FS */
748
749 module->ops->event(module->driver_data, msg_id, msg_length, func);
750 return 0;
751}
752
753static int adsp_get_event(struct adsp_info *info)
754{
755 uint32_t ctrl_word;
756 uint32_t ready;
757 void *dsp_addr;
758 uint32_t cmd_type;
759 int cnt;
760 unsigned long flags;
761 int rc = 0;
762
763 spin_lock_irqsave(&adsp_cmd_lock, flags);
764
765 /* Whenever the DSP has a message, it updates this control word
766 * and generates an interrupt. When we receive the interrupt, we
767 * read this register to find out what ADSP task the command is
768 * comming from.
769 *
770 * The ADSP should *always* be ready on the first call, but the
771 * irq handler calls us in a loop (to handle back-to-back command
772 * processing), so we give the DSP some time to return to the
773 * ready state. The DSP will not issue another IRQ for events
774 * pending between the first IRQ and the event queue being drained,
775 * unfortunately.
776 */
777
778 for (cnt = 0; cnt < 50; cnt++) {
779 ctrl_word = readl(info->read_ctrl);
780
781 if ((ctrl_word & ADSP_RTOS_READ_CTRL_WORD_FLAG_M) ==
782 ADSP_RTOS_READ_CTRL_WORD_FLAG_UP_CONT_V)
783 goto ready;
784
785 udelay(2);
786 }
787 MM_ERR("not ready after 100uS\n");
788 rc = -EBUSY;
789 goto done;
790
791ready:
792 /* Here we check to see if there are pending messages. If there are
793 * none, we siply return -EAGAIN to indicate that there are no more
794 * messages pending.
795 */
796 ready = ctrl_word & ADSP_RTOS_READ_CTRL_WORD_READY_M;
797 if ((ready != ADSP_RTOS_READ_CTRL_WORD_READY_V) &&
798 (ready != ADSP_RTOS_READ_CTRL_WORD_CONT_V)) {
799 rc = -EAGAIN;
800 goto done;
801 }
802
803 /* DSP says that there are messages waiting for the host to read */
804
805 /* Get the Command Type */
806 cmd_type = ctrl_word & ADSP_RTOS_READ_CTRL_WORD_CMD_TYPE_M;
807
808 /* Get the DSP buffer address */
809 dsp_addr = (void *)((ctrl_word &
810 ADSP_RTOS_READ_CTRL_WORD_DSP_ADDR_M) +
811 (uint32_t)MSM_AD5_BASE);
812
813 /* We can only handle Task-to-Host messages */
814 if (cmd_type != ADSP_RTOS_READ_CTRL_WORD_CMD_TASK_TO_H_V) {
815 MM_ERR("unknown dsp cmd_type %d\n", cmd_type);
816 rc = -EIO;
817 goto done;
818 }
819
820 adsp_rtos_read_ctrl_word_cmd_tast_to_h_v(info, dsp_addr);
821
822 ctrl_word = readl(info->read_ctrl);
823 ctrl_word &= ~ADSP_RTOS_READ_CTRL_WORD_READY_M;
824
825 /* Write ctrl word to the DSP */
826 writel(ctrl_word, info->read_ctrl);
827
828 /* Generate an interrupt to the DSP */
829 writel(1, info->send_irq);
830
831done:
832 spin_unlock_irqrestore(&adsp_cmd_lock, flags);
833 return rc;
834}
835
836static irqreturn_t adsp_irq_handler(int irq, void *data)
837{
838 struct adsp_info *info = &adsp_info;
839 int cnt = 0;
840 for (cnt = 0; cnt < 15; cnt++)
841 if (adsp_get_event(info) < 0)
842 break;
843 if (cnt > info->event_backlog_max)
844 info->event_backlog_max = cnt;
845 info->events_received += cnt;
846 if (cnt == 15)
847 MM_ERR("too many (%d) events for single irq!\n", cnt);
848 return IRQ_HANDLED;
849}
850
851int adsp_set_clkrate(struct msm_adsp_module *module, unsigned long clk_rate)
852{
853 if (module->clk && clk_rate)
854 return clk_set_min_rate(module->clk, clk_rate);
855
856 return -EINVAL;
857}
858
859int msm_adsp_enable(struct msm_adsp_module *module)
860{
861 int rc = 0;
862
863 MM_INFO("enable '%s'state[%d] id[%d]\n",
864 module->name, module->state, module->id);
865
866 mutex_lock(&module->lock);
867 switch (module->state) {
868 case ADSP_STATE_DISABLED:
869 module->state = ADSP_STATE_ENABLING;
870 mutex_unlock(&module->lock);
871 rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_ENABLE,
872 module->id, module);
873 if (rc) {
874 mutex_lock(&module->lock);
875 module->state = ADSP_STATE_DISABLED;
876 break;
877 }
878 rc = wait_event_timeout(module->state_wait,
879 module->state != ADSP_STATE_ENABLING,
880 1 * HZ);
881 mutex_lock(&module->lock);
882 if (module->state == ADSP_STATE_ENABLED) {
883 rc = 0;
884 } else {
885 MM_ERR("module '%s' enable timed out\n", module->name);
886 rc = -ETIMEDOUT;
887 }
888 if (module->open_count++ == 0 && module->clk)
889 clk_enable(module->clk);
890
891 mutex_lock(&adsp_open_lock);
892 if (adsp_open_count++ == 0)
893 enable_irq(INT_ADSP);
894 mutex_unlock(&adsp_open_lock);
895 break;
896 case ADSP_STATE_ENABLING:
897 MM_DBG("module '%s' enable in progress\n", module->name);
898 break;
899 case ADSP_STATE_ENABLED:
900 MM_DBG("module '%s' already enabled\n", module->name);
901 break;
902 case ADSP_STATE_DISABLING:
903 MM_ERR("module '%s' disable in progress\n", module->name);
904 rc = -EBUSY;
905 break;
906 }
907 mutex_unlock(&module->lock);
908 return rc;
909}
910EXPORT_SYMBOL(msm_adsp_enable);
911
912int msm_adsp_disable_event_rsp(struct msm_adsp_module *module)
913{
914 int rc = 0;
915
916 mutex_lock(&module->lock);
917
918 rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_DISABLE_EVENT_RSP,
919 module->id, module);
920 mutex_unlock(&module->lock);
921
922 return rc;
923}
924EXPORT_SYMBOL(msm_adsp_disable_event_rsp);
925
926int msm_adsp_disable(struct msm_adsp_module *module)
927{
928 int rc = 0;
929
930 mutex_lock(&module->lock);
931 switch (module->state) {
932 case ADSP_STATE_DISABLED:
933 MM_DBG("module '%s' already disabled\n", module->name);
934 mutex_unlock(&module->lock);
935 break;
936 case ADSP_STATE_ENABLING:
937 case ADSP_STATE_ENABLED:
938 mutex_unlock(&module->lock);
939 rc = rpc_adsp_rtos_app_to_modem(RPC_ADSP_RTOS_CMD_DISABLE,
940 module->id, module);
941 mutex_lock(&module->lock);
942 module->state = ADSP_STATE_DISABLED;
943 if (--module->open_count == 0 && module->clk)
944 clk_disable(module->clk);
945 mutex_unlock(&module->lock);
946 mutex_lock(&adsp_open_lock);
947 if (--adsp_open_count == 0) {
948 disable_irq(INT_ADSP);
949 MM_INFO("disable interrupt\n");
950 }
951 mutex_unlock(&adsp_open_lock);
952 break;
953 }
954 return rc;
955}
956EXPORT_SYMBOL(msm_adsp_disable);
957
958static int msm_adsp_probe(struct platform_device *pdev)
959{
960 unsigned count;
961 int rc, i;
962
963 adsp_info.init_info_ptr = kzalloc(
964 (sizeof(struct adsp_rtos_mp_mtoa_init_info_type)), GFP_KERNEL);
965 if (!adsp_info.init_info_ptr)
966 return -ENOMEM;
967
968 adsp_info.raw_event = kzalloc(
969 (sizeof(struct adsp_rtos_mp_mtoa_s_type)), GFP_KERNEL);
970 if (!adsp_info.raw_event) {
971 kfree(adsp_info.init_info_ptr);
972 return -ENOMEM;
973 }
974
975 rc = adsp_init_info(&adsp_info);
976 if (rc) {
977 kfree(adsp_info.init_info_ptr);
978 kfree(adsp_info.raw_event);
979 return rc;
980 }
981 adsp_info.send_irq += (uint32_t) MSM_AD5_BASE;
982 adsp_info.read_ctrl += (uint32_t) MSM_AD5_BASE;
983 adsp_info.write_ctrl += (uint32_t) MSM_AD5_BASE;
984 count = adsp_info.module_count;
985
986 adsp_modules = kzalloc(
987 (sizeof(struct msm_adsp_module) + sizeof(void *)) *
988 count, GFP_KERNEL);
989 if (!adsp_modules) {
990 kfree(adsp_info.init_info_ptr);
991 kfree(adsp_info.raw_event);
992 return -ENOMEM;
993 }
994
995 adsp_info.id_to_module = (void *) (adsp_modules + count);
996
997 spin_lock_init(&adsp_cmd_lock);
998 spin_lock_init(&adsp_write_lock);
999
1000 rc = request_irq(INT_ADSP, adsp_irq_handler,
1001 IRQF_TRIGGER_RISING, "adsp", 0);
1002 if (rc < 0)
1003 goto fail_request_irq;
1004 disable_irq(INT_ADSP);
1005
1006 for (i = 0; i < count; i++) {
1007 struct msm_adsp_module *mod = adsp_modules + i;
1008 mutex_init(&mod->lock);
1009 init_waitqueue_head(&mod->state_wait);
1010 mod->info = &adsp_info;
1011 mod->name = adsp_info.module[i].name;
1012 mod->id = adsp_info.module[i].id;
1013 if (adsp_info.module[i].clk_name)
1014 mod->clk = clk_get(NULL, adsp_info.module[i].clk_name);
1015 else
1016 mod->clk = NULL;
1017 if (mod->clk && adsp_info.module[i].clk_rate)
1018 clk_set_min_rate(mod->clk,
1019 adsp_info.module[i].clk_rate);
1020 mod->verify_cmd = adsp_info.module[i].verify_cmd;
1021 mod->patch_event = adsp_info.module[i].patch_event;
1022 INIT_HLIST_HEAD(&mod->pmem_regions);
1023 mod->pdev.name = adsp_info.module[i].pdev_name;
1024 mod->pdev.id = -1;
1025 adsp_info.id_to_module[i] = mod;
1026 platform_device_register(&mod->pdev);
1027 }
1028
1029 msm_adsp_publish_cdevs(adsp_modules, count);
1030
1031 rc = daldevice_attach(DALRPC_ADSPSVC_DEVICEID, DALRPC_ADSPSVC_PORT,
1032 DALRPC_ADSPSVC_DEST, &adsp_info.handle);
1033 if (rc) {
1034 MM_ERR("adsp attach failed : %d\n", rc);
1035 goto fail_dal_attach;
1036 }
1037
1038 adsp_info.cb_handle = dalrpc_alloc_cb(adsp_info.handle,
1039 adsp_rtos_mtoa_cb, NULL);
1040 if (adsp_info.cb_handle == NULL) {
1041 MM_ERR("Callback registration failed\n");
1042 goto fail_allocate_cb;
1043 }
1044
1045 /* Get INIT_INFO */
1046 init_waitqueue_head(&adsp_info.init_info_wait);
1047 msm_get_init_info();
1048 rc = wait_event_timeout(adsp_info.init_info_wait,
1049 adsp_info.init_info_state == ADSP_STATE_INIT_INFO,
1050 10 * HZ);
1051 if (!rc) {
1052 MM_ERR("INIT_INFO failed\n");
1053 rc = -ETIMEDOUT;
1054 } else
1055 return 0;
1056
1057fail_allocate_cb:
1058 daldevice_detach(adsp_info.handle);
1059 adsp_info.handle = NULL;
1060fail_dal_attach:
1061 enable_irq(INT_ADSP);
1062 free_irq(INT_ADSP, 0);
1063fail_request_irq:
1064 kfree(adsp_modules);
1065 kfree(adsp_info.init_info_ptr);
1066 kfree(adsp_info.raw_event);
1067 return rc;
1068}
1069
1070#ifdef CONFIG_DEBUG_FS
1071static int get_parameters(char *buf, long int *param1, int num_of_par)
1072{
1073 char *token;
1074 int base, cnt;
1075
1076 token = strsep(&buf, " ");
1077
1078 for (cnt = 0; cnt < num_of_par; cnt++) {
1079 if (token != NULL) {
1080 if ((token[1] == 'x') || (token[1] == 'X'))
1081 base = 16;
1082 else
1083 base = 10;
1084
1085 if (strict_strtoul(token, base, &param1[cnt]) != 0)
1086 return -EINVAL;
1087
1088 token = strsep(&buf, " ");
1089 }
1090 else
1091 return -EINVAL;
1092 }
1093 return 0;
1094}
1095
1096static ssize_t adsp_debug_open(struct inode *inode, struct file *file)
1097{
1098 file->private_data = inode->i_private;
1099 pr_debug("adsp debugfs opened\n");
1100 return 0;
1101}
1102static ssize_t adsp_debug_write(struct file *file, const char __user *buf,
1103 size_t cnt, loff_t *ppos)
1104{
1105 char *access_str = file->private_data;
1106 char lbuf[32];
1107 int rc;
1108 long int param[5];
1109
1110 if (cnt > sizeof(lbuf) - 1)
1111 return -EINVAL;
1112 rc = copy_from_user(lbuf, buf, cnt);
1113 if (rc) {
1114 pr_info("Unable to copy data from user space\n");
1115 return -EFAULT;
1116 }
1117 lbuf[cnt] = '\0';
1118
1119 if (!strncmp(access_str, "write_log", 9)) {
1120 if (get_parameters(lbuf, param, 1) == 0) {
1121 switch (param[0]) {
1122 case 1:
1123 if (wdump <= 0)
1124 wdump = 1;
1125 pr_debug("write cmd to DSP(A->D) dump \
1126 started:%d\n", wdump);
1127 break;
1128 case 0:
1129 if (wdump > 0)
1130 wdump = 0;
1131 pr_debug("Stop write cmd to \
1132 DSP(A->D):%d\n", wdump);
1133 break;
1134 default:
1135 rc = -EINVAL;
1136 break;
1137 }
1138 } else
1139 rc = -EINVAL;
1140 } else if (!strncmp(access_str, "read_log", 8)) {
1141 if (get_parameters(lbuf, param, 1) == 0) {
1142 switch (param[0]) {
1143 case 1:
1144 if (rdump <= 0)
1145 rdump = 1;
1146 pr_debug("write cmd from DSP(D->A) dump \
1147 started:%d\n", wdump);
1148 break;
1149 case 0:
1150 if (rdump > 0)
1151 rdump = 0;
1152 pr_debug("Stop write cmd from \
1153 DSP(D->A):%d\n", wdump);
1154 break;
1155 default:
1156 rc = -EINVAL;
1157 break;
1158 }
1159 } else
1160 rc = -EINVAL;
1161 } else {
1162 rc = -EINVAL;
1163 }
1164 if (rc == 0)
1165 rc = cnt;
1166 else {
1167 pr_err("%s: rc = %d\n", __func__, rc);
1168 pr_info("\nWrong command: Use =>\n");
1169 pr_info("-------------------------\n");
1170 pr_info("To Start A->D:: echo \"1\">/sys/kernel/debug/ \
1171 adsp_cmd/write_log\n");
1172 pr_info("To Start D->A:: echo \"1\">/sys/kernel/debug/ \
1173 adsp_cmd/read_log\n");
1174 pr_info("To Stop A->D:: echo \"0\">/sys/kernel/debug/ \
1175 adsp_cmd/write_log\n");
1176 pr_info("To Stop D->A:: echo \"0\">/sys/kernel/debug/ \
1177 adsp_cmd/read_log\n");
1178 pr_info("------------------------\n");
1179 }
1180
1181 return rc;
1182}
1183#endif
1184
1185static struct platform_driver msm_adsp_driver = {
1186 .probe = msm_adsp_probe,
1187 .driver = {
1188 .owner = THIS_MODULE,
1189 },
1190};
1191
1192struct platform_device msm_adsp_device = {
1193 .name = "msm_adsp",
1194 .id = -1,
1195};
1196
1197static char msm_adsp_driver_name[] = "msm_adsp";
1198
1199#ifdef CONFIG_DEBUG_FS
1200static const struct file_operations adsp_debug_fops = {
1201 .write = adsp_debug_write,
1202 .open = adsp_debug_open,
1203};
1204#endif
1205
1206static int __init adsp_init(void)
1207{
1208 int rc;
1209
1210#ifdef CONFIG_DEBUG_FS
1211 dentry_adsp = debugfs_create_dir("adsp_cmd", 0);
1212 if (!IS_ERR(dentry_adsp)) {
1213 dentry_wdata = debugfs_create_file("write_log", \
1214 S_IFREG | S_IRUGO, dentry_adsp,
1215 (void *) "write_log" , &adsp_debug_fops);
1216 dentry_rdata = debugfs_create_file("read_log", \
1217 S_IFREG | S_IRUGO, dentry_adsp,
1218 (void *) "read_log", &adsp_debug_fops);
1219 }
1220#endif /* CONFIG_DEBUG_FS */
1221
1222 msm_adsp_driver.driver.name = msm_adsp_driver_name;
1223 rc = platform_device_register(&msm_adsp_device);
1224 rc = platform_driver_register(&msm_adsp_driver);
1225 MM_INFO("%s -- %d\n", msm_adsp_driver_name, rc);
1226 return rc;
1227}
1228
1229device_initcall(adsp_init);