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gerrit-public.fairphone.software / kernel / msm / e096c8e6d5ed965f346d94befbbec2275dde3621 / . / arch / arm / mach-u300 / core.c
blob: 5f34eb674d68ec4ebbc3a763d01b97e10285b844 [file] [log] [blame]
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1/*
2 *
3 * arch/arm/mach-u300/core.c
4 *
5 *
Linus Walleij633e81a2010-01-25 07:18:16 +0100[diff] [blame]6 * Copyright (C) 2007-2010 ST-Ericsson AB
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
19#include <linux/amba/bus.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]22#include <mach/coh901318.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]23
24#include <asm/types.h>
25#include <asm/setup.h>
26#include <asm/memory.h>
27#include <asm/hardware/vic.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30
31#include <mach/hardware.h>
32#include <mach/syscon.h>
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]33#include <mach/dma_channels.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]34
35#include "clock.h"
36#include "mmc.h"
Linus Walleijc7c8c782009-08-14 10:59:05 +0100[diff] [blame]37#include "spi.h"
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]38#include "i2c.h"
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]39
40/*
41 * Static I/O mappings that are needed for booting the U300 platforms. The
42 * only things we need are the areas where we find the timer, syscon and
43 * intcon, since the remaining device drivers will map their own memory
44 * physical to virtual as the need arise.
45 */
46static struct map_desc u300_io_desc[] __initdata = {
47 {
48 .virtual = U300_SLOW_PER_VIRT_BASE,
49 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
50 .length = SZ_64K,
51 .type = MT_DEVICE,
52 },
53 {
54 .virtual = U300_AHB_PER_VIRT_BASE,
55 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
56 .length = SZ_32K,
57 .type = MT_DEVICE,
58 },
59 {
60 .virtual = U300_FAST_PER_VIRT_BASE,
61 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
62 .length = SZ_32K,
63 .type = MT_DEVICE,
64 },
65 {
66 .virtual = 0xffff2000, /* TCM memory */
67 .pfn = __phys_to_pfn(0xffff2000),
68 .length = SZ_16K,
69 .type = MT_DEVICE,
70 },
71
72 /*
73 * This overlaps with the IRQ vectors etc at 0xffff0000, so these
74 * may have to be moved to 0x00000000 in order to use the ROM.
75 */
76 /*
77 {
78 .virtual = U300_BOOTROM_VIRT_BASE,
79 .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
80 .length = SZ_64K,
81 .type = MT_ROM,
82 },
83 */
84};
85
86void __init u300_map_io(void)
87{
88 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
89}
90
91/*
92 * Declaration of devices found on the U300 board and
93 * their respective memory locations.
94 */
95static struct amba_device uart0_device = {
96 .dev = {
97 .init_name = "uart0", /* Slow device at 0x3000 offset */
98 .platform_data = NULL,
99 },
100 .res = {
101 .start = U300_UART0_BASE,
102 .end = U300_UART0_BASE + SZ_4K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 .irq = { IRQ_U300_UART0, NO_IRQ },
106};
107
108/* The U335 have an additional UART1 on the APP CPU */
109#ifdef CONFIG_MACH_U300_BS335
110static struct amba_device uart1_device = {
111 .dev = {
112 .init_name = "uart1", /* Fast device at 0x7000 offset */
113 .platform_data = NULL,
114 },
115 .res = {
116 .start = U300_UART1_BASE,
117 .end = U300_UART1_BASE + SZ_4K - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 .irq = { IRQ_U300_UART1, NO_IRQ },
121};
122#endif
123
124static struct amba_device pl172_device = {
125 .dev = {
126 .init_name = "pl172", /* AHB device at 0x4000 offset */
127 .platform_data = NULL,
128 },
129 .res = {
130 .start = U300_EMIF_CFG_BASE,
131 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
132 .flags = IORESOURCE_MEM,
133 },
134};
135
136
137/*
138 * Everything within this next ifdef deals with external devices connected to
139 * the APP SPI bus.
140 */
141static struct amba_device pl022_device = {
142 .dev = {
143 .coherent_dma_mask = ~0,
144 .init_name = "pl022", /* Fast device at 0x6000 offset */
145 },
146 .res = {
147 .start = U300_SPI_BASE,
148 .end = U300_SPI_BASE + SZ_4K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 .irq = {IRQ_U300_SPI, NO_IRQ },
152 /*
153 * This device has a DMA channel but the Linux driver does not use
154 * it currently.
155 */
156};
157
158static struct amba_device mmcsd_device = {
159 .dev = {
160 .init_name = "mmci", /* Fast device at 0x1000 offset */
161 .platform_data = NULL, /* Added later */
162 },
163 .res = {
164 .start = U300_MMCSD_BASE,
165 .end = U300_MMCSD_BASE + SZ_4K - 1,
166 .flags = IORESOURCE_MEM,
167 },
168 .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
169 /*
170 * This device has a DMA channel but the Linux driver does not use
171 * it currently.
172 */
173};
174
175/*
176 * The order of device declaration may be important, since some devices
177 * have dependencies on other devices being initialized first.
178 */
179static struct amba_device *amba_devs[] __initdata = {
180 &uart0_device,
181#ifdef CONFIG_MACH_U300_BS335
182 &uart1_device,
183#endif
184 &pl022_device,
185 &pl172_device,
186 &mmcsd_device,
187};
188
189/* Here follows a list of all hw resources that the platform devices
190 * allocate. Note, clock dependencies are not included
191 */
192
193static struct resource gpio_resources[] = {
194 {
195 .start = U300_GPIO_BASE,
196 .end = (U300_GPIO_BASE + SZ_4K - 1),
197 .flags = IORESOURCE_MEM,
198 },
199 {
200 .name = "gpio0",
201 .start = IRQ_U300_GPIO_PORT0,
202 .end = IRQ_U300_GPIO_PORT0,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .name = "gpio1",
207 .start = IRQ_U300_GPIO_PORT1,
208 .end = IRQ_U300_GPIO_PORT1,
209 .flags = IORESOURCE_IRQ,
210 },
211 {
212 .name = "gpio2",
213 .start = IRQ_U300_GPIO_PORT2,
214 .end = IRQ_U300_GPIO_PORT2,
215 .flags = IORESOURCE_IRQ,
216 },
217#ifdef U300_COH901571_3
218 {
219 .name = "gpio3",
220 .start = IRQ_U300_GPIO_PORT3,
221 .end = IRQ_U300_GPIO_PORT3,
222 .flags = IORESOURCE_IRQ,
223 },
224 {
225 .name = "gpio4",
226 .start = IRQ_U300_GPIO_PORT4,
227 .end = IRQ_U300_GPIO_PORT4,
228 .flags = IORESOURCE_IRQ,
229 },
230#ifdef CONFIG_MACH_U300_BS335
231 {
232 .name = "gpio5",
233 .start = IRQ_U300_GPIO_PORT5,
234 .end = IRQ_U300_GPIO_PORT5,
235 .flags = IORESOURCE_IRQ,
236 },
237 {
238 .name = "gpio6",
239 .start = IRQ_U300_GPIO_PORT6,
240 .end = IRQ_U300_GPIO_PORT6,
241 .flags = IORESOURCE_IRQ,
242 },
243#endif /* CONFIG_MACH_U300_BS335 */
244#endif /* U300_COH901571_3 */
245};
246
247static struct resource keypad_resources[] = {
248 {
249 .start = U300_KEYPAD_BASE,
250 .end = U300_KEYPAD_BASE + SZ_4K - 1,
251 .flags = IORESOURCE_MEM,
252 },
253 {
254 .name = "coh901461-press",
255 .start = IRQ_U300_KEYPAD_KEYBF,
256 .end = IRQ_U300_KEYPAD_KEYBF,
257 .flags = IORESOURCE_IRQ,
258 },
259 {
260 .name = "coh901461-release",
261 .start = IRQ_U300_KEYPAD_KEYBR,
262 .end = IRQ_U300_KEYPAD_KEYBR,
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267static struct resource rtc_resources[] = {
268 {
269 .start = U300_RTC_BASE,
270 .end = U300_RTC_BASE + SZ_4K - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 {
274 .start = IRQ_U300_RTC,
275 .end = IRQ_U300_RTC,
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280/*
281 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
282 * but these are not yet used by the driver.
283 */
284static struct resource fsmc_resources[] = {
285 {
286 .start = U300_NAND_IF_PHYS_BASE,
287 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
288 .flags = IORESOURCE_MEM,
289 },
290};
291
292static struct resource i2c0_resources[] = {
293 {
294 .start = U300_I2C0_BASE,
295 .end = U300_I2C0_BASE + SZ_4K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .start = IRQ_U300_I2C0,
300 .end = IRQ_U300_I2C0,
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct resource i2c1_resources[] = {
306 {
307 .start = U300_I2C1_BASE,
308 .end = U300_I2C1_BASE + SZ_4K - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 {
312 .start = IRQ_U300_I2C1,
313 .end = IRQ_U300_I2C1,
314 .flags = IORESOURCE_IRQ,
315 },
316
317};
318
319static struct resource wdog_resources[] = {
320 {
321 .start = U300_WDOG_BASE,
322 .end = U300_WDOG_BASE + SZ_4K - 1,
323 .flags = IORESOURCE_MEM,
324 },
325 {
326 .start = IRQ_U300_WDOG,
327 .end = IRQ_U300_WDOG,
328 .flags = IORESOURCE_IRQ,
329 }
330};
331
332/* TODO: These should be protected by suitable #ifdef's */
333static struct resource ave_resources[] = {
334 {
335 .name = "AVE3e I/O Area",
336 .start = U300_VIDEOENC_BASE,
337 .end = U300_VIDEOENC_BASE + SZ_512K - 1,
338 .flags = IORESOURCE_MEM,
339 },
340 {
341 .name = "AVE3e IRQ0",
342 .start = IRQ_U300_VIDEO_ENC_0,
343 .end = IRQ_U300_VIDEO_ENC_0,
344 .flags = IORESOURCE_IRQ,
345 },
346 {
347 .name = "AVE3e IRQ1",
348 .start = IRQ_U300_VIDEO_ENC_1,
349 .end = IRQ_U300_VIDEO_ENC_1,
350 .flags = IORESOURCE_IRQ,
351 },
352 {
353 .name = "AVE3e Physmem Area",
354 .start = 0, /* 0 will be remapped to reserved memory */
355 .end = SZ_1M - 1,
356 .flags = IORESOURCE_MEM,
357 },
358 /*
359 * The AVE3e requires two regions of 256MB that it considers
360 * "invisible". The hardware will not be able to access these
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800[diff] [blame]361 * addresses, so they should never point to system RAM.
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]362 */
363 {
364 .name = "AVE3e Reserved 0",
365 .start = 0xd0000000,
366 .end = 0xd0000000 + SZ_256M - 1,
367 .flags = IORESOURCE_MEM,
368 },
369 {
370 .name = "AVE3e Reserved 1",
371 .start = 0xe0000000,
372 .end = 0xe0000000 + SZ_256M - 1,
373 .flags = IORESOURCE_MEM,
374 },
375};
376
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]377static struct resource dma_resource[] = {
378 {
379 .start = U300_DMAC_BASE,
380 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
381 .flags = IORESOURCE_MEM,
382 },
383 {
384 .start = IRQ_U300_DMA,
385 .end = IRQ_U300_DMA,
386 .flags = IORESOURCE_IRQ,
387 }
388};
389
390#ifdef CONFIG_MACH_U300_BS335
391/* points out all dma slave channels.
392 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
393 * Select all channels from A to B, end of list is marked with -1,-1
394 */
395static int dma_slave_channels[] = {
396 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
397 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
398
399/* points out all dma memcpy channels. */
400static int dma_memcpy_channels[] = {
401 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
402
403#else /* CONFIG_MACH_U300_BS335 */
404
405static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
406static int dma_memcpy_channels[] = {
407 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
408
409#endif
410
411/** register dma for memory access
412 *
413 * active 1 means dma intends to access memory
414 * 0 means dma wont access memory
415 */
416static void coh901318_access_memory_state(struct device *dev, bool active)
417{
418}
419
420#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
421 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
422 COH901318_CX_CFG_LCR_DISABLE | \
423 COH901318_CX_CFG_TC_IRQ_ENABLE | \
424 COH901318_CX_CFG_BE_IRQ_ENABLE)
425#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
426 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
427 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
428 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
429 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
430 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
431 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
432 COH901318_CX_CTRL_TCP_DISABLE | \
433 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
434 COH901318_CX_CTRL_HSP_DISABLE | \
435 COH901318_CX_CTRL_HSS_DISABLE | \
436 COH901318_CX_CTRL_DDMA_LEGACY | \
437 COH901318_CX_CTRL_PRDD_SOURCE)
438#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
439 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
440 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
441 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
442 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
443 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
444 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
445 COH901318_CX_CTRL_TCP_DISABLE | \
446 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
447 COH901318_CX_CTRL_HSP_DISABLE | \
448 COH901318_CX_CTRL_HSS_DISABLE | \
449 COH901318_CX_CTRL_DDMA_LEGACY | \
450 COH901318_CX_CTRL_PRDD_SOURCE)
451#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
452 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
453 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
454 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
455 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
456 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
457 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
458 COH901318_CX_CTRL_TCP_DISABLE | \
459 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
460 COH901318_CX_CTRL_HSP_DISABLE | \
461 COH901318_CX_CTRL_HSS_DISABLE | \
462 COH901318_CX_CTRL_DDMA_LEGACY | \
463 COH901318_CX_CTRL_PRDD_SOURCE)
464
465const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
466 {
467 .number = U300_DMA_MSL_TX_0,
468 .name = "MSL TX 0",
469 .priority_high = 0,
470 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
471 },
472 {
473 .number = U300_DMA_MSL_TX_1,
474 .name = "MSL TX 1",
475 .priority_high = 0,
476 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
477 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]478 COH901318_CX_CFG_LCR_DISABLE |
479 COH901318_CX_CFG_TC_IRQ_ENABLE |
480 COH901318_CX_CFG_BE_IRQ_ENABLE,
481 .param.ctrl_lli_chained = 0 |
482 COH901318_CX_CTRL_TC_ENABLE |
483 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
484 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
485 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
486 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
487 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
488 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
489 COH901318_CX_CTRL_TCP_DISABLE |
490 COH901318_CX_CTRL_TC_IRQ_DISABLE |
491 COH901318_CX_CTRL_HSP_ENABLE |
492 COH901318_CX_CTRL_HSS_DISABLE |
493 COH901318_CX_CTRL_DDMA_LEGACY |
494 COH901318_CX_CTRL_PRDD_SOURCE,
495 .param.ctrl_lli = 0 |
496 COH901318_CX_CTRL_TC_ENABLE |
497 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
498 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
499 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
500 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
501 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
502 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
503 COH901318_CX_CTRL_TCP_ENABLE |
504 COH901318_CX_CTRL_TC_IRQ_DISABLE |
505 COH901318_CX_CTRL_HSP_ENABLE |
506 COH901318_CX_CTRL_HSS_DISABLE |
507 COH901318_CX_CTRL_DDMA_LEGACY |
508 COH901318_CX_CTRL_PRDD_SOURCE,
509 .param.ctrl_lli_last = 0 |
510 COH901318_CX_CTRL_TC_ENABLE |
511 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
512 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
513 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
514 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
515 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
516 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
517 COH901318_CX_CTRL_TCP_ENABLE |
518 COH901318_CX_CTRL_TC_IRQ_ENABLE |
519 COH901318_CX_CTRL_HSP_ENABLE |
520 COH901318_CX_CTRL_HSS_DISABLE |
521 COH901318_CX_CTRL_DDMA_LEGACY |
522 COH901318_CX_CTRL_PRDD_SOURCE,
523 },
524 {
525 .number = U300_DMA_MSL_TX_2,
526 .name = "MSL TX 2",
527 .priority_high = 0,
528 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
529 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]530 COH901318_CX_CFG_LCR_DISABLE |
531 COH901318_CX_CFG_TC_IRQ_ENABLE |
532 COH901318_CX_CFG_BE_IRQ_ENABLE,
533 .param.ctrl_lli_chained = 0 |
534 COH901318_CX_CTRL_TC_ENABLE |
535 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
536 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
537 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
538 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
539 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
540 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
541 COH901318_CX_CTRL_TCP_DISABLE |
542 COH901318_CX_CTRL_TC_IRQ_DISABLE |
543 COH901318_CX_CTRL_HSP_ENABLE |
544 COH901318_CX_CTRL_HSS_DISABLE |
545 COH901318_CX_CTRL_DDMA_LEGACY |
546 COH901318_CX_CTRL_PRDD_SOURCE,
547 .param.ctrl_lli = 0 |
548 COH901318_CX_CTRL_TC_ENABLE |
549 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
550 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
551 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
552 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
553 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
554 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
555 COH901318_CX_CTRL_TCP_ENABLE |
556 COH901318_CX_CTRL_TC_IRQ_DISABLE |
557 COH901318_CX_CTRL_HSP_ENABLE |
558 COH901318_CX_CTRL_HSS_DISABLE |
559 COH901318_CX_CTRL_DDMA_LEGACY |
560 COH901318_CX_CTRL_PRDD_SOURCE,
561 .param.ctrl_lli_last = 0 |
562 COH901318_CX_CTRL_TC_ENABLE |
563 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
564 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
565 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
566 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
567 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
568 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
569 COH901318_CX_CTRL_TCP_ENABLE |
570 COH901318_CX_CTRL_TC_IRQ_ENABLE |
571 COH901318_CX_CTRL_HSP_ENABLE |
572 COH901318_CX_CTRL_HSS_DISABLE |
573 COH901318_CX_CTRL_DDMA_LEGACY |
574 COH901318_CX_CTRL_PRDD_SOURCE,
575 .desc_nbr_max = 10,
576 },
577 {
578 .number = U300_DMA_MSL_TX_3,
579 .name = "MSL TX 3",
580 .priority_high = 0,
581 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
582 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]583 COH901318_CX_CFG_LCR_DISABLE |
584 COH901318_CX_CFG_TC_IRQ_ENABLE |
585 COH901318_CX_CFG_BE_IRQ_ENABLE,
586 .param.ctrl_lli_chained = 0 |
587 COH901318_CX_CTRL_TC_ENABLE |
588 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
589 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
590 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
591 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
592 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
593 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
594 COH901318_CX_CTRL_TCP_DISABLE |
595 COH901318_CX_CTRL_TC_IRQ_DISABLE |
596 COH901318_CX_CTRL_HSP_ENABLE |
597 COH901318_CX_CTRL_HSS_DISABLE |
598 COH901318_CX_CTRL_DDMA_LEGACY |
599 COH901318_CX_CTRL_PRDD_SOURCE,
600 .param.ctrl_lli = 0 |
601 COH901318_CX_CTRL_TC_ENABLE |
602 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
603 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
604 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
605 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
606 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
607 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
608 COH901318_CX_CTRL_TCP_ENABLE |
609 COH901318_CX_CTRL_TC_IRQ_DISABLE |
610 COH901318_CX_CTRL_HSP_ENABLE |
611 COH901318_CX_CTRL_HSS_DISABLE |
612 COH901318_CX_CTRL_DDMA_LEGACY |
613 COH901318_CX_CTRL_PRDD_SOURCE,
614 .param.ctrl_lli_last = 0 |
615 COH901318_CX_CTRL_TC_ENABLE |
616 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
617 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
618 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
619 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
620 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
621 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
622 COH901318_CX_CTRL_TCP_ENABLE |
623 COH901318_CX_CTRL_TC_IRQ_ENABLE |
624 COH901318_CX_CTRL_HSP_ENABLE |
625 COH901318_CX_CTRL_HSS_DISABLE |
626 COH901318_CX_CTRL_DDMA_LEGACY |
627 COH901318_CX_CTRL_PRDD_SOURCE,
628 },
629 {
630 .number = U300_DMA_MSL_TX_4,
631 .name = "MSL TX 4",
632 .priority_high = 0,
633 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
634 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]635 COH901318_CX_CFG_LCR_DISABLE |
636 COH901318_CX_CFG_TC_IRQ_ENABLE |
637 COH901318_CX_CFG_BE_IRQ_ENABLE,
638 .param.ctrl_lli_chained = 0 |
639 COH901318_CX_CTRL_TC_ENABLE |
640 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
641 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
642 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
643 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
644 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
645 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
646 COH901318_CX_CTRL_TCP_DISABLE |
647 COH901318_CX_CTRL_TC_IRQ_DISABLE |
648 COH901318_CX_CTRL_HSP_ENABLE |
649 COH901318_CX_CTRL_HSS_DISABLE |
650 COH901318_CX_CTRL_DDMA_LEGACY |
651 COH901318_CX_CTRL_PRDD_SOURCE,
652 .param.ctrl_lli = 0 |
653 COH901318_CX_CTRL_TC_ENABLE |
654 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
655 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
656 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
657 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
658 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
659 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
660 COH901318_CX_CTRL_TCP_ENABLE |
661 COH901318_CX_CTRL_TC_IRQ_DISABLE |
662 COH901318_CX_CTRL_HSP_ENABLE |
663 COH901318_CX_CTRL_HSS_DISABLE |
664 COH901318_CX_CTRL_DDMA_LEGACY |
665 COH901318_CX_CTRL_PRDD_SOURCE,
666 .param.ctrl_lli_last = 0 |
667 COH901318_CX_CTRL_TC_ENABLE |
668 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
669 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
670 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
671 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
672 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
673 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
674 COH901318_CX_CTRL_TCP_ENABLE |
675 COH901318_CX_CTRL_TC_IRQ_ENABLE |
676 COH901318_CX_CTRL_HSP_ENABLE |
677 COH901318_CX_CTRL_HSS_DISABLE |
678 COH901318_CX_CTRL_DDMA_LEGACY |
679 COH901318_CX_CTRL_PRDD_SOURCE,
680 },
681 {
682 .number = U300_DMA_MSL_TX_5,
683 .name = "MSL TX 5",
684 .priority_high = 0,
685 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
686 },
687 {
688 .number = U300_DMA_MSL_TX_6,
689 .name = "MSL TX 6",
690 .priority_high = 0,
691 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
692 },
693 {
694 .number = U300_DMA_MSL_RX_0,
695 .name = "MSL RX 0",
696 .priority_high = 0,
697 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
698 },
699 {
700 .number = U300_DMA_MSL_RX_1,
701 .name = "MSL RX 1",
702 .priority_high = 0,
703 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
704 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]705 COH901318_CX_CFG_LCR_DISABLE |
706 COH901318_CX_CFG_TC_IRQ_ENABLE |
707 COH901318_CX_CFG_BE_IRQ_ENABLE,
708 .param.ctrl_lli_chained = 0 |
709 COH901318_CX_CTRL_TC_ENABLE |
710 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
711 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
713 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
714 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
715 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
716 COH901318_CX_CTRL_TCP_DISABLE |
717 COH901318_CX_CTRL_TC_IRQ_DISABLE |
718 COH901318_CX_CTRL_HSP_ENABLE |
719 COH901318_CX_CTRL_HSS_DISABLE |
720 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
721 COH901318_CX_CTRL_PRDD_DEST,
722 .param.ctrl_lli = 0,
723 .param.ctrl_lli_last = 0 |
724 COH901318_CX_CTRL_TC_ENABLE |
725 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
726 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
727 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
728 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
729 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
730 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
731 COH901318_CX_CTRL_TCP_DISABLE |
732 COH901318_CX_CTRL_TC_IRQ_ENABLE |
733 COH901318_CX_CTRL_HSP_ENABLE |
734 COH901318_CX_CTRL_HSS_DISABLE |
735 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
736 COH901318_CX_CTRL_PRDD_DEST,
737 },
738 {
739 .number = U300_DMA_MSL_RX_2,
740 .name = "MSL RX 2",
741 .priority_high = 0,
742 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
743 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]744 COH901318_CX_CFG_LCR_DISABLE |
745 COH901318_CX_CFG_TC_IRQ_ENABLE |
746 COH901318_CX_CFG_BE_IRQ_ENABLE,
747 .param.ctrl_lli_chained = 0 |
748 COH901318_CX_CTRL_TC_ENABLE |
749 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
750 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
751 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
752 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
753 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
754 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
755 COH901318_CX_CTRL_TCP_DISABLE |
756 COH901318_CX_CTRL_TC_IRQ_DISABLE |
757 COH901318_CX_CTRL_HSP_ENABLE |
758 COH901318_CX_CTRL_HSS_DISABLE |
759 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
760 COH901318_CX_CTRL_PRDD_DEST,
761 .param.ctrl_lli = 0 |
762 COH901318_CX_CTRL_TC_ENABLE |
763 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
764 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
765 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
766 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
767 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
768 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
769 COH901318_CX_CTRL_TCP_DISABLE |
770 COH901318_CX_CTRL_TC_IRQ_ENABLE |
771 COH901318_CX_CTRL_HSP_ENABLE |
772 COH901318_CX_CTRL_HSS_DISABLE |
773 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
774 COH901318_CX_CTRL_PRDD_DEST,
775 .param.ctrl_lli_last = 0 |
776 COH901318_CX_CTRL_TC_ENABLE |
777 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
778 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
779 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
780 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
781 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
782 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
783 COH901318_CX_CTRL_TCP_DISABLE |
784 COH901318_CX_CTRL_TC_IRQ_ENABLE |
785 COH901318_CX_CTRL_HSP_ENABLE |
786 COH901318_CX_CTRL_HSS_DISABLE |
787 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
788 COH901318_CX_CTRL_PRDD_DEST,
789 },
790 {
791 .number = U300_DMA_MSL_RX_3,
792 .name = "MSL RX 3",
793 .priority_high = 0,
794 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
795 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]796 COH901318_CX_CFG_LCR_DISABLE |
797 COH901318_CX_CFG_TC_IRQ_ENABLE |
798 COH901318_CX_CFG_BE_IRQ_ENABLE,
799 .param.ctrl_lli_chained = 0 |
800 COH901318_CX_CTRL_TC_ENABLE |
801 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
802 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
803 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
804 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
805 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
806 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
807 COH901318_CX_CTRL_TCP_DISABLE |
808 COH901318_CX_CTRL_TC_IRQ_DISABLE |
809 COH901318_CX_CTRL_HSP_ENABLE |
810 COH901318_CX_CTRL_HSS_DISABLE |
811 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
812 COH901318_CX_CTRL_PRDD_DEST,
813 .param.ctrl_lli = 0 |
814 COH901318_CX_CTRL_TC_ENABLE |
815 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
816 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
817 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
818 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
819 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
820 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
821 COH901318_CX_CTRL_TCP_DISABLE |
822 COH901318_CX_CTRL_TC_IRQ_ENABLE |
823 COH901318_CX_CTRL_HSP_ENABLE |
824 COH901318_CX_CTRL_HSS_DISABLE |
825 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
826 COH901318_CX_CTRL_PRDD_DEST,
827 .param.ctrl_lli_last = 0 |
828 COH901318_CX_CTRL_TC_ENABLE |
829 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
830 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
831 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
832 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
833 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
834 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
835 COH901318_CX_CTRL_TCP_DISABLE |
836 COH901318_CX_CTRL_TC_IRQ_ENABLE |
837 COH901318_CX_CTRL_HSP_ENABLE |
838 COH901318_CX_CTRL_HSS_DISABLE |
839 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
840 COH901318_CX_CTRL_PRDD_DEST,
841 },
842 {
843 .number = U300_DMA_MSL_RX_4,
844 .name = "MSL RX 4",
845 .priority_high = 0,
846 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
847 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]848 COH901318_CX_CFG_LCR_DISABLE |
849 COH901318_CX_CFG_TC_IRQ_ENABLE |
850 COH901318_CX_CFG_BE_IRQ_ENABLE,
851 .param.ctrl_lli_chained = 0 |
852 COH901318_CX_CTRL_TC_ENABLE |
853 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
854 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
855 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
856 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
857 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
858 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
859 COH901318_CX_CTRL_TCP_DISABLE |
860 COH901318_CX_CTRL_TC_IRQ_DISABLE |
861 COH901318_CX_CTRL_HSP_ENABLE |
862 COH901318_CX_CTRL_HSS_DISABLE |
863 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
864 COH901318_CX_CTRL_PRDD_DEST,
865 .param.ctrl_lli = 0 |
866 COH901318_CX_CTRL_TC_ENABLE |
867 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
868 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
869 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
870 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
871 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
872 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
873 COH901318_CX_CTRL_TCP_DISABLE |
874 COH901318_CX_CTRL_TC_IRQ_ENABLE |
875 COH901318_CX_CTRL_HSP_ENABLE |
876 COH901318_CX_CTRL_HSS_DISABLE |
877 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
878 COH901318_CX_CTRL_PRDD_DEST,
879 .param.ctrl_lli_last = 0 |
880 COH901318_CX_CTRL_TC_ENABLE |
881 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
882 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
883 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
884 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
885 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
886 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
887 COH901318_CX_CTRL_TCP_DISABLE |
888 COH901318_CX_CTRL_TC_IRQ_ENABLE |
889 COH901318_CX_CTRL_HSP_ENABLE |
890 COH901318_CX_CTRL_HSS_DISABLE |
891 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
892 COH901318_CX_CTRL_PRDD_DEST,
893 },
894 {
895 .number = U300_DMA_MSL_RX_5,
896 .name = "MSL RX 5",
897 .priority_high = 0,
898 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
899 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]900 COH901318_CX_CFG_LCR_DISABLE |
901 COH901318_CX_CFG_TC_IRQ_ENABLE |
902 COH901318_CX_CFG_BE_IRQ_ENABLE,
903 .param.ctrl_lli_chained = 0 |
904 COH901318_CX_CTRL_TC_ENABLE |
905 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
906 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
907 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
908 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
909 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
910 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
911 COH901318_CX_CTRL_TCP_DISABLE |
912 COH901318_CX_CTRL_TC_IRQ_DISABLE |
913 COH901318_CX_CTRL_HSP_ENABLE |
914 COH901318_CX_CTRL_HSS_DISABLE |
915 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
916 COH901318_CX_CTRL_PRDD_DEST,
917 .param.ctrl_lli = 0 |
918 COH901318_CX_CTRL_TC_ENABLE |
919 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
920 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
921 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
922 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
923 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
924 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
925 COH901318_CX_CTRL_TCP_DISABLE |
926 COH901318_CX_CTRL_TC_IRQ_ENABLE |
927 COH901318_CX_CTRL_HSP_ENABLE |
928 COH901318_CX_CTRL_HSS_DISABLE |
929 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
930 COH901318_CX_CTRL_PRDD_DEST,
931 .param.ctrl_lli_last = 0 |
932 COH901318_CX_CTRL_TC_ENABLE |
933 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
934 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
935 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
936 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
937 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
938 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
939 COH901318_CX_CTRL_TCP_DISABLE |
940 COH901318_CX_CTRL_TC_IRQ_ENABLE |
941 COH901318_CX_CTRL_HSP_ENABLE |
942 COH901318_CX_CTRL_HSS_DISABLE |
943 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
944 COH901318_CX_CTRL_PRDD_DEST,
945 },
946 {
947 .number = U300_DMA_MSL_RX_6,
948 .name = "MSL RX 6",
949 .priority_high = 0,
950 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
951 },
952 {
953 .number = U300_DMA_MMCSD_RX_TX,
954 .name = "MMCSD RX TX",
955 .priority_high = 0,
956 .dev_addr = U300_MMCSD_BASE + 0x080,
957 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]958 COH901318_CX_CFG_LCR_DISABLE |
959 COH901318_CX_CFG_TC_IRQ_ENABLE |
960 COH901318_CX_CFG_BE_IRQ_ENABLE,
961 .param.ctrl_lli_chained = 0 |
962 COH901318_CX_CTRL_TC_ENABLE |
963 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
964 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
965 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
966 COH901318_CX_CTRL_MASTER_MODE_M1RW |
Linus Walleijd4095662010-02-14 19:41:35 +0100[diff] [blame]967 COH901318_CX_CTRL_TCP_ENABLE |
968 COH901318_CX_CTRL_TC_IRQ_ENABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]969 COH901318_CX_CTRL_HSP_ENABLE |
970 COH901318_CX_CTRL_HSS_DISABLE |
971 COH901318_CX_CTRL_DDMA_LEGACY,
972 .param.ctrl_lli = 0 |
973 COH901318_CX_CTRL_TC_ENABLE |
974 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
975 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
976 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
977 COH901318_CX_CTRL_MASTER_MODE_M1RW |
978 COH901318_CX_CTRL_TCP_ENABLE |
Linus Walleijd4095662010-02-14 19:41:35 +0100[diff] [blame]979 COH901318_CX_CTRL_TC_IRQ_ENABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]980 COH901318_CX_CTRL_HSP_ENABLE |
981 COH901318_CX_CTRL_HSS_DISABLE |
982 COH901318_CX_CTRL_DDMA_LEGACY,
983 .param.ctrl_lli_last = 0 |
984 COH901318_CX_CTRL_TC_ENABLE |
985 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
986 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
Linus Walleijd4095662010-02-14 19:41:35 +0100[diff] [blame]989 COH901318_CX_CTRL_TCP_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]990 COH901318_CX_CTRL_TC_IRQ_ENABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY,
994
995 },
996 {
997 .number = U300_DMA_MSPRO_TX,
998 .name = "MSPRO TX",
999 .priority_high = 0,
1000 },
1001 {
1002 .number = U300_DMA_MSPRO_RX,
1003 .name = "MSPRO RX",
1004 .priority_high = 0,
1005 },
1006 {
1007 .number = U300_DMA_UART0_TX,
1008 .name = "UART0 TX",
1009 .priority_high = 0,
1010 },
1011 {
1012 .number = U300_DMA_UART0_RX,
1013 .name = "UART0 RX",
1014 .priority_high = 0,
1015 },
1016 {
1017 .number = U300_DMA_APEX_TX,
1018 .name = "APEX TX",
1019 .priority_high = 0,
1020 },
1021 {
1022 .number = U300_DMA_APEX_RX,
1023 .name = "APEX RX",
1024 .priority_high = 0,
1025 },
1026 {
1027 .number = U300_DMA_PCM_I2S0_TX,
1028 .name = "PCM I2S0 TX",
1029 .priority_high = 1,
1030 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1031 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1032 COH901318_CX_CFG_LCR_DISABLE |
1033 COH901318_CX_CFG_TC_IRQ_ENABLE |
1034 COH901318_CX_CFG_BE_IRQ_ENABLE,
1035 .param.ctrl_lli_chained = 0 |
1036 COH901318_CX_CTRL_TC_ENABLE |
1037 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1038 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1039 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1040 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1041 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1042 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1043 COH901318_CX_CTRL_TCP_DISABLE |
1044 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1045 COH901318_CX_CTRL_HSP_ENABLE |
1046 COH901318_CX_CTRL_HSS_DISABLE |
1047 COH901318_CX_CTRL_DDMA_LEGACY |
1048 COH901318_CX_CTRL_PRDD_SOURCE,
1049 .param.ctrl_lli = 0 |
1050 COH901318_CX_CTRL_TC_ENABLE |
1051 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1052 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1053 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1054 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1055 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1056 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1057 COH901318_CX_CTRL_TCP_ENABLE |
1058 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1059 COH901318_CX_CTRL_HSP_ENABLE |
1060 COH901318_CX_CTRL_HSS_DISABLE |
1061 COH901318_CX_CTRL_DDMA_LEGACY |
1062 COH901318_CX_CTRL_PRDD_SOURCE,
1063 .param.ctrl_lli_last = 0 |
1064 COH901318_CX_CTRL_TC_ENABLE |
1065 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1066 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1067 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1068 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1069 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1070 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1071 COH901318_CX_CTRL_TCP_ENABLE |
1072 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1073 COH901318_CX_CTRL_HSP_ENABLE |
1074 COH901318_CX_CTRL_HSS_DISABLE |
1075 COH901318_CX_CTRL_DDMA_LEGACY |
1076 COH901318_CX_CTRL_PRDD_SOURCE,
1077 },
1078 {
1079 .number = U300_DMA_PCM_I2S0_RX,
1080 .name = "PCM I2S0 RX",
1081 .priority_high = 1,
1082 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1083 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1084 COH901318_CX_CFG_LCR_DISABLE |
1085 COH901318_CX_CFG_TC_IRQ_ENABLE |
1086 COH901318_CX_CFG_BE_IRQ_ENABLE,
1087 .param.ctrl_lli_chained = 0 |
1088 COH901318_CX_CTRL_TC_ENABLE |
1089 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1090 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1091 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1092 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1093 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1094 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1095 COH901318_CX_CTRL_TCP_DISABLE |
1096 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1097 COH901318_CX_CTRL_HSP_ENABLE |
1098 COH901318_CX_CTRL_HSS_DISABLE |
1099 COH901318_CX_CTRL_DDMA_LEGACY |
1100 COH901318_CX_CTRL_PRDD_DEST,
1101 .param.ctrl_lli = 0 |
1102 COH901318_CX_CTRL_TC_ENABLE |
1103 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1104 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1105 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1106 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1107 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1108 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1109 COH901318_CX_CTRL_TCP_ENABLE |
1110 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1111 COH901318_CX_CTRL_HSP_ENABLE |
1112 COH901318_CX_CTRL_HSS_DISABLE |
1113 COH901318_CX_CTRL_DDMA_LEGACY |
1114 COH901318_CX_CTRL_PRDD_DEST,
1115 .param.ctrl_lli_last = 0 |
1116 COH901318_CX_CTRL_TC_ENABLE |
1117 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1118 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1119 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1120 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1121 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1122 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1123 COH901318_CX_CTRL_TCP_ENABLE |
1124 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1125 COH901318_CX_CTRL_HSP_ENABLE |
1126 COH901318_CX_CTRL_HSS_DISABLE |
1127 COH901318_CX_CTRL_DDMA_LEGACY |
1128 COH901318_CX_CTRL_PRDD_DEST,
1129 },
1130 {
1131 .number = U300_DMA_PCM_I2S1_TX,
1132 .name = "PCM I2S1 TX",
1133 .priority_high = 1,
1134 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1135 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1136 COH901318_CX_CFG_LCR_DISABLE |
1137 COH901318_CX_CFG_TC_IRQ_ENABLE |
1138 COH901318_CX_CFG_BE_IRQ_ENABLE,
1139 .param.ctrl_lli_chained = 0 |
1140 COH901318_CX_CTRL_TC_ENABLE |
1141 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1142 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1143 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1144 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1145 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1146 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1147 COH901318_CX_CTRL_TCP_DISABLE |
1148 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1149 COH901318_CX_CTRL_HSP_ENABLE |
1150 COH901318_CX_CTRL_HSS_DISABLE |
1151 COH901318_CX_CTRL_DDMA_LEGACY |
1152 COH901318_CX_CTRL_PRDD_SOURCE,
1153 .param.ctrl_lli = 0 |
1154 COH901318_CX_CTRL_TC_ENABLE |
1155 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1156 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1157 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1158 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1159 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1160 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1161 COH901318_CX_CTRL_TCP_ENABLE |
1162 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1163 COH901318_CX_CTRL_HSP_ENABLE |
1164 COH901318_CX_CTRL_HSS_DISABLE |
1165 COH901318_CX_CTRL_DDMA_LEGACY |
1166 COH901318_CX_CTRL_PRDD_SOURCE,
1167 .param.ctrl_lli_last = 0 |
1168 COH901318_CX_CTRL_TC_ENABLE |
1169 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1170 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1171 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1172 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1173 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1174 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1175 COH901318_CX_CTRL_TCP_ENABLE |
1176 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1177 COH901318_CX_CTRL_HSP_ENABLE |
1178 COH901318_CX_CTRL_HSS_DISABLE |
1179 COH901318_CX_CTRL_DDMA_LEGACY |
1180 COH901318_CX_CTRL_PRDD_SOURCE,
1181 },
1182 {
1183 .number = U300_DMA_PCM_I2S1_RX,
1184 .name = "PCM I2S1 RX",
1185 .priority_high = 1,
1186 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1187 .param.config = COH901318_CX_CFG_CH_DISABLE |
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1188 COH901318_CX_CFG_LCR_DISABLE |
1189 COH901318_CX_CFG_TC_IRQ_ENABLE |
1190 COH901318_CX_CFG_BE_IRQ_ENABLE,
1191 .param.ctrl_lli_chained = 0 |
1192 COH901318_CX_CTRL_TC_ENABLE |
1193 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1194 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1195 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1196 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1197 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1198 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1199 COH901318_CX_CTRL_TCP_DISABLE |
1200 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1201 COH901318_CX_CTRL_HSP_ENABLE |
1202 COH901318_CX_CTRL_HSS_DISABLE |
1203 COH901318_CX_CTRL_DDMA_LEGACY |
1204 COH901318_CX_CTRL_PRDD_DEST,
1205 .param.ctrl_lli = 0 |
1206 COH901318_CX_CTRL_TC_ENABLE |
1207 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1208 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1209 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1210 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1211 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1212 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1213 COH901318_CX_CTRL_TCP_ENABLE |
1214 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1215 COH901318_CX_CTRL_HSP_ENABLE |
1216 COH901318_CX_CTRL_HSS_DISABLE |
1217 COH901318_CX_CTRL_DDMA_LEGACY |
1218 COH901318_CX_CTRL_PRDD_DEST,
1219 .param.ctrl_lli_last = 0 |
1220 COH901318_CX_CTRL_TC_ENABLE |
1221 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1222 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1223 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1224 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1225 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1226 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1227 COH901318_CX_CTRL_TCP_ENABLE |
1228 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1229 COH901318_CX_CTRL_HSP_ENABLE |
1230 COH901318_CX_CTRL_HSS_DISABLE |
1231 COH901318_CX_CTRL_DDMA_LEGACY |
1232 COH901318_CX_CTRL_PRDD_DEST,
1233 },
1234 {
1235 .number = U300_DMA_XGAM_CDI,
1236 .name = "XGAM CDI",
1237 .priority_high = 0,
1238 },
1239 {
1240 .number = U300_DMA_XGAM_PDI,
1241 .name = "XGAM PDI",
1242 .priority_high = 0,
1243 },
1244 {
1245 .number = U300_DMA_SPI_TX,
1246 .name = "SPI TX",
1247 .priority_high = 0,
1248 },
1249 {
1250 .number = U300_DMA_SPI_RX,
1251 .name = "SPI RX",
1252 .priority_high = 0,
1253 },
1254 {
1255 .number = U300_DMA_GENERAL_PURPOSE_0,
1256 .name = "GENERAL 00",
1257 .priority_high = 0,
1258
1259 .param.config = flags_memcpy_config,
1260 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1261 .param.ctrl_lli = flags_memcpy_lli,
1262 .param.ctrl_lli_last = flags_memcpy_lli_last,
1263 },
1264 {
1265 .number = U300_DMA_GENERAL_PURPOSE_1,
1266 .name = "GENERAL 01",
1267 .priority_high = 0,
1268
1269 .param.config = flags_memcpy_config,
1270 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1271 .param.ctrl_lli = flags_memcpy_lli,
1272 .param.ctrl_lli_last = flags_memcpy_lli_last,
1273 },
1274 {
1275 .number = U300_DMA_GENERAL_PURPOSE_2,
1276 .name = "GENERAL 02",
1277 .priority_high = 0,
1278
1279 .param.config = flags_memcpy_config,
1280 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1281 .param.ctrl_lli = flags_memcpy_lli,
1282 .param.ctrl_lli_last = flags_memcpy_lli_last,
1283 },
1284 {
1285 .number = U300_DMA_GENERAL_PURPOSE_3,
1286 .name = "GENERAL 03",
1287 .priority_high = 0,
1288
1289 .param.config = flags_memcpy_config,
1290 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1291 .param.ctrl_lli = flags_memcpy_lli,
1292 .param.ctrl_lli_last = flags_memcpy_lli_last,
1293 },
1294 {
1295 .number = U300_DMA_GENERAL_PURPOSE_4,
1296 .name = "GENERAL 04",
1297 .priority_high = 0,
1298
1299 .param.config = flags_memcpy_config,
1300 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1301 .param.ctrl_lli = flags_memcpy_lli,
1302 .param.ctrl_lli_last = flags_memcpy_lli_last,
1303 },
1304 {
1305 .number = U300_DMA_GENERAL_PURPOSE_5,
1306 .name = "GENERAL 05",
1307 .priority_high = 0,
1308
1309 .param.config = flags_memcpy_config,
1310 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1311 .param.ctrl_lli = flags_memcpy_lli,
1312 .param.ctrl_lli_last = flags_memcpy_lli_last,
1313 },
1314 {
1315 .number = U300_DMA_GENERAL_PURPOSE_6,
1316 .name = "GENERAL 06",
1317 .priority_high = 0,
1318
1319 .param.config = flags_memcpy_config,
1320 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1321 .param.ctrl_lli = flags_memcpy_lli,
1322 .param.ctrl_lli_last = flags_memcpy_lli_last,
1323 },
1324 {
1325 .number = U300_DMA_GENERAL_PURPOSE_7,
1326 .name = "GENERAL 07",
1327 .priority_high = 0,
1328
1329 .param.config = flags_memcpy_config,
1330 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1331 .param.ctrl_lli = flags_memcpy_lli,
1332 .param.ctrl_lli_last = flags_memcpy_lli_last,
1333 },
1334 {
1335 .number = U300_DMA_GENERAL_PURPOSE_8,
1336 .name = "GENERAL 08",
1337 .priority_high = 0,
1338
1339 .param.config = flags_memcpy_config,
1340 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1341 .param.ctrl_lli = flags_memcpy_lli,
1342 .param.ctrl_lli_last = flags_memcpy_lli_last,
1343 },
1344#ifdef CONFIG_MACH_U300_BS335
1345 {
1346 .number = U300_DMA_UART1_TX,
1347 .name = "UART1 TX",
1348 .priority_high = 0,
1349 },
1350 {
1351 .number = U300_DMA_UART1_RX,
1352 .name = "UART1 RX",
1353 .priority_high = 0,
1354 }
1355#else
1356 {
1357 .number = U300_DMA_GENERAL_PURPOSE_9,
1358 .name = "GENERAL 09",
1359 .priority_high = 0,
1360
1361 .param.config = flags_memcpy_config,
1362 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1363 .param.ctrl_lli = flags_memcpy_lli,
1364 .param.ctrl_lli_last = flags_memcpy_lli_last,
1365 },
1366 {
1367 .number = U300_DMA_GENERAL_PURPOSE_10,
1368 .name = "GENERAL 10",
1369 .priority_high = 0,
1370
1371 .param.config = flags_memcpy_config,
1372 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1373 .param.ctrl_lli = flags_memcpy_lli,
1374 .param.ctrl_lli_last = flags_memcpy_lli_last,
1375 }
1376#endif
1377};
1378
1379
1380static struct coh901318_platform coh901318_platform = {
1381 .chans_slave = dma_slave_channels,
1382 .chans_memcpy = dma_memcpy_channels,
1383 .access_memory_state = coh901318_access_memory_state,
1384 .chan_conf = chan_config,
1385 .max_channels = U300_DMA_CHANNELS,
1386};
1387
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1388static struct platform_device wdog_device = {
Linus Walleij633e81a2010-01-25 07:18:16 +0100[diff] [blame]1389 .name = "coh901327_wdog",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1390 .id = -1,
1391 .num_resources = ARRAY_SIZE(wdog_resources),
1392 .resource = wdog_resources,
1393};
1394
1395static struct platform_device i2c0_device = {
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]1396 .name = "stu300",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1397 .id = 0,
1398 .num_resources = ARRAY_SIZE(i2c0_resources),
1399 .resource = i2c0_resources,
1400};
1401
1402static struct platform_device i2c1_device = {
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]1403 .name = "stu300",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1404 .id = 1,
1405 .num_resources = ARRAY_SIZE(i2c1_resources),
1406 .resource = i2c1_resources,
1407};
1408
1409static struct platform_device gpio_device = {
1410 .name = "u300-gpio",
1411 .id = -1,
1412 .num_resources = ARRAY_SIZE(gpio_resources),
1413 .resource = gpio_resources,
1414};
1415
1416static struct platform_device keypad_device = {
1417 .name = "keypad",
1418 .id = -1,
1419 .num_resources = ARRAY_SIZE(keypad_resources),
1420 .resource = keypad_resources,
1421};
1422
1423static struct platform_device rtc_device = {
Linus Walleij378ce742009-11-14 01:03:24 +0100[diff] [blame]1424 .name = "rtc-coh901331",
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1425 .id = -1,
1426 .num_resources = ARRAY_SIZE(rtc_resources),
1427 .resource = rtc_resources,
1428};
1429
1430static struct platform_device fsmc_device = {
1431 .name = "nandif",
1432 .id = -1,
1433 .num_resources = ARRAY_SIZE(fsmc_resources),
1434 .resource = fsmc_resources,
1435};
1436
1437static struct platform_device ave_device = {
1438 .name = "video_enc",
1439 .id = -1,
1440 .num_resources = ARRAY_SIZE(ave_resources),
1441 .resource = ave_resources,
1442};
1443
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1444static struct platform_device dma_device = {
1445 .name = "coh901318",
1446 .id = -1,
1447 .resource = dma_resource,
1448 .num_resources = ARRAY_SIZE(dma_resource),
1449 .dev = {
1450 .platform_data = &coh901318_platform,
1451 .coherent_dma_mask = ~0,
1452 },
1453};
1454
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1455/*
1456 * Notice that AMBA devices are initialized before platform devices.
1457 *
1458 */
1459static struct platform_device *platform_devs[] __initdata = {
Linus Walleij08d1e2e2009-12-17 09:46:24 +0100[diff] [blame]1460 &dma_device,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1461 &i2c0_device,
1462 &i2c1_device,
1463 &keypad_device,
1464 &rtc_device,
1465 &gpio_device,
1466 &fsmc_device,
1467 &wdog_device,
1468 &ave_device
1469};
1470
1471
1472/*
1473 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1474 * together so some interrupts are connected to the first one and some
1475 * to the second one.
1476 */
1477void __init u300_init_irq(void)
1478{
1479 u32 mask[2] = {0, 0};
1480 int i;
1481
1482 for (i = 0; i < NR_IRQS; i++)
1483 set_bit(i, (unsigned long *) &mask[0]);
1484 u300_enable_intcon_clock();
Linus Walleij68601072009-07-06 18:04:28 +0100[diff] [blame]1485 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1486 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1487}
1488
1489
1490/*
1491 * U300 platforms peripheral handling
1492 */
1493struct db_chip {
1494 u16 chipid;
1495 const char *name;
1496};
1497
1498/*
1499 * This is a list of the Digital Baseband chips used in the U300 platform.
1500 */
1501static struct db_chip db_chips[] __initdata = {
1502 {
1503 .chipid = 0xb800,
1504 .name = "DB3000",
1505 },
1506 {
1507 .chipid = 0xc000,
1508 .name = "DB3100",
1509 },
1510 {
1511 .chipid = 0xc800,
1512 .name = "DB3150",
1513 },
1514 {
1515 .chipid = 0xd800,
1516 .name = "DB3200",
1517 },
1518 {
1519 .chipid = 0xe000,
1520 .name = "DB3250",
1521 },
1522 {
1523 .chipid = 0xe800,
1524 .name = "DB3210",
1525 },
1526 {
1527 .chipid = 0xf000,
1528 .name = "DB3350 P1x",
1529 },
1530 {
1531 .chipid = 0xf100,
1532 .name = "DB3350 P2x",
1533 },
1534 {
1535 .chipid = 0x0000, /* List terminator */
1536 .name = NULL,
1537 }
1538};
1539
Linus Walleija2bb9f42009-08-13 21:57:22 +0100[diff] [blame]1540static void __init u300_init_check_chip(void)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1541{
1542
1543 u16 val;
1544 struct db_chip *chip;
1545 const char *chipname;
1546 const char unknown[] = "UNKNOWN";
1547
1548 /* Read out and print chip ID */
1549 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1550 /* This is in funky bigendian order... */
1551 val = (val & 0xFFU) << 8 | (val >> 8);
1552 chip = db_chips;
1553 chipname = unknown;
1554
1555 for ( ; chip->chipid; chip++) {
1556 if (chip->chipid == (val & 0xFF00U)) {
1557 chipname = chip->name;
1558 break;
1559 }
1560 }
1561 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1562 "(chip ID 0x%04x)\n", chipname, val);
1563
1564#ifdef CONFIG_MACH_U300_BS26
1565 if ((val & 0xFF00U) != 0xc800) {
1566 printk(KERN_ERR "Platform configured for BS25/BS26 " \
1567 "with DB3150 but %s detected, expect problems!",
1568 chipname);
1569 }
1570#endif
1571#ifdef CONFIG_MACH_U300_BS330
1572 if ((val & 0xFF00U) != 0xd800) {
1573 printk(KERN_ERR "Platform configured for BS330 " \
1574 "with DB3200 but %s detected, expect problems!",
1575 chipname);
1576 }
1577#endif
1578#ifdef CONFIG_MACH_U300_BS335
1579 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1580 printk(KERN_ERR "Platform configured for BS365 " \
1581 " with DB3350 but %s detected, expect problems!",
1582 chipname);
1583 }
1584#endif
1585#ifdef CONFIG_MACH_U300_BS365
1586 if ((val & 0xFF00U) != 0xe800) {
1587 printk(KERN_ERR "Platform configured for BS365 " \
1588 "with DB3210 but %s detected, expect problems!",
1589 chipname);
1590 }
1591#endif
1592
1593
1594}
1595
1596/*
1597 * Some devices and their resources require reserved physical memory from
1598 * the end of the available RAM. This function traverses the list of devices
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800[diff] [blame]1599 * and assigns actual addresses to these.
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1600 */
1601static void __init u300_assign_physmem(void)
1602{
1603 unsigned long curr_start = __pa(high_memory);
1604 int i, j;
1605
1606 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1607 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1608 struct resource *const res =
1609 &platform_devs[i]->resource[j];
1610
1611 if (IORESOURCE_MEM == res->flags &&
1612 0 == res->start) {
1613 res->start = curr_start;
1614 res->end += curr_start;
1615 curr_start += (res->end - res->start + 1);
1616
1617 printk(KERN_INFO "core.c: Mapping RAM " \
1618 "%#x-%#x to device %s:%s\n",
1619 res->start, res->end,
1620 platform_devs[i]->name, res->name);
1621 }
1622 }
1623 }
1624}
1625
1626void __init u300_init_devices(void)
1627{
1628 int i;
1629 u16 val;
1630
1631 /* Check what platform we run and print some status information */
1632 u300_init_check_chip();
1633
1634 /* Set system to run at PLL208, max performance, a known state. */
1635 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1636 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1637 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1638 /* Wait for the PLL208 to lock if not locked in yet */
1639 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1640 U300_SYSCON_CSR_PLL208_LOCK_IND));
Linus Walleijc7c8c782009-08-14 10:59:05 +0100[diff] [blame]1641 /* Initialize SPI device with some board specifics */
1642 u300_spi_init(&pl022_device);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1643
1644 /* Register the AMBA devices in the AMBA bus abstraction layer */
1645 u300_clock_primecells();
1646 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1647 struct amba_device *d = amba_devs[i];
1648 amba_device_register(d, &iomem_resource);
1649 }
1650 u300_unclock_primecells();
1651
1652 u300_assign_physmem();
1653
Linus Walleij6be2a0c2009-08-13 21:42:01 +0100[diff] [blame]1654 /* Register subdevices on the I2C buses */
1655 u300_i2c_register_board_devices();
1656
Linus Walleijc7c8c782009-08-14 10:59:05 +0100[diff] [blame]1657 /* Register subdevices on the SPI bus */
1658 u300_spi_register_board_devices();
1659
Linus Walleijbb3cee22009-04-23 10:22:13 +0100[diff] [blame]1660 /* Register the platform devices */
1661 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1662
1663#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1664 /*
1665 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1666 * both subsystems are requesting this mode.
1667 * If we not share the Acc SDRAM, this is never the case. Therefore
1668 * enable it here from the App side.
1669 */
1670 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1671 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1672 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1673#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1674}
1675
1676static int core_module_init(void)
1677{
1678 /*
1679 * This needs to be initialized later: it needs the input framework
1680 * to be initialized first.
1681 */
1682 return mmc_init(&mmcsd_device);
1683}
1684module_init(core_module_init);