Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1 | /* |
| 2 | * AD7190 AD7192 AD7195 SPI ADC driver |
| 3 | * |
| 4 | * Copyright 2011 Analog Devices Inc. |
| 5 | * |
| 6 | * Licensed under the GPL-2. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/device.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/slab.h> |
| 13 | #include <linux/sysfs.h> |
| 14 | #include <linux/spi/spi.h> |
| 15 | #include <linux/regulator/consumer.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/sched.h> |
| 18 | #include <linux/delay.h> |
| 19 | |
| 20 | #include "../iio.h" |
| 21 | #include "../sysfs.h" |
Jonathan Cameron | af5046a | 2011-10-26 17:41:32 +0100 | [diff] [blame] | 22 | #include "../buffer.h" |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 23 | #include "../ring_sw.h" |
| 24 | #include "../trigger.h" |
Jonathan Cameron | 3f72395 | 2011-08-24 17:28:39 +0100 | [diff] [blame] | 25 | #include "../trigger_consumer.h" |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 26 | |
| 27 | #include "ad7192.h" |
| 28 | |
| 29 | /* Registers */ |
| 30 | #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ |
| 31 | #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ |
| 32 | #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ |
| 33 | #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ |
| 34 | #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ |
| 35 | #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ |
| 36 | #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ |
| 37 | #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit |
| 38 | * (AD7792)/24-bit (AD7192)) */ |
| 39 | #define AD7192_REG_FULLSALE 7 /* Full-Scale Register |
| 40 | * (RW, 16-bit (AD7792)/24-bit (AD7192)) */ |
| 41 | |
| 42 | /* Communications Register Bit Designations (AD7192_REG_COMM) */ |
| 43 | #define AD7192_COMM_WEN (1 << 7) /* Write Enable */ |
| 44 | #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */ |
| 45 | #define AD7192_COMM_READ (1 << 6) /* Read Operation */ |
| 46 | #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ |
| 47 | #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ |
| 48 | |
| 49 | /* Status Register Bit Designations (AD7192_REG_STAT) */ |
| 50 | #define AD7192_STAT_RDY (1 << 7) /* Ready */ |
| 51 | #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ |
| 52 | #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */ |
| 53 | #define AD7192_STAT_PARITY (1 << 4) /* Parity */ |
| 54 | #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */ |
| 55 | #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */ |
| 56 | #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */ |
| 57 | |
| 58 | /* Mode Register Bit Designations (AD7192_REG_MODE) */ |
| 59 | #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ |
| 60 | #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */ |
| 61 | #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ |
| 62 | #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */ |
| 63 | #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/ |
| 64 | #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */ |
| 65 | #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/ |
| 66 | #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */ |
| 67 | #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */ |
| 68 | #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ |
| 69 | |
| 70 | /* Mode Register: AD7192_MODE_SEL options */ |
| 71 | #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ |
| 72 | #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ |
| 73 | #define AD7192_MODE_IDLE 2 /* Idle Mode */ |
| 74 | #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ |
| 75 | #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ |
| 76 | #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ |
| 77 | #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ |
| 78 | #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ |
| 79 | |
| 80 | /* Mode Register: AD7192_MODE_CLKSRC options */ |
| 81 | #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected |
| 82 | * from MCLK1 to MCLK2 */ |
| 83 | #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ |
| 84 | #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not |
| 85 | * available at the MCLK2 pin */ |
| 86 | #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available |
| 87 | * at the MCLK2 pin */ |
| 88 | |
| 89 | |
| 90 | /* Configuration Register Bit Designations (AD7192_REG_CONF) */ |
| 91 | |
| 92 | #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */ |
| 93 | #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */ |
| 94 | #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */ |
| 95 | #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */ |
| 96 | #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */ |
| 97 | #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */ |
| 98 | #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */ |
| 99 | #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ |
| 100 | |
| 101 | #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */ |
| 102 | #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */ |
| 103 | #define AD7192_CH_TEMP 2 /* Temp Sensor */ |
| 104 | #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */ |
| 105 | #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */ |
| 106 | #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */ |
| 107 | #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */ |
| 108 | #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */ |
| 109 | |
| 110 | /* ID Register Bit Designations (AD7192_REG_ID) */ |
| 111 | #define ID_AD7190 0x4 |
| 112 | #define ID_AD7192 0x0 |
| 113 | #define ID_AD7195 0x6 |
| 114 | #define AD7192_ID_MASK 0x0F |
| 115 | |
| 116 | /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ |
| 117 | #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */ |
| 118 | #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */ |
| 119 | #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */ |
| 120 | #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */ |
| 121 | #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */ |
| 122 | #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */ |
| 123 | #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */ |
| 124 | |
| 125 | #define AD7192_INT_FREQ_MHz 4915200 |
| 126 | |
| 127 | /* NOTE: |
| 128 | * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. |
| 129 | * In order to avoid contentions on the SPI bus, it's therefore necessary |
| 130 | * to use spi bus locking. |
| 131 | * |
| 132 | * The DOUT/RDY output must also be wired to an interrupt capable GPIO. |
| 133 | */ |
| 134 | |
| 135 | struct ad7192_state { |
| 136 | struct spi_device *spi; |
| 137 | struct iio_trigger *trig; |
| 138 | struct regulator *reg; |
| 139 | struct ad7192_platform_data *pdata; |
| 140 | wait_queue_head_t wq_data_avail; |
| 141 | bool done; |
| 142 | bool irq_dis; |
| 143 | u16 int_vref_mv; |
| 144 | u32 mclk; |
| 145 | u32 f_order; |
| 146 | u32 mode; |
| 147 | u32 conf; |
| 148 | u32 scale_avail[8][2]; |
Jonathan Cameron | 32b5eec | 2011-09-02 17:14:38 +0100 | [diff] [blame] | 149 | long available_scan_masks[9]; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 150 | u8 gpocon; |
| 151 | u8 devid; |
| 152 | /* |
| 153 | * DMA (thus cache coherency maintenance) requires the |
| 154 | * transfer buffers to live in their own cache lines. |
| 155 | */ |
| 156 | u8 data[4] ____cacheline_aligned; |
| 157 | }; |
| 158 | |
| 159 | static int __ad7192_write_reg(struct ad7192_state *st, bool locked, |
| 160 | bool cs_change, unsigned char reg, |
| 161 | unsigned size, unsigned val) |
| 162 | { |
| 163 | u8 *data = st->data; |
| 164 | struct spi_transfer t = { |
| 165 | .tx_buf = data, |
| 166 | .len = size + 1, |
| 167 | .cs_change = cs_change, |
| 168 | }; |
| 169 | struct spi_message m; |
| 170 | |
| 171 | data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg); |
| 172 | |
| 173 | switch (size) { |
| 174 | case 3: |
| 175 | data[1] = val >> 16; |
| 176 | data[2] = val >> 8; |
| 177 | data[3] = val; |
| 178 | break; |
| 179 | case 2: |
| 180 | data[1] = val >> 8; |
| 181 | data[2] = val; |
| 182 | break; |
| 183 | case 1: |
| 184 | data[1] = val; |
| 185 | break; |
| 186 | default: |
| 187 | return -EINVAL; |
| 188 | } |
| 189 | |
| 190 | spi_message_init(&m); |
| 191 | spi_message_add_tail(&t, &m); |
| 192 | |
| 193 | if (locked) |
| 194 | return spi_sync_locked(st->spi, &m); |
| 195 | else |
| 196 | return spi_sync(st->spi, &m); |
| 197 | } |
| 198 | |
| 199 | static int ad7192_write_reg(struct ad7192_state *st, |
| 200 | unsigned reg, unsigned size, unsigned val) |
| 201 | { |
| 202 | return __ad7192_write_reg(st, false, false, reg, size, val); |
| 203 | } |
| 204 | |
| 205 | static int __ad7192_read_reg(struct ad7192_state *st, bool locked, |
| 206 | bool cs_change, unsigned char reg, |
| 207 | int *val, unsigned size) |
| 208 | { |
| 209 | u8 *data = st->data; |
| 210 | int ret; |
| 211 | struct spi_transfer t[] = { |
| 212 | { |
| 213 | .tx_buf = data, |
| 214 | .len = 1, |
| 215 | }, { |
| 216 | .rx_buf = data, |
| 217 | .len = size, |
| 218 | .cs_change = cs_change, |
| 219 | }, |
| 220 | }; |
| 221 | struct spi_message m; |
| 222 | |
| 223 | data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg); |
| 224 | |
| 225 | spi_message_init(&m); |
| 226 | spi_message_add_tail(&t[0], &m); |
| 227 | spi_message_add_tail(&t[1], &m); |
| 228 | |
| 229 | if (locked) |
| 230 | ret = spi_sync_locked(st->spi, &m); |
| 231 | else |
| 232 | ret = spi_sync(st->spi, &m); |
| 233 | |
| 234 | if (ret < 0) |
| 235 | return ret; |
| 236 | |
| 237 | switch (size) { |
| 238 | case 3: |
| 239 | *val = data[0] << 16 | data[1] << 8 | data[2]; |
| 240 | break; |
| 241 | case 2: |
| 242 | *val = data[0] << 8 | data[1]; |
| 243 | break; |
| 244 | case 1: |
| 245 | *val = data[0]; |
| 246 | break; |
| 247 | default: |
| 248 | return -EINVAL; |
| 249 | } |
| 250 | |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | static int ad7192_read_reg(struct ad7192_state *st, |
| 255 | unsigned reg, int *val, unsigned size) |
| 256 | { |
| 257 | return __ad7192_read_reg(st, 0, 0, reg, val, size); |
| 258 | } |
| 259 | |
| 260 | static int ad7192_read(struct ad7192_state *st, unsigned ch, |
| 261 | unsigned len, int *val) |
| 262 | { |
| 263 | int ret; |
| 264 | st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | |
| 265 | AD7192_CONF_CHAN(1 << ch); |
| 266 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | |
| 267 | AD7192_MODE_SEL(AD7192_MODE_SINGLE); |
| 268 | |
| 269 | ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); |
| 270 | |
| 271 | spi_bus_lock(st->spi->master); |
| 272 | st->done = false; |
| 273 | |
| 274 | ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode); |
| 275 | if (ret < 0) |
| 276 | goto out; |
| 277 | |
| 278 | st->irq_dis = false; |
| 279 | enable_irq(st->spi->irq); |
| 280 | wait_event_interruptible(st->wq_data_avail, st->done); |
| 281 | |
| 282 | ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len); |
| 283 | out: |
| 284 | spi_bus_unlock(st->spi->master); |
| 285 | |
| 286 | return ret; |
| 287 | } |
| 288 | |
| 289 | static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch) |
| 290 | { |
| 291 | int ret; |
| 292 | |
| 293 | st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | |
| 294 | AD7192_CONF_CHAN(1 << ch); |
| 295 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode); |
| 296 | |
| 297 | ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); |
| 298 | |
| 299 | spi_bus_lock(st->spi->master); |
| 300 | st->done = false; |
| 301 | |
| 302 | ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, |
| 303 | (st->devid != ID_AD7195) ? |
| 304 | st->mode | AD7192_MODE_CLKDIV : |
| 305 | st->mode); |
| 306 | if (ret < 0) |
| 307 | goto out; |
| 308 | |
| 309 | st->irq_dis = false; |
| 310 | enable_irq(st->spi->irq); |
| 311 | wait_event_interruptible(st->wq_data_avail, st->done); |
| 312 | |
| 313 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | |
| 314 | AD7192_MODE_SEL(AD7192_MODE_IDLE); |
| 315 | |
| 316 | ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode); |
| 317 | out: |
| 318 | spi_bus_unlock(st->spi->master); |
| 319 | |
| 320 | return ret; |
| 321 | } |
| 322 | |
| 323 | static const u8 ad7192_calib_arr[8][2] = { |
| 324 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, |
| 325 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, |
| 326 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, |
| 327 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, |
| 328 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, |
| 329 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, |
| 330 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, |
| 331 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} |
| 332 | }; |
| 333 | |
| 334 | static int ad7192_calibrate_all(struct ad7192_state *st) |
| 335 | { |
| 336 | int i, ret; |
| 337 | |
| 338 | for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) { |
| 339 | ret = ad7192_calibrate(st, ad7192_calib_arr[i][0], |
| 340 | ad7192_calib_arr[i][1]); |
| 341 | if (ret) |
| 342 | goto out; |
| 343 | } |
| 344 | |
| 345 | return 0; |
| 346 | out: |
| 347 | dev_err(&st->spi->dev, "Calibration failed\n"); |
| 348 | return ret; |
| 349 | } |
| 350 | |
| 351 | static int ad7192_setup(struct ad7192_state *st) |
| 352 | { |
| 353 | struct iio_dev *indio_dev = spi_get_drvdata(st->spi); |
| 354 | struct ad7192_platform_data *pdata = st->pdata; |
| 355 | unsigned long long scale_uv; |
| 356 | int i, ret, id; |
| 357 | u8 ones[6]; |
| 358 | |
| 359 | /* reset the serial interface */ |
| 360 | memset(&ones, 0xFF, 6); |
| 361 | ret = spi_write(st->spi, &ones, 6); |
| 362 | if (ret < 0) |
| 363 | goto out; |
| 364 | msleep(1); /* Wait for at least 500us */ |
| 365 | |
| 366 | /* write/read test for device presence */ |
| 367 | ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1); |
| 368 | if (ret) |
| 369 | goto out; |
| 370 | |
| 371 | id &= AD7192_ID_MASK; |
| 372 | |
| 373 | if (id != st->devid) |
| 374 | dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id); |
| 375 | |
| 376 | switch (pdata->clock_source_sel) { |
| 377 | case AD7192_CLK_EXT_MCLK1_2: |
| 378 | case AD7192_CLK_EXT_MCLK2: |
| 379 | st->mclk = AD7192_INT_FREQ_MHz; |
| 380 | break; |
| 381 | case AD7192_CLK_INT: |
| 382 | case AD7192_CLK_INT_CO: |
| 383 | if (pdata->ext_clk_Hz) |
| 384 | st->mclk = pdata->ext_clk_Hz; |
| 385 | else |
| 386 | st->mclk = AD7192_INT_FREQ_MHz; |
| 387 | break; |
| 388 | default: |
| 389 | ret = -EINVAL; |
| 390 | goto out; |
| 391 | } |
| 392 | |
| 393 | st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | |
| 394 | AD7192_MODE_CLKSRC(pdata->clock_source_sel) | |
| 395 | AD7192_MODE_RATE(480); |
| 396 | |
| 397 | st->conf = AD7192_CONF_GAIN(0); |
| 398 | |
| 399 | if (pdata->rej60_en) |
| 400 | st->mode |= AD7192_MODE_REJ60; |
| 401 | |
| 402 | if (pdata->sinc3_en) |
| 403 | st->mode |= AD7192_MODE_SINC3; |
| 404 | |
| 405 | if (pdata->refin2_en && (st->devid != ID_AD7195)) |
| 406 | st->conf |= AD7192_CONF_REFSEL; |
| 407 | |
| 408 | if (pdata->chop_en) { |
| 409 | st->conf |= AD7192_CONF_CHOP; |
| 410 | if (pdata->sinc3_en) |
| 411 | st->f_order = 3; /* SINC 3rd order */ |
| 412 | else |
| 413 | st->f_order = 4; /* SINC 4th order */ |
| 414 | } else { |
| 415 | st->f_order = 1; |
| 416 | } |
| 417 | |
| 418 | if (pdata->buf_en) |
| 419 | st->conf |= AD7192_CONF_BUF; |
| 420 | |
| 421 | if (pdata->unipolar_en) |
| 422 | st->conf |= AD7192_CONF_UNIPOLAR; |
| 423 | |
| 424 | if (pdata->burnout_curr_en) |
| 425 | st->conf |= AD7192_CONF_BURN; |
| 426 | |
| 427 | ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode); |
| 428 | if (ret) |
| 429 | goto out; |
| 430 | |
| 431 | ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); |
| 432 | if (ret) |
| 433 | goto out; |
| 434 | |
| 435 | ret = ad7192_calibrate_all(st); |
| 436 | if (ret) |
| 437 | goto out; |
| 438 | |
| 439 | /* Populate available ADC input ranges */ |
| 440 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { |
| 441 | scale_uv = ((u64)st->int_vref_mv * 100000000) |
| 442 | >> (indio_dev->channels[0].scan_type.realbits - |
| 443 | ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); |
| 444 | scale_uv >>= i; |
| 445 | |
| 446 | st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; |
| 447 | st->scale_avail[i][0] = scale_uv; |
| 448 | } |
| 449 | |
| 450 | return 0; |
| 451 | out: |
| 452 | dev_err(&st->spi->dev, "setup failed\n"); |
| 453 | return ret; |
| 454 | } |
| 455 | |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 456 | static int ad7192_ring_preenable(struct iio_dev *indio_dev) |
| 457 | { |
| 458 | struct ad7192_state *st = iio_priv(indio_dev); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 459 | struct iio_buffer *ring = indio_dev->buffer; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 460 | size_t d_size; |
| 461 | unsigned channel; |
| 462 | |
Jonathan Cameron | 550268c | 2011-12-05 22:18:15 +0000 | [diff] [blame] | 463 | if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 464 | return -EINVAL; |
| 465 | |
Jonathan Cameron | 550268c | 2011-12-05 22:18:15 +0000 | [diff] [blame] | 466 | channel = find_first_bit(indio_dev->active_scan_mask, |
| 467 | indio_dev->masklength); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 468 | |
Jonathan Cameron | 550268c | 2011-12-05 22:18:15 +0000 | [diff] [blame] | 469 | d_size = bitmap_weight(indio_dev->active_scan_mask, |
| 470 | indio_dev->masklength) * |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 471 | indio_dev->channels[0].scan_type.storagebits / 8; |
| 472 | |
| 473 | if (ring->scan_timestamp) { |
| 474 | d_size += sizeof(s64); |
| 475 | |
| 476 | if (d_size % sizeof(s64)) |
| 477 | d_size += sizeof(s64) - (d_size % sizeof(s64)); |
| 478 | } |
| 479 | |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 480 | if (indio_dev->buffer->access->set_bytes_per_datum) |
| 481 | indio_dev->buffer->access-> |
| 482 | set_bytes_per_datum(indio_dev->buffer, d_size); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 483 | |
| 484 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | |
| 485 | AD7192_MODE_SEL(AD7192_MODE_CONT); |
| 486 | st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | |
| 487 | AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address); |
| 488 | |
| 489 | ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); |
| 490 | |
| 491 | spi_bus_lock(st->spi->master); |
| 492 | __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode); |
| 493 | |
| 494 | st->irq_dis = false; |
| 495 | enable_irq(st->spi->irq); |
| 496 | |
| 497 | return 0; |
| 498 | } |
| 499 | |
| 500 | static int ad7192_ring_postdisable(struct iio_dev *indio_dev) |
| 501 | { |
| 502 | struct ad7192_state *st = iio_priv(indio_dev); |
| 503 | |
| 504 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | |
| 505 | AD7192_MODE_SEL(AD7192_MODE_IDLE); |
| 506 | |
| 507 | st->done = false; |
| 508 | wait_event_interruptible(st->wq_data_avail, st->done); |
| 509 | |
| 510 | if (!st->irq_dis) |
| 511 | disable_irq_nosync(st->spi->irq); |
| 512 | |
| 513 | __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode); |
| 514 | |
| 515 | return spi_bus_unlock(st->spi->master); |
| 516 | } |
| 517 | |
| 518 | /** |
| 519 | * ad7192_trigger_handler() bh of trigger launched polling to ring buffer |
| 520 | **/ |
| 521 | static irqreturn_t ad7192_trigger_handler(int irq, void *p) |
| 522 | { |
| 523 | struct iio_poll_func *pf = p; |
Jonathan Cameron | e65bc6a | 2011-08-24 17:28:36 +0100 | [diff] [blame] | 524 | struct iio_dev *indio_dev = pf->indio_dev; |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 525 | struct iio_buffer *ring = indio_dev->buffer; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 526 | struct ad7192_state *st = iio_priv(indio_dev); |
| 527 | s64 dat64[2]; |
| 528 | s32 *dat32 = (s32 *)dat64; |
| 529 | |
Jonathan Cameron | 550268c | 2011-12-05 22:18:15 +0000 | [diff] [blame] | 530 | if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 531 | __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA, |
| 532 | dat32, |
| 533 | indio_dev->channels[0].scan_type.realbits/8); |
| 534 | |
| 535 | /* Guaranteed to be aligned with 8 byte boundary */ |
| 536 | if (ring->scan_timestamp) |
| 537 | dat64[1] = pf->timestamp; |
| 538 | |
| 539 | ring->access->store_to(ring, (u8 *)dat64, pf->timestamp); |
| 540 | |
| 541 | iio_trigger_notify_done(indio_dev->trig); |
| 542 | st->irq_dis = false; |
| 543 | enable_irq(st->spi->irq); |
| 544 | |
| 545 | return IRQ_HANDLED; |
| 546 | } |
| 547 | |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 548 | static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 549 | .preenable = &ad7192_ring_preenable, |
Jonathan Cameron | 3b99fb7 | 2011-09-21 11:15:53 +0100 | [diff] [blame] | 550 | .postenable = &iio_triggered_buffer_postenable, |
| 551 | .predisable = &iio_triggered_buffer_predisable, |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 552 | .postdisable = &ad7192_ring_postdisable, |
| 553 | }; |
| 554 | |
| 555 | static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev) |
| 556 | { |
| 557 | int ret; |
| 558 | |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 559 | indio_dev->buffer = iio_sw_rb_allocate(indio_dev); |
| 560 | if (!indio_dev->buffer) { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 561 | ret = -ENOMEM; |
| 562 | goto error_ret; |
| 563 | } |
| 564 | /* Effectively select the ring buffer implementation */ |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 565 | indio_dev->buffer->access = &ring_sw_access_funcs; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 566 | indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time, |
| 567 | &ad7192_trigger_handler, |
| 568 | IRQF_ONESHOT, |
| 569 | indio_dev, |
| 570 | "ad7192_consumer%d", |
| 571 | indio_dev->id); |
| 572 | if (indio_dev->pollfunc == NULL) { |
| 573 | ret = -ENOMEM; |
| 574 | goto error_deallocate_sw_rb; |
| 575 | } |
| 576 | |
| 577 | /* Ring buffer functions - here trigger setup related */ |
Jonathan Cameron | 1612244 | 2011-12-05 22:18:14 +0000 | [diff] [blame] | 578 | indio_dev->setup_ops = &ad7192_ring_setup_ops; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 579 | |
| 580 | /* Flag that polled ring buffering is possible */ |
Jonathan Cameron | ec3afa4 | 2011-09-21 11:15:54 +0100 | [diff] [blame] | 581 | indio_dev->modes |= INDIO_BUFFER_TRIGGERED; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 582 | return 0; |
| 583 | |
| 584 | error_deallocate_sw_rb: |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 585 | iio_sw_rb_free(indio_dev->buffer); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 586 | error_ret: |
| 587 | return ret; |
| 588 | } |
| 589 | |
| 590 | static void ad7192_ring_cleanup(struct iio_dev *indio_dev) |
| 591 | { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 592 | iio_dealloc_pollfunc(indio_dev->pollfunc); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 593 | iio_sw_rb_free(indio_dev->buffer); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | /** |
| 597 | * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig |
| 598 | **/ |
| 599 | static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private) |
| 600 | { |
| 601 | struct ad7192_state *st = iio_priv(private); |
| 602 | |
| 603 | st->done = true; |
| 604 | wake_up_interruptible(&st->wq_data_avail); |
| 605 | disable_irq_nosync(irq); |
| 606 | st->irq_dis = true; |
| 607 | iio_trigger_poll(st->trig, iio_get_time_ns()); |
| 608 | |
| 609 | return IRQ_HANDLED; |
| 610 | } |
| 611 | |
| 612 | static int ad7192_probe_trigger(struct iio_dev *indio_dev) |
| 613 | { |
| 614 | struct ad7192_state *st = iio_priv(indio_dev); |
| 615 | int ret; |
| 616 | |
| 617 | st->trig = iio_allocate_trigger("%s-dev%d", |
| 618 | spi_get_device_id(st->spi)->name, |
| 619 | indio_dev->id); |
| 620 | if (st->trig == NULL) { |
| 621 | ret = -ENOMEM; |
| 622 | goto error_ret; |
| 623 | } |
| 624 | |
| 625 | ret = request_irq(st->spi->irq, |
| 626 | ad7192_data_rdy_trig_poll, |
| 627 | IRQF_TRIGGER_LOW, |
| 628 | spi_get_device_id(st->spi)->name, |
| 629 | indio_dev); |
| 630 | if (ret) |
| 631 | goto error_free_trig; |
| 632 | |
| 633 | disable_irq_nosync(st->spi->irq); |
| 634 | st->irq_dis = true; |
| 635 | st->trig->dev.parent = &st->spi->dev; |
| 636 | st->trig->owner = THIS_MODULE; |
| 637 | st->trig->private_data = indio_dev; |
| 638 | |
| 639 | ret = iio_trigger_register(st->trig); |
| 640 | |
| 641 | /* select default trigger */ |
| 642 | indio_dev->trig = st->trig; |
| 643 | if (ret) |
| 644 | goto error_free_irq; |
| 645 | |
| 646 | return 0; |
| 647 | |
| 648 | error_free_irq: |
| 649 | free_irq(st->spi->irq, indio_dev); |
| 650 | error_free_trig: |
| 651 | iio_free_trigger(st->trig); |
| 652 | error_ret: |
| 653 | return ret; |
| 654 | } |
| 655 | |
| 656 | static void ad7192_remove_trigger(struct iio_dev *indio_dev) |
| 657 | { |
| 658 | struct ad7192_state *st = iio_priv(indio_dev); |
| 659 | |
| 660 | iio_trigger_unregister(st->trig); |
| 661 | free_irq(st->spi->irq, indio_dev); |
| 662 | iio_free_trigger(st->trig); |
| 663 | } |
| 664 | |
| 665 | static ssize_t ad7192_read_frequency(struct device *dev, |
| 666 | struct device_attribute *attr, |
| 667 | char *buf) |
| 668 | { |
| 669 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 670 | struct ad7192_state *st = iio_priv(indio_dev); |
| 671 | |
| 672 | return sprintf(buf, "%d\n", st->mclk / |
| 673 | (st->f_order * 1024 * AD7192_MODE_RATE(st->mode))); |
| 674 | } |
| 675 | |
| 676 | static ssize_t ad7192_write_frequency(struct device *dev, |
| 677 | struct device_attribute *attr, |
| 678 | const char *buf, |
| 679 | size_t len) |
| 680 | { |
| 681 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 682 | struct ad7192_state *st = iio_priv(indio_dev); |
| 683 | unsigned long lval; |
| 684 | int div, ret; |
| 685 | |
| 686 | ret = strict_strtoul(buf, 10, &lval); |
| 687 | if (ret) |
| 688 | return ret; |
| 689 | |
| 690 | mutex_lock(&indio_dev->mlock); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 691 | if (iio_buffer_enabled(indio_dev)) { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 692 | mutex_unlock(&indio_dev->mlock); |
| 693 | return -EBUSY; |
| 694 | } |
| 695 | |
| 696 | div = st->mclk / (lval * st->f_order * 1024); |
| 697 | if (div < 1 || div > 1023) { |
| 698 | ret = -EINVAL; |
| 699 | goto out; |
| 700 | } |
| 701 | |
| 702 | st->mode &= ~AD7192_MODE_RATE(-1); |
| 703 | st->mode |= AD7192_MODE_RATE(div); |
| 704 | ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode); |
| 705 | |
| 706 | out: |
| 707 | mutex_unlock(&indio_dev->mlock); |
| 708 | |
| 709 | return ret ? ret : len; |
| 710 | } |
| 711 | |
| 712 | static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, |
| 713 | ad7192_read_frequency, |
| 714 | ad7192_write_frequency); |
| 715 | |
| 716 | |
| 717 | static ssize_t ad7192_show_scale_available(struct device *dev, |
| 718 | struct device_attribute *attr, char *buf) |
| 719 | { |
| 720 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 721 | struct ad7192_state *st = iio_priv(indio_dev); |
| 722 | int i, len = 0; |
| 723 | |
| 724 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) |
| 725 | len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0], |
| 726 | st->scale_avail[i][1]); |
| 727 | |
| 728 | len += sprintf(buf + len, "\n"); |
| 729 | |
| 730 | return len; |
| 731 | } |
| 732 | |
Jonathan Cameron | 322c956 | 2011-09-14 13:01:23 +0100 | [diff] [blame] | 733 | static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available, |
| 734 | in_voltage-voltage_scale_available, |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 735 | S_IRUGO, ad7192_show_scale_available, NULL, 0); |
| 736 | |
Jonathan Cameron | 322c956 | 2011-09-14 13:01:23 +0100 | [diff] [blame] | 737 | static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 738 | ad7192_show_scale_available, NULL, 0); |
| 739 | |
| 740 | static ssize_t ad7192_show_ac_excitation(struct device *dev, |
| 741 | struct device_attribute *attr, |
| 742 | char *buf) |
| 743 | { |
| 744 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 745 | struct ad7192_state *st = iio_priv(indio_dev); |
| 746 | |
| 747 | return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); |
| 748 | } |
| 749 | |
| 750 | static ssize_t ad7192_show_bridge_switch(struct device *dev, |
| 751 | struct device_attribute *attr, |
| 752 | char *buf) |
| 753 | { |
| 754 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 755 | struct ad7192_state *st = iio_priv(indio_dev); |
| 756 | |
| 757 | return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); |
| 758 | } |
| 759 | |
| 760 | static ssize_t ad7192_set(struct device *dev, |
| 761 | struct device_attribute *attr, |
| 762 | const char *buf, |
| 763 | size_t len) |
| 764 | { |
| 765 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 766 | struct ad7192_state *st = iio_priv(indio_dev); |
| 767 | struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); |
| 768 | int ret; |
| 769 | bool val; |
| 770 | |
| 771 | ret = strtobool(buf, &val); |
| 772 | if (ret < 0) |
| 773 | return ret; |
| 774 | |
| 775 | mutex_lock(&indio_dev->mlock); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 776 | if (iio_buffer_enabled(indio_dev)) { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 777 | mutex_unlock(&indio_dev->mlock); |
| 778 | return -EBUSY; |
| 779 | } |
| 780 | |
Michael Hennerich | e15fbc9 | 2011-10-25 10:51:04 +0200 | [diff] [blame] | 781 | switch ((u32) this_attr->address) { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 782 | case AD7192_REG_GPOCON: |
| 783 | if (val) |
| 784 | st->gpocon |= AD7192_GPOCON_BPDSW; |
| 785 | else |
| 786 | st->gpocon &= ~AD7192_GPOCON_BPDSW; |
| 787 | |
| 788 | ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon); |
| 789 | break; |
| 790 | case AD7192_REG_MODE: |
| 791 | if (val) |
| 792 | st->mode |= AD7192_MODE_ACX; |
| 793 | else |
| 794 | st->mode &= ~AD7192_MODE_ACX; |
| 795 | |
| 796 | ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode); |
| 797 | break; |
| 798 | default: |
| 799 | ret = -EINVAL; |
| 800 | } |
| 801 | |
| 802 | mutex_unlock(&indio_dev->mlock); |
| 803 | |
| 804 | return ret ? ret : len; |
| 805 | } |
| 806 | |
| 807 | static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR, |
| 808 | ad7192_show_bridge_switch, ad7192_set, |
| 809 | AD7192_REG_GPOCON); |
| 810 | |
| 811 | static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR, |
| 812 | ad7192_show_ac_excitation, ad7192_set, |
| 813 | AD7192_REG_MODE); |
| 814 | |
| 815 | static struct attribute *ad7192_attributes[] = { |
| 816 | &iio_dev_attr_sampling_frequency.dev_attr.attr, |
Jonathan Cameron | 322c956 | 2011-09-14 13:01:23 +0100 | [diff] [blame] | 817 | &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr, |
| 818 | &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 819 | &iio_dev_attr_bridge_switch_en.dev_attr.attr, |
| 820 | &iio_dev_attr_ac_excitation_en.dev_attr.attr, |
| 821 | NULL |
| 822 | }; |
| 823 | |
| 824 | static mode_t ad7192_attr_is_visible(struct kobject *kobj, |
| 825 | struct attribute *attr, int n) |
| 826 | { |
| 827 | struct device *dev = container_of(kobj, struct device, kobj); |
Jonathan Cameron | 84f79ec | 2011-10-06 17:14:37 +0100 | [diff] [blame] | 828 | struct iio_dev *indio_dev = dev_get_drvdata(dev); |
| 829 | struct ad7192_state *st = iio_priv(indio_dev); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 830 | |
| 831 | mode_t mode = attr->mode; |
| 832 | |
| 833 | if ((st->devid != ID_AD7195) && |
| 834 | (attr == &iio_dev_attr_ac_excitation_en.dev_attr.attr)) |
| 835 | mode = 0; |
| 836 | |
| 837 | return mode; |
| 838 | } |
| 839 | |
| 840 | static const struct attribute_group ad7192_attribute_group = { |
| 841 | .attrs = ad7192_attributes, |
| 842 | .is_visible = ad7192_attr_is_visible, |
| 843 | }; |
| 844 | |
| 845 | static int ad7192_read_raw(struct iio_dev *indio_dev, |
| 846 | struct iio_chan_spec const *chan, |
| 847 | int *val, |
| 848 | int *val2, |
| 849 | long m) |
| 850 | { |
| 851 | struct ad7192_state *st = iio_priv(indio_dev); |
| 852 | int ret, smpl = 0; |
| 853 | bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); |
| 854 | |
| 855 | switch (m) { |
| 856 | case 0: |
| 857 | mutex_lock(&indio_dev->mlock); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 858 | if (iio_buffer_enabled(indio_dev)) |
Jonathan Cameron | e0f0dda | 2011-12-05 22:18:18 +0000 | [diff] [blame^] | 859 | ret = -EBUSY; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 860 | else |
| 861 | ret = ad7192_read(st, chan->address, |
| 862 | chan->scan_type.realbits / 8, &smpl); |
| 863 | mutex_unlock(&indio_dev->mlock); |
| 864 | |
| 865 | if (ret < 0) |
| 866 | return ret; |
| 867 | |
| 868 | *val = (smpl >> chan->scan_type.shift) & |
| 869 | ((1 << (chan->scan_type.realbits)) - 1); |
| 870 | |
| 871 | switch (chan->type) { |
Jonathan Cameron | ade7ef7 | 2011-09-02 17:14:45 +0100 | [diff] [blame] | 872 | case IIO_VOLTAGE: |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 873 | if (!unipolar) |
| 874 | *val -= (1 << (chan->scan_type.realbits - 1)); |
| 875 | break; |
| 876 | case IIO_TEMP: |
| 877 | *val -= 0x800000; |
| 878 | *val /= 2815; /* temp Kelvin */ |
| 879 | *val -= 273; /* temp Celsius */ |
| 880 | break; |
| 881 | default: |
| 882 | return -EINVAL; |
| 883 | } |
| 884 | return IIO_VAL_INT; |
| 885 | |
Jonathan Cameron | c8a9f80 | 2011-10-26 17:41:36 +0100 | [diff] [blame] | 886 | case IIO_CHAN_INFO_SCALE: |
| 887 | switch (chan->type) { |
| 888 | case IIO_VOLTAGE: |
| 889 | mutex_lock(&indio_dev->mlock); |
| 890 | *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; |
| 891 | *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; |
| 892 | mutex_unlock(&indio_dev->mlock); |
| 893 | return IIO_VAL_INT_PLUS_NANO; |
| 894 | case IIO_TEMP: |
| 895 | *val = 1000; |
| 896 | return IIO_VAL_INT; |
| 897 | default: |
| 898 | return -EINVAL; |
| 899 | } |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 900 | } |
| 901 | |
| 902 | return -EINVAL; |
| 903 | } |
| 904 | |
| 905 | static int ad7192_write_raw(struct iio_dev *indio_dev, |
| 906 | struct iio_chan_spec const *chan, |
| 907 | int val, |
| 908 | int val2, |
| 909 | long mask) |
| 910 | { |
| 911 | struct ad7192_state *st = iio_priv(indio_dev); |
| 912 | int ret, i; |
| 913 | unsigned int tmp; |
| 914 | |
| 915 | mutex_lock(&indio_dev->mlock); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 916 | if (iio_buffer_enabled(indio_dev)) { |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 917 | mutex_unlock(&indio_dev->mlock); |
| 918 | return -EBUSY; |
| 919 | } |
| 920 | |
| 921 | switch (mask) { |
Jonathan Cameron | c8a9f80 | 2011-10-26 17:41:36 +0100 | [diff] [blame] | 922 | case IIO_CHAN_INFO_SCALE: |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 923 | ret = -EINVAL; |
| 924 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) |
| 925 | if (val2 == st->scale_avail[i][1]) { |
| 926 | tmp = st->conf; |
| 927 | st->conf &= ~AD7192_CONF_GAIN(-1); |
| 928 | st->conf |= AD7192_CONF_GAIN(i); |
| 929 | |
| 930 | if (tmp != st->conf) { |
| 931 | ad7192_write_reg(st, AD7192_REG_CONF, |
| 932 | 3, st->conf); |
| 933 | ad7192_calibrate_all(st); |
| 934 | } |
| 935 | ret = 0; |
| 936 | } |
| 937 | |
| 938 | default: |
| 939 | ret = -EINVAL; |
| 940 | } |
| 941 | |
| 942 | mutex_unlock(&indio_dev->mlock); |
| 943 | |
| 944 | return ret; |
| 945 | } |
| 946 | |
| 947 | static int ad7192_validate_trigger(struct iio_dev *indio_dev, |
| 948 | struct iio_trigger *trig) |
| 949 | { |
| 950 | if (indio_dev->trig != trig) |
| 951 | return -EINVAL; |
| 952 | |
| 953 | return 0; |
| 954 | } |
| 955 | |
| 956 | static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, |
| 957 | struct iio_chan_spec const *chan, |
| 958 | long mask) |
| 959 | { |
| 960 | return IIO_VAL_INT_PLUS_NANO; |
| 961 | } |
| 962 | |
| 963 | static const struct iio_info ad7192_info = { |
| 964 | .read_raw = &ad7192_read_raw, |
| 965 | .write_raw = &ad7192_write_raw, |
| 966 | .write_raw_get_fmt = &ad7192_write_raw_get_fmt, |
| 967 | .attrs = &ad7192_attribute_group, |
| 968 | .validate_trigger = ad7192_validate_trigger, |
| 969 | .driver_module = THIS_MODULE, |
| 970 | }; |
| 971 | |
| 972 | #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \ |
Jonathan Cameron | ade7ef7 | 2011-09-02 17:14:45 +0100 | [diff] [blame] | 973 | { .type = IIO_VOLTAGE, \ |
| 974 | .differential = 1, \ |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 975 | .indexed = 1, \ |
| 976 | .extend_name = _name, \ |
| 977 | .channel = _chan, \ |
| 978 | .channel2 = _chan2, \ |
Jonathan Cameron | c8a9f80 | 2011-10-26 17:41:36 +0100 | [diff] [blame] | 979 | .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, \ |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 980 | .address = _address, \ |
| 981 | .scan_index = _si, \ |
| 982 | .scan_type = IIO_ST('s', 24, 32, 0)} |
| 983 | |
| 984 | #define AD7192_CHAN(_chan, _address, _si) \ |
Jonathan Cameron | ade7ef7 | 2011-09-02 17:14:45 +0100 | [diff] [blame] | 985 | { .type = IIO_VOLTAGE, \ |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 986 | .indexed = 1, \ |
| 987 | .channel = _chan, \ |
Jonathan Cameron | c8a9f80 | 2011-10-26 17:41:36 +0100 | [diff] [blame] | 988 | .info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT, \ |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 989 | .address = _address, \ |
| 990 | .scan_index = _si, \ |
| 991 | .scan_type = IIO_ST('s', 24, 32, 0)} |
| 992 | |
| 993 | #define AD7192_CHAN_TEMP(_chan, _address, _si) \ |
| 994 | { .type = IIO_TEMP, \ |
| 995 | .indexed = 1, \ |
| 996 | .channel = _chan, \ |
Jonathan Cameron | c8a9f80 | 2011-10-26 17:41:36 +0100 | [diff] [blame] | 997 | .info_mask = IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \ |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 998 | .address = _address, \ |
| 999 | .scan_index = _si, \ |
| 1000 | .scan_type = IIO_ST('s', 24, 32, 0)} |
| 1001 | |
| 1002 | static struct iio_chan_spec ad7192_channels[] = { |
| 1003 | AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0), |
| 1004 | AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1), |
| 1005 | AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2), |
| 1006 | AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3), |
| 1007 | AD7192_CHAN(1, AD7192_CH_AIN1, 4), |
| 1008 | AD7192_CHAN(2, AD7192_CH_AIN2, 5), |
| 1009 | AD7192_CHAN(3, AD7192_CH_AIN3, 6), |
| 1010 | AD7192_CHAN(4, AD7192_CH_AIN4, 7), |
| 1011 | IIO_CHAN_SOFT_TIMESTAMP(8), |
| 1012 | }; |
| 1013 | |
| 1014 | static int __devinit ad7192_probe(struct spi_device *spi) |
| 1015 | { |
| 1016 | struct ad7192_platform_data *pdata = spi->dev.platform_data; |
| 1017 | struct ad7192_state *st; |
| 1018 | struct iio_dev *indio_dev; |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1019 | int ret, i , voltage_uv = 0; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1020 | |
| 1021 | if (!pdata) { |
| 1022 | dev_err(&spi->dev, "no platform data?\n"); |
| 1023 | return -ENODEV; |
| 1024 | } |
| 1025 | |
| 1026 | if (!spi->irq) { |
| 1027 | dev_err(&spi->dev, "no IRQ?\n"); |
| 1028 | return -ENODEV; |
| 1029 | } |
| 1030 | |
| 1031 | indio_dev = iio_allocate_device(sizeof(*st)); |
| 1032 | if (indio_dev == NULL) |
| 1033 | return -ENOMEM; |
| 1034 | |
| 1035 | st = iio_priv(indio_dev); |
| 1036 | |
| 1037 | st->reg = regulator_get(&spi->dev, "vcc"); |
| 1038 | if (!IS_ERR(st->reg)) { |
| 1039 | ret = regulator_enable(st->reg); |
| 1040 | if (ret) |
| 1041 | goto error_put_reg; |
| 1042 | |
| 1043 | voltage_uv = regulator_get_voltage(st->reg); |
| 1044 | } |
| 1045 | |
| 1046 | st->pdata = pdata; |
| 1047 | |
| 1048 | if (pdata && pdata->vref_mv) |
| 1049 | st->int_vref_mv = pdata->vref_mv; |
| 1050 | else if (voltage_uv) |
| 1051 | st->int_vref_mv = voltage_uv / 1000; |
| 1052 | else |
| 1053 | dev_warn(&spi->dev, "reference voltage undefined\n"); |
| 1054 | |
| 1055 | spi_set_drvdata(spi, indio_dev); |
| 1056 | st->spi = spi; |
| 1057 | st->devid = spi_get_device_id(spi)->driver_data; |
| 1058 | indio_dev->dev.parent = &spi->dev; |
| 1059 | indio_dev->name = spi_get_device_id(spi)->name; |
| 1060 | indio_dev->modes = INDIO_DIRECT_MODE; |
| 1061 | indio_dev->channels = ad7192_channels; |
| 1062 | indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); |
| 1063 | indio_dev->available_scan_masks = st->available_scan_masks; |
| 1064 | indio_dev->info = &ad7192_info; |
| 1065 | |
| 1066 | for (i = 0; i < indio_dev->num_channels; i++) |
| 1067 | st->available_scan_masks[i] = (1 << i) | (1 << |
| 1068 | indio_dev->channels[indio_dev->num_channels - 1]. |
| 1069 | scan_index); |
| 1070 | |
| 1071 | init_waitqueue_head(&st->wq_data_avail); |
| 1072 | |
| 1073 | ret = ad7192_register_ring_funcs_and_init(indio_dev); |
| 1074 | if (ret) |
| 1075 | goto error_disable_reg; |
| 1076 | |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1077 | ret = ad7192_probe_trigger(indio_dev); |
| 1078 | if (ret) |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1079 | goto error_ring_cleanup; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1080 | |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 1081 | ret = iio_buffer_register(indio_dev, |
| 1082 | indio_dev->channels, |
| 1083 | indio_dev->num_channels); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1084 | if (ret) |
| 1085 | goto error_remove_trigger; |
| 1086 | |
| 1087 | ret = ad7192_setup(st); |
| 1088 | if (ret) |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1089 | goto error_unreg_ring; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1090 | |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1091 | ret = iio_device_register(indio_dev); |
| 1092 | if (ret < 0) |
| 1093 | goto error_unreg_ring; |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1094 | return 0; |
| 1095 | |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1096 | error_unreg_ring: |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 1097 | iio_buffer_unregister(indio_dev); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1098 | error_remove_trigger: |
| 1099 | ad7192_remove_trigger(indio_dev); |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1100 | error_ring_cleanup: |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1101 | ad7192_ring_cleanup(indio_dev); |
| 1102 | error_disable_reg: |
| 1103 | if (!IS_ERR(st->reg)) |
| 1104 | regulator_disable(st->reg); |
| 1105 | error_put_reg: |
| 1106 | if (!IS_ERR(st->reg)) |
| 1107 | regulator_put(st->reg); |
| 1108 | |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1109 | iio_free_device(indio_dev); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1110 | |
| 1111 | return ret; |
| 1112 | } |
| 1113 | |
| 1114 | static int ad7192_remove(struct spi_device *spi) |
| 1115 | { |
| 1116 | struct iio_dev *indio_dev = spi_get_drvdata(spi); |
| 1117 | struct ad7192_state *st = iio_priv(indio_dev); |
| 1118 | |
Jonathan Cameron | d2fffd6 | 2011-10-14 14:46:58 +0100 | [diff] [blame] | 1119 | iio_device_unregister(indio_dev); |
Jonathan Cameron | 14555b1 | 2011-09-21 11:15:57 +0100 | [diff] [blame] | 1120 | iio_buffer_unregister(indio_dev); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1121 | ad7192_remove_trigger(indio_dev); |
| 1122 | ad7192_ring_cleanup(indio_dev); |
| 1123 | |
| 1124 | if (!IS_ERR(st->reg)) { |
| 1125 | regulator_disable(st->reg); |
| 1126 | regulator_put(st->reg); |
| 1127 | } |
| 1128 | |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1129 | return 0; |
| 1130 | } |
| 1131 | |
| 1132 | static const struct spi_device_id ad7192_id[] = { |
| 1133 | {"ad7190", ID_AD7190}, |
| 1134 | {"ad7192", ID_AD7192}, |
| 1135 | {"ad7195", ID_AD7195}, |
| 1136 | {} |
| 1137 | }; |
Lars-Peter Clausen | 55e4390 | 2011-11-16 08:53:31 +0100 | [diff] [blame] | 1138 | MODULE_DEVICE_TABLE(spi, ad7192_id); |
Michael Hennerich | 7a27b04 | 2011-08-17 17:29:34 +0200 | [diff] [blame] | 1139 | |
| 1140 | static struct spi_driver ad7192_driver = { |
| 1141 | .driver = { |
| 1142 | .name = "ad7192", |
| 1143 | .owner = THIS_MODULE, |
| 1144 | }, |
| 1145 | .probe = ad7192_probe, |
| 1146 | .remove = __devexit_p(ad7192_remove), |
| 1147 | .id_table = ad7192_id, |
| 1148 | }; |
| 1149 | |
| 1150 | static int __init ad7192_init(void) |
| 1151 | { |
| 1152 | return spi_register_driver(&ad7192_driver); |
| 1153 | } |
| 1154 | module_init(ad7192_init); |
| 1155 | |
| 1156 | static void __exit ad7192_exit(void) |
| 1157 | { |
| 1158 | spi_unregister_driver(&ad7192_driver); |
| 1159 | } |
| 1160 | module_exit(ad7192_exit); |
| 1161 | |
| 1162 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); |
| 1163 | MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC"); |
| 1164 | MODULE_LICENSE("GPL v2"); |