Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 1 | * msm-qpnp-pin |
| 2 | |
| 3 | msm-qpnp-pin is a GPIO chip driver for the MSM SPMI implementation. |
| 4 | It creates a spmi_device for every spmi-dev-container block of device_nodes. |
| 5 | These device_nodes contained within specify the PMIC pin number associated |
| 6 | with each gpio chip. The driver will map these to Linux GPIO numbers. |
| 7 | |
| 8 | [PMIC GPIO Device Declarations] |
| 9 | |
| 10 | -Root Node- |
| 11 | |
| 12 | Required properties : |
| 13 | - spmi-dev-container : Used to specify the following child nodes as part of the |
| 14 | same SPMI device. |
| 15 | - gpio-controller : Specify as gpio-contoller. All child nodes will belong to |
| 16 | this gpio_chip. |
| 17 | - #gpio-cells: We encode a PMIC pin number and a 32-bit flag field to |
| 18 | specify the gpio configuration. This must be set to '2'. |
| 19 | - #address-cells: Specify one address field. This must be set to '1'. |
| 20 | - #size-cells: Specify one size-cell. This must be set to '1'. |
| 21 | - compatible = "qcom,qpnp-pin" : Specify driver matching for this driver. |
Michael Bohan | 6ea2cd2 | 2012-05-29 15:40:18 -0700 | [diff] [blame] | 22 | - label: String giving the name for the gpio_chip device. This name |
| 23 | should be unique on the system and portray the specifics of the device. |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 24 | |
| 25 | -Child Nodes- |
| 26 | |
| 27 | Required properties : |
| 28 | - reg : Specify the spmi offset and size for this pin device. |
| 29 | - qcom,pin-num : Specify the PMIC pin number for this device. |
| 30 | |
| 31 | Optional configuration properties : |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 32 | - qcom,mode: indicates whether the pin should be input, output, or |
| 33 | both for gpios. mpp pins also support bidirectional, |
| 34 | analog in, analog out and current sink. |
| 35 | QPNP_PIN_MODE_DIG_IN = 0, (GPIO/MPP) |
| 36 | QPNP_PIN_MODE_DIG_OUT = 1, (GPIO/MPP) |
| 37 | QPNP_PIN_MODE_DIG_IN_OUT = 2, (GPIO/MPP) |
| 38 | QPNP_PIN_MODE_BIDIR = 3, (MPP) |
| 39 | QPNP_PIN_MODE_AIN = 4, (MPP) |
| 40 | QPNP_PIN_MODE_AOUT = 5, (MPP) |
| 41 | QPNP_PIN_MODE_SINK = 6 (MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 42 | |
| 43 | - qcom,output-type: indicates gpio should be configured as CMOS or open |
| 44 | drain. |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 45 | QPNP_PIN_OUT_BUF_CMOS = 0, (GPIO) |
| 46 | QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS = 1, (GPIO) |
| 47 | QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS = 2 (GPIO) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 48 | |
| 49 | - qcom,invert: Invert the signal of the gpio line - |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 50 | QPNP_PIN_INVERT_DISABLE = 0 (GPIO/MPP) |
| 51 | QPNP_PIN_INVERT_ENABLE = 1 (GPIO/MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 52 | |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 53 | - qcom,pull: This parameter should be programmed to different values |
| 54 | depending on whether it's GPIO or MPP. |
| 55 | For GPIO, it indicates whether a pull up or pull down |
| 56 | should be applied. If a pullup is required the |
| 57 | current strength needs to be specified. |
| 58 | Current values of 30uA, 1.5uA, 31.5uA, 1.5uA with 30uA |
| 59 | boost are supported. This value should be one of |
| 60 | the QPNP_PIN_GPIO_PULL_*. Note that the hardware ignores |
| 61 | this configuration if the GPIO is not set to input or |
| 62 | output open-drain mode. |
| 63 | QPNP_PIN_PULL_UP_30 = 0, (GPIO) |
| 64 | QPNP_PIN_PULL_UP_1P5 = 1, (GPIO) |
| 65 | QPNP_PIN_PULL_UP_31P5 = 2, (GPIO) |
| 66 | QPNP_PIN_PULL_UP_1P5_30 = 3, (GPIO) |
| 67 | QPNP_PIN_PULL_DN = 4, (GPIO) |
| 68 | QPNP_PIN_PULL_NO = 5 (GPIO) |
| 69 | |
| 70 | For MPP, it indicates whether a pullup should be |
| 71 | applied for bidirectitional mode only. The hardware |
| 72 | ignores the configuration when operating in other modes. |
| 73 | This value should be one of the QPNP_PIN_MPP_PULL_*. |
| 74 | |
| 75 | QPNP_PIN_MPP_PULL_UP_0P6KOHM = 0, (MPP) |
| 76 | QPNP_PIN_MPP_PULL_UP_OPEN = 1 (MPP) |
| 77 | QPNP_PIN_MPP_PULL_UP_10KOHM = 2, (MPP) |
| 78 | QPNP_PIN_MPP_PULL_UP_30KOHM = 3, (MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 79 | |
| 80 | - qcom,vin-sel: specifies the voltage level when the output is set to 1. |
| 81 | For an input gpio specifies the voltage level at which |
| 82 | the input is interpreted as a logical 1. |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 83 | QPNP_PIN_VIN0 = 0, (GPIO/MPP) |
| 84 | QPNP_PIN_VIN1 = 1, (GPIO/MPP) |
| 85 | QPNP_PIN_VIN2 = 2, (GPIO/MPP) |
| 86 | QPNP_PIN_VIN3 = 3, (GPIO/MPP) |
| 87 | QPNP_PIN_VIN4 = 4, (GPIO/MPP) |
| 88 | QPNP_PIN_VIN5 = 5, (GPIO/MPP) |
| 89 | QPNP_PIN_VIN6 = 6, (GPIO/MPP) |
| 90 | QPNP_PIN_VIN7 = 7 (GPIO/MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 91 | |
| 92 | - qcom,out-strength: the amount of current supplied for an output gpio. |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 93 | QPNP_PIN_OUT_STRENGTH_LOW = 1 (GPIO) |
| 94 | QPNP_PIN_OUT_STRENGTH_MED = 2, (GPIO) |
| 95 | QPNP_PIN_OUT_STRENGTH_HIGH = 3, (GPIO) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 96 | |
Michael Bohan | 5cda3c9 | 2012-08-14 18:23:59 -0700 | [diff] [blame] | 97 | - qcom,src-select: select a function for the pin. Certain pins |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 98 | can be paired (shorted) with each other. Some gpio pins |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 99 | can act as alternate functions. |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 100 | In the context of gpio, this acts as a source select. |
| 101 | For mpps, this is an enable select. |
| 102 | QPNP_PIN_SEL_FUNC_CONSTANT = 0, (GPIO/MPP) |
| 103 | QPNP_PIN_SEL_FUNC_PAIRED = 1, (GPIO/MPP) |
| 104 | QPNP_PIN_SEL_FUNC_1 = 2, (GPIO/MPP) |
| 105 | QPNP_PIN_SEL_FUNC_2 = 3, (GPIO/MPP) |
| 106 | QPNP_PIN_SEL_DTEST1 = 4, (GPIO/MPP) |
| 107 | QPNP_PIN_SEL_DTEST2 = 5, (GPIO/MPP) |
| 108 | QPNP_PIN_SEL_DTEST3 = 6, (GPIO/MPP) |
| 109 | QPNP_PIN_SEL_DTEST4 = 7 (GPIO/MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 110 | |
| 111 | - qcom,master-en: 1 = Enable features within the |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 112 | pin block based on configurations. (GPIO/MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 113 | 0 = Completely disable the block and |
| 114 | let the pin float with high impedance |
Michael Bohan | 6b90157 | 2012-05-30 13:32:24 -0700 | [diff] [blame] | 115 | regardless of other settings. (GPIO/MPP) |
| 116 | - qcom,aout-ref: set the analog output reference. |
| 117 | |
| 118 | QPNP_PIN_AOUT_1V25 = 0, (MPP) |
| 119 | QPNP_PIN_AOUT_0V625 = 1, (MPP) |
| 120 | QPNP_PIN_AOUT_0V3125 = 2, (MPP) |
| 121 | QPNP_PIN_AOUT_MPP = 3, (MPP) |
| 122 | QPNP_PIN_AOUT_ABUS1 = 4, (MPP) |
| 123 | QPNP_PIN_AOUT_ABUS2 = 5, (MPP) |
| 124 | QPNP_PIN_AOUT_ABUS3 = 6, (MPP) |
| 125 | QPNP_PIN_AOUT_ABUS4 = 7 (MPP) |
| 126 | |
| 127 | - qcom,ain-route: Set the destination for analog input. |
| 128 | QPNP_PIN_AIN_AMUX_CH5 = 0, (MPP) |
| 129 | QPNP_PIN_AIN_AMUX_CH6 = 1, (MPP) |
| 130 | QPNP_PIN_AIN_AMUX_CH7 = 2, (MPP) |
| 131 | QPNP_PIN_AIN_AMUX_CH8 = 3, (MPP) |
| 132 | QPNP_PIN_AIN_AMUX_ABUS1 = 4, (MPP) |
| 133 | QPNP_PIN_AIN_AMUX_ABUS2 = 5, (MPP) |
| 134 | QPNP_PIN_AIN_AMUX_ABUS3 = 6, (MPP) |
| 135 | QPNP_PIN_AIN_AMUX_ABUS4 = 7 (MPP) |
| 136 | |
| 137 | - qcom,cs-out: Set the the amount of output to sync in mA. |
| 138 | QPNP_PIN_CS_OUT_5MA = 0, (MPP) |
| 139 | QPNP_PIN_CS_OUT_10MA = 1, (MPP) |
| 140 | QPNP_PIN_CS_OUT_15MA = 2, (MPP) |
| 141 | QPNP_PIN_CS_OUT_20MA = 3, (MPP) |
| 142 | QPNP_PIN_CS_OUT_25MA = 4, (MPP) |
| 143 | QPNP_PIN_CS_OUT_30MA = 5, (MPP) |
| 144 | QPNP_PIN_CS_OUT_35MA = 6, (MPP) |
| 145 | QPNP_PIN_CS_OUT_40MA = 7 (MPP) |
Michael Bohan | a05f455 | 2012-05-24 15:58:11 -0700 | [diff] [blame] | 146 | |
| 147 | *Note: If any of the configuration properties are not specified, then the |
| 148 | qpnp-pin driver will not modify that respective configuration in |
| 149 | hardware. |
| 150 | |
| 151 | [PMIC GPIO clients] |
| 152 | |
| 153 | Required properties : |
| 154 | - gpios : Contains 3 fields of the form <&gpio_controller pmic_pin_num flags> |
| 155 | |
| 156 | [Example] |
| 157 | |
| 158 | qpnp: qcom,spmi@fc4c0000 { |
| 159 | #address-cells = <1>; |
| 160 | #size-cells = <0>; |
| 161 | interrupt-controller; |
| 162 | #interrupt-cells = <3>; |
| 163 | |
| 164 | qcom,pm8941@0 { |
| 165 | spmi-slave-container; |
| 166 | reg = <0x0>; |
| 167 | #address-cells = <1>; |
| 168 | #size-cells = <1>; |
| 169 | |
| 170 | pm8941_gpios: gpios { |
| 171 | spmi-dev-container; |
| 172 | compatible = "qcom,qpnp-pin"; |
| 173 | gpio-controller; |
| 174 | #gpio-cells = <2>; |
| 175 | #address-cells = <1>; |
| 176 | #size-cells = <1>; |
| 177 | |
| 178 | gpio@c000 { |
| 179 | reg = <0xc000 0x100>; |
| 180 | qcom,pin-num = <62>; |
| 181 | }; |
| 182 | |
| 183 | gpio@c100 { |
| 184 | reg = <0xc100 0x100>; |
| 185 | qcom,pin-num = <20>; |
| 186 | qcom,source_sel = <2>; |
| 187 | qcom,pull = <5>; |
| 188 | }; |
| 189 | }; |
| 190 | |
| 191 | qcom,testgpio@1000 { |
| 192 | compatible = "qcom,qpnp-testgpio"; |
| 193 | reg = <0x1000 0x1000>; |
| 194 | gpios = <&pm8941_gpios 62 0x0 &pm8941_gpios 20 0x1>; |
| 195 | }; |
| 196 | }; |
| 197 | }; |
| 198 | }; |