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Kevin Chan1d5fd4a2013-01-11 14:08:14 -08001#ifndef MSM_CAM_ISPIF_H
2#define MSM_CAM_ISPIF_H
3
4#define CSID_VERSION_V2 0x02000011
5#define CSID_VERSION_V3 0x30000000
6
7enum msm_ispif_vfe_intf {
8 VFE0,
9 VFE1,
10 VFE_MAX
11};
12#define VFE0_MASK (1 << VFE0)
13#define VFE1_MASK (1 << VFE1)
14
15enum msm_ispif_intftype {
16 PIX0,
17 RDI0,
18 PIX1,
19 RDI1,
20 RDI2,
21 INTF_MAX
22};
Mingcheng Zhu8d117332013-04-01 12:05:56 -070023#define MAX_PARAM_ENTRIES (INTF_MAX * 2)
24
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080025#define PIX0_MASK (1 << PIX0)
26#define PIX1_MASK (1 << PIX1)
27#define RDI0_MASK (1 << RDI0)
28#define RDI1_MASK (1 << RDI1)
29#define RDI2_MASK (1 << RDI2)
30
31
32enum msm_ispif_vc {
33 VC0,
34 VC1,
35 VC2,
36 VC3,
37 VC_MAX
38};
39
40enum msm_ispif_cid {
41 CID0,
42 CID1,
43 CID2,
44 CID3,
45 CID4,
46 CID5,
47 CID6,
48 CID7,
49 CID8,
50 CID9,
51 CID10,
52 CID11,
53 CID12,
54 CID13,
55 CID14,
56 CID15,
57 CID_MAX
58};
59
60enum msm_ispif_csid {
61 CSID0,
62 CSID1,
63 CSID2,
64 CSID3,
65 CSID_MAX
66};
67
68struct msm_ispif_params_entry {
Mingcheng Zhu1329a6c2013-03-29 18:09:49 -070069 enum msm_ispif_vfe_intf vfe_intf;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080070 enum msm_ispif_intftype intftype;
71 int num_cids;
72 enum msm_ispif_cid cids[3];
73 enum msm_ispif_csid csid;
Mingcheng Zhu43fe0982013-03-29 18:11:08 -070074 int crop_enable;
75 uint16_t crop_start_pixel;
76 uint16_t crop_end_pixel;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080077};
78
79struct msm_ispif_param_data {
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080080 uint32_t num;
Mingcheng Zhu8d117332013-04-01 12:05:56 -070081 struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080082};
83
Vladislav Hristovb9a0b332013-03-18 10:11:46 -070084struct msm_isp_info {
85 uint32_t max_resolution;
86 uint32_t id;
87 uint32_t ver;
88};
89
90struct msm_ispif_vfe_info {
91 int num_vfe;
92 struct msm_isp_info info[VFE_MAX];
93};
94
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080095enum ispif_cfg_type_t {
96 ISPIF_CLK_ENABLE,
97 ISPIF_CLK_DISABLE,
98 ISPIF_INIT,
99 ISPIF_CFG,
100 ISPIF_START_FRAME_BOUNDARY,
101 ISPIF_STOP_FRAME_BOUNDARY,
102 ISPIF_STOP_IMMEDIATELY,
103 ISPIF_RELEASE,
104 ISPIF_ENABLE_REG_DUMP,
Vladislav Hristovb9a0b332013-03-18 10:11:46 -0700105 ISPIF_SET_VFE_INFO,
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800106};
107
108struct ispif_cfg_data {
109 enum ispif_cfg_type_t cfg_type;
110 union {
111 int reg_dump; /* ISPIF_ENABLE_REG_DUMP */
112 uint32_t csid_version; /* ISPIF_INIT */
Vladislav Hristovb9a0b332013-03-18 10:11:46 -0700113 struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800114 struct msm_ispif_param_data params; /* CFG, START, STOP */
115 };
116};
117
118#define VIDIOC_MSM_ISPIF_CFG \
119 _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
120
121#endif /* MSM_CAM_ISPIF_H */