blob: 427c7b8c9d25e883d0f101e9724a26ed6dcf1211 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/*
2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18
19#include <linux/dma-mapping.h>
20#include <asm/clkdev.h>
21#include <mach/irqs.h>
22#include <mach/msm_iomap.h>
23#include <mach/dma.h>
24#include <mach/board.h>
25
26#include "devices.h"
27#include "smd_private.h"
28
29#include <asm/mach/flash.h>
30
31#include <asm/mach/mmc.h>
32#include <mach/msm_hsusb.h>
33#include <mach/usbdiag.h>
34#include <mach/usb_gadget_fserial.h>
35#include <mach/rpc_hsusb.h>
36
37#include "clock-pcom.h"
38
39static struct resource resources_uart1[] = {
40 {
41 .start = INT_UART1,
42 .end = INT_UART1,
43 .flags = IORESOURCE_IRQ,
44 },
45 {
46 .start = MSM_UART1_PHYS,
47 .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
48 .flags = IORESOURCE_MEM,
49 },
50};
51
52static struct resource resources_uart2[] = {
53 {
54 .start = INT_UART2,
55 .end = INT_UART2,
56 .flags = IORESOURCE_IRQ,
57 },
58 {
59 .start = MSM_UART2_PHYS,
60 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
61 .flags = IORESOURCE_MEM,
62 },
63};
64
65static struct resource resources_uart3[] = {
66 {
67 .start = INT_UART3,
68 .end = INT_UART3,
69 .flags = IORESOURCE_IRQ,
70 },
71 {
72 .start = MSM_UART3_PHYS,
73 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
74 .flags = IORESOURCE_MEM,
75 },
76};
77
78struct platform_device msm_device_uart1 = {
79 .name = "msm_serial",
80 .id = 0,
81 .num_resources = ARRAY_SIZE(resources_uart1),
82 .resource = resources_uart1,
83};
84
85struct platform_device msm_device_uart2 = {
86 .name = "msm_serial",
87 .id = 1,
88 .num_resources = ARRAY_SIZE(resources_uart2),
89 .resource = resources_uart2,
90};
91
92struct platform_device msm_device_uart3 = {
93 .name = "msm_serial",
94 .id = 2,
95 .num_resources = ARRAY_SIZE(resources_uart3),
96 .resource = resources_uart3,
97};
98
99#define MSM_UART1DM_PHYS 0xA0200000
100#define MSM_UART2DM_PHYS 0xA0300000
101static struct resource msm_uart1_dm_resources[] = {
102 {
103 .start = MSM_UART1DM_PHYS,
104 .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
105 .flags = IORESOURCE_MEM,
106 },
107 {
108 .start = INT_UART1DM_IRQ,
109 .end = INT_UART1DM_IRQ,
110 .flags = IORESOURCE_IRQ,
111 },
112 {
113 .start = INT_UART1DM_RX,
114 .end = INT_UART1DM_RX,
115 .flags = IORESOURCE_IRQ,
116 },
117 {
118 .start = DMOV_HSUART1_TX_CHAN,
119 .end = DMOV_HSUART1_RX_CHAN,
120 .name = "uartdm_channels",
121 .flags = IORESOURCE_DMA,
122 },
123 {
124 .start = DMOV_HSUART1_TX_CRCI,
125 .end = DMOV_HSUART1_RX_CRCI,
126 .name = "uartdm_crci",
127 .flags = IORESOURCE_DMA,
128 },
129};
130
131static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32);
132
133struct platform_device msm_device_uart_dm1 = {
134 .name = "msm_serial_hs",
135 .id = 0,
136 .num_resources = ARRAY_SIZE(msm_uart1_dm_resources),
137 .resource = msm_uart1_dm_resources,
138 .dev = {
139 .dma_mask = &msm_uart_dm1_dma_mask,
140 .coherent_dma_mask = DMA_BIT_MASK(32),
141 },
142};
143
144static struct resource msm_uart2_dm_resources[] = {
145 {
146 .start = MSM_UART2DM_PHYS,
147 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 {
151 .start = INT_UART2DM_IRQ,
152 .end = INT_UART2DM_IRQ,
153 .flags = IORESOURCE_IRQ,
154 },
155 {
156 .start = INT_UART2DM_RX,
157 .end = INT_UART2DM_RX,
158 .flags = IORESOURCE_IRQ,
159 },
160 {
161 .start = DMOV_HSUART2_TX_CHAN,
162 .end = DMOV_HSUART2_RX_CHAN,
163 .name = "uartdm_channels",
164 .flags = IORESOURCE_DMA,
165 },
166 {
167 .start = DMOV_HSUART2_TX_CRCI,
168 .end = DMOV_HSUART2_RX_CRCI,
169 .name = "uartdm_crci",
170 .flags = IORESOURCE_DMA,
171 },
172};
173
174static u64 msm_uart_dm2_dma_mask = DMA_BIT_MASK(32);
175
176struct platform_device msm_device_uart_dm2 = {
177 .name = "msm_serial_hs",
178 .id = 1,
179 .num_resources = ARRAY_SIZE(msm_uart2_dm_resources),
180 .resource = msm_uart2_dm_resources,
181 .dev = {
182 .dma_mask = &msm_uart_dm2_dma_mask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187#define MSM_I2C_SIZE SZ_4K
188#define MSM_I2C_PHYS 0xA9900000
189static struct resource resources_i2c[] = {
190 {
191 .start = MSM_I2C_PHYS,
192 .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .start = INT_PWB_I2C,
197 .end = INT_PWB_I2C,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202struct platform_device msm_device_i2c = {
203 .name = "msm_i2c",
204 .id = 0,
205 .num_resources = ARRAY_SIZE(resources_i2c),
206 .resource = resources_i2c,
207};
208
209#define MSM_HSUSB_PHYS 0xA0800000
210static struct resource resources_hsusb_otg[] = {
211 {
212 .start = MSM_HSUSB_PHYS,
213 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 {
217 .start = INT_USB_HS,
218 .end = INT_USB_HS,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static u64 dma_mask = 0xffffffffULL;
224struct platform_device msm_device_hsusb_otg = {
225 .name = "msm_hsusb_otg",
226 .id = -1,
227 .num_resources = ARRAY_SIZE(resources_hsusb_otg),
228 .resource = resources_hsusb_otg,
229 .dev = {
230 .dma_mask = &dma_mask,
231 .coherent_dma_mask = 0xffffffffULL,
232 },
233};
234
235static struct resource resources_hsusb_peripheral[] = {
236 {
237 .start = MSM_HSUSB_PHYS,
238 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
239 .flags = IORESOURCE_MEM,
240 },
241 {
242 .start = INT_USB_HS,
243 .end = INT_USB_HS,
244 .flags = IORESOURCE_IRQ,
245 },
246};
247
248static struct resource resources_gadget_peripheral[] = {
249 {
250 .start = MSM_HSUSB_PHYS,
251 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 {
255 .start = INT_USB_HS,
256 .end = INT_USB_HS,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261struct platform_device msm_device_hsusb_peripheral = {
262 .name = "msm_hsusb_peripheral",
263 .id = -1,
264 .num_resources = ARRAY_SIZE(resources_hsusb_peripheral),
265 .resource = resources_hsusb_peripheral,
266 .dev = {
267 .dma_mask = &dma_mask,
268 .coherent_dma_mask = 0xffffffffULL,
269 },
270};
271
272struct platform_device msm_device_gadget_peripheral = {
273 .name = "msm_hsusb",
274 .id = -1,
275 .num_resources = ARRAY_SIZE(resources_gadget_peripheral),
276 .resource = resources_gadget_peripheral,
277 .dev = {
278 .dma_mask = &dma_mask,
279 .coherent_dma_mask = 0xffffffffULL,
280 },
281};
282
283static struct resource resources_hsusb_host[] = {
284 {
285 .start = MSM_HSUSB_PHYS,
286 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
287 .flags = IORESOURCE_MEM,
288 },
289 {
290 .start = INT_USB_HS,
291 .end = INT_USB_HS,
292 .flags = IORESOURCE_IRQ,
293 },
294};
295
296struct platform_device msm_device_hsusb_host = {
297 .name = "msm_hsusb_host",
298 .id = 0,
299 .num_resources = ARRAY_SIZE(resources_hsusb_host),
300 .resource = resources_hsusb_host,
301 .dev = {
302 .dma_mask = &dma_mask,
303 .coherent_dma_mask = 0xffffffffULL,
304 },
305};
306
307static struct platform_device *msm_host_devices[] = {
308 &msm_device_hsusb_host,
309};
310
311int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat)
312{
313 struct platform_device *pdev;
314
315 pdev = msm_host_devices[host];
316 if (!pdev)
317 return -ENODEV;
318 pdev->dev.platform_data = plat;
319 return platform_device_register(pdev);
320}
321
322#ifdef CONFIG_USB_ANDROID_DIAG
323struct usb_diag_platform_data usb_diag_pdata = {
324 .ch_name = DIAG_LEGACY,
325 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
326};
327
328struct platform_device usb_diag_device = {
329 .name = "usb_diag",
330 .id = -1,
331 .dev = {
332 .platform_data = &usb_diag_pdata,
333 },
334};
335#endif
336
337#ifdef CONFIG_USB_F_SERIAL
338static struct usb_gadget_fserial_platform_data fserial_pdata = {
339 .no_ports = 2,
340};
341
342struct platform_device usb_gadget_fserial_device = {
343 .name = "usb_fserial",
344 .id = -1,
345 .dev = {
346 .platform_data = &fserial_pdata,
347 },
348};
349#endif
350
351#define MSM_NAND_PHYS 0xA0A00000
352static struct resource resources_nand[] = {
353 [0] = {
354 .name = "msm_nand_dmac",
355 .start = DMOV_NAND_CHAN,
356 .end = DMOV_NAND_CHAN,
357 .flags = IORESOURCE_DMA,
358 },
359 [1] = {
360 .name = "msm_nand_phys",
361 .start = MSM_NAND_PHYS,
362 .end = MSM_NAND_PHYS + 0x7FF,
363 .flags = IORESOURCE_MEM,
364 },
365};
366
367static struct resource resources_otg[] = {
368 {
369 .start = MSM_HSUSB_PHYS,
370 .end = MSM_HSUSB_PHYS + SZ_1K - 1,
371 .flags = IORESOURCE_MEM,
372 },
373 {
374 .start = INT_USB_HS,
375 .end = INT_USB_HS,
376 .flags = IORESOURCE_IRQ,
377 },
378};
379
380struct platform_device msm_device_otg = {
381 .name = "msm_otg",
382 .id = -1,
383 .num_resources = ARRAY_SIZE(resources_otg),
384 .resource = resources_otg,
385 .dev = {
386 .coherent_dma_mask = 0xffffffffULL,
387 },
388};
389
390struct flash_platform_data msm_nand_data = {
391 .parts = NULL,
392 .nr_parts = 0,
393};
394
395struct platform_device msm_device_nand = {
396 .name = "msm_nand",
397 .id = -1,
398 .num_resources = ARRAY_SIZE(resources_nand),
399 .resource = resources_nand,
400 .dev = {
401 .platform_data = &msm_nand_data,
402 },
403};
404
405struct platform_device msm_device_smd = {
406 .name = "msm_smd",
407 .id = -1,
408};
409
410struct resource msm_dmov_resource[] = {
411 {
412 .start = INT_ADM_AARM,
413 .end = (resource_size_t)MSM_DMOV_BASE,
414 .flags = IORESOURCE_IRQ,
415 },
416};
417
418struct platform_device msm_device_dmov = {
419 .name = "msm_dmov",
420 .id = -1,
421 .resource = msm_dmov_resource,
422 .num_resources = ARRAY_SIZE(msm_dmov_resource),
423};
424
425#define MSM_SDC1_BASE 0xA0400000
426#define MSM_SDC2_BASE 0xA0500000
427#define MSM_SDC3_BASE 0xA0600000
428#define MSM_SDC4_BASE 0xA0700000
429static struct resource resources_sdc1[] = {
430 {
431 .start = MSM_SDC1_BASE,
432 .end = MSM_SDC1_BASE + SZ_4K - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 {
436 .start = INT_SDC1_0,
437 .end = INT_SDC1_1,
438 .flags = IORESOURCE_IRQ,
439 },
440 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700441 .name = "sdcc_dma_chnl",
442 .start = DMOV_SDC1_CHAN,
443 .end = DMOV_SDC1_CHAN,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700444 .flags = IORESOURCE_DMA,
445 },
Krishna Konda25786ec2011-07-25 16:21:36 -0700446 {
447 .name = "sdcc_dma_crci",
448 .start = DMOV_SDC1_CRCI,
449 .end = DMOV_SDC1_CRCI,
450 .flags = IORESOURCE_DMA,
451 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700452};
453
454static struct resource resources_sdc2[] = {
455 {
456 .start = MSM_SDC2_BASE,
457 .end = MSM_SDC2_BASE + SZ_4K - 1,
458 .flags = IORESOURCE_MEM,
459 },
460 {
461 .start = INT_SDC2_0,
462 .end = INT_SDC2_1,
463 .flags = IORESOURCE_IRQ,
464 },
465 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700466 .name = "sdcc_dma_chnl",
467 .start = DMOV_SDC2_CHAN,
468 .end = DMOV_SDC2_CHAN,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700469 .flags = IORESOURCE_DMA,
470 },
Krishna Konda25786ec2011-07-25 16:21:36 -0700471 {
472 .name = "sdcc_dma_crci",
473 .start = DMOV_SDC2_CRCI,
474 .end = DMOV_SDC2_CRCI,
475 .flags = IORESOURCE_DMA,
476 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700477};
478
479static struct resource resources_sdc3[] = {
480 {
481 .start = MSM_SDC3_BASE,
482 .end = MSM_SDC3_BASE + SZ_4K - 1,
483 .flags = IORESOURCE_MEM,
484 },
485 {
486 .start = INT_SDC3_0,
487 .end = INT_SDC3_1,
488 .flags = IORESOURCE_IRQ,
489 },
490 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700491 .name = "sdcc_dma_chnl",
492 .start = DMOV_SDC3_CHAN,
493 .end = DMOV_SDC3_CHAN,
494 .flags = IORESOURCE_DMA,
495 },
496 {
497 .name = "sdcc_dma_crci",
498 .start = DMOV_SDC3_CRCI,
499 .end = DMOV_SDC3_CRCI,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700500 .flags = IORESOURCE_DMA,
501 },
502};
503
504static struct resource resources_sdc4[] = {
505 {
506 .start = MSM_SDC4_BASE,
507 .end = MSM_SDC4_BASE + SZ_4K - 1,
508 .flags = IORESOURCE_MEM,
509 },
510 {
511 .start = INT_SDC4_0,
512 .end = INT_SDC4_1,
513 .flags = IORESOURCE_IRQ,
514 },
515 {
Krishna Konda25786ec2011-07-25 16:21:36 -0700516 .name = "sdcc_dma_chnl",
517 .start = DMOV_SDC4_CHAN,
518 .end = DMOV_SDC4_CHAN,
519 .flags = IORESOURCE_DMA,
520 },
521 {
522 .name = "sdcc_dma_crci",
523 .start = DMOV_SDC4_CRCI,
524 .end = DMOV_SDC4_CRCI,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700525 .flags = IORESOURCE_DMA,
526 },
527};
528
529struct platform_device msm_device_sdc1 = {
530 .name = "msm_sdcc",
531 .id = 1,
532 .num_resources = ARRAY_SIZE(resources_sdc1),
533 .resource = resources_sdc1,
534 .dev = {
535 .coherent_dma_mask = 0xffffffff,
536 },
537};
538
539struct platform_device msm_device_sdc2 = {
540 .name = "msm_sdcc",
541 .id = 2,
542 .num_resources = ARRAY_SIZE(resources_sdc2),
543 .resource = resources_sdc2,
544 .dev = {
545 .coherent_dma_mask = 0xffffffff,
546 },
547};
548
549struct platform_device msm_device_sdc3 = {
550 .name = "msm_sdcc",
551 .id = 3,
552 .num_resources = ARRAY_SIZE(resources_sdc3),
553 .resource = resources_sdc3,
554 .dev = {
555 .coherent_dma_mask = 0xffffffff,
556 },
557};
558
559struct platform_device msm_device_sdc4 = {
560 .name = "msm_sdcc",
561 .id = 4,
562 .num_resources = ARRAY_SIZE(resources_sdc4),
563 .resource = resources_sdc4,
564 .dev = {
565 .coherent_dma_mask = 0xffffffff,
566 },
567};
568
569static struct platform_device *msm_sdcc_devices[] __initdata = {
570 &msm_device_sdc1,
571 &msm_device_sdc2,
572 &msm_device_sdc3,
573 &msm_device_sdc4,
574};
575
576int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
577{
578 struct platform_device *pdev;
579
580 if (controller < 1 || controller > 4)
581 return -EINVAL;
582
583 pdev = msm_sdcc_devices[controller-1];
584 pdev->dev.platform_data = plat;
585 return platform_device_register(pdev);
586}
587
588#define RAMFS_INFO_MAGICNUMBER 0x654D4D43
589#define RAMFS_INFO_VERSION 0x00000001
590#define RAMFS_MODEMSTORAGE_ID 0x4D454653
591
592static struct resource rmt_storage_resources[] = {
593 {
594 .flags = IORESOURCE_MEM,
595 },
596};
597
598static struct platform_device rmt_storage_device = {
599 .name = "rmt_storage",
600 .id = -1,
601 .num_resources = ARRAY_SIZE(rmt_storage_resources),
602 .resource = rmt_storage_resources,
603};
604
605struct shared_ramfs_entry {
606 uint32_t client_id; /* Client id to uniquely identify a client */
607 uint32_t base_addr; /* Base address of shared RAMFS memory */
608 uint32_t size; /* Size of the shared RAMFS memory */
609 uint32_t reserved; /* Reserved attribute for future use */
610};
611struct shared_ramfs_table {
612 uint32_t magic_id; /* Identify RAMFS details in SMEM */
613 uint32_t version; /* Version of shared_ramfs_table */
614 uint32_t entries; /* Total number of valid entries */
615 struct shared_ramfs_entry ramfs_entry[3]; /* List all entries */
616};
617
618int __init rmt_storage_add_ramfs(void)
619{
620 struct shared_ramfs_table *ramfs_table;
621 struct shared_ramfs_entry *ramfs_entry;
622 int index;
623
624 ramfs_table = smem_alloc(SMEM_SEFS_INFO,
625 sizeof(struct shared_ramfs_table));
626
627 if (!ramfs_table) {
628 printk(KERN_WARNING "%s: No RAMFS table in SMEM\n", __func__);
629 return -ENOENT;
630 }
631
632 if ((ramfs_table->magic_id != (u32) RAMFS_INFO_MAGICNUMBER) ||
633 (ramfs_table->version != (u32) RAMFS_INFO_VERSION)) {
634 printk(KERN_WARNING "%s: Magic / Version mismatch:, "
635 "magic_id=%#x, format_version=%#x\n", __func__,
636 ramfs_table->magic_id, ramfs_table->version);
637 return -ENOENT;
638 }
639
640 for (index = 0; index < ramfs_table->entries; index++) {
641 ramfs_entry = &ramfs_table->ramfs_entry[index];
642
643 /* Find a match for the Modem Storage RAMFS area */
644 if (ramfs_entry->client_id == (u32) RAMFS_MODEMSTORAGE_ID) {
645 printk(KERN_INFO "%s: RAMFS Info (from SMEM): "
646 "Baseaddr = 0x%08x, Size = 0x%08x\n", __func__,
647 ramfs_entry->base_addr, ramfs_entry->size);
648
649 rmt_storage_resources[0].start = ramfs_entry->base_addr;
650 rmt_storage_resources[0].end = ramfs_entry->base_addr +
651 ramfs_entry->size - 1;
652 platform_device_register(&rmt_storage_device);
653 return 0;
654 }
655 }
656 return -ENOENT;
657}
658
659#if defined(CONFIG_FB_MSM_MDP40)
660#define MDP_BASE 0xA3F00000
661#define PMDH_BASE 0xAD600000
662#define EMDH_BASE 0xAD700000
663#define TVENC_BASE 0xAD400000
664#else
665#define MDP_BASE 0xAA200000
666#define PMDH_BASE 0xAA600000
667#define EMDH_BASE 0xAA700000
668#define TVENC_BASE 0xAA400000
669#endif
670
671static struct resource msm_mdp_resources[] = {
672 {
673 .name = "mdp",
674 .start = MDP_BASE,
675 .end = MDP_BASE + 0x000F0000 - 1,
676 .flags = IORESOURCE_MEM,
677 },
678 {
679 .start = INT_MDP,
680 .end = INT_MDP,
681 .flags = IORESOURCE_IRQ,
682 },
683};
684
685static struct resource msm_mddi_resources[] = {
686 {
687 .name = "pmdh",
688 .start = PMDH_BASE,
689 .end = PMDH_BASE + PAGE_SIZE - 1,
690 .flags = IORESOURCE_MEM,
691 }
692};
693
694static struct resource msm_mddi_ext_resources[] = {
695 {
696 .name = "emdh",
697 .start = EMDH_BASE,
698 .end = EMDH_BASE + PAGE_SIZE - 1,
699 .flags = IORESOURCE_MEM,
700 }
701};
702
703static struct resource msm_ebi2_lcd_resources[] = {
704 {
705 .name = "base",
706 .start = 0xa0d00000,
707 .end = 0xa0d00000 + PAGE_SIZE - 1,
708 .flags = IORESOURCE_MEM,
709 },
710 {
711 .name = "lcd01",
712 .start = 0x98000000,
713 .end = 0x98000000 + 0x80000 - 1,
714 .flags = IORESOURCE_MEM,
715 },
716 {
717 .name = "lcd02",
718 .start = 0x9c000000,
719 .end = 0x9c000000 + 0x80000 - 1,
720 .flags = IORESOURCE_MEM,
721 },
722};
723
724static struct resource msm_tvenc_resources[] = {
725 {
726 .name = "tvenc",
727 .start = TVENC_BASE,
728 .end = TVENC_BASE + PAGE_SIZE - 1,
729 .flags = IORESOURCE_MEM,
730 }
731};
732
733static struct platform_device msm_mdp_device = {
734 .name = "mdp",
735 .id = 0,
736 .num_resources = ARRAY_SIZE(msm_mdp_resources),
737 .resource = msm_mdp_resources,
738};
739
740static struct platform_device msm_mddi_device = {
741 .name = "mddi",
742 .id = 0,
743 .num_resources = ARRAY_SIZE(msm_mddi_resources),
744 .resource = msm_mddi_resources,
745};
746
747static struct platform_device msm_mddi_ext_device = {
748 .name = "mddi_ext",
749 .id = 0,
750 .num_resources = ARRAY_SIZE(msm_mddi_ext_resources),
751 .resource = msm_mddi_ext_resources,
752};
753
754static struct platform_device msm_ebi2_lcd_device = {
755 .name = "ebi2_lcd",
756 .id = 0,
757 .num_resources = ARRAY_SIZE(msm_ebi2_lcd_resources),
758 .resource = msm_ebi2_lcd_resources,
759};
760
761static struct platform_device msm_lcdc_device = {
762 .name = "lcdc",
763 .id = 0,
764};
765
766static struct platform_device msm_tvenc_device = {
767 .name = "tvenc",
768 .id = 0,
769 .num_resources = ARRAY_SIZE(msm_tvenc_resources),
770 .resource = msm_tvenc_resources,
771};
772
773/* TSIF begin */
774#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
775
776#define MSM_TSIF_PHYS (0xa0100000)
777#define MSM_TSIF_SIZE (0x200)
778
779static struct resource tsif_resources[] = {
780 [0] = {
781 .flags = IORESOURCE_IRQ,
782 .start = INT_TSIF_IRQ,
783 .end = INT_TSIF_IRQ,
784 },
785 [1] = {
786 .flags = IORESOURCE_MEM,
787 .start = MSM_TSIF_PHYS,
788 .end = MSM_TSIF_PHYS + MSM_TSIF_SIZE - 1,
789 },
790 [2] = {
791 .flags = IORESOURCE_DMA,
792 .start = DMOV_TSIF_CHAN,
793 .end = DMOV_TSIF_CRCI,
794 },
795};
796
797static void tsif_release(struct device *dev)
798{
799 dev_info(dev, "release\n");
800}
801
802struct platform_device msm_device_tsif = {
803 .name = "msm_tsif",
804 .id = 0,
805 .num_resources = ARRAY_SIZE(tsif_resources),
806 .resource = tsif_resources,
807 .dev = {
808 .release = tsif_release,
809 },
810};
811#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
812/* TSIF end */
813
814#define MSM_TSSC_PHYS 0xAA300000
815static struct resource resources_tssc[] = {
816 {
817 .start = MSM_TSSC_PHYS,
818 .end = MSM_TSSC_PHYS + SZ_4K - 1,
819 .name = "tssc",
820 .flags = IORESOURCE_MEM,
821 },
822 {
823 .start = INT_TCHSCRN1,
824 .end = INT_TCHSCRN1,
825 .name = "tssc1",
826 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
827 },
828 {
829 .start = INT_TCHSCRN2,
830 .end = INT_TCHSCRN2,
831 .name = "tssc2",
832 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
833 },
834};
835
836struct platform_device msm_device_tssc = {
837 .name = "msm_touchscreen",
838 .id = 0,
839 .num_resources = ARRAY_SIZE(resources_tssc),
840 .resource = resources_tssc,
841};
842
843static void __init msm_register_device(struct platform_device *pdev, void *data)
844{
845 int ret;
846
847 pdev->dev.platform_data = data;
848
849 ret = platform_device_register(pdev);
850 if (ret)
851 dev_err(&pdev->dev,
852 "%s: platform_device_register() failed = %d\n",
853 __func__, ret);
854}
855
856void __init msm_fb_register_device(char *name, void *data)
857{
858 if (!strncmp(name, "mdp", 3))
859 msm_register_device(&msm_mdp_device, data);
860 else if (!strncmp(name, "pmdh", 4))
861 msm_register_device(&msm_mddi_device, data);
862 else if (!strncmp(name, "emdh", 4))
863 msm_register_device(&msm_mddi_ext_device, data);
864 else if (!strncmp(name, "ebi2", 4))
865 msm_register_device(&msm_ebi2_lcd_device, data);
866 else if (!strncmp(name, "tvenc", 5))
867 msm_register_device(&msm_tvenc_device, data);
868 else if (!strncmp(name, "lcdc", 4))
869 msm_register_device(&msm_lcdc_device, data);
870 else
871 printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
872}
873
874static struct platform_device msm_camera_device = {
875 .name = "msm_camera",
876 .id = 0,
877};
878
879void __init msm_camera_register_device(void *res, uint32_t num,
880 void *data)
881{
882 msm_camera_device.num_resources = num;
883 msm_camera_device.resource = res;
884
885 msm_register_device(&msm_camera_device, data);
886}
887
888static DEFINE_CLK_PCOM(adm_clk, ADM_CLK, 0);
889static DEFINE_CLK_PCOM(adsp_clk, ADSP_CLK, 0);
890static DEFINE_CLK_PCOM(ebi1_clk, EBI1_CLK, CLK_MIN);
891static DEFINE_CLK_PCOM(ebi2_clk, EBI2_CLK, 0);
892static DEFINE_CLK_PCOM(ecodec_clk, ECODEC_CLK, 0);
893static DEFINE_CLK_PCOM(gp_clk, GP_CLK, 0);
894static DEFINE_CLK_PCOM(i2c_clk, I2C_CLK, 0);
895static DEFINE_CLK_PCOM(icodec_rx_clk, ICODEC_RX_CLK, 0);
896static DEFINE_CLK_PCOM(icodec_tx_clk, ICODEC_TX_CLK, 0);
897static DEFINE_CLK_PCOM(imem_clk, IMEM_CLK, OFF);
898static DEFINE_CLK_PCOM(mdc_clk, MDC_CLK, 0);
899static DEFINE_CLK_PCOM(pmdh_clk, PMDH_CLK, OFF | CLK_MINMAX);
900static DEFINE_CLK_PCOM(mdp_clk, MDP_CLK, OFF);
901static DEFINE_CLK_PCOM(mdp_lcdc_pclk_clk, MDP_LCDC_PCLK_CLK, 0);
902static DEFINE_CLK_PCOM(mdp_lcdc_pad_pclk_clk, MDP_LCDC_PAD_PCLK_CLK, 0);
903static DEFINE_CLK_PCOM(mdp_vsync_clk, MDP_VSYNC_CLK, OFF);
904static DEFINE_CLK_PCOM(pbus_clk, PBUS_CLK, CLK_MIN);
905static DEFINE_CLK_PCOM(pcm_clk, PCM_CLK, 0);
906static DEFINE_CLK_PCOM(sdac_clk, SDAC_CLK, OFF);
907static DEFINE_CLK_PCOM(sdc1_clk, SDC1_CLK, OFF);
908static DEFINE_CLK_PCOM(sdc1_p_clk, SDC1_P_CLK, OFF);
909static DEFINE_CLK_PCOM(sdc2_clk, SDC2_CLK, OFF);
910static DEFINE_CLK_PCOM(sdc2_p_clk, SDC2_P_CLK, OFF);
911static DEFINE_CLK_PCOM(sdc3_clk, SDC3_CLK, OFF);
912static DEFINE_CLK_PCOM(sdc3_p_clk, SDC3_P_CLK, OFF);
913static DEFINE_CLK_PCOM(sdc4_clk, SDC4_CLK, OFF);
914static DEFINE_CLK_PCOM(sdc4_p_clk, SDC4_P_CLK, OFF);
915static DEFINE_CLK_PCOM(uart1_clk, UART1_CLK, OFF);
916static DEFINE_CLK_PCOM(uart2_clk, UART2_CLK, 0);
917static DEFINE_CLK_PCOM(uart3_clk, UART3_CLK, OFF);
918static DEFINE_CLK_PCOM(uart1dm_clk, UART1DM_CLK, OFF);
919static DEFINE_CLK_PCOM(uart2dm_clk, UART2DM_CLK, 0);
920static DEFINE_CLK_PCOM(usb_hs_clk, USB_HS_CLK, OFF);
921static DEFINE_CLK_PCOM(usb_hs_p_clk, USB_HS_P_CLK, OFF);
922static DEFINE_CLK_PCOM(usb_otg_clk, USB_OTG_CLK, 0);
923static DEFINE_CLK_PCOM(vdc_clk, VDC_CLK, OFF | CLK_MIN);
924static DEFINE_CLK_PCOM(vfe_clk, VFE_CLK, OFF);
925static DEFINE_CLK_PCOM(vfe_mdc_clk, VFE_MDC_CLK, OFF);
926
927struct clk_lookup msm_clocks_7x25[] = {
928 CLK_LOOKUP("adm_clk", adm_clk.c, NULL),
929 CLK_LOOKUP("adsp_clk", adsp_clk.c, NULL),
930 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
931 CLK_LOOKUP("ebi2_clk", ebi2_clk.c, NULL),
932 CLK_LOOKUP("ecodec_clk", ecodec_clk.c, NULL),
933 CLK_LOOKUP("gp_clk", gp_clk.c, NULL),
934 CLK_LOOKUP("i2c_clk", i2c_clk.c, "msm_i2c.0"),
935 CLK_LOOKUP("icodec_rx_clk", icodec_rx_clk.c, NULL),
936 CLK_LOOKUP("icodec_tx_clk", icodec_tx_clk.c, NULL),
937 CLK_LOOKUP("imem_clk", imem_clk.c, NULL),
938 CLK_LOOKUP("mdc_clk", mdc_clk.c, NULL),
939 CLK_LOOKUP("mddi_clk", pmdh_clk.c, NULL),
940 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
941 CLK_LOOKUP("mdp_lcdc_pclk_clk", mdp_lcdc_pclk_clk.c, NULL),
942 CLK_LOOKUP("mdp_lcdc_pad_pclk_clk", mdp_lcdc_pad_pclk_clk.c, NULL),
943 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
944 CLK_LOOKUP("pbus_clk", pbus_clk.c, NULL),
945 CLK_LOOKUP("pcm_clk", pcm_clk.c, NULL),
946 CLK_LOOKUP("sdac_clk", sdac_clk.c, NULL),
947 CLK_LOOKUP("sdc_clk", sdc1_clk.c, "msm_sdcc.1"),
948 CLK_LOOKUP("sdc_pclk", sdc1_p_clk.c, "msm_sdcc.1"),
949 CLK_LOOKUP("sdc_clk", sdc2_clk.c, "msm_sdcc.2"),
950 CLK_LOOKUP("sdc_pclk", sdc2_p_clk.c, "msm_sdcc.2"),
951 CLK_LOOKUP("sdc_clk", sdc3_clk.c, "msm_sdcc.3"),
952 CLK_LOOKUP("sdc_pclk", sdc3_p_clk.c, "msm_sdcc.3"),
953 CLK_LOOKUP("sdc_clk", sdc4_clk.c, "msm_sdcc.4"),
954 CLK_LOOKUP("sdc_pclk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -0700955 CLK_LOOKUP("core_clk", uart1_clk.c, "msm_serial.0"),
956 CLK_LOOKUP("core_clk", uart2_clk.c, "msm_serial.1"),
957 CLK_LOOKUP("core_clk", uart3_clk.c, "msm_serial.2"),
958 CLK_LOOKUP("core_clk", uart1dm_clk.c, "msm_serial_hs.0"),
959 CLK_LOOKUP("core_clk", uart2dm_clk.c, "msm_serial_hs.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700960 CLK_LOOKUP("usb_hs_clk", usb_hs_clk.c, NULL),
961 CLK_LOOKUP("usb_hs_pclk", usb_hs_p_clk.c, NULL),
962 CLK_LOOKUP("usb_otg_clk", usb_otg_clk.c, NULL),
963 CLK_LOOKUP("vdc_clk", vdc_clk.c, NULL),
964 CLK_LOOKUP("vfe_clk", vfe_clk.c, NULL),
965 CLK_LOOKUP("vfe_mdc_clk", vfe_mdc_clk.c, NULL),
966};
967
968unsigned msm_num_clocks_7x25 = ARRAY_SIZE(msm_clocks_7x25);
969