Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 1 | /* |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 2 | * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 3 | * http://www.samsung.com |
| 4 | * |
| 5 | * EXYNOS4210 - Clock support |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/err.h> |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/io.h> |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 16 | #include <linux/syscore_ops.h> |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 17 | |
| 18 | #include <plat/cpu-freq.h> |
| 19 | #include <plat/clock.h> |
| 20 | #include <plat/cpu.h> |
| 21 | #include <plat/pll.h> |
| 22 | #include <plat/s5p-clock.h> |
| 23 | #include <plat/clock-clksrc.h> |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 24 | #include <plat/pm.h> |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 25 | |
| 26 | #include <mach/hardware.h> |
| 27 | #include <mach/map.h> |
| 28 | #include <mach/regs-clock.h> |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 29 | |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 30 | #include "common.h" |
Kukjin Kim | ce9c00e | 2012-03-09 13:51:24 -0800 | [diff] [blame] | 31 | #include "clock-exynos4.h" |
Kukjin Kim | cc511b8 | 2011-12-27 08:18:36 +0100 | [diff] [blame] | 32 | |
Kukjin Kim | 7cdf04d | 2012-01-27 14:56:17 +0900 | [diff] [blame] | 33 | #ifdef CONFIG_PM_SLEEP |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 34 | static struct sleep_save exynos4210_clock_save[] = { |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 35 | SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE), |
| 36 | SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE), |
| 37 | SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1), |
| 38 | SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1), |
| 39 | SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1), |
| 40 | SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE), |
| 41 | SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1), |
| 42 | SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR), |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 43 | }; |
Kukjin Kim | 7cdf04d | 2012-01-27 14:56:17 +0900 | [diff] [blame] | 44 | #endif |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 45 | |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 46 | static struct clksrc_clk *sysclks[] = { |
| 47 | /* nothing here yet */ |
| 48 | }; |
| 49 | |
| 50 | static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) |
| 51 | { |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 52 | return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable); |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 53 | } |
| 54 | |
| 55 | static struct clksrc_clk clksrcs[] = { |
| 56 | { |
| 57 | .clk = { |
| 58 | .name = "sclk_sata", |
| 59 | .id = -1, |
| 60 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
| 61 | .ctrlbit = (1 << 24), |
| 62 | }, |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 63 | .sources = &exynos4_clkset_mout_corebus, |
| 64 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 }, |
| 65 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 }, |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 66 | }, { |
| 67 | .clk = { |
| 68 | .name = "sclk_fimd", |
| 69 | .devname = "exynos4-fb.1", |
| 70 | .enable = exynos4_clksrc_mask_lcd1_ctrl, |
| 71 | .ctrlbit = (1 << 0), |
| 72 | }, |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 73 | .sources = &exynos4_clkset_group, |
| 74 | .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 }, |
| 75 | .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 }, |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 76 | }, |
| 77 | }; |
| 78 | |
| 79 | static struct clk init_clocks_off[] = { |
| 80 | { |
| 81 | .name = "sataphy", |
| 82 | .id = -1, |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 83 | .parent = &exynos4_clk_aclk_133.clk, |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 84 | .enable = exynos4_clk_ip_fsys_ctrl, |
| 85 | .ctrlbit = (1 << 3), |
| 86 | }, { |
| 87 | .name = "sata", |
| 88 | .id = -1, |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 89 | .parent = &exynos4_clk_aclk_133.clk, |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 90 | .enable = exynos4_clk_ip_fsys_ctrl, |
| 91 | .ctrlbit = (1 << 10), |
| 92 | }, { |
| 93 | .name = "fimd", |
| 94 | .devname = "exynos4-fb.1", |
| 95 | .enable = exynos4_clk_ip_lcd1_ctrl, |
| 96 | .ctrlbit = (1 << 0), |
| 97 | }, |
| 98 | }; |
| 99 | |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 100 | #ifdef CONFIG_PM_SLEEP |
| 101 | static int exynos4210_clock_suspend(void) |
| 102 | { |
| 103 | s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | static void exynos4210_clock_resume(void) |
| 109 | { |
| 110 | s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); |
| 111 | } |
| 112 | |
| 113 | #else |
| 114 | #define exynos4210_clock_suspend NULL |
| 115 | #define exynos4210_clock_resume NULL |
| 116 | #endif |
| 117 | |
Kukjin Kim | e745e06 | 2012-01-21 10:47:14 +0900 | [diff] [blame] | 118 | static struct syscore_ops exynos4210_clock_syscore_ops = { |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 119 | .suspend = exynos4210_clock_suspend, |
| 120 | .resume = exynos4210_clock_resume, |
| 121 | }; |
| 122 | |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 123 | void __init exynos4210_register_clocks(void) |
| 124 | { |
| 125 | int ptr; |
| 126 | |
Kukjin Kim | a855039 | 2012-03-09 14:19:10 -0800 | [diff] [blame] | 127 | exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU; |
| 128 | exynos4_clk_mout_mpll.reg_src.shift = 8; |
| 129 | exynos4_clk_mout_mpll.reg_src.size = 1; |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 130 | |
| 131 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) |
| 132 | s3c_register_clksrc(sysclks[ptr], 1); |
| 133 | |
| 134 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
| 135 | |
| 136 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
| 137 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
Jonghwan Choi | acd3561 | 2011-08-24 21:52:45 +0900 | [diff] [blame] | 138 | |
| 139 | register_syscore_ops(&exynos4210_clock_syscore_ops); |
Kukjin Kim | 2bc02c0 | 2011-08-24 17:25:09 +0900 | [diff] [blame] | 140 | } |