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Kevin Hilmane38d92f2009-04-29 17:44:58 -07001/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15
16#include <mach/dm646x.h>
17#include <mach/clock.h>
18#include <mach/cputype.h>
19#include <mach/edma.h>
20#include <mach/irqs.h>
21#include <mach/psc.h>
22#include <mach/mux.h>
23
24#include "clock.h"
25#include "mux.h"
26
27/*
28 * Device specific clocks
29 */
30#define DM646X_REF_FREQ 27000000
31#define DM646X_AUX_FREQ 24000000
32
33static struct pll_data pll1_data = {
34 .num = 1,
35 .phys_base = DAVINCI_PLL1_BASE,
36};
37
38static struct pll_data pll2_data = {
39 .num = 2,
40 .phys_base = DAVINCI_PLL2_BASE,
41};
42
43static struct clk ref_clk = {
44 .name = "ref_clk",
45 .rate = DM646X_REF_FREQ,
46};
47
48static struct clk aux_clkin = {
49 .name = "aux_clkin",
50 .rate = DM646X_AUX_FREQ,
51};
52
53static struct clk pll1_clk = {
54 .name = "pll1",
55 .parent = &ref_clk,
56 .pll_data = &pll1_data,
57 .flags = CLK_PLL,
58};
59
60static struct clk pll1_sysclk1 = {
61 .name = "pll1_sysclk1",
62 .parent = &pll1_clk,
63 .flags = CLK_PLL,
64 .div_reg = PLLDIV1,
65};
66
67static struct clk pll1_sysclk2 = {
68 .name = "pll1_sysclk2",
69 .parent = &pll1_clk,
70 .flags = CLK_PLL,
71 .div_reg = PLLDIV2,
72};
73
74static struct clk pll1_sysclk3 = {
75 .name = "pll1_sysclk3",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV3,
79};
80
81static struct clk pll1_sysclk4 = {
82 .name = "pll1_sysclk4",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV4,
86};
87
88static struct clk pll1_sysclk5 = {
89 .name = "pll1_sysclk5",
90 .parent = &pll1_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV5,
93};
94
95static struct clk pll1_sysclk6 = {
96 .name = "pll1_sysclk6",
97 .parent = &pll1_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV6,
100};
101
102static struct clk pll1_sysclk8 = {
103 .name = "pll1_sysclk8",
104 .parent = &pll1_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV8,
107};
108
109static struct clk pll1_sysclk9 = {
110 .name = "pll1_sysclk9",
111 .parent = &pll1_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV9,
114};
115
116static struct clk pll1_sysclkbp = {
117 .name = "pll1_sysclkbp",
118 .parent = &pll1_clk,
119 .flags = CLK_PLL | PRE_PLL,
120 .div_reg = BPDIV,
121};
122
123static struct clk pll1_aux_clk = {
124 .name = "pll1_aux_clk",
125 .parent = &pll1_clk,
126 .flags = CLK_PLL | PRE_PLL,
127};
128
129static struct clk pll2_clk = {
130 .name = "pll2_clk",
131 .parent = &ref_clk,
132 .pll_data = &pll2_data,
133 .flags = CLK_PLL,
134};
135
136static struct clk pll2_sysclk1 = {
137 .name = "pll2_sysclk1",
138 .parent = &pll2_clk,
139 .flags = CLK_PLL,
140 .div_reg = PLLDIV1,
141};
142
143static struct clk dsp_clk = {
144 .name = "dsp",
145 .parent = &pll1_sysclk1,
146 .lpsc = DM646X_LPSC_C64X_CPU,
147 .flags = PSC_DSP,
148 .usecount = 1, /* REVISIT how to disable? */
149};
150
151static struct clk arm_clk = {
152 .name = "arm",
153 .parent = &pll1_sysclk2,
154 .lpsc = DM646X_LPSC_ARM,
155 .flags = ALWAYS_ENABLED,
156};
157
158static struct clk uart0_clk = {
159 .name = "uart0",
160 .parent = &aux_clkin,
161 .lpsc = DM646X_LPSC_UART0,
162};
163
164static struct clk uart1_clk = {
165 .name = "uart1",
166 .parent = &aux_clkin,
167 .lpsc = DM646X_LPSC_UART1,
168};
169
170static struct clk uart2_clk = {
171 .name = "uart2",
172 .parent = &aux_clkin,
173 .lpsc = DM646X_LPSC_UART2,
174};
175
176static struct clk i2c_clk = {
177 .name = "I2CCLK",
178 .parent = &pll1_sysclk3,
179 .lpsc = DM646X_LPSC_I2C,
180};
181
182static struct clk gpio_clk = {
183 .name = "gpio",
184 .parent = &pll1_sysclk3,
185 .lpsc = DM646X_LPSC_GPIO,
186};
187
188static struct clk aemif_clk = {
189 .name = "aemif",
190 .parent = &pll1_sysclk3,
191 .lpsc = DM646X_LPSC_AEMIF,
192 .flags = ALWAYS_ENABLED,
193};
194
195static struct clk emac_clk = {
196 .name = "emac",
197 .parent = &pll1_sysclk3,
198 .lpsc = DM646X_LPSC_EMAC,
199};
200
201static struct clk pwm0_clk = {
202 .name = "pwm0",
203 .parent = &pll1_sysclk3,
204 .lpsc = DM646X_LPSC_PWM0,
205 .usecount = 1, /* REVIST: disabling hangs system */
206};
207
208static struct clk pwm1_clk = {
209 .name = "pwm1",
210 .parent = &pll1_sysclk3,
211 .lpsc = DM646X_LPSC_PWM1,
212 .usecount = 1, /* REVIST: disabling hangs system */
213};
214
215static struct clk timer0_clk = {
216 .name = "timer0",
217 .parent = &pll1_sysclk3,
218 .lpsc = DM646X_LPSC_TIMER0,
219};
220
221static struct clk timer1_clk = {
222 .name = "timer1",
223 .parent = &pll1_sysclk3,
224 .lpsc = DM646X_LPSC_TIMER1,
225};
226
227static struct clk timer2_clk = {
228 .name = "timer2",
229 .parent = &pll1_sysclk3,
230 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
231};
232
233static struct clk vpif0_clk = {
234 .name = "vpif0",
235 .parent = &ref_clk,
236 .lpsc = DM646X_LPSC_VPSSMSTR,
237 .flags = ALWAYS_ENABLED,
238};
239
240static struct clk vpif1_clk = {
241 .name = "vpif1",
242 .parent = &ref_clk,
243 .lpsc = DM646X_LPSC_VPSSSLV,
244 .flags = ALWAYS_ENABLED,
245};
246
247struct davinci_clk dm646x_clks[] = {
248 CLK(NULL, "ref", &ref_clk),
249 CLK(NULL, "aux", &aux_clkin),
250 CLK(NULL, "pll1", &pll1_clk),
251 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
252 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
253 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
254 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
255 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
256 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
257 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
258 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
259 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
260 CLK(NULL, "pll1_aux", &pll1_aux_clk),
261 CLK(NULL, "pll2", &pll2_clk),
262 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
263 CLK(NULL, "dsp", &dsp_clk),
264 CLK(NULL, "arm", &arm_clk),
265 CLK(NULL, "uart0", &uart0_clk),
266 CLK(NULL, "uart1", &uart1_clk),
267 CLK(NULL, "uart2", &uart2_clk),
268 CLK("i2c_davinci.1", NULL, &i2c_clk),
269 CLK(NULL, "gpio", &gpio_clk),
270 CLK(NULL, "aemif", &aemif_clk),
271 CLK("davinci_emac.1", NULL, &emac_clk),
272 CLK(NULL, "pwm0", &pwm0_clk),
273 CLK(NULL, "pwm1", &pwm1_clk),
274 CLK(NULL, "timer0", &timer0_clk),
275 CLK(NULL, "timer1", &timer1_clk),
276 CLK("watchdog", NULL, &timer2_clk),
277 CLK(NULL, "vpif0", &vpif0_clk),
278 CLK(NULL, "vpif1", &vpif1_clk),
279 CLK(NULL, NULL, NULL),
280};
281
282/*
283 * Device specific mux setup
284 *
285 * soc description mux mode mode mux dbg
286 * reg offset mask mode
287 */
288static const struct mux_config dm646x_pins[] = {
289MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
290
291MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
292
293MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
294
295MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
296
297MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
298
299MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
300
301MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
302
303MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
304
305MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
306
307MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
308
309MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
310
311MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
312
313MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
314
315MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
316};
317
318/*----------------------------------------------------------------------*/
319
320static const s8 dma_chan_dm646x_no_event[] = {
321 0, 1, 2, 3, 13,
322 14, 15, 24, 25, 26,
323 27, 30, 31, 54, 55,
324 56,
325 -1
326};
327
328static struct edma_soc_info dm646x_edma_info = {
329 .n_channel = 64,
330 .n_region = 6, /* 0-1, 4-7 */
331 .n_slot = 512,
332 .n_tc = 4,
333 .noevent = dma_chan_dm646x_no_event,
334};
335
336static struct resource edma_resources[] = {
337 {
338 .name = "edma_cc",
339 .start = 0x01c00000,
340 .end = 0x01c00000 + SZ_64K - 1,
341 .flags = IORESOURCE_MEM,
342 },
343 {
344 .name = "edma_tc0",
345 .start = 0x01c10000,
346 .end = 0x01c10000 + SZ_1K - 1,
347 .flags = IORESOURCE_MEM,
348 },
349 {
350 .name = "edma_tc1",
351 .start = 0x01c10400,
352 .end = 0x01c10400 + SZ_1K - 1,
353 .flags = IORESOURCE_MEM,
354 },
355 {
356 .name = "edma_tc2",
357 .start = 0x01c10800,
358 .end = 0x01c10800 + SZ_1K - 1,
359 .flags = IORESOURCE_MEM,
360 },
361 {
362 .name = "edma_tc3",
363 .start = 0x01c10c00,
364 .end = 0x01c10c00 + SZ_1K - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 {
368 .start = IRQ_CCINT0,
369 .flags = IORESOURCE_IRQ,
370 },
371 {
372 .start = IRQ_CCERRINT,
373 .flags = IORESOURCE_IRQ,
374 },
375 /* not using TC*_ERR */
376};
377
378static struct platform_device dm646x_edma_device = {
379 .name = "edma",
380 .id = -1,
381 .dev.platform_data = &dm646x_edma_info,
382 .num_resources = ARRAY_SIZE(edma_resources),
383 .resource = edma_resources,
384};
385
386/*----------------------------------------------------------------------*/
387
388void __init dm646x_init(void)
389{
390 davinci_clk_init(dm646x_clks);
391 davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins));
392}
393
394static int __init dm646x_init_devices(void)
395{
396 if (!cpu_is_davinci_dm646x())
397 return 0;
398
399 platform_device_register(&dm646x_edma_device);
400 return 0;
401}
402postcore_initcall(dm646x_init_devices);