Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Philips UCB1400 touchscreen driver |
| 3 | * |
| 4 | * Author: Nicolas Pitre |
| 5 | * Created: September 25, 2006 |
| 6 | * Copyright: MontaVista Software, Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This code is heavily based on ucb1x00-*.c copyrighted by Russell King |
| 13 | * covering the UCB1100, UCB1200 and UCB1300.. Support for the UCB1400 has |
| 14 | * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/module.h> |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 18 | #include <linux/init.h> |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 19 | #include <linux/completion.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/input.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/suspend.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/kthread.h> |
Dmitry Torokhov | bff19b1 | 2006-12-08 01:37:03 -0500 | [diff] [blame] | 27 | #include <linux/freezer.h> |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 28 | |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 29 | #include <sound/core.h> |
| 30 | #include <sound/ac97_codec.h> |
| 31 | |
| 32 | |
| 33 | /* |
| 34 | * Interesting UCB1400 AC-link registers |
| 35 | */ |
| 36 | |
| 37 | #define UCB_IE_RIS 0x5e |
| 38 | #define UCB_IE_FAL 0x60 |
| 39 | #define UCB_IE_STATUS 0x62 |
| 40 | #define UCB_IE_CLEAR 0x62 |
| 41 | #define UCB_IE_ADC (1 << 11) |
| 42 | #define UCB_IE_TSPX (1 << 12) |
| 43 | |
| 44 | #define UCB_TS_CR 0x64 |
| 45 | #define UCB_TS_CR_TSMX_POW (1 << 0) |
| 46 | #define UCB_TS_CR_TSPX_POW (1 << 1) |
| 47 | #define UCB_TS_CR_TSMY_POW (1 << 2) |
| 48 | #define UCB_TS_CR_TSPY_POW (1 << 3) |
| 49 | #define UCB_TS_CR_TSMX_GND (1 << 4) |
| 50 | #define UCB_TS_CR_TSPX_GND (1 << 5) |
| 51 | #define UCB_TS_CR_TSMY_GND (1 << 6) |
| 52 | #define UCB_TS_CR_TSPY_GND (1 << 7) |
| 53 | #define UCB_TS_CR_MODE_INT (0 << 8) |
| 54 | #define UCB_TS_CR_MODE_PRES (1 << 8) |
| 55 | #define UCB_TS_CR_MODE_POS (2 << 8) |
| 56 | #define UCB_TS_CR_BIAS_ENA (1 << 11) |
| 57 | #define UCB_TS_CR_TSPX_LOW (1 << 12) |
| 58 | #define UCB_TS_CR_TSMX_LOW (1 << 13) |
| 59 | |
| 60 | #define UCB_ADC_CR 0x66 |
| 61 | #define UCB_ADC_SYNC_ENA (1 << 0) |
| 62 | #define UCB_ADC_VREFBYP_CON (1 << 1) |
| 63 | #define UCB_ADC_INP_TSPX (0 << 2) |
| 64 | #define UCB_ADC_INP_TSMX (1 << 2) |
| 65 | #define UCB_ADC_INP_TSPY (2 << 2) |
| 66 | #define UCB_ADC_INP_TSMY (3 << 2) |
| 67 | #define UCB_ADC_INP_AD0 (4 << 2) |
| 68 | #define UCB_ADC_INP_AD1 (5 << 2) |
| 69 | #define UCB_ADC_INP_AD2 (6 << 2) |
| 70 | #define UCB_ADC_INP_AD3 (7 << 2) |
| 71 | #define UCB_ADC_EXT_REF (1 << 5) |
| 72 | #define UCB_ADC_START (1 << 7) |
| 73 | #define UCB_ADC_ENA (1 << 15) |
| 74 | |
| 75 | #define UCB_ADC_DATA 0x68 |
| 76 | #define UCB_ADC_DAT_VALID (1 << 15) |
| 77 | #define UCB_ADC_DAT_VALUE(x) ((x) & 0x3ff) |
| 78 | |
| 79 | #define UCB_ID 0x7e |
| 80 | #define UCB_ID_1400 0x4304 |
| 81 | |
| 82 | |
| 83 | struct ucb1400 { |
Andrew Morton | ca377fe | 2006-12-15 09:26:20 +0100 | [diff] [blame] | 84 | struct snd_ac97 *ac97; |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 85 | struct input_dev *ts_idev; |
| 86 | |
| 87 | int irq; |
| 88 | |
| 89 | wait_queue_head_t ts_wait; |
| 90 | struct task_struct *ts_task; |
| 91 | |
| 92 | unsigned int irq_pending; /* not bit field shared */ |
| 93 | unsigned int ts_restart:1; |
| 94 | unsigned int adcsync:1; |
| 95 | }; |
| 96 | |
| 97 | static int adcsync; |
Cliff Brake | b5b16c5 | 2007-04-12 01:35:43 -0400 | [diff] [blame] | 98 | static int ts_delay = 55; /* us */ |
| 99 | static int ts_delay_pressure; /* us */ |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 100 | |
| 101 | static inline u16 ucb1400_reg_read(struct ucb1400 *ucb, u16 reg) |
| 102 | { |
| 103 | return ucb->ac97->bus->ops->read(ucb->ac97, reg); |
| 104 | } |
| 105 | |
| 106 | static inline void ucb1400_reg_write(struct ucb1400 *ucb, u16 reg, u16 val) |
| 107 | { |
| 108 | ucb->ac97->bus->ops->write(ucb->ac97, reg, val); |
| 109 | } |
| 110 | |
| 111 | static inline void ucb1400_adc_enable(struct ucb1400 *ucb) |
| 112 | { |
| 113 | ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); |
| 114 | } |
| 115 | |
| 116 | static unsigned int ucb1400_adc_read(struct ucb1400 *ucb, u16 adc_channel) |
| 117 | { |
| 118 | unsigned int val; |
| 119 | |
| 120 | if (ucb->adcsync) |
| 121 | adc_channel |= UCB_ADC_SYNC_ENA; |
| 122 | |
| 123 | ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel); |
| 124 | ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel | UCB_ADC_START); |
| 125 | |
| 126 | for (;;) { |
| 127 | val = ucb1400_reg_read(ucb, UCB_ADC_DATA); |
| 128 | if (val & UCB_ADC_DAT_VALID) |
| 129 | break; |
| 130 | /* yield to other processes */ |
Rene Herman | 1788180 | 2007-09-26 00:02:19 -0400 | [diff] [blame] | 131 | schedule_timeout_uninterruptible(1); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 132 | } |
| 133 | |
| 134 | return UCB_ADC_DAT_VALUE(val); |
| 135 | } |
| 136 | |
| 137 | static inline void ucb1400_adc_disable(struct ucb1400 *ucb) |
| 138 | { |
| 139 | ucb1400_reg_write(ucb, UCB_ADC_CR, 0); |
| 140 | } |
| 141 | |
| 142 | /* Switch to interrupt mode. */ |
| 143 | static inline void ucb1400_ts_mode_int(struct ucb1400 *ucb) |
| 144 | { |
| 145 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 146 | UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW | |
| 147 | UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND | |
| 148 | UCB_TS_CR_MODE_INT); |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * Switch to pressure mode, and read pressure. We don't need to wait |
| 153 | * here, since both plates are being driven. |
| 154 | */ |
| 155 | static inline unsigned int ucb1400_ts_read_pressure(struct ucb1400 *ucb) |
| 156 | { |
| 157 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 158 | UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW | |
| 159 | UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND | |
| 160 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
Cliff Brake | b5b16c5 | 2007-04-12 01:35:43 -0400 | [diff] [blame] | 161 | udelay(ts_delay_pressure); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 162 | return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY); |
| 163 | } |
| 164 | |
| 165 | /* |
| 166 | * Switch to X position mode and measure Y plate. We switch the plate |
| 167 | * configuration in pressure mode, then switch to position mode. This |
| 168 | * gives a faster response time. Even so, we need to wait about 55us |
| 169 | * for things to stabilise. |
| 170 | */ |
| 171 | static inline unsigned int ucb1400_ts_read_xpos(struct ucb1400 *ucb) |
| 172 | { |
| 173 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 174 | UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW | |
| 175 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
| 176 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 177 | UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW | |
| 178 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
| 179 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 180 | UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW | |
| 181 | UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA); |
| 182 | |
Cliff Brake | b5b16c5 | 2007-04-12 01:35:43 -0400 | [diff] [blame] | 183 | udelay(ts_delay); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 184 | |
| 185 | return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY); |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * Switch to Y position mode and measure X plate. We switch the plate |
| 190 | * configuration in pressure mode, then switch to position mode. This |
| 191 | * gives a faster response time. Even so, we need to wait about 55us |
| 192 | * for things to stabilise. |
| 193 | */ |
| 194 | static inline unsigned int ucb1400_ts_read_ypos(struct ucb1400 *ucb) |
| 195 | { |
| 196 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 197 | UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW | |
| 198 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
| 199 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 200 | UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW | |
| 201 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
| 202 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 203 | UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW | |
| 204 | UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA); |
| 205 | |
Cliff Brake | b5b16c5 | 2007-04-12 01:35:43 -0400 | [diff] [blame] | 206 | udelay(ts_delay); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 207 | |
| 208 | return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPX); |
| 209 | } |
| 210 | |
| 211 | /* |
| 212 | * Switch to X plate resistance mode. Set MX to ground, PX to |
| 213 | * supply. Measure current. |
| 214 | */ |
| 215 | static inline unsigned int ucb1400_ts_read_xres(struct ucb1400 *ucb) |
| 216 | { |
| 217 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 218 | UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW | |
| 219 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
| 220 | return ucb1400_adc_read(ucb, 0); |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Switch to Y plate resistance mode. Set MY to ground, PY to |
| 225 | * supply. Measure current. |
| 226 | */ |
| 227 | static inline unsigned int ucb1400_ts_read_yres(struct ucb1400 *ucb) |
| 228 | { |
| 229 | ucb1400_reg_write(ucb, UCB_TS_CR, |
| 230 | UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW | |
| 231 | UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA); |
| 232 | return ucb1400_adc_read(ucb, 0); |
| 233 | } |
| 234 | |
| 235 | static inline int ucb1400_ts_pen_down(struct ucb1400 *ucb) |
| 236 | { |
| 237 | unsigned short val = ucb1400_reg_read(ucb, UCB_TS_CR); |
| 238 | return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW)); |
| 239 | } |
| 240 | |
| 241 | static inline void ucb1400_ts_irq_enable(struct ucb1400 *ucb) |
| 242 | { |
| 243 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, UCB_IE_TSPX); |
| 244 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0); |
| 245 | ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_TSPX); |
| 246 | } |
| 247 | |
| 248 | static inline void ucb1400_ts_irq_disable(struct ucb1400 *ucb) |
| 249 | { |
| 250 | ucb1400_reg_write(ucb, UCB_IE_FAL, 0); |
| 251 | } |
| 252 | |
| 253 | static void ucb1400_ts_evt_add(struct input_dev *idev, u16 pressure, u16 x, u16 y) |
| 254 | { |
| 255 | input_report_abs(idev, ABS_X, x); |
| 256 | input_report_abs(idev, ABS_Y, y); |
| 257 | input_report_abs(idev, ABS_PRESSURE, pressure); |
| 258 | input_sync(idev); |
| 259 | } |
| 260 | |
| 261 | static void ucb1400_ts_event_release(struct input_dev *idev) |
| 262 | { |
| 263 | input_report_abs(idev, ABS_PRESSURE, 0); |
| 264 | input_sync(idev); |
| 265 | } |
| 266 | |
| 267 | static void ucb1400_handle_pending_irq(struct ucb1400 *ucb) |
| 268 | { |
| 269 | unsigned int isr; |
| 270 | |
| 271 | isr = ucb1400_reg_read(ucb, UCB_IE_STATUS); |
| 272 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, isr); |
| 273 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0); |
| 274 | |
| 275 | if (isr & UCB_IE_TSPX) |
| 276 | ucb1400_ts_irq_disable(ucb); |
| 277 | else |
| 278 | printk(KERN_ERR "ucb1400: unexpected IE_STATUS = %#x\n", isr); |
| 279 | |
| 280 | enable_irq(ucb->irq); |
| 281 | } |
| 282 | |
| 283 | static int ucb1400_ts_thread(void *_ucb) |
| 284 | { |
| 285 | struct ucb1400 *ucb = _ucb; |
| 286 | struct task_struct *tsk = current; |
| 287 | int valid = 0; |
Satoru Takeuchi | c130bdb | 2007-05-14 23:52:07 -0400 | [diff] [blame] | 288 | struct sched_param param = { .sched_priority = 1 }; |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 289 | |
Satoru Takeuchi | c130bdb | 2007-05-14 23:52:07 -0400 | [diff] [blame] | 290 | sched_setscheduler(tsk, SCHED_FIFO, ¶m); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 291 | |
Rafael J. Wysocki | 8314418 | 2007-07-17 04:03:35 -0700 | [diff] [blame] | 292 | set_freezable(); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 293 | while (!kthread_should_stop()) { |
| 294 | unsigned int x, y, p; |
| 295 | long timeout; |
| 296 | |
| 297 | ucb->ts_restart = 0; |
| 298 | |
| 299 | if (ucb->irq_pending) { |
| 300 | ucb->irq_pending = 0; |
| 301 | ucb1400_handle_pending_irq(ucb); |
| 302 | } |
| 303 | |
| 304 | ucb1400_adc_enable(ucb); |
| 305 | x = ucb1400_ts_read_xpos(ucb); |
| 306 | y = ucb1400_ts_read_ypos(ucb); |
| 307 | p = ucb1400_ts_read_pressure(ucb); |
| 308 | ucb1400_adc_disable(ucb); |
| 309 | |
| 310 | /* Switch back to interrupt mode. */ |
| 311 | ucb1400_ts_mode_int(ucb); |
| 312 | |
| 313 | msleep(10); |
| 314 | |
| 315 | if (ucb1400_ts_pen_down(ucb)) { |
| 316 | ucb1400_ts_irq_enable(ucb); |
| 317 | |
| 318 | /* |
| 319 | * If we spat out a valid sample set last time, |
| 320 | * spit out a "pen off" sample here. |
| 321 | */ |
| 322 | if (valid) { |
| 323 | ucb1400_ts_event_release(ucb->ts_idev); |
| 324 | valid = 0; |
| 325 | } |
| 326 | |
| 327 | timeout = MAX_SCHEDULE_TIMEOUT; |
| 328 | } else { |
| 329 | valid = 1; |
| 330 | ucb1400_ts_evt_add(ucb->ts_idev, p, x, y); |
| 331 | timeout = msecs_to_jiffies(10); |
| 332 | } |
| 333 | |
Rafael J. Wysocki | e42837b | 2007-10-18 03:04:45 -0700 | [diff] [blame] | 334 | wait_event_freezable_timeout(ucb->ts_wait, |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 335 | ucb->irq_pending || ucb->ts_restart || kthread_should_stop(), |
| 336 | timeout); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 337 | } |
| 338 | |
| 339 | /* Send the "pen off" if we are stopping with the pen still active */ |
| 340 | if (valid) |
| 341 | ucb1400_ts_event_release(ucb->ts_idev); |
| 342 | |
| 343 | ucb->ts_task = NULL; |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * A restriction with interrupts exists when using the ucb1400, as |
| 349 | * the codec read/write routines may sleep while waiting for codec |
| 350 | * access completion and uses semaphores for access control to the |
| 351 | * AC97 bus. A complete codec read cycle could take anywhere from |
| 352 | * 60 to 100uSec so we *definitely* don't want to spin inside the |
| 353 | * interrupt handler waiting for codec access. So, we handle the |
| 354 | * interrupt by scheduling a RT kernel thread to run in process |
| 355 | * context instead of interrupt context. |
| 356 | */ |
| 357 | static irqreturn_t ucb1400_hard_irq(int irqnr, void *devid) |
| 358 | { |
| 359 | struct ucb1400 *ucb = devid; |
| 360 | |
| 361 | if (irqnr == ucb->irq) { |
| 362 | disable_irq(ucb->irq); |
| 363 | ucb->irq_pending = 1; |
| 364 | wake_up(&ucb->ts_wait); |
| 365 | return IRQ_HANDLED; |
| 366 | } |
| 367 | return IRQ_NONE; |
| 368 | } |
| 369 | |
| 370 | static int ucb1400_ts_open(struct input_dev *idev) |
| 371 | { |
Dmitry Torokhov | 40b9b0b | 2007-04-12 01:34:08 -0400 | [diff] [blame] | 372 | struct ucb1400 *ucb = input_get_drvdata(idev); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 373 | int ret = 0; |
| 374 | |
| 375 | BUG_ON(ucb->ts_task); |
| 376 | |
| 377 | ucb->ts_task = kthread_run(ucb1400_ts_thread, ucb, "UCB1400_ts"); |
| 378 | if (IS_ERR(ucb->ts_task)) { |
| 379 | ret = PTR_ERR(ucb->ts_task); |
| 380 | ucb->ts_task = NULL; |
| 381 | } |
| 382 | |
| 383 | return ret; |
| 384 | } |
| 385 | |
| 386 | static void ucb1400_ts_close(struct input_dev *idev) |
| 387 | { |
Dmitry Torokhov | 40b9b0b | 2007-04-12 01:34:08 -0400 | [diff] [blame] | 388 | struct ucb1400 *ucb = input_get_drvdata(idev); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 389 | |
| 390 | if (ucb->ts_task) |
| 391 | kthread_stop(ucb->ts_task); |
| 392 | |
| 393 | ucb1400_ts_irq_disable(ucb); |
| 394 | ucb1400_reg_write(ucb, UCB_TS_CR, 0); |
| 395 | } |
| 396 | |
| 397 | #ifdef CONFIG_PM |
| 398 | static int ucb1400_ts_resume(struct device *dev) |
| 399 | { |
| 400 | struct ucb1400 *ucb = dev_get_drvdata(dev); |
| 401 | |
| 402 | if (ucb->ts_task) { |
| 403 | /* |
| 404 | * Restart the TS thread to ensure the |
| 405 | * TS interrupt mode is set up again |
| 406 | * after sleep. |
| 407 | */ |
| 408 | ucb->ts_restart = 1; |
| 409 | wake_up(&ucb->ts_wait); |
| 410 | } |
| 411 | return 0; |
| 412 | } |
| 413 | #else |
| 414 | #define ucb1400_ts_resume NULL |
| 415 | #endif |
| 416 | |
| 417 | #ifndef NO_IRQ |
| 418 | #define NO_IRQ 0 |
| 419 | #endif |
| 420 | |
| 421 | /* |
| 422 | * Try to probe our interrupt, rather than relying on lots of |
| 423 | * hard-coded machine dependencies. |
| 424 | */ |
| 425 | static int ucb1400_detect_irq(struct ucb1400 *ucb) |
| 426 | { |
| 427 | unsigned long mask, timeout; |
| 428 | |
| 429 | mask = probe_irq_on(); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 430 | |
| 431 | /* Enable the ADC interrupt. */ |
| 432 | ucb1400_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); |
| 433 | ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); |
| 434 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff); |
| 435 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0); |
| 436 | |
| 437 | /* Cause an ADC interrupt. */ |
| 438 | ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); |
| 439 | ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); |
| 440 | |
| 441 | /* Wait for the conversion to complete. */ |
| 442 | timeout = jiffies + HZ/2; |
| 443 | while (!(ucb1400_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VALID)) { |
| 444 | cpu_relax(); |
| 445 | if (time_after(jiffies, timeout)) { |
| 446 | printk(KERN_ERR "ucb1400: timed out in IRQ probe\n"); |
| 447 | probe_irq_off(mask); |
| 448 | return -ENODEV; |
| 449 | } |
| 450 | } |
| 451 | ucb1400_reg_write(ucb, UCB_ADC_CR, 0); |
| 452 | |
| 453 | /* Disable and clear interrupt. */ |
| 454 | ucb1400_reg_write(ucb, UCB_IE_RIS, 0); |
| 455 | ucb1400_reg_write(ucb, UCB_IE_FAL, 0); |
| 456 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff); |
| 457 | ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0); |
| 458 | |
| 459 | /* Read triggered interrupt. */ |
| 460 | ucb->irq = probe_irq_off(mask); |
| 461 | if (ucb->irq < 0 || ucb->irq == NO_IRQ) |
| 462 | return -ENODEV; |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | static int ucb1400_ts_probe(struct device *dev) |
| 468 | { |
| 469 | struct ucb1400 *ucb; |
| 470 | struct input_dev *idev; |
| 471 | int error, id, x_res, y_res; |
| 472 | |
| 473 | ucb = kzalloc(sizeof(struct ucb1400), GFP_KERNEL); |
| 474 | idev = input_allocate_device(); |
| 475 | if (!ucb || !idev) { |
| 476 | error = -ENOMEM; |
| 477 | goto err_free_devs; |
| 478 | } |
| 479 | |
| 480 | ucb->ts_idev = idev; |
| 481 | ucb->adcsync = adcsync; |
| 482 | ucb->ac97 = to_ac97_t(dev); |
| 483 | init_waitqueue_head(&ucb->ts_wait); |
| 484 | |
| 485 | id = ucb1400_reg_read(ucb, UCB_ID); |
| 486 | if (id != UCB_ID_1400) { |
| 487 | error = -ENODEV; |
| 488 | goto err_free_devs; |
| 489 | } |
| 490 | |
| 491 | error = ucb1400_detect_irq(ucb); |
| 492 | if (error) { |
| 493 | printk(KERN_ERR "UCB1400: IRQ probe failed\n"); |
| 494 | goto err_free_devs; |
| 495 | } |
| 496 | |
| 497 | error = request_irq(ucb->irq, ucb1400_hard_irq, IRQF_TRIGGER_RISING, |
| 498 | "UCB1400", ucb); |
| 499 | if (error) { |
| 500 | printk(KERN_ERR "ucb1400: unable to grab irq%d: %d\n", |
| 501 | ucb->irq, error); |
| 502 | goto err_free_devs; |
| 503 | } |
| 504 | printk(KERN_DEBUG "UCB1400: found IRQ %d\n", ucb->irq); |
| 505 | |
Dmitry Torokhov | 40b9b0b | 2007-04-12 01:34:08 -0400 | [diff] [blame] | 506 | input_set_drvdata(idev, ucb); |
| 507 | |
Dmitry Torokhov | a5394fb0 | 2007-04-12 01:35:14 -0400 | [diff] [blame] | 508 | idev->dev.parent = dev; |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 509 | idev->name = "UCB1400 touchscreen interface"; |
| 510 | idev->id.vendor = ucb1400_reg_read(ucb, AC97_VENDOR_ID1); |
| 511 | idev->id.product = id; |
| 512 | idev->open = ucb1400_ts_open; |
| 513 | idev->close = ucb1400_ts_close; |
Jiri Slaby | 7b19ada | 2007-10-18 23:40:32 -0700 | [diff] [blame] | 514 | idev->evbit[0] = BIT_MASK(EV_ABS); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 515 | |
| 516 | ucb1400_adc_enable(ucb); |
| 517 | x_res = ucb1400_ts_read_xres(ucb); |
| 518 | y_res = ucb1400_ts_read_yres(ucb); |
| 519 | ucb1400_adc_disable(ucb); |
| 520 | printk(KERN_DEBUG "UCB1400: x/y = %d/%d\n", x_res, y_res); |
| 521 | |
| 522 | input_set_abs_params(idev, ABS_X, 0, x_res, 0, 0); |
| 523 | input_set_abs_params(idev, ABS_Y, 0, y_res, 0, 0); |
| 524 | input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0); |
| 525 | |
| 526 | error = input_register_device(idev); |
| 527 | if (error) |
| 528 | goto err_free_irq; |
| 529 | |
| 530 | dev_set_drvdata(dev, ucb); |
| 531 | return 0; |
| 532 | |
| 533 | err_free_irq: |
| 534 | free_irq(ucb->irq, ucb); |
| 535 | err_free_devs: |
| 536 | input_free_device(idev); |
| 537 | kfree(ucb); |
| 538 | return error; |
| 539 | } |
| 540 | |
| 541 | static int ucb1400_ts_remove(struct device *dev) |
| 542 | { |
| 543 | struct ucb1400 *ucb = dev_get_drvdata(dev); |
| 544 | |
| 545 | free_irq(ucb->irq, ucb); |
| 546 | input_unregister_device(ucb->ts_idev); |
| 547 | dev_set_drvdata(dev, NULL); |
| 548 | kfree(ucb); |
| 549 | return 0; |
| 550 | } |
| 551 | |
| 552 | static struct device_driver ucb1400_ts_driver = { |
Cliff Brake | ff78b20 | 2007-04-09 23:50:50 -0400 | [diff] [blame] | 553 | .name = "ucb1400_ts", |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 554 | .owner = THIS_MODULE, |
| 555 | .bus = &ac97_bus_type, |
| 556 | .probe = ucb1400_ts_probe, |
| 557 | .remove = ucb1400_ts_remove, |
| 558 | .resume = ucb1400_ts_resume, |
| 559 | }; |
| 560 | |
| 561 | static int __init ucb1400_ts_init(void) |
| 562 | { |
| 563 | return driver_register(&ucb1400_ts_driver); |
| 564 | } |
| 565 | |
| 566 | static void __exit ucb1400_ts_exit(void) |
| 567 | { |
| 568 | driver_unregister(&ucb1400_ts_driver); |
| 569 | } |
| 570 | |
Cliff Brake | b5b16c5 | 2007-04-12 01:35:43 -0400 | [diff] [blame] | 571 | module_param(adcsync, bool, 0444); |
| 572 | MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin."); |
| 573 | |
| 574 | module_param(ts_delay, int, 0444); |
| 575 | MODULE_PARM_DESC(ts_delay, "Delay between panel setup and position read. Default = 55us."); |
| 576 | |
| 577 | module_param(ts_delay_pressure, int, 0444); |
| 578 | MODULE_PARM_DESC(ts_delay_pressure, |
| 579 | "delay between panel setup and pressure read. Default = 0us."); |
Nicolas Pitre | f40219b | 2006-11-17 01:07:26 -0500 | [diff] [blame] | 580 | |
| 581 | module_init(ucb1400_ts_init); |
| 582 | module_exit(ucb1400_ts_exit); |
| 583 | |
| 584 | MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver"); |
| 585 | MODULE_LICENSE("GPL"); |