blob: 94ddfe01d673adfb42eefa49d87c91dc328053a0 [file] [log] [blame]
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +03001/*
2 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
3 *
4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29#include <linux/init.h>
30#include <linux/clk.h>
31#include <linux/io.h>
Felipe Balbi8ceae512010-12-02 09:19:35 +020032#include <linux/platform_device.h>
33#include <linux/dma-mapping.h>
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +030034
35#include <mach/da8xx.h>
36#include <mach/usb.h>
37
38#include "musb_core.h"
39
40/*
41 * DA8XX specific definitions
42 */
43
44/* USB 2.0 OTG module registers */
45#define DA8XX_USB_REVISION_REG 0x00
46#define DA8XX_USB_CTRL_REG 0x04
47#define DA8XX_USB_STAT_REG 0x08
48#define DA8XX_USB_EMULATION_REG 0x0c
49#define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
50#define DA8XX_USB_AUTOREQ_REG 0x14
51#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
52#define DA8XX_USB_TEARDOWN_REG 0x1c
53#define DA8XX_USB_INTR_SRC_REG 0x20
54#define DA8XX_USB_INTR_SRC_SET_REG 0x24
55#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
56#define DA8XX_USB_INTR_MASK_REG 0x2c
57#define DA8XX_USB_INTR_MASK_SET_REG 0x30
58#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
59#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
60#define DA8XX_USB_END_OF_INTR_REG 0x3c
61#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
62
63/* Control register bits */
64#define DA8XX_SOFT_RESET_MASK 1
65
66#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
67#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
68
69/* USB interrupt register bits */
70#define DA8XX_INTR_USB_SHIFT 16
71#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
72 /* interrupts and DRVVBUS interrupt */
73#define DA8XX_INTR_DRVVBUS 0x100
74#define DA8XX_INTR_RX_SHIFT 8
75#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
76#define DA8XX_INTR_TX_SHIFT 0
77#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
78
79#define DA8XX_MENTOR_CORE_OFFSET 0x400
80
81#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
82
Felipe Balbie6480fa2010-12-02 09:40:34 +020083struct da8xx_glue {
84 struct device *dev;
85 struct platform_device *musb;
86};
87
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +030088/*
89 * REVISIT (PM): we should be able to keep the PHY in low power mode most
90 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
91 * and, when in host mode, autosuspending idle root ports... PHY_PLLON
92 * (overriding SUSPENDM?) then likely needs to stay off.
93 */
94
95static inline void phy_on(void)
96{
97 u32 cfgchip2 = __raw_readl(CFGCHIP2);
98
99 /*
100 * Start the on-chip PHY and its PLL.
101 */
102 cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
103 cfgchip2 |= CFGCHIP2_PHY_PLLON;
104 __raw_writel(cfgchip2, CFGCHIP2);
105
106 pr_info("Waiting for USB PHY clock good...\n");
107 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
108 cpu_relax();
109}
110
111static inline void phy_off(void)
112{
113 u32 cfgchip2 = __raw_readl(CFGCHIP2);
114
115 /*
116 * Ensure that USB 1.1 reference clock is not being sourced from
117 * USB 2.0 PHY. Otherwise do not power down the PHY.
118 */
119 if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
120 (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
121 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
122 "can't power it down\n");
123 return;
124 }
125
126 /*
127 * Power down the on-chip PHY.
128 */
129 cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
130 __raw_writel(cfgchip2, CFGCHIP2);
131}
132
133/*
134 * Because we don't set CTRL.UINT, it's "important" to:
135 * - not read/write INTRUSB/INTRUSBE (except during
136 * initial setup, as a workaround);
137 * - use INTSET/INTCLR instead.
138 */
139
140/**
Felipe Balbi743411b2010-12-01 13:22:05 +0200141 * da8xx_musb_enable - enable interrupts
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300142 */
Felipe Balbi743411b2010-12-01 13:22:05 +0200143static void da8xx_musb_enable(struct musb *musb)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300144{
145 void __iomem *reg_base = musb->ctrl_base;
146 u32 mask;
147
148 /* Workaround: setup IRQs through both register sets. */
149 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
150 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
151 DA8XX_INTR_USB_MASK;
152 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
153
154 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
155 if (is_otg_enabled(musb))
156 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
157 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
158}
159
160/**
Felipe Balbi743411b2010-12-01 13:22:05 +0200161 * da8xx_musb_disable - disable HDRC and flush interrupts
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300162 */
Felipe Balbi743411b2010-12-01 13:22:05 +0200163static void da8xx_musb_disable(struct musb *musb)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300164{
165 void __iomem *reg_base = musb->ctrl_base;
166
167 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
168 DA8XX_INTR_USB_MASK |
169 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
170 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
171 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
172}
173
174#ifdef CONFIG_USB_MUSB_HDRC_HCD
175#define portstate(stmt) stmt
176#else
177#define portstate(stmt)
178#endif
179
Felipe Balbi743411b2010-12-01 13:22:05 +0200180static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300181{
182 WARN_ON(is_on && is_peripheral_active(musb));
183}
184
185#define POLL_SECONDS 2
186
187static struct timer_list otg_workaround;
188
189static void otg_timer(unsigned long _musb)
190{
191 struct musb *musb = (void *)_musb;
192 void __iomem *mregs = musb->mregs;
193 u8 devctl;
194 unsigned long flags;
195
196 /*
197 * We poll because DaVinci's won't expose several OTG-critical
198 * status change events (from the transceiver) otherwise.
199 */
200 devctl = musb_readb(mregs, MUSB_DEVCTL);
201 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
202
203 spin_lock_irqsave(&musb->lock, flags);
204 switch (musb->xceiv->state) {
205 case OTG_STATE_A_WAIT_BCON:
206 devctl &= ~MUSB_DEVCTL_SESSION;
207 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
208
209 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
210 if (devctl & MUSB_DEVCTL_BDEVICE) {
211 musb->xceiv->state = OTG_STATE_B_IDLE;
212 MUSB_DEV_MODE(musb);
213 } else {
214 musb->xceiv->state = OTG_STATE_A_IDLE;
215 MUSB_HST_MODE(musb);
216 }
217 break;
218 case OTG_STATE_A_WAIT_VFALL:
219 /*
220 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
221 * RTL seems to mis-handle session "start" otherwise (or in
222 * our case "recover"), in routine "VBUS was valid by the time
223 * VBUSERR got reported during enumeration" cases.
224 */
225 if (devctl & MUSB_DEVCTL_VBUS) {
226 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
227 break;
228 }
229 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
230 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
231 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
232 break;
233 case OTG_STATE_B_IDLE:
234 if (!is_peripheral_enabled(musb))
235 break;
236
237 /*
238 * There's no ID-changed IRQ, so we have no good way to tell
239 * when to switch to the A-Default state machine (by setting
240 * the DEVCTL.Session bit).
241 *
242 * Workaround: whenever we're in B_IDLE, try setting the
243 * session flag every few seconds. If it works, ID was
244 * grounded and we're now in the A-Default state machine.
245 *
246 * NOTE: setting the session flag is _supposed_ to trigger
247 * SRP but clearly it doesn't.
248 */
249 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
250 devctl = musb_readb(mregs, MUSB_DEVCTL);
251 if (devctl & MUSB_DEVCTL_BDEVICE)
252 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
253 else
254 musb->xceiv->state = OTG_STATE_A_IDLE;
255 break;
256 default:
257 break;
258 }
259 spin_unlock_irqrestore(&musb->lock, flags);
260}
261
Felipe Balbi743411b2010-12-01 13:22:05 +0200262static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300263{
264 static unsigned long last_timer;
265
266 if (!is_otg_enabled(musb))
267 return;
268
269 if (timeout == 0)
270 timeout = jiffies + msecs_to_jiffies(3);
271
272 /* Never idle if active, or when VBUS timeout is not set as host */
273 if (musb->is_active || (musb->a_wait_bcon == 0 &&
274 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
275 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
276 del_timer(&otg_workaround);
277 last_timer = jiffies;
278 return;
279 }
280
281 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
282 DBG(4, "Longer idle timer already pending, ignoring...\n");
283 return;
284 }
285 last_timer = timeout;
286
287 DBG(4, "%s inactive, starting idle timer for %u ms\n",
288 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
289 mod_timer(&otg_workaround, timeout);
290}
291
Felipe Balbi743411b2010-12-01 13:22:05 +0200292static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300293{
294 struct musb *musb = hci;
295 void __iomem *reg_base = musb->ctrl_base;
296 unsigned long flags;
297 irqreturn_t ret = IRQ_NONE;
298 u32 status;
299
300 spin_lock_irqsave(&musb->lock, flags);
301
302 /*
303 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
304 * the Mentor registers (except for setup), use the TI ones and EOI.
305 */
306
307 /* Acknowledge and handle non-CPPI interrupts */
308 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
309 if (!status)
310 goto eoi;
311
312 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
313 DBG(4, "USB IRQ %08x\n", status);
314
315 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
316 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
317 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
318
319 /*
320 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
321 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
322 * switch appropriately between halves of the OTG state machine.
323 * Managing DEVCTL.Session per Mentor docs requires that we know its
324 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
325 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
326 */
327 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
328 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
329 void __iomem *mregs = musb->mregs;
330 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
331 int err;
332
333 err = is_host_enabled(musb) && (musb->int_usb &
334 MUSB_INTR_VBUSERROR);
335 if (err) {
336 /*
337 * The Mentor core doesn't debounce VBUS as needed
338 * to cope with device connect current spikes. This
339 * means it's not uncommon for bus-powered devices
340 * to get VBUS errors during enumeration.
341 *
342 * This is a workaround, but newer RTL from Mentor
343 * seems to allow a better one: "re"-starting sessions
344 * without waiting for VBUS to stop registering in
345 * devctl.
346 */
347 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
348 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
349 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
350 WARNING("VBUS error workaround (delay coming)\n");
351 } else if (is_host_enabled(musb) && drvvbus) {
352 MUSB_HST_MODE(musb);
353 musb->xceiv->default_a = 1;
354 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
355 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
356 del_timer(&otg_workaround);
357 } else {
358 musb->is_active = 0;
359 MUSB_DEV_MODE(musb);
360 musb->xceiv->default_a = 0;
361 musb->xceiv->state = OTG_STATE_B_IDLE;
362 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
363 }
364
365 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
366 drvvbus ? "on" : "off",
367 otg_state_string(musb),
368 err ? " ERROR" : "",
369 devctl);
370 ret = IRQ_HANDLED;
371 }
372
373 if (musb->int_tx || musb->int_rx || musb->int_usb)
374 ret |= musb_interrupt(musb);
375
376 eoi:
377 /* EOI needs to be written for the IRQ to be re-asserted. */
378 if (ret == IRQ_HANDLED || status)
379 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
380
381 /* Poll for ID change */
382 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
383 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
384
385 spin_unlock_irqrestore(&musb->lock, flags);
386
387 return ret;
388}
389
Felipe Balbi743411b2010-12-01 13:22:05 +0200390static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300391{
392 u32 cfgchip2 = __raw_readl(CFGCHIP2);
393
394 cfgchip2 &= ~CFGCHIP2_OTGMODE;
395 switch (musb_mode) {
396#ifdef CONFIG_USB_MUSB_HDRC_HCD
397 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
398 cfgchip2 |= CFGCHIP2_FORCE_HOST;
399 break;
400#endif
401#ifdef CONFIG_USB_GADGET_MUSB_HDRC
402 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
403 cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
404 break;
405#endif
406#ifdef CONFIG_USB_MUSB_OTG
407 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
408 cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
409 break;
410#endif
411 default:
412 DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
413 }
414
415 __raw_writel(cfgchip2, CFGCHIP2);
416 return 0;
417}
418
Felipe Balbi743411b2010-12-01 13:22:05 +0200419static int da8xx_musb_init(struct musb *musb)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300420{
421 void __iomem *reg_base = musb->ctrl_base;
422 u32 rev;
423
424 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
425
426 clk_enable(musb->clock);
427
428 /* Returns zero if e.g. not clocked */
429 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
430 if (!rev)
431 goto fail;
432
433 usb_nop_xceiv_register();
434 musb->xceiv = otg_get_transceiver();
435 if (!musb->xceiv)
436 goto fail;
437
438 if (is_host_enabled(musb))
439 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
440
Felipe Balbi743411b2010-12-01 13:22:05 +0200441 musb->board_set_vbus = da8xx_musb_set_vbus;
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300442
443 /* Reset the controller */
444 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
445
446 /* Start the on-chip PHY and its PLL. */
447 phy_on();
448
449 msleep(5);
450
451 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
452 pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
453 rev, __raw_readl(CFGCHIP2),
454 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
455
Felipe Balbi743411b2010-12-01 13:22:05 +0200456 musb->isr = da8xx_musb_interrupt;
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300457 return 0;
458fail:
459 clk_disable(musb->clock);
460 return -ENODEV;
461}
462
Felipe Balbi743411b2010-12-01 13:22:05 +0200463static int da8xx_musb_exit(struct musb *musb)
Sergei Shtylyov3ee076d2010-09-24 13:44:03 +0300464{
465 if (is_host_enabled(musb))
466 del_timer_sync(&otg_workaround);
467
468 phy_off();
469
470 otg_put_transceiver(musb->xceiv);
471 usb_nop_xceiv_unregister();
472
473 clk_disable(musb->clock);
474
475 return 0;
476}
Felipe Balbi743411b2010-12-01 13:22:05 +0200477
478const struct musb_platform_ops musb_ops = {
479 .init = da8xx_musb_init,
480 .exit = da8xx_musb_exit,
481
482 .enable = da8xx_musb_enable,
483 .disable = da8xx_musb_disable,
484
485 .set_mode = da8xx_musb_set_mode,
486 .try_idle = da8xx_musb_try_idle,
487
488 .set_vbus = da8xx_musb_set_vbus,
489};
Felipe Balbi8ceae512010-12-02 09:19:35 +0200490
491static u64 da8xx_dmamask = DMA_BIT_MASK(32);
492
493static int __init da8xx_probe(struct platform_device *pdev)
494{
495 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
496 struct platform_device *musb;
Felipe Balbie6480fa2010-12-02 09:40:34 +0200497 struct da8xx_glue *glue;
Felipe Balbi8ceae512010-12-02 09:19:35 +0200498
499 int ret = -ENOMEM;
500
Felipe Balbie6480fa2010-12-02 09:40:34 +0200501 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
502 if (!glue) {
503 dev_err(&pdev->dev, "failed to allocate glue context\n");
504 goto err0;
505 }
506
Felipe Balbi8ceae512010-12-02 09:19:35 +0200507 musb = platform_device_alloc("musb-hdrc", -1);
508 if (!musb) {
509 dev_err(&pdev->dev, "failed to allocate musb device\n");
Felipe Balbie6480fa2010-12-02 09:40:34 +0200510 goto err1;
Felipe Balbi8ceae512010-12-02 09:19:35 +0200511 }
512
513 musb->dev.parent = &pdev->dev;
514 musb->dev.dma_mask = &da8xx_dmamask;
515 musb->dev.coherent_dma_mask = da8xx_dmamask;
516
Felipe Balbie6480fa2010-12-02 09:40:34 +0200517 glue->dev = &pdev->dev;
518 glue->musb = musb;
519
520 platform_set_drvdata(pdev, glue);
Felipe Balbi8ceae512010-12-02 09:19:35 +0200521
522 ret = platform_device_add_resources(musb, pdev->resource,
523 pdev->num_resources);
524 if (ret) {
525 dev_err(&pdev->dev, "failed to add resources\n");
Felipe Balbie6480fa2010-12-02 09:40:34 +0200526 goto err2;
Felipe Balbi8ceae512010-12-02 09:19:35 +0200527 }
528
529 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
530 if (ret) {
531 dev_err(&pdev->dev, "failed to add platform_data\n");
Felipe Balbie6480fa2010-12-02 09:40:34 +0200532 goto err2;
Felipe Balbi8ceae512010-12-02 09:19:35 +0200533 }
534
535 ret = platform_device_add(musb);
536 if (ret) {
537 dev_err(&pdev->dev, "failed to register musb device\n");
Felipe Balbie6480fa2010-12-02 09:40:34 +0200538 goto err2;
Felipe Balbi8ceae512010-12-02 09:19:35 +0200539 }
540
541 return 0;
542
Felipe Balbie6480fa2010-12-02 09:40:34 +0200543err2:
Felipe Balbi8ceae512010-12-02 09:19:35 +0200544 platform_device_put(musb);
545
Felipe Balbie6480fa2010-12-02 09:40:34 +0200546err1:
547 kfree(glue);
548
Felipe Balbi8ceae512010-12-02 09:19:35 +0200549err0:
550 return ret;
551}
552
553static int __exit da8xx_remove(struct platform_device *pdev)
554{
Felipe Balbie6480fa2010-12-02 09:40:34 +0200555 struct da8xx_glue *glue = platform_get_drvdata(pdev);
Felipe Balbi8ceae512010-12-02 09:19:35 +0200556
Felipe Balbie6480fa2010-12-02 09:40:34 +0200557 platform_device_del(glue->musb);
558 platform_device_put(glue->musb);
559 kfree(glue);
Felipe Balbi8ceae512010-12-02 09:19:35 +0200560
561 return 0;
562}
563
564static struct platform_driver da8xx_driver = {
565 .remove = __exit_p(da8xx_remove),
566 .driver = {
567 .name = "musb-da8xx",
568 },
569};
570
571MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
572MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
573MODULE_LICENSE("GPL v2");
574
575static int __init da8xx_init(void)
576{
577 return platform_driver_probe(&da8xx_driver, da8xx_probe);
578}
579subsys_initcall(da8xx_init);
580
581static void __exit da8xx_exit(void)
582{
583 platform_driver_unregister(&da8xx_driver);
584}
585module_exit(da8xx_exit);