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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
33
34/* Maximum outstanding splits to be configured into xena. */
35typedef enum xena_max_outstanding_splits {
36 XENA_ONE_SPLIT_TRANSACTION = 0,
37 XENA_TWO_SPLIT_TRANSACTION = 1,
38 XENA_THREE_SPLIT_TRANSACTION = 2,
39 XENA_FOUR_SPLIT_TRANSACTION = 3,
40 XENA_EIGHT_SPLIT_TRANSACTION = 4,
41 XENA_TWELVE_SPLIT_TRANSACTION = 5,
42 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
43 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
44} xena_max_outstanding_splits;
45#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
46
47/* OS concerned variables and constants */
48#define WATCH_DOG_TIMEOUT 5*HZ
49#define EFILL 0x1234
50#define ALIGN_SIZE 127
51#define PCIX_COMMAND_REGISTER 0x62
52
53/*
54 * Debug related variables.
55 */
56/* different debug levels. */
57#define ERR_DBG 0
58#define INIT_DBG 1
59#define INFO_DBG 2
60#define TX_DBG 3
61#define INTR_DBG 4
62
63/* Global variable that defines the present debug level of the driver. */
64static int debug_level = ERR_DBG; /* Default level. */
65
66/* DEBUG message print. */
67#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
68
69/* Protocol assist features of the NIC */
70#define L3_CKSUM_OK 0xFFFF
71#define L4_CKSUM_OK 0xFFFF
72#define S2IO_JUMBO_SIZE 9600
73
74/* The statistics block of Xena */
75typedef struct stat_block {
76/* Tx MAC statistics counters. */
77 u32 tmac_data_octets;
78 u32 tmac_frms;
79 u64 tmac_drop_frms;
80 u32 tmac_bcst_frms;
81 u32 tmac_mcst_frms;
82 u64 tmac_pause_ctrl_frms;
83 u32 tmac_ucst_frms;
84 u32 tmac_ttl_octets;
85 u32 tmac_any_err_frms;
86 u32 tmac_nucst_frms;
87 u64 tmac_ttl_less_fb_octets;
88 u64 tmac_vld_ip_octets;
89 u32 tmac_drop_ip;
90 u32 tmac_vld_ip;
91 u32 tmac_rst_tcp;
92 u32 tmac_icmp;
93 u64 tmac_tcp;
94 u32 reserved_0;
95 u32 tmac_udp;
96
97/* Rx MAC Statistics counters. */
98 u32 rmac_data_octets;
99 u32 rmac_vld_frms;
100 u64 rmac_fcs_err_frms;
101 u64 rmac_drop_frms;
102 u32 rmac_vld_bcst_frms;
103 u32 rmac_vld_mcst_frms;
104 u32 rmac_out_rng_len_err_frms;
105 u32 rmac_in_rng_len_err_frms;
106 u64 rmac_long_frms;
107 u64 rmac_pause_ctrl_frms;
108 u64 rmac_unsup_ctrl_frms;
109 u32 rmac_accepted_ucst_frms;
110 u32 rmac_ttl_octets;
111 u32 rmac_discarded_frms;
112 u32 rmac_accepted_nucst_frms;
113 u32 reserved_1;
114 u32 rmac_drop_events;
115 u64 rmac_ttl_less_fb_octets;
116 u64 rmac_ttl_frms;
117 u64 reserved_2;
118 u32 rmac_usized_frms;
119 u32 reserved_3;
120 u32 rmac_frag_frms;
121 u32 rmac_osized_frms;
122 u32 reserved_4;
123 u32 rmac_jabber_frms;
124 u64 rmac_ttl_64_frms;
125 u64 rmac_ttl_65_127_frms;
126 u64 reserved_5;
127 u64 rmac_ttl_128_255_frms;
128 u64 rmac_ttl_256_511_frms;
129 u64 reserved_6;
130 u64 rmac_ttl_512_1023_frms;
131 u64 rmac_ttl_1024_1518_frms;
132 u32 rmac_ip;
133 u32 reserved_7;
134 u64 rmac_ip_octets;
135 u32 rmac_drop_ip;
136 u32 rmac_hdr_err_ip;
137 u32 reserved_8;
138 u32 rmac_icmp;
139 u64 rmac_tcp;
140 u32 rmac_err_drp_udp;
141 u32 rmac_udp;
142 u64 rmac_xgmii_err_sym;
143 u64 rmac_frms_q0;
144 u64 rmac_frms_q1;
145 u64 rmac_frms_q2;
146 u64 rmac_frms_q3;
147 u64 rmac_frms_q4;
148 u64 rmac_frms_q5;
149 u64 rmac_frms_q6;
150 u64 rmac_frms_q7;
151 u16 rmac_full_q3;
152 u16 rmac_full_q2;
153 u16 rmac_full_q1;
154 u16 rmac_full_q0;
155 u16 rmac_full_q7;
156 u16 rmac_full_q6;
157 u16 rmac_full_q5;
158 u16 rmac_full_q4;
159 u32 reserved_9;
160 u32 rmac_pause_cnt;
161 u64 rmac_xgmii_data_err_cnt;
162 u64 rmac_xgmii_ctrl_err_cnt;
163 u32 rmac_err_tcp;
164 u32 rmac_accepted_ip;
165
166/* PCI/PCI-X Read transaction statistics. */
167 u32 new_rd_req_cnt;
168 u32 rd_req_cnt;
169 u32 rd_rtry_cnt;
170 u32 new_rd_req_rtry_cnt;
171
172/* PCI/PCI-X Write/Read transaction statistics. */
173 u32 wr_req_cnt;
174 u32 wr_rtry_rd_ack_cnt;
175 u32 new_wr_req_rtry_cnt;
176 u32 new_wr_req_cnt;
177 u32 wr_disc_cnt;
178 u32 wr_rtry_cnt;
179
180/* PCI/PCI-X Write / DMA Transaction statistics. */
181 u32 txp_wr_cnt;
182 u32 rd_rtry_wr_ack_cnt;
183 u32 txd_wr_cnt;
184 u32 txd_rd_cnt;
185 u32 rxd_wr_cnt;
186 u32 rxd_rd_cnt;
187 u32 rxf_wr_cnt;
188 u32 txf_rd_cnt;
189} StatInfo_t;
190
191/* Structures representing different init time configuration
192 * parameters of the NIC.
193 */
194
195/* Maintains Per FIFO related information. */
196typedef struct tx_fifo_config {
197#define MAX_AVAILABLE_TXDS 8192
198 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
199/* Priority definition */
200#define TX_FIFO_PRI_0 0 /*Highest */
201#define TX_FIFO_PRI_1 1
202#define TX_FIFO_PRI_2 2
203#define TX_FIFO_PRI_3 3
204#define TX_FIFO_PRI_4 4
205#define TX_FIFO_PRI_5 5
206#define TX_FIFO_PRI_6 6
207#define TX_FIFO_PRI_7 7 /*lowest */
208 u8 fifo_priority; /* specifies pointer level for FIFO */
209 /* user should not set twos fifos with same pri */
210 u8 f_no_snoop;
211#define NO_SNOOP_TXD 0x01
212#define NO_SNOOP_TXD_BUFFER 0x02
213} tx_fifo_config_t;
214
215
216/* Maintains per Ring related information */
217typedef struct rx_ring_config {
218 u32 num_rxd; /*No of RxDs per Rx Ring */
219#define RX_RING_PRI_0 0 /* highest */
220#define RX_RING_PRI_1 1
221#define RX_RING_PRI_2 2
222#define RX_RING_PRI_3 3
223#define RX_RING_PRI_4 4
224#define RX_RING_PRI_5 5
225#define RX_RING_PRI_6 6
226#define RX_RING_PRI_7 7 /* lowest */
227
228 u8 ring_priority; /*Specifies service priority of ring */
229 /* OSM should not set any two rings with same priority */
230 u8 ring_org; /*Organization of ring */
231#define RING_ORG_BUFF1 0x01
232#define RX_RING_ORG_BUFF3 0x03
233#define RX_RING_ORG_BUFF5 0x05
234
235 u8 f_no_snoop;
236#define NO_SNOOP_RXD 0x01
237#define NO_SNOOP_RXD_BUFFER 0x02
238} rx_ring_config_t;
239
240/* This structure provides contains values of the tunable parameters
241 * of the H/W
242 */
243struct config_param {
244/* Tx Side */
245 u32 tx_fifo_num; /*Number of Tx FIFOs */
246#define MAX_TX_FIFOS 8
247
248 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
249 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
250 u64 tx_intr_type;
251 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
252
253/* Rx Side */
254 u32 rx_ring_num; /*Number of receive rings */
255#define MAX_RX_RINGS 8
256#define MAX_RX_BLOCKS_PER_RING 150
257
258 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
259
260#define HEADER_ETHERNET_II_802_3_SIZE 14
261#define HEADER_802_2_SIZE 3
262#define HEADER_SNAP_SIZE 5
263#define HEADER_VLAN_SIZE 4
264
265#define MIN_MTU 46
266#define MAX_PYLD 1500
267#define MAX_MTU (MAX_PYLD+18)
268#define MAX_MTU_VLAN (MAX_PYLD+22)
269#define MAX_PYLD_JUMBO 9600
270#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
271#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
272};
273
274/* Structure representing MAC Addrs */
275typedef struct mac_addr {
276 u8 mac_addr[ETH_ALEN];
277} macaddr_t;
278
279/* Structure that represent every FIFO element in the BAR1
280 * Address location.
281 */
282typedef struct _TxFIFO_element {
283 u64 TxDL_Pointer;
284
285 u64 List_Control;
286#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
287#define TX_FIFO_FIRST_LIST BIT(14)
288#define TX_FIFO_LAST_LIST BIT(15)
289#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
290#define TX_FIFO_SPECIAL_FUNC BIT(23)
291#define TX_FIFO_DS_NO_SNOOP BIT(31)
292#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
293} TxFIFO_element_t;
294
295/* Tx descriptor structure */
296typedef struct _TxD {
297 u64 Control_1;
298/* bit mask */
299#define TXD_LIST_OWN_XENA BIT(7)
300#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
301#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
302#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
303#define TXD_GATHER_CODE (BIT(22) | BIT(23))
304#define TXD_GATHER_CODE_FIRST BIT(22)
305#define TXD_GATHER_CODE_LAST BIT(23)
306#define TXD_TCP_LSO_EN BIT(30)
307#define TXD_UDP_COF_EN BIT(31)
308#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
309#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
310
311 u64 Control_2;
312#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
313#define TXD_TX_CKO_IPV4_EN BIT(5)
314#define TXD_TX_CKO_TCP_EN BIT(6)
315#define TXD_TX_CKO_UDP_EN BIT(7)
316#define TXD_VLAN_ENABLE BIT(15)
317#define TXD_VLAN_TAG(val) vBIT(val,16,16)
318#define TXD_INT_NUMBER(val) vBIT(val,34,6)
319#define TXD_INT_TYPE_PER_LIST BIT(47)
320#define TXD_INT_TYPE_UTILZ BIT(46)
321#define TXD_SET_MARKER vBIT(0x6,0,4)
322
323 u64 Buffer_Pointer;
324 u64 Host_Control; /* reserved for host */
325} TxD_t;
326
327/* Structure to hold the phy and virt addr of every TxDL. */
328typedef struct list_info_hold {
329 dma_addr_t list_phy_addr;
330 void *list_virt_addr;
331} list_info_hold_t;
332
333/* Rx descriptor structure */
334typedef struct _RxD_t {
335 u64 Host_Control; /* reserved for host */
336 u64 Control_1;
337#define RXD_OWN_XENA BIT(7)
338#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
339#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
340#define RXD_FRAME_PROTO_IPV4 BIT(27)
341#define RXD_FRAME_PROTO_IPV6 BIT(28)
342#define RXD_FRAME_PROTO_TCP BIT(30)
343#define RXD_FRAME_PROTO_UDP BIT(31)
344#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
345#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
346#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
347
348 u64 Control_2;
349#ifndef CONFIG_2BUFF_MODE
350#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
351#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
352#else
353#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16)
354#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
355#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
356#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
357#define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
358#define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
359#endif
360
361#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
362#define SET_VLAN_TAG(val) vBIT(val,48,16)
363#define SET_NUM_TAG(val) vBIT(val,16,32)
364
365#ifndef CONFIG_2BUFF_MODE
366#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
367#else
368#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
369 >> 48)
370#define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
371 >> 32)
372#define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
373 >> 16)
374#define BUF0_LEN 40
375#define BUF1_LEN 1
376#endif
377
378 u64 Buffer0_ptr;
379#ifdef CONFIG_2BUFF_MODE
380 u64 Buffer1_ptr;
381 u64 Buffer2_ptr;
382#endif
383} RxD_t;
384
385/* Structure that represents the Rx descriptor block which contains
386 * 128 Rx descriptors.
387 */
388#ifndef CONFIG_2BUFF_MODE
389typedef struct _RxD_block {
390#define MAX_RXDS_PER_BLOCK 127
391 RxD_t rxd[MAX_RXDS_PER_BLOCK];
392
393 u64 reserved_0;
394#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
395 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
396 * Rxd in this blk */
397 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
398 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
399 * the upper 32 bits should
400 * be 0 */
401} RxD_block_t;
402#else
403typedef struct _RxD_block {
404#define MAX_RXDS_PER_BLOCK 85
405 RxD_t rxd[MAX_RXDS_PER_BLOCK];
406
407#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
408 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
409 * in this blk */
410 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
411} RxD_block_t;
412#define SIZE_OF_BLOCK 4096
413
414/* Structure to hold virtual addresses of Buf0 and Buf1 in
415 * 2buf mode. */
416typedef struct bufAdd {
417 void *ba_0_org;
418 void *ba_1_org;
419 void *ba_0;
420 void *ba_1;
421} buffAdd_t;
422#endif
423
424/* Structure which stores all the MAC control parameters */
425
426/* This structure stores the offset of the RxD in the ring
427 * from which the Rx Interrupt processor can start picking
428 * up the RxDs for processing.
429 */
430typedef struct _rx_curr_get_info_t {
431 u32 block_index;
432 u32 offset;
433 u32 ring_len;
434} rx_curr_get_info_t;
435
436typedef rx_curr_get_info_t rx_curr_put_info_t;
437
438/* This structure stores the offset of the TxDl in the FIFO
439 * from which the Tx Interrupt processor can start picking
440 * up the TxDLs for send complete interrupt processing.
441 */
442typedef struct {
443 u32 offset;
444 u32 fifo_len;
445} tx_curr_get_info_t;
446
447typedef tx_curr_get_info_t tx_curr_put_info_t;
448
449/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
450 * is maintained in this structure.
451 */
452typedef struct mac_info {
453/* rx side stuff */
454 /* Put pointer info which indictes which RxD has to be replenished
455 * with a new buffer.
456 */
457 rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
458
459 /* Get pointer info which indictes which is the last RxD that was
460 * processed by the driver.
461 */
462 rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
463
464 u16 rmac_pause_time;
465 u16 mc_pause_threshold_q0q3;
466 u16 mc_pause_threshold_q4q7;
467
468/* tx side stuff */
469 /* logical pointer of start of each Tx FIFO */
470 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
471
472/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
473 tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
474 tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
475
476 void *stats_mem; /* orignal pointer to allocated mem */
477 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
478 u32 stats_mem_sz;
479 StatInfo_t *stats_info; /* Logical address of the stat block */
480} mac_info_t;
481
482/* structure representing the user defined MAC addresses */
483typedef struct {
484 char addr[ETH_ALEN];
485 int usage_cnt;
486} usr_addr_t;
487
488/* Structure that holds the Phy and virt addresses of the Blocks */
489typedef struct rx_block_info {
490 RxD_t *block_virt_addr;
491 dma_addr_t block_dma_addr;
492} rx_block_info_t;
493
494/* Default Tunable parameters of the NIC. */
495#define DEFAULT_FIFO_LEN 4096
496#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
497#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
498#define SMALL_BLK_CNT 30
499#define LARGE_BLK_CNT 100
500
501/* Structure representing one instance of the NIC */
502typedef struct s2io_nic {
503#define MAX_MAC_SUPPORTED 16
504#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
505
506 macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
507 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
508
509 struct net_device_stats stats;
510 void __iomem *bar0;
511 void __iomem *bar1;
512 struct config_param config;
513 mac_info_t mac_control;
514 int high_dma_flag;
515 int device_close_flag;
516 int device_enabled_once;
517
518 char name[32];
519 struct tasklet_struct task;
520 volatile unsigned long tasklet_status;
521 struct timer_list timer;
522 struct net_device *dev;
523 struct pci_dev *pdev;
524
525 u16 vendor_id;
526 u16 device_id;
527 u16 ccmd;
528 u32 cbar0_1;
529 u32 cbar0_2;
530 u32 cbar1_1;
531 u32 cbar1_2;
532 u32 cirq;
533 u8 cache_line;
534 u32 rom_expansion;
535 u16 pcix_cmd;
536 u32 irq;
537 atomic_t rx_bufs_left[MAX_RX_RINGS];
538
539 spinlock_t tx_lock;
540#ifndef CONFIG_S2IO_NAPI
541 spinlock_t put_lock;
542#endif
543
544#define PROMISC 1
545#define ALL_MULTI 2
546
547#define MAX_ADDRS_SUPPORTED 64
548 u16 usr_addr_count;
549 u16 mc_addr_count;
550 usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
551
552 u16 m_cast_flg;
553 u16 all_multi_pos;
554 u16 promisc_flg;
555
556 u16 tx_pkt_count;
557 u16 rx_pkt_count;
558 u16 tx_err_count;
559 u16 rx_err_count;
560
561#ifndef CONFIG_S2IO_NAPI
562 /* Index to the absolute position of the put pointer of Rx ring. */
563 int put_pos[MAX_RX_RINGS];
564#endif
565
566 /*
567 * Place holders for the virtual and physical addresses of
568 * all the Rx Blocks
569 */
570 rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
571 int block_count[MAX_RX_RINGS];
572 int pkt_cnt[MAX_RX_RINGS];
573
574 /* Place holder of all the TX List's Phy and Virt addresses. */
575 list_info_hold_t *list_info[MAX_TX_FIFOS];
576
577 /* Id timer, used to blink NIC to physically identify NIC. */
578 struct timer_list id_timer;
579
580 /* Restart timer, used to restart NIC if the device is stuck and
581 * a schedule task that will set the correct Link state once the
582 * NIC's PHY has stabilized after a state change.
583 */
584#ifdef INIT_TQUEUE
585 struct tq_struct rst_timer_task;
586 struct tq_struct set_link_task;
587#else
588 struct work_struct rst_timer_task;
589 struct work_struct set_link_task;
590#endif
591
592 /* Flag that can be used to turn on or turn off the Rx checksum
593 * offload feature.
594 */
595 int rx_csum;
596
597 /* after blink, the adapter must be restored with original
598 * values.
599 */
600 u64 adapt_ctrl_org;
601
602 /* Last known link state. */
603 u16 last_link_state;
604#define LINK_DOWN 1
605#define LINK_UP 2
606
607#ifdef CONFIG_2BUFF_MODE
608 /* Buffer Address store. */
609 buffAdd_t **ba[MAX_RX_RINGS];
610#endif
611 int task_flag;
612#define CARD_DOWN 1
613#define CARD_UP 2
614 atomic_t card_state;
615 volatile unsigned long link_state;
616} nic_t;
617
618#define RESET_ERROR 1;
619#define CMD_ERROR 2;
620
621/* OS related system calls */
622#ifndef readq
623static inline u64 readq(void __iomem *addr)
624{
625 u64 ret = readl(addr + 4);
626 ret <<= 32;
627 ret |= readl(addr);
628
629 return ret;
630}
631#endif
632
633#ifndef writeq
634static inline void writeq(u64 val, void __iomem *addr)
635{
636 writel((u32) (val), addr);
637 writel((u32) (val >> 32), (addr + 4));
638}
639
640/* In 32 bit modes, some registers have to be written in a
641 * particular order to expect correct hardware operation. The
642 * macro SPECIAL_REG_WRITE is used to perform such ordered
643 * writes. Defines UF (Upper First) and LF (Lower First) will
644 * be used to specify the required write order.
645 */
646#define UF 1
647#define LF 2
648static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
649{
650 if (order == LF) {
651 writel((u32) (val), addr);
652 writel((u32) (val >> 32), (addr + 4));
653 } else {
654 writel((u32) (val >> 32), (addr + 4));
655 writel((u32) (val), addr);
656 }
657}
658#else
659#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
660#endif
661
662/* Interrupt related values of Xena */
663
664#define ENABLE_INTRS 1
665#define DISABLE_INTRS 2
666
667/* Highest level interrupt blocks */
668#define TX_PIC_INTR (0x0001<<0)
669#define TX_DMA_INTR (0x0001<<1)
670#define TX_MAC_INTR (0x0001<<2)
671#define TX_XGXS_INTR (0x0001<<3)
672#define TX_TRAFFIC_INTR (0x0001<<4)
673#define RX_PIC_INTR (0x0001<<5)
674#define RX_DMA_INTR (0x0001<<6)
675#define RX_MAC_INTR (0x0001<<7)
676#define RX_XGXS_INTR (0x0001<<8)
677#define RX_TRAFFIC_INTR (0x0001<<9)
678#define MC_INTR (0x0001<<10)
679#define ENA_ALL_INTRS ( TX_PIC_INTR | \
680 TX_DMA_INTR | \
681 TX_MAC_INTR | \
682 TX_XGXS_INTR | \
683 TX_TRAFFIC_INTR | \
684 RX_PIC_INTR | \
685 RX_DMA_INTR | \
686 RX_MAC_INTR | \
687 RX_XGXS_INTR | \
688 RX_TRAFFIC_INTR | \
689 MC_INTR )
690
691/* Interrupt masks for the general interrupt mask register */
692#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
693
694#define TXPIC_INT_M BIT(0)
695#define TXDMA_INT_M BIT(1)
696#define TXMAC_INT_M BIT(2)
697#define TXXGXS_INT_M BIT(3)
698#define TXTRAFFIC_INT_M BIT(8)
699#define PIC_RX_INT_M BIT(32)
700#define RXDMA_INT_M BIT(33)
701#define RXMAC_INT_M BIT(34)
702#define MC_INT_M BIT(35)
703#define RXXGXS_INT_M BIT(36)
704#define RXTRAFFIC_INT_M BIT(40)
705
706/* PIC level Interrupts TODO*/
707
708/* DMA level Inressupts */
709#define TXDMA_PFC_INT_M BIT(0)
710#define TXDMA_PCC_INT_M BIT(2)
711
712/* PFC block interrupts */
713#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
714
715/* PCC block interrupts. */
716#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
717 PCC_FB_ECC Error. */
718
719/*
720 * Prototype declaration.
721 */
722static int __devinit s2io_init_nic(struct pci_dev *pdev,
723 const struct pci_device_id *pre);
724static void __devexit s2io_rem_nic(struct pci_dev *pdev);
725static int init_shared_mem(struct s2io_nic *sp);
726static void free_shared_mem(struct s2io_nic *sp);
727static int init_nic(struct s2io_nic *nic);
728#ifndef CONFIG_S2IO_NAPI
729static void rx_intr_handler(struct s2io_nic *sp);
730#endif
731static void tx_intr_handler(struct s2io_nic *sp);
732static void alarm_intr_handler(struct s2io_nic *sp);
733
734static int s2io_starter(void);
735static void s2io_closer(void);
736static void s2io_tx_watchdog(struct net_device *dev);
737static void s2io_tasklet(unsigned long dev_addr);
738static void s2io_set_multicast(struct net_device *dev);
739#ifndef CONFIG_2BUFF_MODE
740static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
741#else
742static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
743 buffAdd_t * ba);
744#endif
745static void s2io_link(nic_t * sp, int link);
746static void s2io_reset(nic_t * sp);
747#ifdef CONFIG_S2IO_NAPI
748static int s2io_poll(struct net_device *dev, int *budget);
749#endif
750static void s2io_init_pci(nic_t * sp);
751static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
752static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
753static int verify_xena_quiescence(u64 val64, int flag);
754static struct ethtool_ops netdev_ethtool_ops;
755static void s2io_set_link(unsigned long data);
756static int s2io_set_swapper(nic_t * sp);
757static void s2io_card_down(nic_t * nic);
758static int s2io_card_up(nic_t * nic);
759
760#endif /* _S2IO_H */