| Duy Truong | 790f06d | 2013-02-13 16:38:12 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_MSM_IRQS_9615_H |
| 14 | #define __ASM_ARCH_MSM_IRQS_9615_H |
| 15 | |
| 16 | /* MSM ACPU Interrupt Numbers */ |
| 17 | |
| Rohit Vaswani | ead426f | 2012-01-05 20:24:52 -0800 | [diff] [blame] | 18 | #define FIQ_START 16 |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 19 | |
| 20 | #define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) |
| 21 | #define INT_GP_TIMER_EXP (GIC_PPI_START + 2) |
| 22 | #define INT_GP_TIMER2_EXP (GIC_PPI_START + 3) |
| 23 | #define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4) |
| 24 | #define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5) |
| 25 | #define AVS_SVICINT (GIC_PPI_START + 6) |
| 26 | #define AVS_SVICINTSWDONE (GIC_PPI_START + 7) |
| 27 | #define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8) |
| 28 | #define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9) |
| 29 | #define INT_ARMQC_PERFMON (GIC_PPI_START + 10) |
| 30 | #define SC_AVSCPUXDOWN (GIC_PPI_START + 11) |
| 31 | #define SC_AVSCPUXUP (GIC_PPI_START + 12) |
| 32 | #define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13) |
| 33 | #define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14) |
| 34 | /* PPI 15 is unused */ |
| 35 | |
| 36 | #define APCC_QGICACGIRPTREQ (GIC_SPI_START + 0) |
| 37 | #define APCC_QGICL2PERFMONIRPTREQ (GIC_SPI_START + 1) |
| 38 | #define SC_SICL2PERFMONIRPTREQ APCC_QGICL2PERFMONIRPTREQ |
| 39 | #define APCC_QGICL2IRPTREQ (GIC_SPI_START + 2) |
| 40 | #define APCC_QGICMPUIRPTREQ (GIC_SPI_START + 3) |
| 41 | #define TLMM_MSM_DIR_CONN_IRQ_0 (GIC_SPI_START + 4) |
| 42 | #define TLMM_MSM_DIR_CONN_IRQ_1 (GIC_SPI_START + 5) |
| 43 | #define TLMM_MSM_DIR_CONN_IRQ_2 (GIC_SPI_START + 6) |
| 44 | #define TLMM_MSM_DIR_CONN_IRQ_3 (GIC_SPI_START + 7) |
| 45 | #define TLMM_MSM_DIR_CONN_IRQ_4 (GIC_SPI_START + 8) |
| 46 | #define TLMM_MSM_DIR_CONN_IRQ_5 (GIC_SPI_START + 9) |
| 47 | #define TLMM_MSM_DIR_CONN_IRQ_6 (GIC_SPI_START + 10) |
| 48 | #define TLMM_MSM_DIR_CONN_IRQ_7 (GIC_SPI_START + 11) |
| 49 | #define TLMM_MSM_DIR_CONN_IRQ_8 (GIC_SPI_START + 12) |
| 50 | #define TLMM_MSM_DIR_CONN_IRQ_9 (GIC_SPI_START + 13) |
| 51 | /* 14 Reserved */ |
| 52 | #define PM8018_SEC_IRQ_N (GIC_SPI_START + 15) |
| 53 | #define TLMM_MSM_SUMMARY_IRQ (GIC_SPI_START + 16) |
| 54 | #define SPDM_RT_1_IRQ (GIC_SPI_START + 17) |
| 55 | #define SPDM_DIAG_IRQ (GIC_SPI_START + 18) |
| 56 | #define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19) |
| 57 | #define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20) |
| 58 | #define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21) |
| 59 | #define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22) |
| 60 | /* 23-28 Reserved */ |
| 61 | #define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29) |
| 62 | #define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30) |
| 63 | /* 31 Reserved */ |
| 64 | #define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32) |
| 65 | #define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33) |
| 66 | #define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34) |
| Rohit Vaswani | 56dd22a | 2011-11-11 16:21:28 -0800 | [diff] [blame] | 67 | #define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35) |
| 68 | #define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36) |
| Jeff Hugo | 56b933a | 2011-09-28 14:42:05 -0600 | [diff] [blame] | 69 | #define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37) |
| 70 | #define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38) |
| 71 | #define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39) |
| 72 | #define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40) |
| 73 | #define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41) |
| 74 | #define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42) |
| 75 | #define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43) |
| 76 | #define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44) |
| 77 | #define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45) |
| 78 | #define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46) |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 79 | /* 47-84 Reserved */ |
| 80 | #define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85) |
| 81 | #define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86) |
| 82 | #define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87) |
| 83 | #define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88) |
| 84 | #define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89) |
| 85 | #define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90) |
| 86 | #define TOP_IMEM_IRQ (GIC_SPI_START + 91) |
| 87 | #define FABRIC_SYS_IRQ (GIC_SPI_START + 92) |
| 88 | /* 93 Reserved */ |
| 89 | #define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) |
| 90 | /* 95,96 unnamed */ |
| 91 | #define SDC2_BAM_IRQ (GIC_SPI_START + 97) |
| 92 | #define SDC1_BAM_IRQ (GIC_SPI_START + 98) |
| 93 | #define FABRIC_SPS_IRQ (GIC_SPI_START + 99) |
| 94 | #define USB1_HS_IRQ (GIC_SPI_START + 100) |
| 95 | /* 101,102 unnamed */ |
| 96 | #define SDC2_IRQ_0 (GIC_SPI_START + 103) |
| 97 | #define SDC1_IRQ_0 (GIC_SPI_START + 104) |
| 98 | #define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105) |
| 99 | #define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106) |
| 100 | #define SPS_MTI_0 (GIC_SPI_START + 107) |
| 101 | #define SPS_MTI_1 (GIC_SPI_START + 108) |
| 102 | #define SPS_MTI_2 (GIC_SPI_START + 109) |
| 103 | #define SPS_MTI_3 (GIC_SPI_START + 110) |
| 104 | #define SPS_MTI_4 (GIC_SPI_START + 111) |
| 105 | #define SPS_MTI_5 (GIC_SPI_START + 112) |
| 106 | #define SPS_MTI_6 (GIC_SPI_START + 113) |
| 107 | #define SPS_MTI_7 (GIC_SPI_START + 114) |
| 108 | #define SPS_MTI_8 (GIC_SPI_START + 115) |
| 109 | #define SPS_MTI_9 (GIC_SPI_START + 116) |
| 110 | #define SPS_MTI_10 (GIC_SPI_START + 117) |
| 111 | #define SPS_MTI_11 (GIC_SPI_START + 118) |
| 112 | #define SPS_MTI_12 (GIC_SPI_START + 119) |
| 113 | #define SPS_MTI_13 (GIC_SPI_START + 120) |
| 114 | #define SPS_MTI_14 (GIC_SPI_START + 121) |
| 115 | #define SPS_MTI_15 (GIC_SPI_START + 122) |
| 116 | #define SPS_MTI_16 (GIC_SPI_START + 123) |
| 117 | #define SPS_MTI_17 (GIC_SPI_START + 124) |
| 118 | #define SPS_MTI_18 (GIC_SPI_START + 125) |
| 119 | #define SPS_MTI_19 (GIC_SPI_START + 126) |
| 120 | #define SPS_MTI_20 (GIC_SPI_START + 127) |
| 121 | #define SPS_MTI_21 (GIC_SPI_START + 128) |
| 122 | #define SPS_MTI_22 (GIC_SPI_START + 129) |
| 123 | #define SPS_MTI_23 (GIC_SPI_START + 130) |
| 124 | #define SPS_MTI_24 (GIC_SPI_START + 131) |
| 125 | #define SPS_MTI_25 (GIC_SPI_START + 132) |
| 126 | #define SPS_MTI_26 (GIC_SPI_START + 133) |
| 127 | #define SPS_MTI_27 (GIC_SPI_START + 134) |
| 128 | #define SPS_MTI_28 (GIC_SPI_START + 135) |
| 129 | #define SPS_MTI_29 (GIC_SPI_START + 136) |
| 130 | #define SPS_MTI_30 (GIC_SPI_START + 137) |
| 131 | #define SPS_MTI_31 (GIC_SPI_START + 138) |
| 132 | #define CSIPHY_0_4LN_IRQ (GIC_SPI_START + 139) |
| 133 | #define CSIPHY_1_2LN_IRQ (GIC_SPI_START + 140) |
| 134 | /* 141-145 Reserved */ |
| 135 | #define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146) |
| 136 | #define GSBI1_QUP_IRQ (GIC_SPI_START + 147) |
| 137 | #define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148) |
| 138 | #define GSBI2_QUP_IRQ (GIC_SPI_START + 149) |
| 139 | #define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150) |
| 140 | #define GSBI3_QUP_IRQ (GIC_SPI_START + 151) |
| 141 | #define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152) |
| 142 | #define GSBI4_QUP_IRQ (GIC_SPI_START + 153) |
| 143 | #define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154) |
| 144 | #define GSBI5_QUP_IRQ (GIC_SPI_START + 155) |
| 145 | /* 156-167 Reserved */ |
| 146 | #define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168) |
| 147 | #define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169) |
| 148 | #define ADM_0_SCSS_0_IRQ (GIC_SPI_START + 170) |
| 149 | #define ADM_0_SCSS_1_IRQ (GIC_SPI_START + 171) |
| 150 | #define ADM_0_SCSS_2_IRQ (GIC_SPI_START + 172) |
| 151 | #define ADM_0_SCSS_3_IRQ (GIC_SPI_START + 173) |
| 152 | /* 174 Reserved */ |
| 153 | #define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175) |
| 154 | /* 176 Reserved */ |
| 155 | #define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177) |
| 156 | #define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178) |
| 157 | /* 179-182 Reserved */ |
| 158 | #define XPU_SUMMARY_IRQ (GIC_SPI_START + 183) |
| 159 | #define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184) |
| 160 | #define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185) |
| 161 | /* 186-208 Reserved */ |
| 162 | #define A2_BAM_IRQ (GIC_SPI_START + 209) |
| 163 | /* 210-215 Reserved */ |
| 164 | #define QDSS_ETB_IRQ (GIC_SPI_START + 216) |
| 165 | /* 216 Reserved */ |
| 166 | #define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218) |
| 167 | #define TLMM_MSM_DIR_CONN_IRQ_16 (GIC_SPI_START + 219) |
| 168 | #define TLMM_MSM_DIR_CONN_IRQ_17 (GIC_SPI_START + 220) |
| 169 | #define TLMM_MSM_DIR_CONN_IRQ_18 (GIC_SPI_START + 221) |
| 170 | #define TLMM_MSM_DIR_CONN_IRQ_19 (GIC_SPI_START + 222) |
| 171 | #define TLMM_MSM_DIR_CONN_IRQ_20 (GIC_SPI_START + 223) |
| 172 | #define TLMM_MSM_DIR_CONN_IRQ_21 (GIC_SPI_START + 224) |
| 173 | #define MSM_SPARE0_IRQ (GIC_SPI_START + 225) |
| 174 | #define PMIC_SEC_IRQ_N (GIC_SPI_START + 226) |
| Ofir Cohen | 010009b | 2012-01-26 16:49:17 +0200 | [diff] [blame] | 175 | #define USB_HSIC_BAM_IRQ (GIC_SPI_START + 231) |
| Ofir Cohen | 06789f1 | 2012-01-16 09:43:13 +0200 | [diff] [blame] | 176 | #define USB_HSIC_IRQ (GIC_SPI_START + 232) |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 177 | |
| Ofir Cohen | 06789f1 | 2012-01-16 09:43:13 +0200 | [diff] [blame] | 178 | #define NR_MSM_IRQS 288 |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 179 | #define NR_GPIO_IRQS 88 |
| David Collins | fb88c43 | 2011-08-25 15:12:47 -0700 | [diff] [blame] | 180 | #define NR_PM8018_IRQS 256 |
| Shiv Maliyappanahalli | 9ec55e9 | 2012-01-09 14:44:59 -0800 | [diff] [blame] | 181 | #define NR_WCD9XXX_IRQS 49 |
| 182 | #define NR_TABLA_IRQS NR_WCD9XXX_IRQS |
| 183 | #define NR_BOARD_IRQS (NR_PM8018_IRQS + NR_WCD9XXX_IRQS) |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 184 | #define NR_MSM_GPIOS NR_GPIO_IRQS |
| 185 | |
| 186 | /* Backwards compatible IRQ macros. */ |
| 187 | #define INT_ADM_AARM ADM_0_SCSS_0_IRQ |
| 188 | |
| 189 | /* smd/smsm interrupts */ |
| 190 | #define INT_A9_M2A_0 MSS_TO_APPS_IRQ_0 |
| 191 | #define INT_A9_M2A_5 MSS_TO_APPS_IRQ_1 |
| 192 | #define INT_ADSP_A11 LPASS_SCSS_GP_HIGH_IRQ |
| 193 | #define INT_ADSP_A11_SMSM LPASS_SCSS_GP_MEDIUM_IRQ |
| Rohit Vaswani | 01c8631 | 2011-08-16 15:25:24 -0700 | [diff] [blame] | 194 | |
| 195 | #endif |