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gerrit-public.fairphone.software / kernel / msm / ea2c51da25e76c7f16a26b7931232bcc39f23405 / . / arch / arm / mach-msm / clock-8226.c
blob: 8e2b7c93380057c581af0b9024457d91880a2cb3 [file] [log] [blame]
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/iopoll.h>
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]22#include <linux/regulator/consumer.h>
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]23
24#include <mach/rpm-regulator-smd.h>
25#include <mach/socinfo.h>
26#include <mach/rpm-smd.h>
27
28#include "clock-local2.h"
29#include "clock-pll.h"
30#include "clock-rpm.h"
31#include "clock-voter.h"
32#include "clock-mdss-8974.h"
33#include "clock.h"
34
35enum {
36 GCC_BASE,
37 MMSS_BASE,
38 LPASS_BASE,
39 APCS_BASE,
40 APCS_PLL_BASE,
41 N_BASES,
42};
43
44static void __iomem *virt_bases[N_BASES];
45
46#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
47#define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x))
48#define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x))
49#define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x))
50
51/* Mux source select values */
52#define xo_source_val 0
53#define gpll0_source_val 1
54#define gpll1_source_val 2
55
56#define xo_mm_source_val 0
57#define mmpll0_pll_mm_source_val 1
58#define mmpll1_pll_mm_source_val 2
59#define mmpll2_pll_mm_source_val 3
60#define gpll0_mm_source_val 5
61#define dsipll_750_mm_source_val 1
62#define dsipll_667_mm_source_val 1
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]63#define dsipll0_byte_mm_source_val 1
64#define dsipll0_pixel_mm_source_val 1
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]65
66#define gpll1_hsic_source_val 4
67
68#define xo_lpass_source_val 0
69#define lpaaudio_pll_lpass_source_val 1
70#define gpll0_lpass_source_val 5
71
72/* Prevent a divider of -1 */
73#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
74
75#define F_GCC(f, s, div, m, n) \
76 { \
77 .freq_hz = (f), \
78 .src_clk = &s.c, \
79 .m_val = (m), \
80 .n_val = ~((n)-(m)) * !!(n), \
81 .d_val = ~(n),\
82 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
83 | BVAL(10, 8, s##_source_val), \
84 }
85
86#define F_MMSS(f, s, div, m, n) \
87 { \
88 .freq_hz = (f), \
89 .src_clk = &s.c, \
90 .m_val = (m), \
91 .n_val = ~((n)-(m)) * !!(n), \
92 .d_val = ~(n),\
93 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
94 | BVAL(10, 8, s##_mm_source_val), \
95 }
96
97#define F_MDSS(f, s, div, m, n) \
98 { \
99 .freq_hz = (f), \
100 .m_val = (m), \
101 .n_val = ~((n)-(m)) * !!(n), \
102 .d_val = ~(n),\
103 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
104 | BVAL(10, 8, s##_mm_source_val), \
105 }
106
107#define F_HSIC(f, s, div, m, n) \
108 { \
109 .freq_hz = (f), \
110 .src_clk = &s.c, \
111 .m_val = (m), \
112 .n_val = ~((n)-(m)) * !!(n), \
113 .d_val = ~(n),\
114 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
115 | BVAL(10, 8, s##_hsic_source_val), \
116 }
117
118#define F_LPASS(f, s, div, m, n) \
119 { \
120 .freq_hz = (f), \
121 .src_clk = &s.c, \
122 .m_val = (m), \
123 .n_val = ~((n)-(m)) * !!(n), \
124 .d_val = ~(n),\
125 .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \
126 | BVAL(10, 8, s##_lpass_source_val), \
127 }
128
129#define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \
130 { \
131 .freq_hz = (f), \
132 .l_val = (l), \
133 .m_val = (m), \
134 .n_val = (n), \
135 .pre_div_val = BVAL(12, 12, (pre_div)), \
136 .post_div_val = BVAL(9, 8, (post_div)), \
137 .vco_val = BVAL(29, 28, (vco)), \
138 }
139
140#define VDD_DIG_FMAX_MAP1(l1, f1) \
141 .vdd_class = &vdd_dig, \
142 .fmax = (unsigned long[VDD_DIG_NUM]) { \
143 [VDD_DIG_##l1] = (f1), \
144 }, \
145 .num_fmax = VDD_DIG_NUM
146
147#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
148 .vdd_class = &vdd_dig, \
149 .fmax = (unsigned long[VDD_DIG_NUM]) { \
150 [VDD_DIG_##l1] = (f1), \
151 [VDD_DIG_##l2] = (f2), \
152 }, \
153 .num_fmax = VDD_DIG_NUM
154
155#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
156 .vdd_class = &vdd_dig, \
157 .fmax = (unsigned long[VDD_DIG_NUM]) { \
158 [VDD_DIG_##l1] = (f1), \
159 [VDD_DIG_##l2] = (f2), \
160 [VDD_DIG_##l3] = (f3), \
161 }, \
162 .num_fmax = VDD_DIG_NUM
163
164enum vdd_dig_levels {
165 VDD_DIG_NONE,
166 VDD_DIG_LOW,
167 VDD_DIG_NOMINAL,
168 VDD_DIG_HIGH,
169 VDD_DIG_NUM
170};
171
172static const int vdd_corner[] = {
173 [VDD_DIG_NONE] = RPM_REGULATOR_CORNER_NONE,
174 [VDD_DIG_LOW] = RPM_REGULATOR_CORNER_SVS_SOC,
175 [VDD_DIG_NOMINAL] = RPM_REGULATOR_CORNER_NORMAL,
176 [VDD_DIG_HIGH] = RPM_REGULATOR_CORNER_SUPER_TURBO,
177};
178
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]179static struct regulator *vdd_dig_reg;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]180
181static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level)
182{
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]183 return regulator_set_voltage(vdd_dig_reg, vdd_corner[level],
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]184 RPM_REGULATOR_CORNER_SUPER_TURBO);
185}
186
187static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig, VDD_DIG_NUM);
188
189#define RPM_MISC_CLK_TYPE 0x306b6c63
190#define RPM_BUS_CLK_TYPE 0x316b6c63
191#define RPM_MEM_CLK_TYPE 0x326b6c63
192
193#define RPM_SMD_KEY_ENABLE 0x62616E45
194
195#define CXO_ID 0x0
196#define QDSS_ID 0x1
197
198#define PNOC_ID 0x0
199#define SNOC_ID 0x1
200#define CNOC_ID 0x2
201#define MMSSNOC_AHB_ID 0x3
202
203#define BIMC_ID 0x0
204#define OXILI_ID 0x1
205#define OCMEM_ID 0x2
206
207#define D0_ID 1
208#define D1_ID 2
209#define A0_ID 4
210#define A1_ID 5
211#define A2_ID 6
212#define DIFF_CLK_ID 7
213#define DIV_CLK1_ID 11
214#define DIV_CLK2_ID 12
215
216DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL);
217DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL);
218DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL);
219DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE,
220 MMSSNOC_AHB_ID, NULL);
221
222DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL);
223DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID,
224 NULL);
225DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID,
226 NULL);
227
228DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk,
229 RPM_MISC_CLK_TYPE, CXO_ID, 19200000);
230DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID);
231
232DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID);
233DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID);
234DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID);
235DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID);
236DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID);
237DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID);
238DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID);
239DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID);
240
241DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID);
242DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID);
243DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID);
244DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID);
245DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID);
246
247struct measure_mux_entry {
248 struct clk *c;
249 int base;
250 u32 debug_mux;
251};
252
253static struct branch_clk oxilicx_axi_clk;
254
255#define MSS_DEBUG_CLOCK_CTL 0x0078
256#define LPASS_DEBUG_CLK_CTL 0x29000
257#define GLB_CLK_DIAG 0x01C
258#define GLB_TEST_BUS_SEL 0x020
259
260#define MMPLL0_PLL_MODE (0x0000)
261#define MMPLL0_PLL_L_VAL (0x0004)
262#define MMPLL0_PLL_M_VAL (0x0008)
263#define MMPLL0_PLL_N_VAL (0x000C)
264#define MMPLL0_PLL_USER_CTL (0x0010)
265#define MMPLL0_PLL_STATUS (0x001C)
266#define MMPLL1_PLL_MODE (0x0040)
267#define MMPLL1_PLL_L_VAL (0x0044)
268#define MMPLL1_PLL_M_VAL (0x0048)
269#define MMPLL1_PLL_N_VAL (0x004C)
270#define MMPLL1_PLL_USER_CTL (0x0050)
271#define MMPLL1_PLL_STATUS (0x005C)
272#define MMSS_PLL_VOTE_APCS (0x0100)
273#define VCODEC0_CMD_RCGR (0x1000)
274#define VENUS0_VCODEC0_CBCR (0x1028)
275#define VENUS0_AHB_CBCR (0x1030)
276#define VENUS0_AXI_CBCR (0x1034)
277#define PCLK0_CMD_RCGR (0x2000)
278#define MDP_CMD_RCGR (0x2040)
279#define VSYNC_CMD_RCGR (0x2080)
280#define BYTE0_CMD_RCGR (0x2120)
281#define ESC0_CMD_RCGR (0x2160)
282#define MDSS_AHB_CBCR (0x2308)
283#define MDSS_AXI_CBCR (0x2310)
284#define MDSS_PCLK0_CBCR (0x2314)
285#define MDSS_MDP_CBCR (0x231C)
286#define MDSS_MDP_LUT_CBCR (0x2320)
287#define MDSS_VSYNC_CBCR (0x2328)
288#define MDSS_BYTE0_CBCR (0x233C)
289#define MDSS_ESC0_CBCR (0x2344)
290#define CSI0PHYTIMER_CMD_RCGR (0x3000)
291#define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024)
292#define CSI1PHYTIMER_CMD_RCGR (0x3030)
293#define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054)
294#define CSI0_CMD_RCGR (0x3090)
295#define CAMSS_CSI0_CBCR (0x30B4)
296#define CAMSS_CSI0_AHB_CBCR (0x30BC)
297#define CAMSS_CSI0PHY_CBCR (0x30C4)
298#define CAMSS_CSI0RDI_CBCR (0x30D4)
299#define CAMSS_CSI0PIX_CBCR (0x30E4)
300#define CSI1_CMD_RCGR (0x3100)
301#define CAMSS_CSI1_CBCR (0x3124)
302#define CAMSS_CSI1_AHB_CBCR (0x3128)
303#define CAMSS_CSI1PHY_CBCR (0x3134)
304#define CAMSS_CSI1RDI_CBCR (0x3144)
305#define CAMSS_CSI1PIX_CBCR (0x3154)
306#define CAMSS_ISPIF_AHB_CBCR (0x3224)
307#define CCI_CMD_RCGR (0x3300)
308#define CAMSS_CCI_CCI_CBCR (0x3344)
309#define CAMSS_CCI_CCI_AHB_CBCR (0x3348)
310#define MCLK0_CMD_RCGR (0x3360)
311#define CAMSS_MCLK0_CBCR (0x3384)
312#define MCLK1_CMD_RCGR (0x3390)
313#define CAMSS_MCLK1_CBCR (0x33B4)
314#define MMSS_GP0_CMD_RCGR (0x3420)
315#define CAMSS_GP0_CBCR (0x3444)
316#define MMSS_GP1_CMD_RCGR (0x3450)
317#define CAMSS_GP1_CBCR (0x3474)
318#define CAMSS_TOP_AHB_CBCR (0x3484)
319#define CAMSS_MICRO_AHB_CBCR (0x3494)
320#define JPEG0_CMD_RCGR (0x3500)
321#define CAMSS_JPEG_JPEG0_CBCR (0x35A8)
322#define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4)
323#define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8)
324#define VFE0_CMD_RCGR (0x3600)
325#define CPP_CMD_RCGR (0x3640)
326#define CAMSS_VFE_VFE0_CBCR (0x36A8)
327#define CAMSS_VFE_CPP_CBCR (0x36B0)
328#define CAMSS_VFE_CPP_AHB_CBCR (0x36B4)
329#define CAMSS_VFE_VFE_AHB_CBCR (0x36B8)
330#define CAMSS_VFE_VFE_AXI_CBCR (0x36BC)
331#define CAMSS_CSI_VFE0_CBCR (0x3704)
332#define OXILI_GFX3D_CBCR (0x4028)
333#define OXILICX_AXI_CBCR (0x4038)
334#define OXILICX_AHB_CBCR (0x403C)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]335#define MMPLL2_PLL_MODE (0x4100)
336#define MMPLL2_PLL_STATUS (0x411C)
337#define MMSS_MMSSNOC_AHB_CBCR (0x5024)
338#define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028)
339#define MMSS_MISC_AHB_CBCR (0x502C)
340#define AXI_CMD_RCGR (0x5040)
341#define MMSS_S0_AXI_CBCR (0x5064)
342#define MMSS_MMSSNOC_AXI_CBCR (0x506C)
343#define MMSS_DEBUG_CLK_CTL (0x0900)
344#define GPLL0_MODE (0x0000)
345#define GPLL0_L_VAL (0x0004)
346#define GPLL0_M_VAL (0x0008)
347#define GPLL0_N_VAL (0x000C)
348#define GPLL0_USER_CTL (0x0010)
349#define GPLL0_STATUS (0x001C)
350#define GPLL1_MODE (0x0040)
351#define GPLL1_L_VAL (0x0044)
352#define GPLL1_M_VAL (0x0048)
353#define GPLL1_N_VAL (0x004C)
354#define GPLL1_USER_CTL (0x0050)
355#define GPLL1_STATUS (0x005C)
356#define PERIPH_NOC_AHB_CBCR (0x0184)
357#define NOC_CONF_XPU_AHB_CBCR (0x01C0)
358#define MMSS_NOC_CFG_AHB_CBCR (0x024C)
359#define MSS_CFG_AHB_CBCR (0x0280)
360#define MSS_Q6_BIMC_AXI_CBCR (0x0284)
361#define USB_HS_HSIC_BCR (0x0400)
362#define USB_HSIC_AHB_CBCR (0x0408)
363#define USB_HSIC_SYSTEM_CMD_RCGR (0x041C)
364#define USB_HSIC_SYSTEM_CBCR (0x040C)
365#define USB_HSIC_CMD_RCGR (0x0440)
366#define USB_HSIC_CBCR (0x0410)
367#define USB_HSIC_IO_CAL_CMD_RCGR (0x0458)
368#define USB_HSIC_IO_CAL_CBCR (0x0414)
369#define USB_HS_BCR (0x0480)
370#define USB_HS_SYSTEM_CBCR (0x0484)
371#define USB_HS_AHB_CBCR (0x0488)
372#define USB_HS_SYSTEM_CMD_RCGR (0x0490)
373#define USB2A_PHY_SLEEP_CBCR (0x04AC)
374#define SDCC1_APPS_CMD_RCGR (0x04D0)
375#define SDCC1_APPS_CBCR (0x04C4)
376#define SDCC1_AHB_CBCR (0x04C8)
377#define SDCC2_APPS_CMD_RCGR (0x0510)
378#define SDCC2_APPS_CBCR (0x0504)
379#define SDCC2_AHB_CBCR (0x0508)
380#define SDCC3_APPS_CMD_RCGR (0x0550)
381#define SDCC3_APPS_CBCR (0x0544)
382#define SDCC3_AHB_CBCR (0x0548)
383#define BLSP1_AHB_CBCR (0x05C4)
384#define BLSP1_QUP1_SPI_APPS_CBCR (0x0644)
385#define BLSP1_QUP1_I2C_APPS_CBCR (0x0648)
386#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660)
387#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0)
388#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760)
389#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0)
390#define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860)
391#define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0)
392#define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C)
393#define BLSP1_UART1_APPS_CBCR (0x0684)
394#define BLSP1_UART1_APPS_CMD_RCGR (0x068C)
395#define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4)
396#define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8)
397#define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC)
398#define BLSP1_UART2_APPS_CBCR (0x0704)
399#define BLSP1_UART2_APPS_CMD_RCGR (0x070C)
400#define BLSP1_QUP3_SPI_APPS_CBCR (0x0744)
401#define BLSP1_QUP3_I2C_APPS_CBCR (0x0748)
402#define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C)
403#define BLSP1_UART3_APPS_CBCR (0x0784)
404#define BLSP1_UART3_APPS_CMD_RCGR (0x078C)
405#define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4)
406#define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8)
407#define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC)
408#define BLSP1_UART4_APPS_CBCR (0x0804)
409#define BLSP1_UART4_APPS_CMD_RCGR (0x080C)
410#define BLSP1_QUP5_SPI_APPS_CBCR (0x0844)
411#define BLSP1_QUP5_I2C_APPS_CBCR (0x0848)
412#define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C)
413#define BLSP1_UART5_APPS_CBCR (0x0884)
414#define BLSP1_UART5_APPS_CMD_RCGR (0x088C)
415#define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4)
416#define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8)
417#define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC)
418#define BLSP1_UART6_APPS_CBCR (0x0904)
419#define BLSP1_UART6_APPS_CMD_RCGR (0x090C)
420#define PDM_AHB_CBCR (0x0CC4)
421#define PDM_XO4_CBCR (0x0CC8)
422#define PDM2_CBCR (0x0CCC)
423#define PDM2_CMD_RCGR (0x0CD0)
424#define PRNG_AHB_CBCR (0x0D04)
425#define BAM_DMA_AHB_CBCR (0x0D44)
426#define BOOT_ROM_AHB_CBCR (0x0E04)
427#define CE1_CMD_RCGR (0x1050)
428#define CE1_CBCR (0x1044)
429#define CE1_AXI_CBCR (0x1048)
430#define CE1_AHB_CBCR (0x104C)
431#define GCC_XO_DIV4_CBCR (0x10C8)
432#define LPASS_Q6_AXI_CBCR (0x11C0)
433#define APCS_GPLL_ENA_VOTE (0x1480)
434#define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484)
435#define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488)
436#define GCC_DEBUG_CLK_CTL (0x1880)
437#define CLOCK_FRQ_MEASURE_CTL (0x1884)
438#define CLOCK_FRQ_MEASURE_STATUS (0x1888)
439#define PLLTEST_PAD_CFG (0x188C)
440#define GP1_CBCR (0x1900)
441#define GP1_CMD_RCGR (0x1904)
442#define GP2_CBCR (0x1940)
443#define GP2_CMD_RCGR (0x1944)
444#define GP3_CBCR (0x1980)
445#define GP3_CMD_RCGR (0x1984)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]446#define Q6SS_BCR (0x6000)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]447#define Q6SS_AHB_LFABIF_CBCR (0x22000)
448#define Q6SS_AHBM_CBCR (0x22004)
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]449#define Q6SS_XO_CBCR (0x26000)
450
451static unsigned int soft_vote_gpll0;
452
453static struct pll_vote_clk gpll0 = {
454 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
455 .en_mask = BIT(0),
456 .status_reg = (void __iomem *)GPLL0_STATUS,
457 .status_mask = BIT(17),
458 .soft_vote = &soft_vote_gpll0,
459 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
460 .base = &virt_bases[GCC_BASE],
461 .c = {
462 .rate = 600000000,
463 .parent = &xo.c,
464 .dbg_name = "gpll0",
465 .ops = &clk_ops_pll_acpu_vote,
466 CLK_INIT(gpll0.c),
467 },
468};
469
470/*Don't vote for xo if using this clock to allow xo shutdown*/
471static struct pll_vote_clk gpll0_ao = {
472 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
473 .en_mask = BIT(0),
474 .status_reg = (void __iomem *)GPLL0_STATUS,
475 .status_mask = BIT(17),
476 .soft_vote = &soft_vote_gpll0,
477 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
478 .base = &virt_bases[GCC_BASE],
479 .c = {
480 .rate = 600000000,
481 .dbg_name = "gpll0_ao",
482 .ops = &clk_ops_pll_acpu_vote,
483 CLK_INIT(gpll0_ao.c),
484 },
485};
486
487static struct pll_vote_clk gpll1 = {
488 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
489 .en_mask = BIT(1),
490 .status_reg = (void __iomem *)GPLL1_STATUS,
491 .status_mask = BIT(17),
492 .base = &virt_bases[GCC_BASE],
493 .c = {
494 .rate = 480000000,
495 .parent = &xo.c,
496 .dbg_name = "gpll1",
497 .ops = &clk_ops_pll_vote,
498 CLK_INIT(gpll1.c),
499 },
500};
501
502static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]503 F_GCC( 19200000, xo, 1, 0, 0),
504 F_GCC( 50000000, gpll0, 12, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]505 F_END
506};
507
508static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
509 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
510 .set_rate = set_rate_hid,
511 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
512 .current_freq = &rcg_dummy_freq,
513 .base = &virt_bases[GCC_BASE],
514 .c = {
515 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
516 .ops = &clk_ops_rcg,
517 VDD_DIG_FMAX_MAP1(LOW, 50000000),
518 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
519 },
520};
521
522static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
523 F_GCC( 960000, xo, 10, 1, 2),
524 F_GCC( 4800000, xo, 4, 0, 0),
525 F_GCC( 9600000, xo, 2, 0, 0),
526 F_GCC( 15000000, gpll0, 10, 1, 4),
527 F_GCC( 19200000, xo, 1, 0, 0),
528 F_GCC( 25000000, gpll0, 12, 1, 2),
529 F_GCC( 50000000, gpll0, 12, 0, 0),
530 F_END
531};
532
533static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
534 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
535 .set_rate = set_rate_mnd,
536 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
537 .current_freq = &rcg_dummy_freq,
538 .base = &virt_bases[GCC_BASE],
539 .c = {
540 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
541 .ops = &clk_ops_rcg_mnd,
542 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
543 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
544 },
545};
546
547static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
548 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
549 .set_rate = set_rate_hid,
550 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
551 .current_freq = &rcg_dummy_freq,
552 .base = &virt_bases[GCC_BASE],
553 .c = {
554 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
555 .ops = &clk_ops_rcg,
556 VDD_DIG_FMAX_MAP1(LOW, 50000000),
557 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
558 },
559};
560
561static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
562 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
563 .set_rate = set_rate_mnd,
564 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
565 .current_freq = &rcg_dummy_freq,
566 .base = &virt_bases[GCC_BASE],
567 .c = {
568 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
569 .ops = &clk_ops_rcg_mnd,
570 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
571 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
572 },
573};
574
575static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
576 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
577 .set_rate = set_rate_hid,
578 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
579 .current_freq = &rcg_dummy_freq,
580 .base = &virt_bases[GCC_BASE],
581 .c = {
582 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
583 .ops = &clk_ops_rcg,
584 VDD_DIG_FMAX_MAP1(LOW, 50000000),
585 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
586 },
587};
588
589static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
590 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
591 .set_rate = set_rate_mnd,
592 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
593 .current_freq = &rcg_dummy_freq,
594 .base = &virt_bases[GCC_BASE],
595 .c = {
596 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
597 .ops = &clk_ops_rcg_mnd,
598 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
599 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
600 },
601};
602
603static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
604 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
605 .set_rate = set_rate_hid,
606 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
607 .current_freq = &rcg_dummy_freq,
608 .base = &virt_bases[GCC_BASE],
609 .c = {
610 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
611 .ops = &clk_ops_rcg,
612 VDD_DIG_FMAX_MAP1(LOW, 50000000),
613 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
614 },
615};
616
617static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
618 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
619 .set_rate = set_rate_mnd,
620 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
621 .current_freq = &rcg_dummy_freq,
622 .base = &virt_bases[GCC_BASE],
623 .c = {
624 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
625 .ops = &clk_ops_rcg_mnd,
626 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
627 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
628 },
629};
630
631static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = {
632 .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR,
633 .set_rate = set_rate_hid,
634 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
635 .current_freq = &rcg_dummy_freq,
636 .base = &virt_bases[GCC_BASE],
637 .c = {
638 .dbg_name = "blsp1_qup5_i2c_apps_clk_src",
639 .ops = &clk_ops_rcg,
640 VDD_DIG_FMAX_MAP1(LOW, 50000000),
641 CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c),
642 },
643};
644
645static struct rcg_clk blsp1_qup5_spi_apps_clk_src = {
646 .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR,
647 .set_rate = set_rate_mnd,
648 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
649 .current_freq = &rcg_dummy_freq,
650 .base = &virt_bases[GCC_BASE],
651 .c = {
652 .dbg_name = "blsp1_qup5_spi_apps_clk_src",
653 .ops = &clk_ops_rcg_mnd,
654 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
655 CLK_INIT(blsp1_qup5_spi_apps_clk_src.c),
656 },
657};
658
659static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = {
660 .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR,
661 .set_rate = set_rate_hid,
662 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
663 .current_freq = &rcg_dummy_freq,
664 .base = &virt_bases[GCC_BASE],
665 .c = {
666 .dbg_name = "blsp1_qup6_i2c_apps_clk_src",
667 .ops = &clk_ops_rcg,
668 VDD_DIG_FMAX_MAP1(LOW, 50000000),
669 CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c),
670 },
671};
672
673static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
674 .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR,
675 .set_rate = set_rate_mnd,
676 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
677 .current_freq = &rcg_dummy_freq,
678 .base = &virt_bases[GCC_BASE],
679 .c = {
680 .dbg_name = "blsp1_qup6_spi_apps_clk_src",
681 .ops = &clk_ops_rcg_mnd,
682 VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000),
683 CLK_INIT(blsp1_qup6_spi_apps_clk_src.c),
684 },
685};
686
687static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
688 F_GCC( 3686400, gpll0, 1, 96, 15625),
689 F_GCC( 7372800, gpll0, 1, 192, 15625),
690 F_GCC( 14745600, gpll0, 1, 384, 15625),
691 F_GCC( 16000000, gpll0, 5, 2, 15),
692 F_GCC( 19200000, xo, 1, 0, 0),
693 F_GCC( 24000000, gpll0, 5, 1, 5),
694 F_GCC( 32000000, gpll0, 1, 4, 75),
695 F_GCC( 40000000, gpll0, 15, 0, 0),
696 F_GCC( 46400000, gpll0, 1, 29, 375),
697 F_GCC( 48000000, gpll0, 12.5, 0, 0),
698 F_GCC( 51200000, gpll0, 1, 32, 375),
699 F_GCC( 56000000, gpll0, 1, 7, 75),
700 F_GCC( 58982400, gpll0, 1, 1536, 15625),
701 F_GCC( 60000000, gpll0, 10, 0, 0),
702 F_END
703};
704
705static struct rcg_clk blsp1_uart1_apps_clk_src = {
706 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
707 .set_rate = set_rate_mnd,
708 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
709 .current_freq = &rcg_dummy_freq,
710 .base = &virt_bases[GCC_BASE],
711 .c = {
712 .dbg_name = "blsp1_uart1_apps_clk_src",
713 .ops = &clk_ops_rcg_mnd,
714 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
715 CLK_INIT(blsp1_uart1_apps_clk_src.c),
716 },
717};
718
719static struct rcg_clk blsp1_uart2_apps_clk_src = {
720 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
721 .set_rate = set_rate_mnd,
722 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
723 .current_freq = &rcg_dummy_freq,
724 .base = &virt_bases[GCC_BASE],
725 .c = {
726 .dbg_name = "blsp1_uart2_apps_clk_src",
727 .ops = &clk_ops_rcg_mnd,
728 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
729 CLK_INIT(blsp1_uart2_apps_clk_src.c),
730 },
731};
732
733static struct rcg_clk blsp1_uart3_apps_clk_src = {
734 .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR,
735 .set_rate = set_rate_mnd,
736 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
737 .current_freq = &rcg_dummy_freq,
738 .base = &virt_bases[GCC_BASE],
739 .c = {
740 .dbg_name = "blsp1_uart3_apps_clk_src",
741 .ops = &clk_ops_rcg_mnd,
742 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
743 CLK_INIT(blsp1_uart3_apps_clk_src.c),
744 },
745};
746
747static struct rcg_clk blsp1_uart4_apps_clk_src = {
748 .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR,
749 .set_rate = set_rate_mnd,
750 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
751 .current_freq = &rcg_dummy_freq,
752 .base = &virt_bases[GCC_BASE],
753 .c = {
754 .dbg_name = "blsp1_uart4_apps_clk_src",
755 .ops = &clk_ops_rcg_mnd,
756 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
757 CLK_INIT(blsp1_uart4_apps_clk_src.c),
758 },
759};
760
761static struct rcg_clk blsp1_uart5_apps_clk_src = {
762 .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR,
763 .set_rate = set_rate_mnd,
764 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
765 .current_freq = &rcg_dummy_freq,
766 .base = &virt_bases[GCC_BASE],
767 .c = {
768 .dbg_name = "blsp1_uart5_apps_clk_src",
769 .ops = &clk_ops_rcg_mnd,
770 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
771 CLK_INIT(blsp1_uart5_apps_clk_src.c),
772 },
773};
774
775static struct rcg_clk blsp1_uart6_apps_clk_src = {
776 .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR,
777 .set_rate = set_rate_mnd,
778 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
779 .current_freq = &rcg_dummy_freq,
780 .base = &virt_bases[GCC_BASE],
781 .c = {
782 .dbg_name = "blsp1_uart6_apps_clk_src",
783 .ops = &clk_ops_rcg_mnd,
784 VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000),
785 CLK_INIT(blsp1_uart6_apps_clk_src.c),
786 },
787};
788
789static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
790 F_GCC( 50000000, gpll0, 12, 0, 0),
791 F_GCC( 100000000, gpll0, 6, 0, 0),
792 F_END
793};
794
795static struct rcg_clk ce1_clk_src = {
796 .cmd_rcgr_reg = CE1_CMD_RCGR,
797 .set_rate = set_rate_hid,
798 .freq_tbl = ftbl_gcc_ce1_clk,
799 .current_freq = &rcg_dummy_freq,
800 .base = &virt_bases[GCC_BASE],
801 .c = {
802 .dbg_name = "ce1_clk_src",
803 .ops = &clk_ops_rcg,
804 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
805 CLK_INIT(ce1_clk_src.c),
806 },
807};
808
809static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
810 F_GCC( 19200000, xo, 1, 0, 0),
811 F_END
812};
813
814static struct rcg_clk gp1_clk_src = {
815 .cmd_rcgr_reg = GP1_CMD_RCGR,
816 .set_rate = set_rate_mnd,
817 .freq_tbl = ftbl_gcc_gp1_3_clk,
818 .current_freq = &rcg_dummy_freq,
819 .base = &virt_bases[GCC_BASE],
820 .c = {
821 .dbg_name = "gp1_clk_src",
822 .ops = &clk_ops_rcg_mnd,
823 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
824 CLK_INIT(gp1_clk_src.c),
825 },
826};
827
828static struct rcg_clk gp2_clk_src = {
829 .cmd_rcgr_reg = GP2_CMD_RCGR,
830 .set_rate = set_rate_mnd,
831 .freq_tbl = ftbl_gcc_gp1_3_clk,
832 .current_freq = &rcg_dummy_freq,
833 .base = &virt_bases[GCC_BASE],
834 .c = {
835 .dbg_name = "gp2_clk_src",
836 .ops = &clk_ops_rcg_mnd,
837 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
838 CLK_INIT(gp2_clk_src.c),
839 },
840};
841
842static struct rcg_clk gp3_clk_src = {
843 .cmd_rcgr_reg = GP3_CMD_RCGR,
844 .set_rate = set_rate_mnd,
845 .freq_tbl = ftbl_gcc_gp1_3_clk,
846 .current_freq = &rcg_dummy_freq,
847 .base = &virt_bases[GCC_BASE],
848 .c = {
849 .dbg_name = "gp3_clk_src",
850 .ops = &clk_ops_rcg_mnd,
851 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
852 CLK_INIT(gp3_clk_src.c),
853 },
854};
855
856static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
857 F_GCC( 60000000, gpll0, 10, 0, 0),
858 F_END
859};
860
861static struct rcg_clk pdm2_clk_src = {
862 .cmd_rcgr_reg = PDM2_CMD_RCGR,
863 .set_rate = set_rate_hid,
864 .freq_tbl = ftbl_gcc_pdm2_clk,
865 .current_freq = &rcg_dummy_freq,
866 .base = &virt_bases[GCC_BASE],
867 .c = {
868 .dbg_name = "pdm2_clk_src",
869 .ops = &clk_ops_rcg,
870 VDD_DIG_FMAX_MAP1(LOW, 60000000),
871 CLK_INIT(pdm2_clk_src.c),
872 },
873};
874
875static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = {
876 F_GCC( 144000, xo, 16, 3, 25),
877 F_GCC( 400000, xo, 12, 1, 4),
878 F_GCC( 20000000, gpll0, 15, 1, 2),
879 F_GCC( 25000000, gpll0, 12, 1, 2),
880 F_GCC( 50000000, gpll0, 12, 0, 0),
881 F_GCC( 100000000, gpll0, 6, 0, 0),
882 F_GCC( 200000000, gpll0, 3, 0, 0),
883 F_END
884};
885
886static struct rcg_clk sdcc1_apps_clk_src = {
887 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
888 .set_rate = set_rate_mnd,
889 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
890 .current_freq = &rcg_dummy_freq,
891 .base = &virt_bases[GCC_BASE],
892 .c = {
893 .dbg_name = "sdcc1_apps_clk_src",
894 .ops = &clk_ops_rcg_mnd,
895 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
896 CLK_INIT(sdcc1_apps_clk_src.c),
897 },
898};
899
900static struct rcg_clk sdcc2_apps_clk_src = {
901 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
902 .set_rate = set_rate_mnd,
903 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
904 .current_freq = &rcg_dummy_freq,
905 .base = &virt_bases[GCC_BASE],
906 .c = {
907 .dbg_name = "sdcc2_apps_clk_src",
908 .ops = &clk_ops_rcg_mnd,
909 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
910 CLK_INIT(sdcc2_apps_clk_src.c),
911 },
912};
913
914static struct rcg_clk sdcc3_apps_clk_src = {
915 .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,
916 .set_rate = set_rate_mnd,
917 .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk,
918 .current_freq = &rcg_dummy_freq,
919 .base = &virt_bases[GCC_BASE],
920 .c = {
921 .dbg_name = "sdcc3_apps_clk_src",
922 .ops = &clk_ops_rcg_mnd,
923 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
924 CLK_INIT(sdcc3_apps_clk_src.c),
925 },
926};
927
928static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
929 F_GCC( 75000000, gpll0, 8, 0, 0),
930 F_END
931};
932
933static struct rcg_clk usb_hs_system_clk_src = {
934 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
935 .set_rate = set_rate_hid,
936 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
937 .current_freq = &rcg_dummy_freq,
938 .base = &virt_bases[GCC_BASE],
939 .c = {
940 .dbg_name = "usb_hs_system_clk_src",
941 .ops = &clk_ops_rcg,
942 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
943 CLK_INIT(usb_hs_system_clk_src.c),
944 },
945};
946
947static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = {
948 F_HSIC( 480000000, gpll1, 0, 0, 0),
949 F_END
950};
951
952static struct rcg_clk usb_hsic_clk_src = {
953 .cmd_rcgr_reg = USB_HSIC_CMD_RCGR,
954 .set_rate = set_rate_hid,
955 .freq_tbl = ftbl_gcc_usb_hsic_clk,
956 .current_freq = &rcg_dummy_freq,
957 .base = &virt_bases[GCC_BASE],
958 .c = {
959 .dbg_name = "usb_hsic_clk_src",
960 .ops = &clk_ops_rcg,
961 VDD_DIG_FMAX_MAP1(LOW, 480000000),
962 CLK_INIT(usb_hsic_clk_src.c),
963 },
964};
965
966static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
967 F_GCC( 9600000, xo, 2, 0, 0),
968 F_END
969};
970
971static struct rcg_clk usb_hsic_io_cal_clk_src = {
972 .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR,
973 .set_rate = set_rate_hid,
974 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
975 .current_freq = &rcg_dummy_freq,
976 .base = &virt_bases[GCC_BASE],
977 .c = {
978 .dbg_name = "usb_hsic_io_cal_clk_src",
979 .ops = &clk_ops_rcg,
980 VDD_DIG_FMAX_MAP1(LOW, 9600000),
981 CLK_INIT(usb_hsic_io_cal_clk_src.c),
982 },
983};
984
985static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
986 F_GCC( 75000000, gpll0, 8, 0, 0),
987 F_END
988};
989
990static struct rcg_clk usb_hsic_system_clk_src = {
991 .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR,
992 .set_rate = set_rate_hid,
993 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
994 .current_freq = &rcg_dummy_freq,
995 .base = &virt_bases[GCC_BASE],
996 .c = {
997 .dbg_name = "usb_hsic_system_clk_src",
998 .ops = &clk_ops_rcg,
999 VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000),
1000 CLK_INIT(usb_hsic_system_clk_src.c),
1001 },
1002};
1003
1004static struct local_vote_clk gcc_bam_dma_ahb_clk = {
1005 .cbcr_reg = BAM_DMA_AHB_CBCR,
1006 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1007 .en_mask = BIT(12),
1008 .base = &virt_bases[GCC_BASE],
1009 .c = {
1010 .dbg_name = "gcc_bam_dma_ahb_clk",
1011 .ops = &clk_ops_vote,
1012 CLK_INIT(gcc_bam_dma_ahb_clk.c),
1013 },
1014};
1015
1016static struct local_vote_clk gcc_blsp1_ahb_clk = {
1017 .cbcr_reg = BLSP1_AHB_CBCR,
1018 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1019 .en_mask = BIT(17),
1020 .base = &virt_bases[GCC_BASE],
1021 .c = {
1022 .dbg_name = "gcc_blsp1_ahb_clk",
1023 .ops = &clk_ops_vote,
1024 CLK_INIT(gcc_blsp1_ahb_clk.c),
1025 },
1026};
1027
1028static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1029 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1030 .has_sibling = 0,
1031 .base = &virt_bases[GCC_BASE],
1032 .c = {
1033 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1034 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1035 .ops = &clk_ops_branch,
1036 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1037 },
1038};
1039
1040static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1041 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1042 .has_sibling = 0,
1043 .base = &virt_bases[GCC_BASE],
1044 .c = {
1045 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1046 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1047 .ops = &clk_ops_branch,
1048 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1049 },
1050};
1051
1052static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1053 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1054 .has_sibling = 0,
1055 .base = &virt_bases[GCC_BASE],
1056 .c = {
1057 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1058 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1059 .ops = &clk_ops_branch,
1060 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1061 },
1062};
1063
1064static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1065 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1066 .has_sibling = 0,
1067 .base = &virt_bases[GCC_BASE],
1068 .c = {
1069 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
1070 .parent = &blsp1_qup2_spi_apps_clk_src.c,
1071 .ops = &clk_ops_branch,
1072 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
1073 },
1074};
1075
1076static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
1077 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
1078 .has_sibling = 0,
1079 .base = &virt_bases[GCC_BASE],
1080 .c = {
1081 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
1082 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
1083 .ops = &clk_ops_branch,
1084 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
1085 },
1086};
1087
1088static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
1089 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
1090 .has_sibling = 0,
1091 .base = &virt_bases[GCC_BASE],
1092 .c = {
1093 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
1094 .parent = &blsp1_qup3_spi_apps_clk_src.c,
1095 .ops = &clk_ops_branch,
1096 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
1097 },
1098};
1099
1100static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
1101 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
1102 .has_sibling = 0,
1103 .base = &virt_bases[GCC_BASE],
1104 .c = {
1105 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
1106 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
1107 .ops = &clk_ops_branch,
1108 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
1109 },
1110};
1111
1112static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
1113 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
1114 .has_sibling = 0,
1115 .base = &virt_bases[GCC_BASE],
1116 .c = {
1117 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
1118 .parent = &blsp1_qup4_spi_apps_clk_src.c,
1119 .ops = &clk_ops_branch,
1120 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
1121 },
1122};
1123
1124static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
1125 .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
1126 .has_sibling = 0,
1127 .base = &virt_bases[GCC_BASE],
1128 .c = {
1129 .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
1130 .parent = &blsp1_qup5_i2c_apps_clk_src.c,
1131 .ops = &clk_ops_branch,
1132 CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
1133 },
1134};
1135
1136static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
1137 .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
1138 .has_sibling = 0,
1139 .base = &virt_bases[GCC_BASE],
1140 .c = {
1141 .dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
1142 .parent = &blsp1_qup5_spi_apps_clk_src.c,
1143 .ops = &clk_ops_branch,
1144 CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
1145 },
1146};
1147
1148static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
1149 .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
1150 .has_sibling = 0,
1151 .base = &virt_bases[GCC_BASE],
1152 .c = {
1153 .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
1154 .parent = &blsp1_qup6_i2c_apps_clk_src.c,
1155 .ops = &clk_ops_branch,
1156 CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
1157 },
1158};
1159
1160static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
1161 .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
1162 .has_sibling = 0,
1163 .base = &virt_bases[GCC_BASE],
1164 .c = {
1165 .dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
1166 .parent = &blsp1_qup6_spi_apps_clk_src.c,
1167 .ops = &clk_ops_branch,
1168 CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
1169 },
1170};
1171
1172static struct branch_clk gcc_blsp1_uart1_apps_clk = {
1173 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
1174 .has_sibling = 0,
1175 .base = &virt_bases[GCC_BASE],
1176 .c = {
1177 .dbg_name = "gcc_blsp1_uart1_apps_clk",
1178 .parent = &blsp1_uart1_apps_clk_src.c,
1179 .ops = &clk_ops_branch,
1180 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
1181 },
1182};
1183
1184static struct branch_clk gcc_blsp1_uart2_apps_clk = {
1185 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
1186 .has_sibling = 0,
1187 .base = &virt_bases[GCC_BASE],
1188 .c = {
1189 .dbg_name = "gcc_blsp1_uart2_apps_clk",
1190 .parent = &blsp1_uart2_apps_clk_src.c,
1191 .ops = &clk_ops_branch,
1192 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
1193 },
1194};
1195
1196static struct branch_clk gcc_blsp1_uart3_apps_clk = {
1197 .cbcr_reg = BLSP1_UART3_APPS_CBCR,
1198 .has_sibling = 0,
1199 .base = &virt_bases[GCC_BASE],
1200 .c = {
1201 .dbg_name = "gcc_blsp1_uart3_apps_clk",
1202 .parent = &blsp1_uart3_apps_clk_src.c,
1203 .ops = &clk_ops_branch,
1204 CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
1205 },
1206};
1207
1208static struct branch_clk gcc_blsp1_uart4_apps_clk = {
1209 .cbcr_reg = BLSP1_UART4_APPS_CBCR,
1210 .has_sibling = 0,
1211 .base = &virt_bases[GCC_BASE],
1212 .c = {
1213 .dbg_name = "gcc_blsp1_uart4_apps_clk",
1214 .parent = &blsp1_uart4_apps_clk_src.c,
1215 .ops = &clk_ops_branch,
1216 CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
1217 },
1218};
1219
1220static struct branch_clk gcc_blsp1_uart5_apps_clk = {
1221 .cbcr_reg = BLSP1_UART5_APPS_CBCR,
1222 .has_sibling = 0,
1223 .base = &virt_bases[GCC_BASE],
1224 .c = {
1225 .dbg_name = "gcc_blsp1_uart5_apps_clk",
1226 .parent = &blsp1_uart5_apps_clk_src.c,
1227 .ops = &clk_ops_branch,
1228 CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
1229 },
1230};
1231
1232static struct branch_clk gcc_blsp1_uart6_apps_clk = {
1233 .cbcr_reg = BLSP1_UART6_APPS_CBCR,
1234 .has_sibling = 0,
1235 .base = &virt_bases[GCC_BASE],
1236 .c = {
1237 .dbg_name = "gcc_blsp1_uart6_apps_clk",
1238 .parent = &blsp1_uart6_apps_clk_src.c,
1239 .ops = &clk_ops_branch,
1240 CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
1241 },
1242};
1243
1244static struct local_vote_clk gcc_boot_rom_ahb_clk = {
1245 .cbcr_reg = BOOT_ROM_AHB_CBCR,
1246 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1247 .en_mask = BIT(10),
1248 .base = &virt_bases[GCC_BASE],
1249 .c = {
1250 .dbg_name = "gcc_boot_rom_ahb_clk",
1251 .ops = &clk_ops_vote,
1252 CLK_INIT(gcc_boot_rom_ahb_clk.c),
1253 },
1254};
1255
1256static struct local_vote_clk gcc_ce1_ahb_clk = {
1257 .cbcr_reg = CE1_AHB_CBCR,
1258 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1259 .en_mask = BIT(3),
1260 .base = &virt_bases[GCC_BASE],
1261 .c = {
1262 .dbg_name = "gcc_ce1_ahb_clk",
1263 .ops = &clk_ops_vote,
1264 CLK_INIT(gcc_ce1_ahb_clk.c),
1265 },
1266};
1267
1268static struct local_vote_clk gcc_ce1_axi_clk = {
1269 .cbcr_reg = CE1_AXI_CBCR,
1270 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1271 .en_mask = BIT(4),
1272 .base = &virt_bases[GCC_BASE],
1273 .c = {
1274 .dbg_name = "gcc_ce1_axi_clk",
1275 .ops = &clk_ops_vote,
1276 CLK_INIT(gcc_ce1_axi_clk.c),
1277 },
1278};
1279
1280static struct local_vote_clk gcc_ce1_clk = {
1281 .cbcr_reg = CE1_CBCR,
1282 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1283 .en_mask = BIT(5),
1284 .base = &virt_bases[GCC_BASE],
1285 .c = {
1286 .dbg_name = "gcc_ce1_clk",
1287 .ops = &clk_ops_vote,
1288 CLK_INIT(gcc_ce1_clk.c),
1289 },
1290};
1291
1292static struct branch_clk gcc_gp1_clk = {
1293 .cbcr_reg = GP1_CBCR,
1294 .has_sibling = 0,
1295 .base = &virt_bases[GCC_BASE],
1296 .c = {
1297 .dbg_name = "gcc_gp1_clk",
1298 .parent = &gp1_clk_src.c,
1299 .ops = &clk_ops_branch,
1300 CLK_INIT(gcc_gp1_clk.c),
1301 },
1302};
1303
1304static struct branch_clk gcc_gp2_clk = {
1305 .cbcr_reg = GP2_CBCR,
1306 .has_sibling = 0,
1307 .base = &virt_bases[GCC_BASE],
1308 .c = {
1309 .dbg_name = "gcc_gp2_clk",
1310 .parent = &gp2_clk_src.c,
1311 .ops = &clk_ops_branch,
1312 CLK_INIT(gcc_gp2_clk.c),
1313 },
1314};
1315
1316static struct branch_clk gcc_gp3_clk = {
1317 .cbcr_reg = GP3_CBCR,
1318 .has_sibling = 0,
1319 .base = &virt_bases[GCC_BASE],
1320 .c = {
1321 .dbg_name = "gcc_gp3_clk",
1322 .parent = &gp3_clk_src.c,
1323 .ops = &clk_ops_branch,
1324 CLK_INIT(gcc_gp3_clk.c),
1325 },
1326};
1327
1328static struct branch_clk gcc_lpass_q6_axi_clk = {
1329 .cbcr_reg = LPASS_Q6_AXI_CBCR,
1330 .has_sibling = 1,
1331 .base = &virt_bases[GCC_BASE],
1332 .c = {
1333 .dbg_name = "gcc_lpass_q6_axi_clk",
1334 .ops = &clk_ops_branch,
1335 CLK_INIT(gcc_lpass_q6_axi_clk.c),
1336 },
1337};
1338
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1339static struct branch_clk gcc_mss_cfg_ahb_clk = {
1340 .cbcr_reg = MSS_CFG_AHB_CBCR,
1341 .has_sibling = 1,
1342 .base = &virt_bases[GCC_BASE],
1343 .c = {
1344 .dbg_name = "gcc_mss_cfg_ahb_clk",
1345 .ops = &clk_ops_branch,
1346 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
1347 },
1348};
1349
1350static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
1351 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
1352 .has_sibling = 1,
1353 .base = &virt_bases[GCC_BASE],
1354 .c = {
1355 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
1356 .ops = &clk_ops_branch,
1357 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
1358 },
1359};
1360
1361static struct branch_clk gcc_noc_conf_xpu_ahb_clk = {
1362 .cbcr_reg = NOC_CONF_XPU_AHB_CBCR,
1363 .has_sibling = 1,
1364 .base = &virt_bases[GCC_BASE],
1365 .c = {
1366 .dbg_name = "gcc_noc_conf_xpu_ahb_clk",
1367 .ops = &clk_ops_branch,
1368 CLK_INIT(gcc_noc_conf_xpu_ahb_clk.c),
1369 },
1370};
1371
1372static struct branch_clk gcc_pdm2_clk = {
1373 .cbcr_reg = PDM2_CBCR,
1374 .has_sibling = 0,
1375 .base = &virt_bases[GCC_BASE],
1376 .c = {
1377 .dbg_name = "gcc_pdm2_clk",
1378 .parent = &pdm2_clk_src.c,
1379 .ops = &clk_ops_branch,
1380 CLK_INIT(gcc_pdm2_clk.c),
1381 },
1382};
1383
1384static struct branch_clk gcc_pdm_ahb_clk = {
1385 .cbcr_reg = PDM_AHB_CBCR,
1386 .has_sibling = 1,
1387 .base = &virt_bases[GCC_BASE],
1388 .c = {
1389 .dbg_name = "gcc_pdm_ahb_clk",
1390 .ops = &clk_ops_branch,
1391 CLK_INIT(gcc_pdm_ahb_clk.c),
1392 },
1393};
1394
1395static struct branch_clk gcc_pdm_xo4_clk = {
1396 .cbcr_reg = PDM_XO4_CBCR,
1397 .has_sibling = 1,
1398 .base = &virt_bases[GCC_BASE],
1399 .c = {
1400 .dbg_name = "gcc_pdm_xo4_clk",
1401 .parent = &xo.c,
1402 .ops = &clk_ops_branch,
1403 CLK_INIT(gcc_pdm_xo4_clk.c),
1404 },
1405};
1406
1407static struct branch_clk gcc_periph_noc_ahb_clk = {
1408 .cbcr_reg = PERIPH_NOC_AHB_CBCR,
1409 .has_sibling = 1,
1410 .base = &virt_bases[GCC_BASE],
1411 .c = {
1412 .dbg_name = "gcc_periph_noc_ahb_clk",
1413 .ops = &clk_ops_branch,
1414 CLK_INIT(gcc_periph_noc_ahb_clk.c),
1415 },
1416};
1417
1418static struct local_vote_clk gcc_prng_ahb_clk = {
1419 .cbcr_reg = PRNG_AHB_CBCR,
1420 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1421 .en_mask = BIT(13),
1422 .base = &virt_bases[GCC_BASE],
1423 .c = {
1424 .dbg_name = "gcc_prng_ahb_clk",
1425 .ops = &clk_ops_vote,
1426 CLK_INIT(gcc_prng_ahb_clk.c),
1427 },
1428};
1429
1430static struct branch_clk gcc_sdcc1_ahb_clk = {
1431 .cbcr_reg = SDCC1_AHB_CBCR,
1432 .has_sibling = 1,
1433 .base = &virt_bases[GCC_BASE],
1434 .c = {
1435 .dbg_name = "gcc_sdcc1_ahb_clk",
1436 .ops = &clk_ops_branch,
1437 CLK_INIT(gcc_sdcc1_ahb_clk.c),
1438 },
1439};
1440
1441static struct branch_clk gcc_sdcc1_apps_clk = {
1442 .cbcr_reg = SDCC1_APPS_CBCR,
1443 .has_sibling = 0,
1444 .base = &virt_bases[GCC_BASE],
1445 .c = {
1446 .dbg_name = "gcc_sdcc1_apps_clk",
1447 .parent = &sdcc1_apps_clk_src.c,
1448 .ops = &clk_ops_branch,
1449 CLK_INIT(gcc_sdcc1_apps_clk.c),
1450 },
1451};
1452
1453static struct branch_clk gcc_sdcc2_ahb_clk = {
1454 .cbcr_reg = SDCC2_AHB_CBCR,
1455 .has_sibling = 1,
1456 .base = &virt_bases[GCC_BASE],
1457 .c = {
1458 .dbg_name = "gcc_sdcc2_ahb_clk",
1459 .ops = &clk_ops_branch,
1460 CLK_INIT(gcc_sdcc2_ahb_clk.c),
1461 },
1462};
1463
1464static struct branch_clk gcc_sdcc2_apps_clk = {
1465 .cbcr_reg = SDCC2_APPS_CBCR,
1466 .has_sibling = 0,
1467 .base = &virt_bases[GCC_BASE],
1468 .c = {
1469 .dbg_name = "gcc_sdcc2_apps_clk",
1470 .parent = &sdcc2_apps_clk_src.c,
1471 .ops = &clk_ops_branch,
1472 CLK_INIT(gcc_sdcc2_apps_clk.c),
1473 },
1474};
1475
1476static struct branch_clk gcc_sdcc3_ahb_clk = {
1477 .cbcr_reg = SDCC3_AHB_CBCR,
1478 .has_sibling = 1,
1479 .base = &virt_bases[GCC_BASE],
1480 .c = {
1481 .dbg_name = "gcc_sdcc3_ahb_clk",
1482 .ops = &clk_ops_branch,
1483 CLK_INIT(gcc_sdcc3_ahb_clk.c),
1484 },
1485};
1486
1487static struct branch_clk gcc_sdcc3_apps_clk = {
1488 .cbcr_reg = SDCC3_APPS_CBCR,
1489 .has_sibling = 0,
1490 .base = &virt_bases[GCC_BASE],
1491 .c = {
1492 .dbg_name = "gcc_sdcc3_apps_clk",
1493 .parent = &sdcc3_apps_clk_src.c,
1494 .ops = &clk_ops_branch,
1495 CLK_INIT(gcc_sdcc3_apps_clk.c),
1496 },
1497};
1498
1499static struct branch_clk gcc_usb2a_phy_sleep_clk = {
1500 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
1501 .has_sibling = 1,
1502 .base = &virt_bases[GCC_BASE],
1503 .c = {
1504 .dbg_name = "gcc_usb2a_phy_sleep_clk",
1505 .ops = &clk_ops_branch,
1506 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
1507 },
1508};
1509
1510static struct branch_clk gcc_usb_hs_ahb_clk = {
1511 .cbcr_reg = USB_HS_AHB_CBCR,
1512 .has_sibling = 1,
1513 .base = &virt_bases[GCC_BASE],
1514 .c = {
1515 .dbg_name = "gcc_usb_hs_ahb_clk",
1516 .ops = &clk_ops_branch,
1517 CLK_INIT(gcc_usb_hs_ahb_clk.c),
1518 },
1519};
1520
1521static struct branch_clk gcc_usb_hs_system_clk = {
1522 .cbcr_reg = USB_HS_SYSTEM_CBCR,
1523 .has_sibling = 0,
1524 .bcr_reg = USB_HS_BCR,
1525 .base = &virt_bases[GCC_BASE],
1526 .c = {
1527 .dbg_name = "gcc_usb_hs_system_clk",
1528 .parent = &usb_hs_system_clk_src.c,
1529 .ops = &clk_ops_branch,
1530 CLK_INIT(gcc_usb_hs_system_clk.c),
1531 },
1532};
1533
1534static struct branch_clk gcc_usb_hsic_ahb_clk = {
1535 .cbcr_reg = USB_HSIC_AHB_CBCR,
1536 .has_sibling = 1,
1537 .base = &virt_bases[GCC_BASE],
1538 .c = {
1539 .dbg_name = "gcc_usb_hsic_ahb_clk",
1540 .ops = &clk_ops_branch,
1541 CLK_INIT(gcc_usb_hsic_ahb_clk.c),
1542 },
1543};
1544
1545static struct branch_clk gcc_usb_hsic_clk = {
1546 .cbcr_reg = USB_HSIC_CBCR,
1547 .has_sibling = 0,
1548 .bcr_reg = USB_HS_HSIC_BCR,
1549 .base = &virt_bases[GCC_BASE],
1550 .c = {
1551 .dbg_name = "gcc_usb_hsic_clk",
1552 .parent = &usb_hsic_clk_src.c,
1553 .ops = &clk_ops_branch,
1554 CLK_INIT(gcc_usb_hsic_clk.c),
1555 },
1556};
1557
1558static struct branch_clk gcc_usb_hsic_io_cal_clk = {
1559 .cbcr_reg = USB_HSIC_IO_CAL_CBCR,
1560 .has_sibling = 0,
1561 .base = &virt_bases[GCC_BASE],
1562 .c = {
1563 .dbg_name = "gcc_usb_hsic_io_cal_clk",
1564 .parent = &usb_hsic_io_cal_clk_src.c,
1565 .ops = &clk_ops_branch,
1566 CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
1567 },
1568};
1569
1570static struct branch_clk gcc_usb_hsic_system_clk = {
1571 .cbcr_reg = USB_HSIC_SYSTEM_CBCR,
1572 .has_sibling = 0,
1573 .bcr_reg = USB_HS_HSIC_BCR,
1574 .base = &virt_bases[GCC_BASE],
1575 .c = {
1576 .dbg_name = "gcc_usb_hsic_system_clk",
1577 .parent = &usb_hsic_system_clk_src.c,
1578 .ops = &clk_ops_branch,
1579 CLK_INIT(gcc_usb_hsic_system_clk.c),
1580 },
1581};
1582
1583static struct measure_mux_entry measure_mux_GCC[] = {
1584 { &gcc_periph_noc_ahb_clk.c, GCC_BASE, 0x0010 },
1585 { &gcc_noc_conf_xpu_ahb_clk.c, GCC_BASE, 0x0018 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1586 { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 },
1587 { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 },
1588 { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 },
1589 { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 },
1590 { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a },
1591 { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b },
1592 { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 },
1593 { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 },
1594 { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 },
1595 { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 },
1596 { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 },
1597 { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 },
1598 { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 },
1599 { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 },
1600 { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 },
1601 { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 },
1602 { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a },
1603 { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b },
1604 { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c },
1605 { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e },
1606 { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 },
1607 { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 },
1608 { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 },
1609 { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 },
1610 { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 },
1611 { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 },
1612 { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 },
1613 { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a },
1614 { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c },
1615 { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d },
1616 { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e },
1617 { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 },
1618 { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 },
1619 { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 },
1620 { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 },
1621 { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 },
1622 { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 },
1623 { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 },
1624 { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 },
1625 { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 },
1626 { &gcc_ce1_clk.c, GCC_BASE, 0x0138 },
1627 { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 },
1628 { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a },
1629 { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 },
1630 {&dummy_clk, N_BASES, 0x0000},
1631};
1632
1633static struct pll_vote_clk mmpll0_pll = {
1634 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1635 .en_mask = BIT(0),
1636 .status_reg = (void __iomem *)MMPLL0_PLL_STATUS,
1637 .status_mask = BIT(17),
1638 .base = &virt_bases[MMSS_BASE],
1639 .c = {
1640 .rate = 800000000,
1641 .parent = &xo.c,
1642 .dbg_name = "mmpll0_pll",
1643 .ops = &clk_ops_pll_vote,
1644 CLK_INIT(mmpll0_pll.c),
1645 },
1646};
1647
1648static struct pll_vote_clk mmpll1_pll = {
1649 .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS,
1650 .en_mask = BIT(1),
1651 .status_reg = (void __iomem *)MMPLL1_PLL_STATUS,
1652 .status_mask = BIT(17),
1653 .base = &virt_bases[MMSS_BASE],
1654 .c = {
1655 .rate = 1000000000,
1656 .parent = &xo.c,
1657 .dbg_name = "mmpll1_pll",
1658 .ops = &clk_ops_pll_vote,
1659 CLK_INIT(mmpll1_pll.c),
1660 },
1661};
1662
1663static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = {
1664 F_MMSS( 19200000, xo, 1, 0, 0),
1665 F_MMSS( 37500000, gpll0, 16, 0, 0),
1666 F_MMSS( 50000000, gpll0, 12, 0, 0),
1667 F_MMSS( 75000000, gpll0, 8, 0, 0),
1668 F_MMSS( 100000000, gpll0, 6, 0, 0),
1669 F_MMSS( 150000000, gpll0, 4, 0, 0),
1670 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1671 F_MMSS( 266000000, mmpll0_pll, 3, 0, 0),
1672 F_END
1673};
1674
1675static struct rcg_clk axi_clk_src = {
1676 .cmd_rcgr_reg = AXI_CMD_RCGR,
1677 .set_rate = set_rate_hid,
1678 .freq_tbl = ftbl_mmss_mmssnoc_axi_clk,
1679 .current_freq = &rcg_dummy_freq,
1680 .base = &virt_bases[MMSS_BASE],
1681 .c = {
1682 .dbg_name = "axi_clk_src",
1683 .ops = &clk_ops_rcg,
1684 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1685 266670000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1686 CLK_INIT(axi_clk_src.c),
1687 },
1688};
1689
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1690static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = {
1691 F_MMSS( 100000000, gpll0, 6, 0, 0),
1692 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1693 F_END
1694};
1695
1696static struct rcg_clk csi0_clk_src = {
1697 .cmd_rcgr_reg = CSI0_CMD_RCGR,
1698 .set_rate = set_rate_hid,
1699 .freq_tbl = ftbl_camss_csi0_1_clk,
1700 .current_freq = &rcg_dummy_freq,
1701 .base = &virt_bases[MMSS_BASE],
1702 .c = {
1703 .dbg_name = "csi0_clk_src",
1704 .ops = &clk_ops_rcg,
1705 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1706 CLK_INIT(csi0_clk_src.c),
1707 },
1708};
1709
1710static struct rcg_clk csi1_clk_src = {
1711 .cmd_rcgr_reg = CSI1_CMD_RCGR,
1712 .set_rate = set_rate_hid,
1713 .freq_tbl = ftbl_camss_csi0_1_clk,
1714 .current_freq = &rcg_dummy_freq,
1715 .base = &virt_bases[MMSS_BASE],
1716 .c = {
1717 .dbg_name = "csi1_clk_src",
1718 .ops = &clk_ops_rcg,
1719 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1720 CLK_INIT(csi1_clk_src.c),
1721 },
1722};
1723
1724static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = {
1725 F_MMSS( 37500000, gpll0, 16, 0, 0),
1726 F_MMSS( 50000000, gpll0, 12, 0, 0),
1727 F_MMSS( 60000000, gpll0, 10, 0, 0),
1728 F_MMSS( 80000000, gpll0, 7.5, 0, 0),
1729 F_MMSS( 100000000, gpll0, 6, 0, 0),
1730 F_MMSS( 109090000, gpll0, 5.5, 0, 0),
1731 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1732 F_MMSS( 200000000, gpll0, 3, 0, 0),
1733 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1734 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1735 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1736 F_END
1737};
1738
1739static struct rcg_clk vfe0_clk_src = {
1740 .cmd_rcgr_reg = VFE0_CMD_RCGR,
1741 .set_rate = set_rate_hid,
1742 .freq_tbl = ftbl_camss_vfe_vfe0_clk,
1743 .current_freq = &rcg_dummy_freq,
1744 .base = &virt_bases[MMSS_BASE],
1745 .c = {
1746 .dbg_name = "vfe0_clk_src",
1747 .ops = &clk_ops_rcg,
1748 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1749 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1750 CLK_INIT(vfe0_clk_src.c),
1751 },
1752};
1753
1754static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = {
1755 F_MMSS( 37500000, gpll0, 16, 0, 0),
1756 F_MMSS( 60000000, gpll0, 10, 0, 0),
1757 F_MMSS( 75000000, gpll0, 8, 0, 0),
1758 F_MMSS( 92310000, gpll0, 6.5, 0, 0),
1759 F_MMSS( 100000000, gpll0, 6, 0, 0),
1760 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
1761 F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0),
1762 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1763 F_END
1764};
1765
1766static struct rcg_clk mdp_clk_src = {
1767 .cmd_rcgr_reg = MDP_CMD_RCGR,
1768 .set_rate = set_rate_hid,
1769 .freq_tbl = ftbl_mdss_mdp_clk,
1770 .current_freq = &rcg_dummy_freq,
1771 .base = &virt_bases[MMSS_BASE],
1772 .c = {
1773 .dbg_name = "mdp_clk_src",
1774 .ops = &clk_ops_rcg,
1775 VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1776 200000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1777 CLK_INIT(mdp_clk_src.c),
1778 },
1779};
1780
1781static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = {
1782 F_MMSS( 75000000, gpll0, 8, 0, 0),
1783 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1784 F_MMSS( 200000000, gpll0, 3, 0, 0),
1785 F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0),
1786 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1787 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1788 F_END
1789};
1790
1791static struct rcg_clk jpeg0_clk_src = {
1792 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1793 .set_rate = set_rate_hid,
1794 .freq_tbl = ftbl_camss_jpeg_jpeg0_clk,
1795 .current_freq = &rcg_dummy_freq,
1796 .base = &virt_bases[MMSS_BASE],
1797 .c = {
1798 .dbg_name = "jpeg0_clk_src",
1799 .ops = &clk_ops_rcg,
1800 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1801 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1802 CLK_INIT(jpeg0_clk_src.c),
1803 },
1804};
1805
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1806static struct branch_clk mdss_ahb_clk;
1807static struct clk dsipll0_byte_clk_src = {
1808 .depends = &mdss_ahb_clk.c,
1809 .parent = &xo.c,
1810 .dbg_name = "dsipll0_byte_clk_src",
1811 .ops = &clk_ops_dsi_byte_pll,
1812 CLK_INIT(dsipll0_byte_clk_src),
1813};
1814
1815static struct clk dsipll0_pixel_clk_src = {
1816 .depends = &mdss_ahb_clk.c,
1817 .parent = &xo.c,
1818 .dbg_name = "dsipll0_pixel_clk_src",
1819 .ops = &clk_ops_dsi_pixel_pll,
1820 CLK_INIT(dsipll0_pixel_clk_src),
1821};
1822
1823static struct clk_freq_tbl pixel_freq = {
1824 .src_clk = &dsipll0_pixel_clk_src,
1825 .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1826};
1827
1828static struct rcg_clk pclk0_clk_src = {
1829 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1830 .current_freq = &pixel_freq,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1831 .base = &virt_bases[MMSS_BASE],
1832 .c = {
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1833 .parent = &dsipll0_pixel_clk_src,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1834 .dbg_name = "pclk0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]1835 .ops = &clk_ops_pixel,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1836 VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000),
1837 CLK_INIT(pclk0_clk_src.c),
1838 },
1839};
1840
1841static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = {
1842 F_MMSS( 66700000, gpll0, 9, 0, 0),
1843 F_MMSS( 100000000, gpll0, 6, 0, 0),
1844 F_MMSS( 133330000, mmpll0_pll, 6, 0, 0),
Patrick Daly4f832432013-02-26 12:40:49 -0800[diff] [blame]1845 F_MMSS( 160000000, mmpll0_pll, 5, 0, 0),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1846 F_END
1847};
1848
1849static struct rcg_clk vcodec0_clk_src = {
1850 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
1851 .set_rate = set_rate_mnd,
1852 .freq_tbl = ftbl_venus0_vcodec0_clk,
1853 .current_freq = &rcg_dummy_freq,
1854 .base = &virt_bases[MMSS_BASE],
1855 .c = {
1856 .dbg_name = "vcodec0_clk_src",
1857 .ops = &clk_ops_rcg_mnd,
1858 VDD_DIG_FMAX_MAP3(LOW, 66670000, NOMINAL, 133330000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]1859 160000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1860 CLK_INIT(vcodec0_clk_src.c),
1861 },
1862};
1863
1864static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = {
1865 F_MMSS( 19200000, xo, 1, 0, 0),
1866 F_END
1867};
1868
1869static struct rcg_clk cci_clk_src = {
1870 .cmd_rcgr_reg = CCI_CMD_RCGR,
1871 .set_rate = set_rate_mnd,
1872 .freq_tbl = ftbl_camss_cci_cci_clk,
1873 .current_freq = &rcg_dummy_freq,
1874 .base = &virt_bases[MMSS_BASE],
1875 .c = {
1876 .dbg_name = "cci_clk_src",
1877 .ops = &clk_ops_rcg_mnd,
1878 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
1879 CLK_INIT(cci_clk_src.c),
1880 },
1881};
1882
1883static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = {
1884 F_MMSS( 10000, xo, 16, 1, 120),
1885 F_MMSS( 24000, xo, 16, 1, 50),
1886 F_MMSS( 6000000, gpll0, 10, 1, 10),
1887 F_MMSS( 12000000, gpll0, 10, 1, 5),
1888 F_MMSS( 13000000, gpll0, 4, 13, 150),
1889 F_MMSS( 24000000, gpll0, 5, 1, 5),
1890 F_END
1891};
1892
1893static struct rcg_clk mmss_gp0_clk_src = {
1894 .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR,
1895 .set_rate = set_rate_mnd,
1896 .freq_tbl = ftbl_camss_gp0_1_clk,
1897 .current_freq = &rcg_dummy_freq,
1898 .base = &virt_bases[MMSS_BASE],
1899 .c = {
1900 .dbg_name = "mmss_gp0_clk_src",
1901 .ops = &clk_ops_rcg_mnd,
1902 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1903 CLK_INIT(mmss_gp0_clk_src.c),
1904 },
1905};
1906
1907static struct rcg_clk mmss_gp1_clk_src = {
1908 .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR,
1909 .set_rate = set_rate_mnd,
1910 .freq_tbl = ftbl_camss_gp0_1_clk,
1911 .current_freq = &rcg_dummy_freq,
1912 .base = &virt_bases[MMSS_BASE],
1913 .c = {
1914 .dbg_name = "mmss_gp1_clk_src",
1915 .ops = &clk_ops_rcg_mnd,
1916 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1917 CLK_INIT(mmss_gp1_clk_src.c),
1918 },
1919};
1920
1921static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = {
Patrick Daly42d2b7a2013-03-07 17:12:33 -0800[diff] [blame]1922 F_MMSS( 19200000, xo, 1, 0, 0),
1923 F_MMSS( 24000000, gpll0, 5, 1, 5),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]1924 F_MMSS( 66670000, gpll0, 9, 0, 0),
1925 F_END
1926};
1927
1928static struct rcg_clk mclk0_clk_src = {
1929 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1930 .set_rate = set_rate_mnd,
1931 .freq_tbl = ftbl_camss_mclk0_1_clk,
1932 .current_freq = &rcg_dummy_freq,
1933 .base = &virt_bases[MMSS_BASE],
1934 .c = {
1935 .dbg_name = "mclk0_clk_src",
1936 .ops = &clk_ops_rcg_mnd,
1937 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1938 CLK_INIT(mclk0_clk_src.c),
1939 },
1940};
1941
1942static struct rcg_clk mclk1_clk_src = {
1943 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1944 .set_rate = set_rate_mnd,
1945 .freq_tbl = ftbl_camss_mclk0_1_clk,
1946 .current_freq = &rcg_dummy_freq,
1947 .base = &virt_bases[MMSS_BASE],
1948 .c = {
1949 .dbg_name = "mclk1_clk_src",
1950 .ops = &clk_ops_rcg_mnd,
1951 VDD_DIG_FMAX_MAP1(LOW, 66670000),
1952 CLK_INIT(mclk1_clk_src.c),
1953 },
1954};
1955
1956static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = {
1957 F_MMSS( 100000000, gpll0, 6, 0, 0),
1958 F_MMSS( 200000000, mmpll0_pll, 4, 0, 0),
1959 F_END
1960};
1961
1962static struct rcg_clk csi0phytimer_clk_src = {
1963 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1964 .set_rate = set_rate_hid,
1965 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1966 .current_freq = &rcg_dummy_freq,
1967 .base = &virt_bases[MMSS_BASE],
1968 .c = {
1969 .dbg_name = "csi0phytimer_clk_src",
1970 .ops = &clk_ops_rcg,
1971 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1972 CLK_INIT(csi0phytimer_clk_src.c),
1973 },
1974};
1975
1976static struct rcg_clk csi1phytimer_clk_src = {
1977 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1978 .set_rate = set_rate_hid,
1979 .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk,
1980 .current_freq = &rcg_dummy_freq,
1981 .base = &virt_bases[MMSS_BASE],
1982 .c = {
1983 .dbg_name = "csi1phytimer_clk_src",
1984 .ops = &clk_ops_rcg,
1985 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
1986 CLK_INIT(csi1phytimer_clk_src.c),
1987 },
1988};
1989
1990static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = {
1991 F_MMSS( 133330000, gpll0, 4.5, 0, 0),
1992 F_MMSS( 266670000, mmpll0_pll, 3, 0, 0),
1993 F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0),
1994 F_END
1995};
1996
1997static struct rcg_clk cpp_clk_src = {
1998 .cmd_rcgr_reg = CPP_CMD_RCGR,
1999 .set_rate = set_rate_hid,
2000 .freq_tbl = ftbl_camss_vfe_cpp_clk,
2001 .current_freq = &rcg_dummy_freq,
2002 .base = &virt_bases[MMSS_BASE],
2003 .c = {
2004 .dbg_name = "cpp_clk_src",
2005 .ops = &clk_ops_rcg,
2006 VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH,
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]2007 320000000),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2008 CLK_INIT(cpp_clk_src.c),
2009 },
2010};
2011
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2012static struct clk_freq_tbl byte_freq = {
2013 .src_clk = &dsipll0_byte_clk_src,
2014 .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2015};
2016
2017static struct rcg_clk byte0_clk_src = {
2018 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2019 .current_freq = &byte_freq,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2020 .base = &virt_bases[MMSS_BASE],
2021 .c = {
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2022 .parent = &dsipll0_byte_clk_src,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2023 .dbg_name = "byte0_clk_src",
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]2024 .ops = &clk_ops_byte,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2025 VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000),
2026 CLK_INIT(byte0_clk_src.c),
2027 },
2028};
2029
2030static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = {
2031 F_MDSS( 19200000, xo, 1, 0, 0),
2032 F_END
2033};
2034
2035static struct rcg_clk esc0_clk_src = {
2036 .cmd_rcgr_reg = ESC0_CMD_RCGR,
2037 .set_rate = set_rate_hid,
2038 .freq_tbl = ftbl_mdss_esc0_clk,
2039 .current_freq = &rcg_dummy_freq,
2040 .base = &virt_bases[MMSS_BASE],
2041 .c = {
2042 .dbg_name = "esc0_clk_src",
2043 .ops = &clk_ops_rcg,
2044 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2045 CLK_INIT(esc0_clk_src.c),
2046 },
2047};
2048
2049static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
2050 F_MDSS( 19200000, xo, 1, 0, 0),
2051 F_END
2052};
2053
2054static struct rcg_clk vsync_clk_src = {
2055 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
2056 .set_rate = set_rate_hid,
2057 .freq_tbl = ftbl_mdss_vsync_clk,
2058 .current_freq = &rcg_dummy_freq,
2059 .base = &virt_bases[MMSS_BASE],
2060 .c = {
2061 .dbg_name = "vsync_clk_src",
2062 .ops = &clk_ops_rcg,
2063 VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000),
2064 CLK_INIT(vsync_clk_src.c),
2065 },
2066};
2067
2068static struct branch_clk camss_cci_cci_ahb_clk = {
2069 .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
2070 .has_sibling = 1,
2071 .base = &virt_bases[MMSS_BASE],
2072 .c = {
2073 .dbg_name = "camss_cci_cci_ahb_clk",
2074 .ops = &clk_ops_branch,
2075 CLK_INIT(camss_cci_cci_ahb_clk.c),
2076 },
2077};
2078
2079static struct branch_clk camss_cci_cci_clk = {
2080 .cbcr_reg = CAMSS_CCI_CCI_CBCR,
2081 .has_sibling = 0,
2082 .base = &virt_bases[MMSS_BASE],
2083 .c = {
2084 .dbg_name = "camss_cci_cci_clk",
2085 .parent = &cci_clk_src.c,
2086 .ops = &clk_ops_branch,
2087 CLK_INIT(camss_cci_cci_clk.c),
2088 },
2089};
2090
2091static struct branch_clk camss_csi0_ahb_clk = {
2092 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2093 .has_sibling = 1,
2094 .base = &virt_bases[MMSS_BASE],
2095 .c = {
2096 .dbg_name = "camss_csi0_ahb_clk",
2097 .ops = &clk_ops_branch,
2098 CLK_INIT(camss_csi0_ahb_clk.c),
2099 },
2100};
2101
2102static struct branch_clk camss_csi0_clk = {
2103 .cbcr_reg = CAMSS_CSI0_CBCR,
2104 .has_sibling = 1,
2105 .base = &virt_bases[MMSS_BASE],
2106 .c = {
2107 .dbg_name = "camss_csi0_clk",
2108 .parent = &csi0_clk_src.c,
2109 .ops = &clk_ops_branch,
2110 CLK_INIT(camss_csi0_clk.c),
2111 },
2112};
2113
2114static struct branch_clk camss_csi0phy_clk = {
2115 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2116 .has_sibling = 1,
2117 .base = &virt_bases[MMSS_BASE],
2118 .c = {
2119 .dbg_name = "camss_csi0phy_clk",
2120 .parent = &csi0_clk_src.c,
2121 .ops = &clk_ops_branch,
2122 CLK_INIT(camss_csi0phy_clk.c),
2123 },
2124};
2125
2126static struct branch_clk camss_csi0pix_clk = {
2127 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2128 .has_sibling = 1,
2129 .base = &virt_bases[MMSS_BASE],
2130 .c = {
2131 .dbg_name = "camss_csi0pix_clk",
2132 .parent = &csi0_clk_src.c,
2133 .ops = &clk_ops_branch,
2134 CLK_INIT(camss_csi0pix_clk.c),
2135 },
2136};
2137
2138static struct branch_clk camss_csi0rdi_clk = {
2139 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2140 .has_sibling = 1,
2141 .base = &virt_bases[MMSS_BASE],
2142 .c = {
2143 .dbg_name = "camss_csi0rdi_clk",
2144 .parent = &csi0_clk_src.c,
2145 .ops = &clk_ops_branch,
2146 CLK_INIT(camss_csi0rdi_clk.c),
2147 },
2148};
2149
2150static struct branch_clk camss_csi1_ahb_clk = {
2151 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2152 .has_sibling = 1,
2153 .base = &virt_bases[MMSS_BASE],
2154 .c = {
2155 .dbg_name = "camss_csi1_ahb_clk",
2156 .ops = &clk_ops_branch,
2157 CLK_INIT(camss_csi1_ahb_clk.c),
2158 },
2159};
2160
2161static struct branch_clk camss_csi1_clk = {
2162 .cbcr_reg = CAMSS_CSI1_CBCR,
2163 .has_sibling = 1,
2164 .base = &virt_bases[MMSS_BASE],
2165 .c = {
2166 .dbg_name = "camss_csi1_clk",
2167 .parent = &csi1_clk_src.c,
2168 .ops = &clk_ops_branch,
2169 CLK_INIT(camss_csi1_clk.c),
2170 },
2171};
2172
2173static struct branch_clk camss_csi1phy_clk = {
2174 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2175 .has_sibling = 1,
2176 .base = &virt_bases[MMSS_BASE],
2177 .c = {
2178 .dbg_name = "camss_csi1phy_clk",
2179 .parent = &csi1_clk_src.c,
2180 .ops = &clk_ops_branch,
2181 CLK_INIT(camss_csi1phy_clk.c),
2182 },
2183};
2184
2185static struct branch_clk camss_csi1pix_clk = {
2186 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2187 .has_sibling = 1,
2188 .base = &virt_bases[MMSS_BASE],
2189 .c = {
2190 .dbg_name = "camss_csi1pix_clk",
2191 .parent = &csi1_clk_src.c,
2192 .ops = &clk_ops_branch,
2193 CLK_INIT(camss_csi1pix_clk.c),
2194 },
2195};
2196
2197static struct branch_clk camss_csi1rdi_clk = {
2198 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2199 .has_sibling = 1,
2200 .base = &virt_bases[MMSS_BASE],
2201 .c = {
2202 .dbg_name = "camss_csi1rdi_clk",
2203 .parent = &csi1_clk_src.c,
2204 .ops = &clk_ops_branch,
2205 CLK_INIT(camss_csi1rdi_clk.c),
2206 },
2207};
2208
2209static struct branch_clk camss_csi_vfe0_clk = {
2210 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2211 .has_sibling = 1,
2212 .base = &virt_bases[MMSS_BASE],
2213 .c = {
2214 .dbg_name = "camss_csi_vfe0_clk",
2215 .parent = &vfe0_clk_src.c,
2216 .ops = &clk_ops_branch,
2217 CLK_INIT(camss_csi_vfe0_clk.c),
2218 },
2219};
2220
2221static struct branch_clk camss_gp0_clk = {
2222 .cbcr_reg = CAMSS_GP0_CBCR,
2223 .has_sibling = 0,
2224 .base = &virt_bases[MMSS_BASE],
2225 .c = {
2226 .dbg_name = "camss_gp0_clk",
2227 .parent = &mmss_gp0_clk_src.c,
2228 .ops = &clk_ops_branch,
2229 CLK_INIT(camss_gp0_clk.c),
2230 },
2231};
2232
2233static struct branch_clk camss_gp1_clk = {
2234 .cbcr_reg = CAMSS_GP1_CBCR,
2235 .has_sibling = 0,
2236 .base = &virt_bases[MMSS_BASE],
2237 .c = {
2238 .dbg_name = "camss_gp1_clk",
2239 .parent = &mmss_gp1_clk_src.c,
2240 .ops = &clk_ops_branch,
2241 CLK_INIT(camss_gp1_clk.c),
2242 },
2243};
2244
2245static struct branch_clk camss_ispif_ahb_clk = {
2246 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2247 .has_sibling = 1,
2248 .base = &virt_bases[MMSS_BASE],
2249 .c = {
2250 .dbg_name = "camss_ispif_ahb_clk",
2251 .ops = &clk_ops_branch,
2252 CLK_INIT(camss_ispif_ahb_clk.c),
2253 },
2254};
2255
2256static struct branch_clk camss_jpeg_jpeg0_clk = {
2257 .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
2258 .has_sibling = 0,
2259 .base = &virt_bases[MMSS_BASE],
2260 .c = {
2261 .dbg_name = "camss_jpeg_jpeg0_clk",
2262 .parent = &jpeg0_clk_src.c,
2263 .ops = &clk_ops_branch,
2264 CLK_INIT(camss_jpeg_jpeg0_clk.c),
2265 },
2266};
2267
2268static struct branch_clk camss_jpeg_jpeg_ahb_clk = {
2269 .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
2270 .has_sibling = 1,
2271 .base = &virt_bases[MMSS_BASE],
2272 .c = {
2273 .dbg_name = "camss_jpeg_jpeg_ahb_clk",
2274 .ops = &clk_ops_branch,
2275 CLK_INIT(camss_jpeg_jpeg_ahb_clk.c),
2276 },
2277};
2278
2279static struct branch_clk camss_jpeg_jpeg_axi_clk = {
2280 .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
2281 .has_sibling = 1,
2282 .base = &virt_bases[MMSS_BASE],
2283 .c = {
2284 .dbg_name = "camss_jpeg_jpeg_axi_clk",
2285 .parent = &axi_clk_src.c,
2286 .ops = &clk_ops_branch,
2287 CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
2288 },
2289};
2290
2291static struct branch_clk camss_mclk0_clk = {
2292 .cbcr_reg = CAMSS_MCLK0_CBCR,
2293 .has_sibling = 0,
2294 .base = &virt_bases[MMSS_BASE],
2295 .c = {
2296 .dbg_name = "camss_mclk0_clk",
2297 .parent = &mclk0_clk_src.c,
2298 .ops = &clk_ops_branch,
2299 CLK_INIT(camss_mclk0_clk.c),
2300 },
2301};
2302
2303static struct branch_clk camss_mclk1_clk = {
2304 .cbcr_reg = CAMSS_MCLK1_CBCR,
2305 .has_sibling = 0,
2306 .base = &virt_bases[MMSS_BASE],
2307 .c = {
2308 .dbg_name = "camss_mclk1_clk",
2309 .parent = &mclk1_clk_src.c,
2310 .ops = &clk_ops_branch,
2311 CLK_INIT(camss_mclk1_clk.c),
2312 },
2313};
2314
2315static struct branch_clk camss_micro_ahb_clk = {
2316 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2317 .has_sibling = 1,
2318 .base = &virt_bases[MMSS_BASE],
2319 .c = {
2320 .dbg_name = "camss_micro_ahb_clk",
2321 .ops = &clk_ops_branch,
2322 CLK_INIT(camss_micro_ahb_clk.c),
2323 },
2324};
2325
2326static struct branch_clk camss_phy0_csi0phytimer_clk = {
2327 .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
2328 .has_sibling = 0,
2329 .base = &virt_bases[MMSS_BASE],
2330 .c = {
2331 .dbg_name = "camss_phy0_csi0phytimer_clk",
2332 .parent = &csi0phytimer_clk_src.c,
2333 .ops = &clk_ops_branch,
2334 CLK_INIT(camss_phy0_csi0phytimer_clk.c),
2335 },
2336};
2337
2338static struct branch_clk camss_phy1_csi1phytimer_clk = {
2339 .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
2340 .has_sibling = 0,
2341 .base = &virt_bases[MMSS_BASE],
2342 .c = {
2343 .dbg_name = "camss_phy1_csi1phytimer_clk",
2344 .parent = &csi1phytimer_clk_src.c,
2345 .ops = &clk_ops_branch,
2346 CLK_INIT(camss_phy1_csi1phytimer_clk.c),
2347 },
2348};
2349
2350static struct branch_clk camss_top_ahb_clk = {
2351 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2352 .has_sibling = 1,
2353 .base = &virt_bases[MMSS_BASE],
2354 .c = {
2355 .dbg_name = "camss_top_ahb_clk",
2356 .ops = &clk_ops_branch,
2357 CLK_INIT(camss_top_ahb_clk.c),
2358 },
2359};
2360
2361static struct branch_clk camss_vfe_cpp_ahb_clk = {
2362 .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
2363 .has_sibling = 1,
2364 .base = &virt_bases[MMSS_BASE],
2365 .c = {
2366 .dbg_name = "camss_vfe_cpp_ahb_clk",
2367 .ops = &clk_ops_branch,
2368 CLK_INIT(camss_vfe_cpp_ahb_clk.c),
2369 },
2370};
2371
2372static struct branch_clk camss_vfe_cpp_clk = {
2373 .cbcr_reg = CAMSS_VFE_CPP_CBCR,
2374 .has_sibling = 0,
2375 .base = &virt_bases[MMSS_BASE],
2376 .c = {
2377 .dbg_name = "camss_vfe_cpp_clk",
2378 .parent = &cpp_clk_src.c,
2379 .ops = &clk_ops_branch,
2380 CLK_INIT(camss_vfe_cpp_clk.c),
2381 },
2382};
2383
2384static struct branch_clk camss_vfe_vfe0_clk = {
2385 .cbcr_reg = CAMSS_VFE_VFE0_CBCR,
2386 .has_sibling = 1,
2387 .base = &virt_bases[MMSS_BASE],
2388 .c = {
2389 .dbg_name = "camss_vfe_vfe0_clk",
2390 .parent = &vfe0_clk_src.c,
2391 .ops = &clk_ops_branch,
2392 CLK_INIT(camss_vfe_vfe0_clk.c),
2393 },
2394};
2395
2396static struct branch_clk camss_vfe_vfe_ahb_clk = {
2397 .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
2398 .has_sibling = 1,
2399 .base = &virt_bases[MMSS_BASE],
2400 .c = {
2401 .dbg_name = "camss_vfe_vfe_ahb_clk",
2402 .ops = &clk_ops_branch,
2403 CLK_INIT(camss_vfe_vfe_ahb_clk.c),
2404 },
2405};
2406
2407static struct branch_clk camss_vfe_vfe_axi_clk = {
2408 .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
2409 .has_sibling = 1,
2410 .base = &virt_bases[MMSS_BASE],
2411 .c = {
2412 .dbg_name = "camss_vfe_vfe_axi_clk",
2413 .parent = &axi_clk_src.c,
2414 .ops = &clk_ops_branch,
2415 CLK_INIT(camss_vfe_vfe_axi_clk.c),
2416 },
2417};
2418
2419static struct branch_clk mdss_ahb_clk = {
2420 .cbcr_reg = MDSS_AHB_CBCR,
2421 .has_sibling = 1,
2422 .base = &virt_bases[MMSS_BASE],
2423 .c = {
2424 .dbg_name = "mdss_ahb_clk",
2425 .ops = &clk_ops_branch,
2426 CLK_INIT(mdss_ahb_clk.c),
2427 },
2428};
2429
2430static struct branch_clk mdss_axi_clk = {
2431 .cbcr_reg = MDSS_AXI_CBCR,
2432 .has_sibling = 1,
2433 .base = &virt_bases[MMSS_BASE],
2434 .c = {
2435 .dbg_name = "mdss_axi_clk",
2436 .parent = &axi_clk_src.c,
2437 .ops = &clk_ops_branch,
2438 CLK_INIT(mdss_axi_clk.c),
2439 },
2440};
2441
2442static struct branch_clk mdss_byte0_clk = {
2443 .cbcr_reg = MDSS_BYTE0_CBCR,
2444 .has_sibling = 0,
2445 .base = &virt_bases[MMSS_BASE],
2446 .c = {
2447 .dbg_name = "mdss_byte0_clk",
2448 .parent = &byte0_clk_src.c,
2449 .ops = &clk_ops_branch,
2450 CLK_INIT(mdss_byte0_clk.c),
2451 },
2452};
2453
2454static struct branch_clk mdss_esc0_clk = {
2455 .cbcr_reg = MDSS_ESC0_CBCR,
2456 .has_sibling = 0,
2457 .base = &virt_bases[MMSS_BASE],
2458 .c = {
2459 .dbg_name = "mdss_esc0_clk",
2460 .parent = &esc0_clk_src.c,
2461 .ops = &clk_ops_branch,
2462 CLK_INIT(mdss_esc0_clk.c),
2463 },
2464};
2465
2466static struct branch_clk mdss_mdp_clk = {
2467 .cbcr_reg = MDSS_MDP_CBCR,
2468 .has_sibling = 1,
2469 .base = &virt_bases[MMSS_BASE],
2470 .c = {
2471 .dbg_name = "mdss_mdp_clk",
2472 .parent = &mdp_clk_src.c,
2473 .ops = &clk_ops_branch,
2474 CLK_INIT(mdss_mdp_clk.c),
2475 },
2476};
2477
2478static struct branch_clk mdss_mdp_lut_clk = {
2479 .cbcr_reg = MDSS_MDP_LUT_CBCR,
2480 .has_sibling = 1,
2481 .base = &virt_bases[MMSS_BASE],
2482 .c = {
2483 .dbg_name = "mdss_mdp_lut_clk",
2484 .parent = &mdp_clk_src.c,
2485 .ops = &clk_ops_branch,
2486 CLK_INIT(mdss_mdp_lut_clk.c),
2487 },
2488};
2489
2490static struct branch_clk mdss_pclk0_clk = {
2491 .cbcr_reg = MDSS_PCLK0_CBCR,
2492 .has_sibling = 0,
2493 .base = &virt_bases[MMSS_BASE],
2494 .c = {
2495 .dbg_name = "mdss_pclk0_clk",
2496 .parent = &pclk0_clk_src.c,
2497 .ops = &clk_ops_branch,
2498 CLK_INIT(mdss_pclk0_clk.c),
2499 },
2500};
2501
2502static struct branch_clk mdss_vsync_clk = {
2503 .cbcr_reg = MDSS_VSYNC_CBCR,
2504 .has_sibling = 0,
2505 .base = &virt_bases[MMSS_BASE],
2506 .c = {
2507 .dbg_name = "mdss_vsync_clk",
2508 .parent = &vsync_clk_src.c,
2509 .ops = &clk_ops_branch,
2510 CLK_INIT(mdss_vsync_clk.c),
2511 },
2512};
2513
2514static struct branch_clk mmss_misc_ahb_clk = {
2515 .cbcr_reg = MMSS_MISC_AHB_CBCR,
2516 .has_sibling = 1,
2517 .base = &virt_bases[MMSS_BASE],
2518 .c = {
2519 .dbg_name = "mmss_misc_ahb_clk",
2520 .ops = &clk_ops_branch,
2521 CLK_INIT(mmss_misc_ahb_clk.c),
2522 },
2523};
2524
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2525static struct branch_clk mmss_mmssnoc_bto_ahb_clk = {
2526 .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
2527 .has_sibling = 1,
2528 .base = &virt_bases[MMSS_BASE],
2529 .c = {
2530 .dbg_name = "mmss_mmssnoc_bto_ahb_clk",
2531 .ops = &clk_ops_branch,
2532 CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c),
2533 },
2534};
2535
2536static struct branch_clk mmss_mmssnoc_axi_clk = {
2537 .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
2538 .has_sibling = 1,
2539 .base = &virt_bases[MMSS_BASE],
2540 .c = {
2541 .dbg_name = "mmss_mmssnoc_axi_clk",
2542 .parent = &axi_clk_src.c,
2543 .ops = &clk_ops_branch,
2544 CLK_INIT(mmss_mmssnoc_axi_clk.c),
2545 },
2546};
2547
2548static struct branch_clk mmss_s0_axi_clk = {
2549 .cbcr_reg = MMSS_S0_AXI_CBCR,
2550 .has_sibling = 0,
2551 .max_div = 0,
2552 .base = &virt_bases[MMSS_BASE],
2553 .c = {
2554 .dbg_name = "mmss_s0_axi_clk",
2555 .parent = &axi_clk_src.c,
2556 .ops = &clk_ops_branch,
2557 CLK_INIT(mmss_s0_axi_clk.c),
2558 .depends = &mmss_mmssnoc_axi_clk.c,
2559 },
2560};
2561
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2562static struct branch_clk oxili_gfx3d_clk = {
2563 .cbcr_reg = OXILI_GFX3D_CBCR,
Patrick Daly295173b2013-03-11 13:35:40 -0700[diff] [blame]2564 .has_sibling = 0,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2565 .max_div = 0,
2566 .base = &virt_bases[MMSS_BASE],
2567 .c = {
2568 .dbg_name = "oxili_gfx3d_clk",
2569 .parent = &gfx3d_clk_src.c,
2570 .ops = &clk_ops_branch,
2571 CLK_INIT(oxili_gfx3d_clk.c),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2572 },
2573};
2574
2575static struct branch_clk oxilicx_ahb_clk = {
2576 .cbcr_reg = OXILICX_AHB_CBCR,
2577 .has_sibling = 1,
2578 .base = &virt_bases[MMSS_BASE],
2579 .c = {
2580 .dbg_name = "oxilicx_ahb_clk",
2581 .ops = &clk_ops_branch,
2582 CLK_INIT(oxilicx_ahb_clk.c),
2583 },
2584};
2585
2586static struct branch_clk oxilicx_axi_clk = {
2587 .cbcr_reg = OXILICX_AXI_CBCR,
2588 .has_sibling = 1,
2589 .base = &virt_bases[MMSS_BASE],
2590 .c = {
2591 .dbg_name = "oxilicx_axi_clk",
2592 .parent = &axi_clk_src.c,
2593 .ops = &clk_ops_branch,
2594 CLK_INIT(oxilicx_axi_clk.c),
2595 },
2596};
2597
2598static struct branch_clk venus0_ahb_clk = {
2599 .cbcr_reg = VENUS0_AHB_CBCR,
2600 .has_sibling = 1,
2601 .base = &virt_bases[MMSS_BASE],
2602 .c = {
2603 .dbg_name = "venus0_ahb_clk",
2604 .ops = &clk_ops_branch,
2605 CLK_INIT(venus0_ahb_clk.c),
2606 },
2607};
2608
2609static struct branch_clk venus0_axi_clk = {
2610 .cbcr_reg = VENUS0_AXI_CBCR,
2611 .has_sibling = 1,
2612 .base = &virt_bases[MMSS_BASE],
2613 .c = {
2614 .dbg_name = "venus0_axi_clk",
2615 .parent = &axi_clk_src.c,
2616 .ops = &clk_ops_branch,
2617 CLK_INIT(venus0_axi_clk.c),
2618 },
2619};
2620
2621static struct branch_clk venus0_vcodec0_clk = {
2622 .cbcr_reg = VENUS0_VCODEC0_CBCR,
2623 .has_sibling = 0,
2624 .base = &virt_bases[MMSS_BASE],
2625 .c = {
2626 .dbg_name = "venus0_vcodec0_clk",
2627 .parent = &vcodec0_clk_src.c,
2628 .ops = &clk_ops_branch,
2629 CLK_INIT(venus0_vcodec0_clk.c),
2630 },
2631};
2632
2633static struct measure_mux_entry measure_mux_MMSS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2634 { &mmss_mmssnoc_bto_ahb_clk.c, MMSS_BASE, 0x0002 },
2635 { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 },
2636 { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 },
2637 { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2638 { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b },
2639 { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c },
2640 { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d },
2641 { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e },
2642 { &venus0_axi_clk.c, MMSS_BASE, 0x000f },
2643 { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 },
2644 { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 },
2645 { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 },
2646 { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 },
2647 { &mdss_vsync_clk.c, MMSS_BASE, 0x001c },
2648 { &mdss_byte0_clk.c, MMSS_BASE, 0x001e },
2649 { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 },
2650 { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 },
2651 { &mdss_axi_clk.c, MMSS_BASE, 0x0024 },
2652 { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 },
2653 { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 },
2654 { &camss_gp0_clk.c, MMSS_BASE, 0x0027 },
2655 { &camss_gp1_clk.c, MMSS_BASE, 0x0028 },
2656 { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 },
2657 { &camss_mclk1_clk.c, MMSS_BASE, 0x002a },
2658 { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d },
2659 { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e },
2660 { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f },
2661 { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 },
2662 { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 },
2663 { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 },
2664 { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 },
2665 { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 },
2666 { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a },
2667 { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b },
2668 { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c },
2669 { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d },
2670 { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f },
2671 { &camss_csi0_clk.c, MMSS_BASE, 0x0041 },
2672 { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 },
2673 { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 },
2674 { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 },
2675 { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 },
2676 { &camss_csi1_clk.c, MMSS_BASE, 0x0046 },
2677 { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 },
2678 { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 },
2679 { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 },
2680 { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a },
2681 { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 },
2682 {&dummy_clk, N_BASES, 0x0000},
2683};
2684
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2685static struct branch_clk q6ss_ahb_lfabif_clk = {
2686 .cbcr_reg = Q6SS_AHB_LFABIF_CBCR,
2687 .has_sibling = 1,
2688 .base = &virt_bases[LPASS_BASE],
2689 .c = {
2690 .dbg_name = "q6ss_ahb_lfabif_clk",
2691 .ops = &clk_ops_branch,
2692 CLK_INIT(q6ss_ahb_lfabif_clk.c),
2693 },
2694};
2695
2696static struct branch_clk q6ss_ahbm_clk = {
2697 .cbcr_reg = Q6SS_AHBM_CBCR,
2698 .has_sibling = 1,
2699 .base = &virt_bases[LPASS_BASE],
2700 .c = {
2701 .dbg_name = "q6ss_ahbm_clk",
2702 .ops = &clk_ops_branch,
2703 CLK_INIT(q6ss_ahbm_clk.c),
2704 },
2705};
2706
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2707static struct branch_clk q6ss_xo_clk = {
2708 .cbcr_reg = Q6SS_XO_CBCR,
2709 .has_sibling = 1,
2710 .bcr_reg = Q6SS_BCR,
2711 .base = &virt_bases[LPASS_BASE],
2712 .c = {
2713 .dbg_name = "q6ss_xo_clk",
2714 .parent = &xo.c,
2715 .ops = &clk_ops_branch,
2716 CLK_INIT(q6ss_xo_clk.c),
2717 },
2718};
2719
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2720static struct measure_mux_entry measure_mux_LPASS[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2721 { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d },
2722 { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2723 { &q6ss_xo_clk.c, LPASS_BASE, 0x002b },
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2724 {&dummy_clk, N_BASES, 0x0000},
2725};
2726
2727
2728static DEFINE_CLK_MEASURE(apc0_m_clk);
2729static DEFINE_CLK_MEASURE(apc1_m_clk);
2730static DEFINE_CLK_MEASURE(apc2_m_clk);
2731static DEFINE_CLK_MEASURE(apc3_m_clk);
2732static DEFINE_CLK_MEASURE(l2_m_clk);
2733
2734static struct measure_mux_entry measure_mux_APSS[] = {
2735 {&apc0_m_clk, APCS_BASE, 0x00010},
2736 {&apc1_m_clk, APCS_BASE, 0x00114},
2737 {&apc2_m_clk, APCS_BASE, 0x00220},
2738 {&apc3_m_clk, APCS_BASE, 0x00324},
2739 {&l2_m_clk, APCS_BASE, 0x01000},
2740 {&dummy_clk, N_BASES, 0x0000}
2741};
2742
2743#define APCS_SH_PLL_MODE (0x000)
2744#define APCS_SH_PLL_L_VAL (0x004)
2745#define APCS_SH_PLL_M_VAL (0x008)
2746#define APCS_SH_PLL_N_VAL (0x00C)
2747#define APCS_SH_PLL_USER_CTL (0x010)
2748#define APCS_SH_PLL_CONFIG_CTL (0x014)
2749#define APCS_SH_PLL_STATUS (0x01C)
2750
2751enum vdd_sr2_pll_levels {
2752 VDD_SR2_PLL_OFF,
2753 VDD_SR2_PLL_ON,
2754 VDD_SR2_PLL_NUM
2755};
2756
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2757static struct regulator *vdd_sr2_reg;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2758static int set_vdd_sr2_pll(struct clk_vdd_class *vdd_class, int level)
2759{
2760 if (level == VDD_SR2_PLL_ON) {
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2761 return regulator_set_voltage(vdd_sr2_reg, 1800000,
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2762 1800000);
2763 } else {
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]2764 return regulator_set_voltage(vdd_sr2_reg, 0, 1800000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2765 }
2766}
2767
2768static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll,
2769 VDD_SR2_PLL_NUM);
2770
2771static struct pll_freq_tbl apcs_pll_freq[] = {
2772 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
2773 F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0),
2774 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
2775 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
2776 PLL_F_END
2777};
2778
2779static struct pll_clk a7sspll = {
2780 .mode_reg = (void __iomem *)APCS_SH_PLL_MODE,
2781 .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL,
2782 .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL,
2783 .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL,
2784 .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL,
2785 .status_reg = (void __iomem *)APCS_SH_PLL_STATUS,
2786 .freq_tbl = apcs_pll_freq,
2787 .masks = {
2788 .vco_mask = BM(29, 28),
2789 .pre_div_mask = BIT(12),
2790 .post_div_mask = BM(9, 8),
2791 .mn_en_mask = BIT(24),
2792 .main_output_mask = BIT(0),
2793 },
2794 .base = &virt_bases[APCS_PLL_BASE],
2795 .c = {
2796 .dbg_name = "a7sspll",
2797 .ops = &clk_ops_sr2_pll,
2798 .vdd_class = &vdd_sr2_pll,
2799 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
2800 [VDD_SR2_PLL_ON] = ULONG_MAX,
2801 },
2802 .num_fmax = VDD_SR2_PLL_NUM,
2803 CLK_INIT(a7sspll.c),
2804 /*
2805 * Need to skip handoff of the acpu pll to avoid
2806 * turning off the pll when the cpu is using it
2807 */
2808 .flags = CLKFLAG_SKIP_HANDOFF,
2809 },
2810};
2811
2812static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
2813static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
2814static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
2815static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
2816static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
2817static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX);
2818
2819static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
2820static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
2821static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX);
2822static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX);
2823static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX);
2824static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX);
2825static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX);
2826
2827static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX);
2828
2829#ifdef CONFIG_DEBUG_FS
2830static int measure_clk_set_parent(struct clk *c, struct clk *parent)
2831{
2832 struct measure_clk *clk = to_measure_clk(c);
2833 unsigned long flags;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2834 u32 regval, clk_sel, found = 0;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2835 int i;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2836 static const struct measure_mux_entry *array[] = {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2837 measure_mux_GCC,
2838 measure_mux_MMSS,
2839 measure_mux_LPASS,
2840 measure_mux_APSS,
2841 NULL
2842 };
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2843 const struct measure_mux_entry *mux = array[0];
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2844
2845 if (!parent)
2846 return -EINVAL;
2847
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2848 for (i = 0; array[i] && !found; i++) {
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2849 for (mux = array[i]; mux->c != &dummy_clk; mux++)
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2850 if (mux->c == parent) {
2851 found = 1;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2852 break;
Patrick Dalyb4997982013-01-31 11:45:28 -0800[diff] [blame]2853 }
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]2854 }
2855
2856 if (mux->c == &dummy_clk)
2857 return -EINVAL;
2858
2859 spin_lock_irqsave(&local_clock_reg_lock, flags);
2860 /*
2861 * Program the test vector, measurement period (sample_ticks)
2862 * and scaling multiplier.
2863 */
2864 clk->sample_ticks = 0x10000;
2865 clk->multiplier = 1;
2866
2867 switch (mux->base) {
2868
2869 case GCC_BASE:
2870 writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2871 clk_sel = mux->debug_mux;
2872 break;
2873
2874 case MMSS_BASE:
2875 writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2876 clk_sel = 0x02C;
2877 regval = BVAL(11, 0, mux->debug_mux);
2878 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2879
2880 /* Activate debug clock output */
2881 regval |= BIT(16);
2882 writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL));
2883 break;
2884
2885 case LPASS_BASE:
2886 writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2887 clk_sel = 0x161;
2888 regval = BVAL(11, 0, mux->debug_mux);
2889 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2890
2891 /* Activate debug clock output */
2892 regval |= BIT(20);
2893 writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL));
2894 break;
2895
2896 case APCS_BASE:
2897 clk->multiplier = 4;
2898 clk_sel = 362;
2899 regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG));
2900 regval &= ~0xC0037335;
2901 /* configure a divider of 4 */
2902 regval = BVAL(31, 30, 0x3) | mux->debug_mux;
2903 writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG));
2904 break;
2905
2906 default:
2907 return -EINVAL;
2908 }
2909
2910 /* Set debug mux clock index */
2911 regval = BVAL(8, 0, clk_sel);
2912 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2913
2914 /* Activate debug clock output */
2915 regval |= BIT(16);
2916 writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL));
2917
2918 /* Make sure test vector is set before starting measurements. */
2919 mb();
2920 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2921
2922 return 0;
2923}
2924
2925/* Sample clock for 'ticks' reference clock ticks. */
2926static u32 run_measurement(unsigned ticks)
2927{
2928 /* Stop counters and set the XO4 counter start value. */
2929 writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2930
2931 /* Wait for timer to become ready. */
2932 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2933 BIT(25)) != 0)
2934 cpu_relax();
2935
2936 /* Run measurement and wait for completion. */
2937 writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL));
2938 while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2939 BIT(25)) == 0)
2940 cpu_relax();
2941
2942 /* Return measured ticks. */
2943 return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) &
2944 BM(24, 0);
2945}
2946
2947/*
2948 * Perform a hardware rate measurement for a given clock.
2949 * FOR DEBUG USE ONLY: Measurements take ~15 ms!
2950 */
2951static unsigned long measure_clk_get_rate(struct clk *c)
2952{
2953 unsigned long flags;
2954 u32 gcc_xo4_reg_backup;
2955 u64 raw_count_short, raw_count_full;
2956 struct measure_clk *clk = to_measure_clk(c);
2957 unsigned ret;
2958
2959 ret = clk_prepare_enable(&xo.c);
2960 if (ret) {
2961 pr_warn("CXO clock failed to enable. Can't measure\n");
2962 return 0;
2963 }
2964
2965 spin_lock_irqsave(&local_clock_reg_lock, flags);
2966
2967 /* Enable CXO/4 and RINGOSC branch. */
2968 gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2969 writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2970
2971 /*
2972 * The ring oscillator counter will not reset if the measured clock
2973 * is not running. To detect this, run a short measurement before
2974 * the full measurement. If the raw results of the two are the same
2975 * then the clock must be off.
2976 */
2977
2978 /* Run a short measurement. (~1 ms) */
2979 raw_count_short = run_measurement(0x1000);
2980 /* Run a full measurement. (~14 ms) */
2981 raw_count_full = run_measurement(clk->sample_ticks);
2982
2983 writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR));
2984
2985 /* Return 0 if the clock is off. */
2986 if (raw_count_full == raw_count_short) {
2987 ret = 0;
2988 } else {
2989 /* Compute rate in Hz. */
2990 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
2991 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
2992 ret = (raw_count_full * clk->multiplier);
2993 }
2994
2995 writel_relaxed(0x51A00, GCC_REG_BASE(PLLTEST_PAD_CFG));
2996 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2997
2998 clk_disable_unprepare(&xo.c);
2999
3000 return ret;
3001}
3002
3003#else /* !CONFIG_DEBUG_FS */
3004static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
3005{
3006 return -EINVAL;
3007}
3008
3009static unsigned long measure_clk_get_rate(struct clk *clk)
3010{
3011 return 0;
3012}
3013#endif /* CONFIG_DEBUG_FS */
3014
3015static struct clk_ops clk_ops_measure = {
3016 .set_parent = measure_clk_set_parent,
3017 .get_rate = measure_clk_get_rate,
3018};
3019
3020static struct measure_clk measure_clk = {
3021 .c = {
3022 .dbg_name = "measure_clk",
3023 .ops = &clk_ops_measure,
3024 CLK_INIT(measure_clk.c),
3025 },
3026 .multiplier = 1,
3027};
3028
3029static struct clk_lookup msm_clocks_8226[] = {
3030 /* Debug Clocks */
3031 CLK_LOOKUP("measure", measure_clk.c, "debug"),
3032 CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""),
3033 CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""),
3034 CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""),
3035 CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""),
3036 CLK_LOOKUP("l2_m_clk", l2_m_clk, ""),
3037
3038 /* PIL-LPASS */
3039 CLK_LOOKUP("xo", xo.c, "fe200000.qcom,lpass"),
3040 CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"),
3041 CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"),
3042 CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"),
3043 CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"),
3044
3045 /* PIL-MODEM */
3046 CLK_LOOKUP("xo", xo.c, "fc880000.qcom,mss"),
3047 CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"),
3048 CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
3049 CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
3050
3051 /* PIL-PRONTO */
3052 CLK_LOOKUP("xo", xo.c, "fb21b000.qcom,pronto"),
3053
3054 /* PIL-VENUS */
3055 CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"),
3056 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"),
3057 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3058 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"),
3059 CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"),
3060
3061 /* ACPUCLOCK */
3062 CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
3063 CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
3064 CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
3065
3066 /* WCNSS CLOCKS */
Patrick Dalyc6355d22013-03-06 13:39:48 -0800[diff] [blame]3067 CLK_LOOKUP("xo", xo.c, "fb000000.qcom,wcnss-wlan"),
3068 CLK_LOOKUP("rf_clk", cxo_a2.c, "fb000000.qcom,wcnss-wlan"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3069
3070 /* BUS DRIVER */
3071 CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"),
3072 CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"),
3073 CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"),
3074 CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"),
3075 CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"),
3076 CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"),
3077 CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"),
3078 CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"),
3079 CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""),
3080 CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"),
3081 CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"),
3082 CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
3083 CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3084
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3085 /* CoreSight clocks */
3086 CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"),
3087 CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"),
3088 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"),
3089 CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"),
3090 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"),
3091 CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"),
3092 CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"),
3093 CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"),
3094 CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"),
3095 CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"),
3096 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"),
3097 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"),
3098 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"),
3099 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3100 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"),
3101 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"),
3102 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"),
3103 CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3104 CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"),
3105 CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"),
3106 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"),
3107 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"),
3108 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"),
3109 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"),
3110 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"),
3111 CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"),
3112 CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"),
3113 CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"),
3114 CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"),
3115 CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"),
3116 CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"),
3117 CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3118
Aparna Das8c8e9752013-02-28 21:23:24 -0800[diff] [blame]3119 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"),
3120 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"),
3121 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"),
3122 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"),
3123 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"),
3124 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"),
3125 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"),
3126 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"),
3127 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"),
3128 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"),
3129 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"),
3130 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"),
3131 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"),
3132 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"),
Pushkar Joshi14676cc2013-03-11 14:53:53 -0700[diff] [blame]3133 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33c000.jtagmm"),
3134 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33d000.jtagmm"),
3135 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33e000.jtagmm"),
3136 CLK_LOOKUP("core_a_clk", qdss_clk.c, "fc33f000.jtagmm"),
Aparna Dasbb65be42013-03-07 12:39:45 -0800[diff] [blame]3137 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"),
3138 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"),
3139 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"),
3140 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"),
3141 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"),
3142 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"),
3143 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"),
3144 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"),
3145 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"),
3146 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"),
3147 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"),
3148 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"),
3149 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"),
3150 CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3151
3152 /* HSUSB-OTG Clocks */
3153 CLK_LOOKUP("xo", xo.c, "f9a55000.usb"),
3154 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"),
3155 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"),
3156
3157 /* SPS CLOCKS */
3158 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"),
3159 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"),
3160 CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"),
3161 CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"),
3162
3163 /* I2C Clocks */
3164 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"),
3165 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"),
3166
Amy Maloche41708ba2013-03-03 15:19:27 -0800[diff] [blame]3167 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
3168 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"),
3169
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3170 /* lsuart-v14 Clocks */
3171 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"),
3172 CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"),
3173
3174 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"),
3175 CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"),
3176
Gilad Avidovd59217c2013-02-01 13:45:59 -0700[diff] [blame]3177 CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"),
3178 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3179
3180 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"),
3181 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"),
3182 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"),
3183 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "qseecom"),
3184
Patrick Dalyd5234252013-03-07 16:35:08 -0800[diff] [blame]3185 CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"),
3186 CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"),
3187 CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"),
3188 CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "scm"),
3189
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3190 /* SDCC */
3191 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"),
3192 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"),
3193 CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"),
3194 CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"),
3195
3196 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"),
3197 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"),
3198 CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"),
3199 CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"),
3200
3201 CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"),
3202 CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"),
3203
3204 CLK_LOOKUP("sleep_a_clk", gcc_usb2a_phy_sleep_clk.c, "msm_dwc3"),
3205 CLK_LOOKUP("ref_clk", diff_clk.c, "msm_dwc3"),
3206
3207
3208 CLK_LOOKUP("bus_clk", pnoc_clk.c, ""),
3209 CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""),
3210 CLK_LOOKUP("bus_clk", snoc_clk.c, ""),
3211 CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""),
3212 CLK_LOOKUP("bus_clk", cnoc_clk.c, ""),
3213 CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""),
3214 CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""),
3215 CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""),
3216 CLK_LOOKUP("bus_clk", bimc_clk.c, ""),
3217 CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""),
3218 CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""),
3219
3220 CLK_LOOKUP("gpll0", gpll0.c, ""),
3221 CLK_LOOKUP("gpll1", gpll1.c, ""),
3222 CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""),
3223 CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3224
3225 CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""),
3226 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
3227 CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
3228 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""),
3229 CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
3230 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""),
3231 CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
3232 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
3233 CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
3234 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
3235 CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
3236 CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
3237 CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""),
3238 CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""),
3239 CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""),
3240 CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""),
3241 CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""),
3242 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""),
3243 CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""),
3244 CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
3245 CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
3246
3247 CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"),
3248 CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"),
3249 CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"),
3250 CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"),
3251 CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"),
3252 CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"),
3253 CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"),
3254 CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"),
3255
3256 /* Multimedia clocks */
3257 CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"),
3258 CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"),
3259 CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"),
3260 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "mdss_dsi_clk_ctrl"),
3261
Adrian Salido-Morenof840a032013-03-01 23:10:03 -0800[diff] [blame]3262 CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"),
3263 CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"),
3264 CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"),
3265 CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"),
3266 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"),
3267 CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3268
3269 CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"),
3270 CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"),
3271
3272 /* MM sensor clocks */
3273 CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6e.qcom,camera"),
3274 CLK_LOOKUP("cam_src_clk", mclk1_clk_src.c, "90.qcom,camera"),
3275 CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6e.qcom,camera"),
3276 CLK_LOOKUP("cam_clk", camss_mclk1_clk.c, "90.qcom,camera"),
3277
3278 /* CCI clocks */
3279 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3280 "fda0c000.qcom,cci"),
3281 CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c,
3282 "fda0c000.qcom,cci"),
3283 CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"),
3284 CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"),
3285
3286 /* CSIPHY clocks */
3287 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3288 "fda0ac00.qcom,csiphy"),
3289 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3290 "fda0ac00.qcom,csiphy"),
3291 CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c,
3292 "fda0ac00.qcom,csiphy"),
3293 CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c,
3294 "fda0ac00.qcom,csiphy"),
3295 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3296 "fda0b000.qcom,csiphy"),
3297 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3298 "fda0b000.qcom,csiphy"),
3299 CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c,
3300 "fda0b000.qcom,csiphy"),
3301 CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c,
3302 "fda0b000.qcom,csiphy"),
3303
3304 /* CSID clocks */
3305 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3306 "fda08000.qcom,csid"),
3307 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3308 "fda08000.qcom,csid"),
3309 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08000.qcom,csid"),
3310 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08000.qcom,csid"),
3311 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08000.qcom,csid"),
3312 CLK_LOOKUP("csi0_clk", camss_csi0_clk.c, "fda08000.qcom,csid"),
3313 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08000.qcom,csid"),
3314 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08000.qcom,csid"),
3315
3316 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3317 "fda08400.qcom,csid"),
3318 CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c,
3319 "fda08400.qcom,csid"),
3320 CLK_LOOKUP("csi0_ahb_clk", camss_csi0_ahb_clk.c, "fda08400.qcom,csid"),
3321 CLK_LOOKUP("csi1_ahb_clk", camss_csi1_ahb_clk.c, "fda08400.qcom,csid"),
3322 CLK_LOOKUP("csi0_src_clk", csi0_clk_src.c, "fda08400.qcom,csid"),
3323 CLK_LOOKUP("csi1_src_clk", csi1_clk_src.c, "fda08400.qcom,csid"),
3324 CLK_LOOKUP("csi0_phy_clk", camss_csi0phy_clk.c, "fda08400.qcom,csid"),
3325 CLK_LOOKUP("csi1_phy_clk", camss_csi1phy_clk.c, "fda08400.qcom,csid"),
3326 CLK_LOOKUP("csi0_pix_clk", camss_csi0pix_clk.c, "fda08400.qcom,csid"),
3327 CLK_LOOKUP("csi1_pix_clk", camss_csi1pix_clk.c, "fda08400.qcom,csid"),
3328 CLK_LOOKUP("csi0_rdi_clk", camss_csi0rdi_clk.c, "fda08400.qcom,csid"),
3329 CLK_LOOKUP("csi1_rdi_clk", camss_csi1rdi_clk.c, "fda08400.qcom,csid"),
3330
3331 /* ISPIF clocks */
3332 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3333 "fda0a000.qcom,ispif"),
3334 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3335 "fda0a000.qcom,ispif"),
3336
3337 /* VFE clocks */
3338 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3339 "fda10000.qcom,vfe"),
3340 CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"),
3341 CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c,
3342 "fda10000.qcom,vfe"),
3343 CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c,
3344 "fda10000.qcom,vfe"),
3345 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"),
3346 CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"),
3347
3348 CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c,
3349 "fda44000.qcom,iommu"),
3350 CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"),
3351 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"),
3352
3353 /* Jpeg Clocks */
3354 CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"),
3355 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3356 "fda1c000.qcom,jpeg"),
3357 CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c,
3358 "fda1c000.qcom,jpeg"),
3359 CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c,
3360 "fda1c000.qcom,jpeg"),
3361
3362 CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"),
3363 CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c,
3364 "fda64000.qcom,iommu"),
3365 CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c,
3366 "fda64000.qcom,iommu"),
3367
3368 /* KGSL Clocks */
3369 CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"),
3370 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"),
liu zhongc45eb8b2013-02-21 11:50:24 -0800[diff] [blame]3371 CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c,
3372 "fdb00000.qcom,kgsl-3d0"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3373
3374 CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"),
3375 CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"),
3376 CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"),
3377
3378 CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3379
3380 /* Venus Clocks */
3381 CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"),
3382 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"),
3383 CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"),
3384
3385 CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c,
3386 "fdc84000.qcom,iommu"),
3387 CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"),
3388 CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"),
Hariprasad Dhalinarasimha92a13222013-03-12 11:59:28 -0700[diff] [blame]3389 CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"),
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3390 CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""),
3391 CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""),
3392 CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""),
3393
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3394 CLK_LOOKUP("", mmss_mmssnoc_bto_ahb_clk.c, ""),
3395 CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""),
3396 CLK_LOOKUP("", mmss_s0_axi_clk.c, ""),
Bhalchandra Gajared5a4ba72013-03-11 16:15:13 -0700[diff] [blame]3397
3398 /* Audio clocks */
3399 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"),
3400 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"),
3401 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"),
3402 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"),
3403 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"),
3404 CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"),
3405
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3406};
3407
3408static struct clk_lookup msm_clocks_8226_rumi[] = {
3409 CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3410 CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF),
3411 CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF),
3412 CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF),
3413 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF),
3414 CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF),
3415 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF),
3416 CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF),
3417 CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF),
3418 CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF),
3419};
3420
3421struct clock_init_data msm8226_rumi_clock_init_data __initdata = {
3422 .table = msm_clocks_8226_rumi,
3423 .size = ARRAY_SIZE(msm_clocks_8226_rumi),
3424};
3425
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3426static void __init reg_init(void)
3427{
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3428 u32 regval;
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3429
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3430 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
3431 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3432 regval |= BIT(0);
3433 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
3434
3435 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3436 * No clocks need to be enabled during sleep.
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3437 */
3438 writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE));
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3439}
Patrick Dalye02a5632013-02-12 20:23:35 -0800[diff] [blame]3440
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3441static void __init msm8226_clock_post_init(void)
3442{
Vikram Mulukutla441db7a2013-03-15 13:56:33 -0700[diff] [blame]3443 /*
3444 * Hold an active set vote for CXO; this is because CXO is expected
3445 * to remain on whenever CPUs aren't power collapsed.
3446 */
3447 clk_prepare_enable(&xo_a_clk.c);
3448
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3449 /* Set rates for single-rate clocks. */
3450 clk_set_rate(&usb_hs_system_clk_src.c,
3451 usb_hs_system_clk_src.freq_tbl[0].freq_hz);
3452 clk_set_rate(&usb_hsic_clk_src.c,
3453 usb_hsic_clk_src.freq_tbl[0].freq_hz);
3454 clk_set_rate(&usb_hsic_io_cal_clk_src.c,
3455 usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz);
3456 clk_set_rate(&usb_hsic_system_clk_src.c,
3457 usb_hsic_system_clk_src.freq_tbl[0].freq_hz);
3458 clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz);
3459 clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz);
3460 clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz);
3461 clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz);
3462 clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz);
3463 clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3464}
3465
3466#define GCC_CC_PHYS 0xFC400000
3467#define GCC_CC_SIZE SZ_16K
3468
3469#define MMSS_CC_PHYS 0xFD8C0000
3470#define MMSS_CC_SIZE SZ_256K
3471
3472#define LPASS_CC_PHYS 0xFE000000
3473#define LPASS_CC_SIZE SZ_256K
3474
3475#define APCS_KPSS_SH_PLL_PHYS 0xF9016000
3476#define APCS_KPSS_SH_PLL_SIZE SZ_64
3477
3478#define APCS_KPSS_GLB_PHYS 0xF9011000
3479#define APCS_KPSS_GLB_SIZE SZ_4K
3480
3481
3482static void __init msm8226_clock_pre_init(void)
3483{
3484 virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE);
3485 if (!virt_bases[GCC_BASE])
3486 panic("clock-8226: Unable to ioremap GCC memory!");
3487
3488 virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE);
3489 if (!virt_bases[MMSS_BASE])
3490 panic("clock-8226: Unable to ioremap MMSS_CC memory!");
3491
3492 virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE);
3493 if (!virt_bases[LPASS_BASE])
3494 panic("clock-8226: Unable to ioremap LPASS_CC memory!");
3495
3496 virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS,
3497 APCS_KPSS_GLB_SIZE);
3498 if (!virt_bases[APCS_BASE])
3499 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3500
3501 virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS,
3502 APCS_KPSS_SH_PLL_SIZE);
3503 if (!virt_bases[APCS_PLL_BASE])
3504 panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!");
3505
3506 clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable;
3507
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3508 vdd_dig_reg = regulator_get(NULL, "vdd_dig");
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3509 if (IS_ERR(vdd_dig_reg))
3510 panic("clock-8226: Unable to get the vdd_dig regulator!");
3511
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3512 vdd_sr2_reg = regulator_get(NULL, "vdd_sr2_pll");
3513 if (IS_ERR(vdd_dig_reg))
3514 panic("clock-8226: Unable to get the sr2_pll regulator!");
3515
3516 /*
Patrick Daly3668dd62013-03-04 20:27:55 -0800[diff] [blame]3517 * These regulators are used at boot. Ensure they stay on
3518 * while the clock framework comes online.
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3519 */
3520 regulator_set_voltage(vdd_sr2_reg, 1800000, 1800000);
3521 regulator_enable(vdd_sr2_reg);
3522
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3523 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Patrick Daly48e00f32013-01-28 19:13:47 -0800[diff] [blame]3524 regulator_enable(vdd_dig_reg);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3525
3526 /*
3527 * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB
3528 * source. Sleep set vote is 0.
3529 * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to
3530 * access mmss clock controller registers.
3531 */
3532 clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3533
Vikram Mulukutla29a06a32013-03-14 10:54:02 -0700[diff] [blame]3534 /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */
3535 clk_set_rate(&axi_clk_src.c, 200000000);
3536
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3537 enable_rpm_scaling();
3538
3539 reg_init();
Patrick Daly5555c2c2013-03-06 21:25:26 -0800[diff] [blame]3540
3541 /*
3542 * MDSS needs the ahb clock and needs to init before we register the
3543 * lookup table.
3544 */
3545 mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c);
Patrick Dalyeb370ea2012-10-23 11:57:50 -0700[diff] [blame]3546}
3547
3548static int __init msm8226_clock_late_init(void)
3549{
3550 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
3551}
3552
3553struct clock_init_data msm8226_clock_init_data __initdata = {
3554 .table = msm_clocks_8226,
3555 .size = ARRAY_SIZE(msm_clocks_8226),
3556 .pre_init = msm8226_clock_pre_init,
3557 .post_init = msm8226_clock_post_init,
3558 .late_init = msm8226_clock_late_init,
3559};