Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1 | /* drivers/serial/msm_serial_hs.c |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2 | * |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3 | * MSM 7k High speed uart driver |
| 4 | * |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 5 | * Copyright (c) 2008 Google Inc. |
Mayank Rana | adc4156 | 2013-01-04 12:44:01 +0530 | [diff] [blame] | 6 | * Copyright (c) 2007-2013, The Linux Foundation. All rights reserved. |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 7 | * Modified: Nick Pelly <npelly@google.com> |
| 8 | * |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 9 | * All source code in this file is licensed under the following license |
| 10 | * except where indicated. |
| 11 | * |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License |
| 14 | * version 2 as published by the Free Software Foundation. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
| 19 | * See the GNU General Public License for more details. |
| 20 | * |
| 21 | * Has optional support for uart power management independent of linux |
| 22 | * suspend/resume: |
| 23 | * |
| 24 | * RX wakeup. |
| 25 | * UART wakeup can be triggered by RX activity (using a wakeup GPIO on the |
| 26 | * UART RX pin). This should only be used if there is not a wakeup |
| 27 | * GPIO on the UART CTS, and the first RX byte is known (for example, with the |
| 28 | * Bluetooth Texas Instruments HCILL protocol), since the first RX byte will |
| 29 | * always be lost. RTS will be asserted even while the UART is off in this mode |
| 30 | * of operation. See msm_serial_hs_platform_data.rx_wakeup_irq. |
| 31 | */ |
| 32 | |
| 33 | #include <linux/module.h> |
| 34 | |
| 35 | #include <linux/serial.h> |
| 36 | #include <linux/serial_core.h> |
| 37 | #include <linux/slab.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/interrupt.h> |
| 40 | #include <linux/irq.h> |
| 41 | #include <linux/io.h> |
| 42 | #include <linux/ioport.h> |
Saket Saurabh | 10e88b3 | 2013-02-04 15:26:34 +0530 | [diff] [blame] | 43 | #include <linux/atomic.h> |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 44 | #include <linux/kernel.h> |
| 45 | #include <linux/timer.h> |
| 46 | #include <linux/clk.h> |
| 47 | #include <linux/platform_device.h> |
| 48 | #include <linux/pm_runtime.h> |
| 49 | #include <linux/dma-mapping.h> |
| 50 | #include <linux/dmapool.h> |
Steve Muckle | f132c6c | 2012-06-06 18:30:57 -0700 | [diff] [blame] | 51 | #include <linux/tty_flip.h> |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 52 | #include <linux/wait.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 53 | #include <linux/sysfs.h> |
| 54 | #include <linux/stat.h> |
| 55 | #include <linux/device.h> |
| 56 | #include <linux/wakelock.h> |
| 57 | #include <linux/debugfs.h> |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 58 | #include <linux/of.h> |
| 59 | #include <linux/of_device.h> |
| 60 | #include <linux/of_gpio.h> |
Saket Saurabh | fe3b93b | 2013-02-04 18:44:12 +0530 | [diff] [blame] | 61 | #include <linux/gpio.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 62 | #include <asm/atomic.h> |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 63 | #include <asm/irq.h> |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 64 | |
| 65 | #include <mach/hardware.h> |
| 66 | #include <mach/dma.h> |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 67 | #include <mach/sps.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 68 | #include <mach/msm_serial_hs.h> |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 69 | #include <mach/msm_bus.h> |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 70 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 71 | #include "msm_serial_hs_hwreg.h" |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 72 | #define UART_SPS_CONS_PERIPHERAL 0 |
| 73 | #define UART_SPS_PROD_PERIPHERAL 1 |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 74 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 75 | static int hs_serial_debug_mask = 1; |
| 76 | module_param_named(debug_mask, hs_serial_debug_mask, |
| 77 | int, S_IRUGO | S_IWUSR | S_IWGRP); |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 78 | /* |
| 79 | * There are 3 different kind of UART Core available on MSM. |
| 80 | * High Speed UART (i.e. Legacy HSUART), GSBI based HSUART |
| 81 | * and BSLP based HSUART. |
| 82 | */ |
| 83 | enum uart_core_type { |
| 84 | LEGACY_HSUART, |
| 85 | GSBI_HSUART, |
| 86 | BLSP_HSUART, |
| 87 | }; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 88 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 89 | enum flush_reason { |
| 90 | FLUSH_NONE, |
| 91 | FLUSH_DATA_READY, |
| 92 | FLUSH_DATA_INVALID, /* values after this indicate invalid data */ |
| 93 | FLUSH_IGNORE = FLUSH_DATA_INVALID, |
| 94 | FLUSH_STOP, |
| 95 | FLUSH_SHUTDOWN, |
| 96 | }; |
| 97 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 98 | enum msm_hs_clk_states_e { |
| 99 | MSM_HS_CLK_PORT_OFF, /* port not in use */ |
| 100 | MSM_HS_CLK_OFF, /* clock disabled */ |
| 101 | MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */ |
| 102 | MSM_HS_CLK_ON, /* clock enabled */ |
| 103 | }; |
| 104 | |
| 105 | /* Track the forced RXSTALE flush during clock off sequence. |
| 106 | * These states are only valid during MSM_HS_CLK_REQUEST_OFF */ |
| 107 | enum msm_hs_clk_req_off_state_e { |
| 108 | CLK_REQ_OFF_START, |
| 109 | CLK_REQ_OFF_RXSTALE_ISSUED, |
| 110 | CLK_REQ_OFF_FLUSH_ISSUED, |
| 111 | CLK_REQ_OFF_RXSTALE_FLUSHED, |
| 112 | }; |
| 113 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 114 | /* SPS data structures to support HSUART with BAM |
| 115 | * @sps_pipe - This struct defines BAM pipe descriptor |
| 116 | * @sps_connect - This struct defines a connection's end point |
| 117 | * @sps_register - This struct defines a event registration parameters |
| 118 | */ |
| 119 | struct msm_hs_sps_ep_conn_data { |
| 120 | struct sps_pipe *pipe_handle; |
| 121 | struct sps_connect config; |
| 122 | struct sps_register_event event; |
| 123 | }; |
| 124 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 125 | struct msm_hs_tx { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 126 | unsigned int tx_ready_int_en; /* ok to dma more tx */ |
| 127 | unsigned int dma_in_flight; /* tx dma in progress */ |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 128 | enum flush_reason flush; |
| 129 | wait_queue_head_t wait; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 130 | struct msm_dmov_cmd xfer; |
| 131 | dmov_box *command_ptr; |
| 132 | u32 *command_ptr_ptr; |
| 133 | dma_addr_t mapped_cmd_ptr; |
| 134 | dma_addr_t mapped_cmd_ptr_ptr; |
| 135 | int tx_count; |
| 136 | dma_addr_t dma_base; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 137 | struct tasklet_struct tlet; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 138 | struct msm_hs_sps_ep_conn_data cons; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 139 | }; |
| 140 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 141 | struct msm_hs_rx { |
| 142 | enum flush_reason flush; |
| 143 | struct msm_dmov_cmd xfer; |
| 144 | dma_addr_t cmdptr_dmaaddr; |
| 145 | dmov_box *command_ptr; |
| 146 | u32 *command_ptr_ptr; |
| 147 | dma_addr_t mapped_cmd_ptr; |
| 148 | wait_queue_head_t wait; |
| 149 | dma_addr_t rbuffer; |
| 150 | unsigned char *buffer; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 151 | unsigned int buffer_pending; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 152 | struct dma_pool *pool; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 153 | struct wake_lock wake_lock; |
| 154 | struct delayed_work flip_insert_work; |
| 155 | struct tasklet_struct tlet; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 156 | struct msm_hs_sps_ep_conn_data prod; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 157 | }; |
| 158 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 159 | enum buffer_states { |
| 160 | NONE_PENDING = 0x0, |
| 161 | FIFO_OVERRUN = 0x1, |
| 162 | PARITY_ERROR = 0x2, |
| 163 | CHARS_NORMAL = 0x4, |
| 164 | }; |
| 165 | |
| 166 | /* optional low power wakeup, typically on a GPIO RX irq */ |
| 167 | struct msm_hs_wakeup { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 168 | int irq; /* < 0 indicates low power wakeup disabled */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 169 | unsigned char ignore; /* bool */ |
| 170 | |
| 171 | /* bool: inject char into rx tty on wakeup */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 172 | unsigned char inject_rx; |
| 173 | char rx_to_inject; |
| 174 | }; |
| 175 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 176 | struct msm_hs_port { |
| 177 | struct uart_port uport; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 178 | unsigned long imr_reg; /* shadow value of UARTDM_IMR */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 179 | struct clk *clk; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 180 | struct clk *pclk; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 181 | struct msm_hs_tx tx; |
| 182 | struct msm_hs_rx rx; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 183 | /* gsbi uarts have to do additional writes to gsbi memory */ |
| 184 | /* block and top control status block. The following pointers */ |
| 185 | /* keep a handle to these blocks. */ |
| 186 | unsigned char __iomem *mapped_gsbi; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 187 | int dma_tx_channel; |
| 188 | int dma_rx_channel; |
| 189 | int dma_tx_crci; |
| 190 | int dma_rx_crci; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 191 | struct hrtimer clk_off_timer; /* to poll TXEMT before clock off */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 192 | ktime_t clk_off_delay; |
| 193 | enum msm_hs_clk_states_e clk_state; |
| 194 | enum msm_hs_clk_req_off_state_e clk_req_off_state; |
| 195 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 196 | struct msm_hs_wakeup wakeup; |
| 197 | struct wake_lock dma_wake_lock; /* held while any DMA active */ |
Mayank Rana | 17e0e1a | 2012-04-07 02:10:33 +0530 | [diff] [blame] | 198 | |
| 199 | struct dentry *loopback_dir; |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 200 | struct work_struct clock_off_w; /* work for actual clock off */ |
| 201 | struct workqueue_struct *hsuart_wq; /* hsuart workqueue */ |
| 202 | struct mutex clk_mutex; /* mutex to guard against clock off/clock on */ |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 203 | struct work_struct disconnect_rx_endpoint; /* disconnect rx_endpoint */ |
Saket Saurabh | ce39410 | 2012-10-29 19:51:28 +0530 | [diff] [blame] | 204 | bool tty_flush_receive; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 205 | enum uart_core_type uart_type; |
| 206 | u32 bam_handle; |
| 207 | resource_size_t bam_mem; |
| 208 | int bam_irq; |
| 209 | unsigned char __iomem *bam_base; |
| 210 | unsigned int bam_tx_ep_pipe_index; |
| 211 | unsigned int bam_rx_ep_pipe_index; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 212 | /* struct sps_event_notify is an argument passed when triggering a |
| 213 | * callback event object registered for an SPS connection end point. |
| 214 | */ |
| 215 | struct sps_event_notify notify; |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 216 | /* bus client handler */ |
| 217 | u32 bus_perf_client; |
| 218 | /* BLSP UART required BUS Scaling data */ |
| 219 | struct msm_bus_scale_pdata *bus_scale_table; |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 220 | bool rx_discard_flush_issued; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 221 | int rx_count_callback; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 222 | }; |
| 223 | |
| 224 | #define MSM_UARTDM_BURST_SIZE 16 /* DM burst size (in bytes) */ |
| 225 | #define UARTDM_TX_BUF_SIZE UART_XMIT_SIZE |
| 226 | #define UARTDM_RX_BUF_SIZE 512 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 227 | #define RETRY_TIMEOUT 5 |
Saket Saurabh | 51690e5 | 2012-08-17 14:17:46 +0530 | [diff] [blame] | 228 | #define UARTDM_NR 256 |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 229 | #define BAM_PIPE_MIN 0 |
| 230 | #define BAM_PIPE_MAX 11 |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 231 | #define BUS_SCALING 1 |
| 232 | #define BUS_RESET 0 |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 233 | #define RX_FLUSH_COMPLETE_TIMEOUT 300 /* In jiffies */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 234 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 235 | static struct dentry *debug_base; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 236 | static struct msm_hs_port q_uart_port[UARTDM_NR]; |
| 237 | static struct platform_driver msm_serial_hs_platform_driver; |
| 238 | static struct uart_driver msm_hs_driver; |
| 239 | static struct uart_ops msm_hs_ops; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 240 | static void msm_hs_start_rx_locked(struct uart_port *uport); |
| 241 | static void msm_serial_hs_rx_tlet(unsigned long tlet_ptr); |
| 242 | static void flip_insert_work(struct work_struct *work); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 243 | |
| 244 | #define UARTDM_TO_MSM(uart_port) \ |
| 245 | container_of((uart_port), struct msm_hs_port, uport) |
| 246 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 247 | static ssize_t show_clock(struct device *dev, struct device_attribute *attr, |
| 248 | char *buf) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 249 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 250 | int state = 1; |
| 251 | enum msm_hs_clk_states_e clk_state; |
| 252 | unsigned long flags; |
| 253 | |
| 254 | struct platform_device *pdev = container_of(dev, struct |
| 255 | platform_device, dev); |
| 256 | struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; |
| 257 | |
| 258 | spin_lock_irqsave(&msm_uport->uport.lock, flags); |
| 259 | clk_state = msm_uport->clk_state; |
| 260 | spin_unlock_irqrestore(&msm_uport->uport.lock, flags); |
| 261 | |
| 262 | if (clk_state <= MSM_HS_CLK_OFF) |
| 263 | state = 0; |
| 264 | |
Mayank Rana | 18958b0 | 2011-09-28 12:33:36 +0530 | [diff] [blame] | 265 | return snprintf(buf, PAGE_SIZE, "%d\n", state); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 266 | } |
| 267 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 268 | static ssize_t set_clock(struct device *dev, struct device_attribute *attr, |
| 269 | const char *buf, size_t count) |
| 270 | { |
| 271 | int state; |
| 272 | struct platform_device *pdev = container_of(dev, struct |
| 273 | platform_device, dev); |
| 274 | struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; |
| 275 | |
| 276 | state = buf[0] - '0'; |
| 277 | switch (state) { |
| 278 | case 0: { |
| 279 | msm_hs_request_clock_off(&msm_uport->uport); |
| 280 | break; |
| 281 | } |
| 282 | case 1: { |
| 283 | msm_hs_request_clock_on(&msm_uport->uport); |
| 284 | break; |
| 285 | } |
| 286 | default: { |
| 287 | return -EINVAL; |
| 288 | } |
| 289 | } |
| 290 | return count; |
| 291 | } |
| 292 | |
| 293 | static DEVICE_ATTR(clock, S_IWUSR | S_IRUGO, show_clock, set_clock); |
| 294 | |
| 295 | static inline unsigned int use_low_power_wakeup(struct msm_hs_port *msm_uport) |
| 296 | { |
| 297 | return (msm_uport->wakeup.irq > 0); |
| 298 | } |
| 299 | |
| 300 | static inline int is_gsbi_uart(struct msm_hs_port *msm_uport) |
| 301 | { |
| 302 | /* assume gsbi uart if gsbi resource found in pdata */ |
| 303 | return ((msm_uport->mapped_gsbi != NULL)); |
| 304 | } |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 305 | static unsigned int is_blsp_uart(struct msm_hs_port *msm_uport) |
| 306 | { |
| 307 | return (msm_uport->uart_type == BLSP_HSUART); |
| 308 | } |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 309 | |
| 310 | static void msm_hs_bus_voting(struct msm_hs_port *msm_uport, unsigned int vote) |
| 311 | { |
| 312 | int ret; |
| 313 | |
| 314 | if (is_blsp_uart(msm_uport) && msm_uport->bus_perf_client) { |
| 315 | pr_debug("Bus voting:%d\n", vote); |
| 316 | ret = msm_bus_scale_client_update_request( |
| 317 | msm_uport->bus_perf_client, vote); |
| 318 | if (ret) |
| 319 | pr_err("%s(): Failed for Bus voting: %d\n", |
| 320 | __func__, vote); |
| 321 | } |
| 322 | } |
| 323 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 324 | static inline unsigned int msm_hs_read(struct uart_port *uport, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 325 | unsigned int offset) |
| 326 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 327 | return readl_relaxed(uport->membase + offset); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 328 | } |
| 329 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 330 | static inline void msm_hs_write(struct uart_port *uport, unsigned int offset, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 331 | unsigned int value) |
| 332 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 333 | writel_relaxed(value, uport->membase + offset); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static void msm_hs_release_port(struct uart_port *port) |
| 337 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 338 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port); |
| 339 | struct platform_device *pdev = to_platform_device(port->dev); |
| 340 | struct resource *gsbi_resource; |
| 341 | resource_size_t size; |
| 342 | |
| 343 | if (is_gsbi_uart(msm_uport)) { |
| 344 | iowrite32(GSBI_PROTOCOL_IDLE, msm_uport->mapped_gsbi + |
| 345 | GSBI_CONTROL_ADDR); |
| 346 | gsbi_resource = platform_get_resource_byname(pdev, |
| 347 | IORESOURCE_MEM, |
| 348 | "gsbi_resource"); |
Mayank Rana | 53a2c77 | 2011-11-01 14:29:14 +0530 | [diff] [blame] | 349 | if (unlikely(!gsbi_resource)) |
| 350 | return; |
| 351 | |
| 352 | size = resource_size(gsbi_resource); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 353 | release_mem_region(gsbi_resource->start, size); |
| 354 | iounmap(msm_uport->mapped_gsbi); |
| 355 | msm_uport->mapped_gsbi = NULL; |
| 356 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | static int msm_hs_request_port(struct uart_port *port) |
| 360 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 361 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port); |
| 362 | struct platform_device *pdev = to_platform_device(port->dev); |
| 363 | struct resource *gsbi_resource; |
| 364 | resource_size_t size; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 365 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 366 | gsbi_resource = platform_get_resource_byname(pdev, |
| 367 | IORESOURCE_MEM, |
| 368 | "gsbi_resource"); |
| 369 | if (gsbi_resource) { |
Mayank Rana | 53a2c77 | 2011-11-01 14:29:14 +0530 | [diff] [blame] | 370 | size = resource_size(gsbi_resource); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 371 | if (unlikely(!request_mem_region(gsbi_resource->start, size, |
| 372 | "msm_serial_hs"))) |
| 373 | return -EBUSY; |
| 374 | msm_uport->mapped_gsbi = ioremap(gsbi_resource->start, |
| 375 | size); |
| 376 | if (!msm_uport->mapped_gsbi) { |
| 377 | release_mem_region(gsbi_resource->start, size); |
| 378 | return -EBUSY; |
| 379 | } |
| 380 | } |
| 381 | /* no gsbi uart */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 382 | return 0; |
| 383 | } |
| 384 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 385 | static int msm_serial_loopback_enable_set(void *data, u64 val) |
| 386 | { |
| 387 | struct msm_hs_port *msm_uport = data; |
| 388 | struct uart_port *uport = &(msm_uport->uport); |
| 389 | unsigned long flags; |
| 390 | int ret = 0; |
| 391 | |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 392 | msm_hs_bus_voting(msm_uport, BUS_SCALING); |
| 393 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 394 | clk_prepare_enable(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 395 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 396 | clk_prepare_enable(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 397 | |
| 398 | if (val) { |
| 399 | spin_lock_irqsave(&uport->lock, flags); |
| 400 | ret = msm_hs_read(uport, UARTDM_MR2_ADDR); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 401 | if (is_blsp_uart(msm_uport)) |
| 402 | ret |= (UARTDM_MR2_LOOP_MODE_BMSK | |
| 403 | UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK); |
| 404 | else |
| 405 | ret |= UARTDM_MR2_LOOP_MODE_BMSK; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 406 | msm_hs_write(uport, UARTDM_MR2_ADDR, ret); |
| 407 | spin_unlock_irqrestore(&uport->lock, flags); |
| 408 | } else { |
| 409 | spin_lock_irqsave(&uport->lock, flags); |
| 410 | ret = msm_hs_read(uport, UARTDM_MR2_ADDR); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 411 | if (is_blsp_uart(msm_uport)) |
| 412 | ret &= ~(UARTDM_MR2_LOOP_MODE_BMSK | |
| 413 | UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK); |
| 414 | else |
| 415 | ret &= ~UARTDM_MR2_LOOP_MODE_BMSK; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 416 | msm_hs_write(uport, UARTDM_MR2_ADDR, ret); |
| 417 | spin_unlock_irqrestore(&uport->lock, flags); |
| 418 | } |
| 419 | /* Calling CLOCK API. Hence mb() requires here. */ |
| 420 | mb(); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 421 | clk_disable_unprepare(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 422 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 423 | clk_disable_unprepare(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 424 | |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 425 | msm_hs_bus_voting(msm_uport, BUS_RESET); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | static int msm_serial_loopback_enable_get(void *data, u64 *val) |
| 430 | { |
| 431 | struct msm_hs_port *msm_uport = data; |
| 432 | struct uart_port *uport = &(msm_uport->uport); |
| 433 | unsigned long flags; |
| 434 | int ret = 0; |
| 435 | |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 436 | msm_hs_bus_voting(msm_uport, BUS_SCALING); |
| 437 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 438 | clk_prepare_enable(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 439 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 440 | clk_prepare_enable(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 441 | |
| 442 | spin_lock_irqsave(&uport->lock, flags); |
| 443 | ret = msm_hs_read(&msm_uport->uport, UARTDM_MR2_ADDR); |
| 444 | spin_unlock_irqrestore(&uport->lock, flags); |
| 445 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 446 | clk_disable_unprepare(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 447 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 448 | clk_disable_unprepare(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 449 | |
| 450 | *val = (ret & UARTDM_MR2_LOOP_MODE_BMSK) ? 1 : 0; |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 451 | |
| 452 | msm_hs_bus_voting(msm_uport, BUS_RESET); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 453 | return 0; |
| 454 | } |
| 455 | DEFINE_SIMPLE_ATTRIBUTE(loopback_enable_fops, msm_serial_loopback_enable_get, |
| 456 | msm_serial_loopback_enable_set, "%llu\n"); |
| 457 | |
| 458 | /* |
| 459 | * msm_serial_hs debugfs node: <debugfs_root>/msm_serial_hs/loopback.<id> |
| 460 | * writing 1 turns on internal loopback mode in HW. Useful for automation |
| 461 | * test scripts. |
| 462 | * writing 0 disables the internal loopback mode. Default is disabled. |
| 463 | */ |
Stephen Boyd | 7bce097 | 2012-04-25 11:54:27 -0700 | [diff] [blame] | 464 | static void __devinit msm_serial_debugfs_init(struct msm_hs_port *msm_uport, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 465 | int id) |
| 466 | { |
| 467 | char node_name[15]; |
| 468 | snprintf(node_name, sizeof(node_name), "loopback.%d", id); |
Mayank Rana | 17e0e1a | 2012-04-07 02:10:33 +0530 | [diff] [blame] | 469 | msm_uport->loopback_dir = debugfs_create_file(node_name, |
| 470 | S_IRUGO | S_IWUSR, |
| 471 | debug_base, |
| 472 | msm_uport, |
| 473 | &loopback_enable_fops); |
| 474 | |
| 475 | if (IS_ERR_OR_NULL(msm_uport->loopback_dir)) |
| 476 | pr_err("%s(): Cannot create loopback.%d debug entry", |
| 477 | __func__, id); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 478 | } |
| 479 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 480 | static int __devexit msm_hs_remove(struct platform_device *pdev) |
| 481 | { |
| 482 | |
| 483 | struct msm_hs_port *msm_uport; |
| 484 | struct device *dev; |
| 485 | |
| 486 | if (pdev->id < 0 || pdev->id >= UARTDM_NR) { |
| 487 | printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id); |
| 488 | return -EINVAL; |
| 489 | } |
| 490 | |
| 491 | msm_uport = &q_uart_port[pdev->id]; |
| 492 | dev = msm_uport->uport.dev; |
| 493 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 494 | sysfs_remove_file(&pdev->dev.kobj, &dev_attr_clock.attr); |
Mayank Rana | 17e0e1a | 2012-04-07 02:10:33 +0530 | [diff] [blame] | 495 | debugfs_remove(msm_uport->loopback_dir); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 496 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 497 | dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box), |
| 498 | DMA_TO_DEVICE); |
| 499 | dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer, |
| 500 | msm_uport->rx.rbuffer); |
| 501 | dma_pool_destroy(msm_uport->rx.pool); |
| 502 | |
Mayank Rana | 8431de8 | 2011-12-08 09:06:08 +0530 | [diff] [blame] | 503 | dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32), |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 504 | DMA_TO_DEVICE); |
Mayank Rana | 8431de8 | 2011-12-08 09:06:08 +0530 | [diff] [blame] | 505 | dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32), |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 506 | DMA_TO_DEVICE); |
| 507 | dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box), |
| 508 | DMA_TO_DEVICE); |
| 509 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 510 | wake_lock_destroy(&msm_uport->rx.wake_lock); |
| 511 | wake_lock_destroy(&msm_uport->dma_wake_lock); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 512 | destroy_workqueue(msm_uport->hsuart_wq); |
| 513 | mutex_destroy(&msm_uport->clk_mutex); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 514 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 515 | uart_remove_one_port(&msm_hs_driver, &msm_uport->uport); |
| 516 | clk_put(msm_uport->clk); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 517 | if (msm_uport->pclk) |
| 518 | clk_put(msm_uport->pclk); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 519 | |
| 520 | /* Free the tx resources */ |
| 521 | kfree(msm_uport->tx.command_ptr); |
| 522 | kfree(msm_uport->tx.command_ptr_ptr); |
| 523 | |
| 524 | /* Free the rx resources */ |
| 525 | kfree(msm_uport->rx.command_ptr); |
| 526 | kfree(msm_uport->rx.command_ptr_ptr); |
| 527 | |
| 528 | iounmap(msm_uport->uport.membase); |
| 529 | |
| 530 | return 0; |
| 531 | } |
| 532 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 533 | static int msm_hs_init_clk(struct uart_port *uport) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 534 | { |
| 535 | int ret; |
| 536 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 537 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 538 | /* Set up the MREG/NREG/DREG/MNDREG */ |
| 539 | ret = clk_set_rate(msm_uport->clk, uport->uartclk); |
| 540 | if (ret) { |
| 541 | printk(KERN_WARNING "Error setting clock rate on UART\n"); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 542 | return ret; |
| 543 | } |
| 544 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 545 | ret = clk_prepare_enable(msm_uport->clk); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 546 | if (ret) { |
| 547 | printk(KERN_ERR "Error could not turn on UART clk\n"); |
| 548 | return ret; |
| 549 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 550 | if (msm_uport->pclk) { |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 551 | ret = clk_prepare_enable(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 552 | if (ret) { |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 553 | clk_disable_unprepare(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 554 | dev_err(uport->dev, |
| 555 | "Error could not turn on UART pclk\n"); |
| 556 | return ret; |
| 557 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 558 | } |
| 559 | |
| 560 | msm_uport->clk_state = MSM_HS_CLK_ON; |
| 561 | return 0; |
| 562 | } |
| 563 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 564 | |
| 565 | /* Connect a UART peripheral's SPS endpoint(consumer endpoint) |
| 566 | * |
| 567 | * Also registers a SPS callback function for the consumer |
| 568 | * process with the SPS driver |
| 569 | * |
| 570 | * @uport - Pointer to uart uport structure |
| 571 | * |
| 572 | * @return - 0 if successful else negative value. |
| 573 | * |
| 574 | */ |
| 575 | |
| 576 | static int msm_hs_spsconnect_tx(struct uart_port *uport) |
| 577 | { |
| 578 | int ret; |
| 579 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 580 | struct msm_hs_tx *tx = &msm_uport->tx; |
| 581 | struct sps_pipe *sps_pipe_handle = tx->cons.pipe_handle; |
| 582 | struct sps_connect *sps_config = &tx->cons.config; |
| 583 | struct sps_register_event *sps_event = &tx->cons.event; |
| 584 | |
| 585 | /* Establish connection between peripheral and memory endpoint */ |
| 586 | ret = sps_connect(sps_pipe_handle, sps_config); |
| 587 | if (ret) { |
| 588 | pr_err("msm_serial_hs: sps_connect() failed for tx!!\n" |
| 589 | "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret); |
| 590 | return ret; |
| 591 | } |
| 592 | /* Register callback event for EOT (End of transfer) event. */ |
| 593 | ret = sps_register_event(sps_pipe_handle, sps_event); |
| 594 | if (ret) { |
| 595 | pr_err("msm_serial_hs: sps_connect() failed for tx!!\n" |
| 596 | "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret); |
| 597 | goto reg_event_err; |
| 598 | } |
| 599 | return 0; |
| 600 | |
| 601 | reg_event_err: |
| 602 | sps_disconnect(sps_pipe_handle); |
| 603 | return ret; |
| 604 | } |
| 605 | |
| 606 | /* Connect a UART peripheral's SPS endpoint(producer endpoint) |
| 607 | * |
| 608 | * Also registers a SPS callback function for the producer |
| 609 | * process with the SPS driver |
| 610 | * |
| 611 | * @uport - Pointer to uart uport structure |
| 612 | * |
| 613 | * @return - 0 if successful else negative value. |
| 614 | * |
| 615 | */ |
| 616 | |
| 617 | static int msm_hs_spsconnect_rx(struct uart_port *uport) |
| 618 | { |
| 619 | int ret; |
| 620 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 621 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 622 | struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; |
| 623 | struct sps_connect *sps_config = &rx->prod.config; |
| 624 | struct sps_register_event *sps_event = &rx->prod.event; |
| 625 | |
| 626 | /* Establish connection between peripheral and memory endpoint */ |
| 627 | ret = sps_connect(sps_pipe_handle, sps_config); |
| 628 | if (ret) { |
| 629 | pr_err("msm_serial_hs: sps_connect() failed for rx!!\n" |
| 630 | "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret); |
| 631 | return ret; |
| 632 | } |
| 633 | /* Register callback event for EOT (End of transfer) event. */ |
| 634 | ret = sps_register_event(sps_pipe_handle, sps_event); |
| 635 | if (ret) { |
| 636 | pr_err("msm_serial_hs: sps_connect() failed for rx!!\n" |
| 637 | "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret); |
| 638 | goto reg_event_err; |
| 639 | } |
| 640 | return 0; |
| 641 | |
| 642 | reg_event_err: |
| 643 | sps_disconnect(sps_pipe_handle); |
| 644 | return ret; |
| 645 | } |
| 646 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 647 | /* |
| 648 | * programs the UARTDM_CSR register with correct bit rates |
| 649 | * |
| 650 | * Interrupts should be disabled before we are called, as |
| 651 | * we modify Set Baud rate |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 652 | * Set receive stale interrupt level, dependant on Bit Rate |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 653 | * Goal is to have around 8 ms before indicate stale. |
| 654 | * roundup (((Bit Rate * .008) / 10) + 1 |
| 655 | */ |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 656 | static void msm_hs_set_bps_locked(struct uart_port *uport, |
| 657 | unsigned int bps) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 658 | { |
| 659 | unsigned long rxstale; |
| 660 | unsigned long data; |
| 661 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 662 | |
| 663 | switch (bps) { |
| 664 | case 300: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 665 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x00); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 666 | rxstale = 1; |
| 667 | break; |
| 668 | case 600: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 669 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x11); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 670 | rxstale = 1; |
| 671 | break; |
| 672 | case 1200: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 673 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x22); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 674 | rxstale = 1; |
| 675 | break; |
| 676 | case 2400: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 677 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x33); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 678 | rxstale = 1; |
| 679 | break; |
| 680 | case 4800: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 681 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x44); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 682 | rxstale = 1; |
| 683 | break; |
| 684 | case 9600: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 685 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x55); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 686 | rxstale = 2; |
| 687 | break; |
| 688 | case 14400: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 689 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x66); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 690 | rxstale = 3; |
| 691 | break; |
| 692 | case 19200: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 693 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x77); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 694 | rxstale = 4; |
| 695 | break; |
| 696 | case 28800: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 697 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x88); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 698 | rxstale = 6; |
| 699 | break; |
| 700 | case 38400: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 701 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 702 | rxstale = 8; |
| 703 | break; |
| 704 | case 57600: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 705 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xaa); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 706 | rxstale = 16; |
| 707 | break; |
| 708 | case 76800: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 709 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xbb); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 710 | rxstale = 16; |
| 711 | break; |
| 712 | case 115200: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 713 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xcc); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 714 | rxstale = 31; |
| 715 | break; |
| 716 | case 230400: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 717 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xee); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 718 | rxstale = 31; |
| 719 | break; |
| 720 | case 460800: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 721 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 722 | rxstale = 31; |
| 723 | break; |
| 724 | case 4000000: |
| 725 | case 3686400: |
| 726 | case 3200000: |
| 727 | case 3500000: |
| 728 | case 3000000: |
| 729 | case 2500000: |
| 730 | case 1500000: |
| 731 | case 1152000: |
| 732 | case 1000000: |
| 733 | case 921600: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 734 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 735 | rxstale = 31; |
| 736 | break; |
| 737 | default: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 738 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 739 | /* default to 9600 */ |
| 740 | bps = 9600; |
| 741 | rxstale = 2; |
| 742 | break; |
| 743 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 744 | /* |
| 745 | * uart baud rate depends on CSR and MND Values |
| 746 | * we are updating CSR before and then calling |
| 747 | * clk_set_rate which updates MND Values. Hence |
| 748 | * dsb requires here. |
| 749 | */ |
| 750 | mb(); |
| 751 | if (bps > 460800) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 752 | uport->uartclk = bps * 16; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 753 | } else { |
| 754 | uport->uartclk = 7372800; |
| 755 | } |
Mayank Rana | e672516 | 2012-08-22 17:44:25 +0530 | [diff] [blame] | 756 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 757 | if (clk_set_rate(msm_uport->clk, uport->uartclk)) { |
| 758 | printk(KERN_WARNING "Error setting clock rate on UART\n"); |
Mayank Rana | e672516 | 2012-08-22 17:44:25 +0530 | [diff] [blame] | 759 | WARN_ON(1); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | data = rxstale & UARTDM_IPR_STALE_LSB_BMSK; |
| 763 | data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2); |
| 764 | |
| 765 | msm_hs_write(uport, UARTDM_IPR_ADDR, data); |
Mayank Rana | 2d4d2f6 | 2011-07-21 17:31:31 +0530 | [diff] [blame] | 766 | /* |
| 767 | * It is suggested to do reset of transmitter and receiver after |
| 768 | * changing any protocol configuration. Here Baud rate and stale |
| 769 | * timeout are getting updated. Hence reset transmitter and receiver. |
| 770 | */ |
| 771 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX); |
| 772 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 773 | } |
| 774 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 775 | |
| 776 | static void msm_hs_set_std_bps_locked(struct uart_port *uport, |
| 777 | unsigned int bps) |
| 778 | { |
| 779 | unsigned long rxstale; |
| 780 | unsigned long data; |
| 781 | |
| 782 | switch (bps) { |
| 783 | case 9600: |
| 784 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99); |
| 785 | rxstale = 2; |
| 786 | break; |
| 787 | case 14400: |
| 788 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xaa); |
| 789 | rxstale = 3; |
| 790 | break; |
| 791 | case 19200: |
| 792 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xbb); |
| 793 | rxstale = 4; |
| 794 | break; |
| 795 | case 28800: |
| 796 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xcc); |
| 797 | rxstale = 6; |
| 798 | break; |
| 799 | case 38400: |
| 800 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xdd); |
| 801 | rxstale = 8; |
| 802 | break; |
| 803 | case 57600: |
| 804 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xee); |
| 805 | rxstale = 16; |
| 806 | break; |
| 807 | case 115200: |
| 808 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0xff); |
| 809 | rxstale = 31; |
| 810 | break; |
| 811 | default: |
| 812 | msm_hs_write(uport, UARTDM_CSR_ADDR, 0x99); |
| 813 | /* default to 9600 */ |
| 814 | bps = 9600; |
| 815 | rxstale = 2; |
| 816 | break; |
| 817 | } |
| 818 | |
| 819 | data = rxstale & UARTDM_IPR_STALE_LSB_BMSK; |
| 820 | data |= UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK & (rxstale << 2); |
| 821 | |
| 822 | msm_hs_write(uport, UARTDM_IPR_ADDR, data); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 823 | } |
| 824 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 825 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 826 | /* |
| 827 | * termios : new ktermios |
| 828 | * oldtermios: old ktermios previous setting |
| 829 | * |
| 830 | * Configure the serial port |
| 831 | */ |
| 832 | static void msm_hs_set_termios(struct uart_port *uport, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 833 | struct ktermios *termios, |
| 834 | struct ktermios *oldtermios) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 835 | { |
| 836 | unsigned int bps; |
| 837 | unsigned long data; |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 838 | int ret; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 839 | unsigned int c_cflag = termios->c_cflag; |
| 840 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 841 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 842 | struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 843 | |
Mayank Rana | e672516 | 2012-08-22 17:44:25 +0530 | [diff] [blame] | 844 | mutex_lock(&msm_uport->clk_mutex); |
Saket Saurabh | a8bd52e | 2013-02-15 12:50:27 +0530 | [diff] [blame] | 845 | msm_hs_write(uport, UARTDM_IMR_ADDR, 0); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 846 | |
Mayank Rana | 2d4d2f6 | 2011-07-21 17:31:31 +0530 | [diff] [blame] | 847 | /* |
| 848 | * Disable Rx channel of UARTDM |
| 849 | * DMA Rx Stall happens if enqueue and flush of Rx command happens |
| 850 | * concurrently. Hence before changing the baud rate/protocol |
| 851 | * configuration and sending flush command to ADM, disable the Rx |
| 852 | * channel of UARTDM. |
| 853 | * Note: should not reset the receiver here immediately as it is not |
| 854 | * suggested to do disable/reset or reset/disable at the same time. |
| 855 | */ |
| 856 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 857 | if (is_blsp_uart(msm_uport)) { |
| 858 | /* Disable UARTDM RX BAM Interface */ |
| 859 | data &= ~UARTDM_RX_BAM_ENABLE_BMSK; |
| 860 | } else { |
| 861 | data &= ~UARTDM_RX_DM_EN_BMSK; |
| 862 | } |
| 863 | |
Mayank Rana | 2d4d2f6 | 2011-07-21 17:31:31 +0530 | [diff] [blame] | 864 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 865 | |
| 866 | /* 300 is the minimum baud support by the driver */ |
| 867 | bps = uart_get_baud_rate(uport, termios, oldtermios, 200, 4000000); |
| 868 | |
| 869 | /* Temporary remapping 200 BAUD to 3.2 mbps */ |
| 870 | if (bps == 200) |
| 871 | bps = 3200000; |
| 872 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 873 | uport->uartclk = clk_get_rate(msm_uport->clk); |
| 874 | if (!uport->uartclk) |
| 875 | msm_hs_set_std_bps_locked(uport, bps); |
| 876 | else |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 877 | msm_hs_set_bps_locked(uport, bps); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 878 | |
| 879 | data = msm_hs_read(uport, UARTDM_MR2_ADDR); |
| 880 | data &= ~UARTDM_MR2_PARITY_MODE_BMSK; |
| 881 | /* set parity */ |
| 882 | if (PARENB == (c_cflag & PARENB)) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 883 | if (PARODD == (c_cflag & PARODD)) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 884 | data |= ODD_PARITY; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 885 | } else if (CMSPAR == (c_cflag & CMSPAR)) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 886 | data |= SPACE_PARITY; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 887 | } else { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 888 | data |= EVEN_PARITY; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 889 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 890 | } |
| 891 | |
| 892 | /* Set bits per char */ |
| 893 | data &= ~UARTDM_MR2_BITS_PER_CHAR_BMSK; |
| 894 | |
| 895 | switch (c_cflag & CSIZE) { |
| 896 | case CS5: |
| 897 | data |= FIVE_BPC; |
| 898 | break; |
| 899 | case CS6: |
| 900 | data |= SIX_BPC; |
| 901 | break; |
| 902 | case CS7: |
| 903 | data |= SEVEN_BPC; |
| 904 | break; |
| 905 | default: |
| 906 | data |= EIGHT_BPC; |
| 907 | break; |
| 908 | } |
| 909 | /* stop bits */ |
| 910 | if (c_cflag & CSTOPB) { |
| 911 | data |= STOP_BIT_TWO; |
| 912 | } else { |
| 913 | /* otherwise 1 stop bit */ |
| 914 | data |= STOP_BIT_ONE; |
| 915 | } |
| 916 | data |= UARTDM_MR2_ERROR_MODE_BMSK; |
| 917 | /* write parity/bits per char/stop bit configuration */ |
| 918 | msm_hs_write(uport, UARTDM_MR2_ADDR, data); |
| 919 | |
| 920 | /* Configure HW flow control */ |
| 921 | data = msm_hs_read(uport, UARTDM_MR1_ADDR); |
| 922 | |
| 923 | data &= ~(UARTDM_MR1_CTS_CTL_BMSK | UARTDM_MR1_RX_RDY_CTL_BMSK); |
| 924 | |
| 925 | if (c_cflag & CRTSCTS) { |
| 926 | data |= UARTDM_MR1_CTS_CTL_BMSK; |
| 927 | data |= UARTDM_MR1_RX_RDY_CTL_BMSK; |
| 928 | } |
| 929 | |
| 930 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); |
| 931 | |
| 932 | uport->ignore_status_mask = termios->c_iflag & INPCK; |
| 933 | uport->ignore_status_mask |= termios->c_iflag & IGNPAR; |
Mayank Rana | adc4156 | 2013-01-04 12:44:01 +0530 | [diff] [blame] | 934 | uport->ignore_status_mask |= termios->c_iflag & IGNBRK; |
Mayank Rana | 85aeee1 | 2012-11-27 14:49:46 +0530 | [diff] [blame] | 935 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 936 | uport->read_status_mask = (termios->c_cflag & CREAD); |
| 937 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 938 | |
| 939 | /* Set Transmit software time out */ |
| 940 | uart_update_timeout(uport, c_cflag, bps); |
| 941 | |
| 942 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); |
| 943 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX); |
| 944 | |
| 945 | if (msm_uport->rx.flush == FLUSH_NONE) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 946 | wake_lock(&msm_uport->rx.wake_lock); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 947 | msm_uport->rx.flush = FLUSH_IGNORE; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 948 | /* |
| 949 | * Before using dmov APIs make sure that |
| 950 | * previous writel are completed. Hence |
| 951 | * dsb requires here. |
| 952 | */ |
| 953 | mb(); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 954 | if (is_blsp_uart(msm_uport)) { |
| 955 | sps_disconnect(sps_pipe_handle); |
| 956 | msm_hs_spsconnect_rx(uport); |
| 957 | msm_serial_hs_rx_tlet((unsigned long) &rx->tlet); |
| 958 | } else { |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 959 | msm_uport->rx_discard_flush_issued = true; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 960 | /* do discard flush */ |
| 961 | msm_dmov_flush(msm_uport->dma_rx_channel, 0); |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 962 | pr_debug("%s(): wainting for flush completion.\n", |
| 963 | __func__); |
| 964 | ret = wait_event_timeout(msm_uport->rx.wait, |
| 965 | msm_uport->rx_discard_flush_issued == false, |
| 966 | RX_FLUSH_COMPLETE_TIMEOUT); |
| 967 | if (!ret) |
| 968 | pr_err("%s(): Discard flush pending.\n", |
| 969 | __func__); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 970 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 971 | } |
| 972 | |
| 973 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 974 | mb(); |
Mayank Rana | e672516 | 2012-08-22 17:44:25 +0530 | [diff] [blame] | 975 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 976 | } |
| 977 | |
| 978 | /* |
| 979 | * Standard API, Transmitter |
| 980 | * Any character in the transmit shift register is sent |
| 981 | */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 982 | unsigned int msm_hs_tx_empty(struct uart_port *uport) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 983 | { |
| 984 | unsigned int data; |
| 985 | unsigned int ret = 0; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 986 | |
| 987 | data = msm_hs_read(uport, UARTDM_SR_ADDR); |
| 988 | if (data & UARTDM_SR_TXEMT_BMSK) |
| 989 | ret = TIOCSER_TEMT; |
| 990 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 991 | return ret; |
| 992 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 993 | EXPORT_SYMBOL(msm_hs_tx_empty); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 994 | |
| 995 | /* |
| 996 | * Standard API, Stop transmitter. |
| 997 | * Any character in the transmit shift register is sent as |
| 998 | * well as the current data mover transfer . |
| 999 | */ |
| 1000 | static void msm_hs_stop_tx_locked(struct uart_port *uport) |
| 1001 | { |
| 1002 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1003 | |
| 1004 | msm_uport->tx.tx_ready_int_en = 0; |
| 1005 | } |
| 1006 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1007 | /* Disconnect BAM RX Endpoint Pipe Index from workqueue context*/ |
| 1008 | static void hsuart_disconnect_rx_endpoint_work(struct work_struct *w) |
| 1009 | { |
| 1010 | struct msm_hs_port *msm_uport = container_of(w, struct msm_hs_port, |
| 1011 | disconnect_rx_endpoint); |
| 1012 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 1013 | struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; |
| 1014 | |
| 1015 | sps_disconnect(sps_pipe_handle); |
| 1016 | wake_lock_timeout(&msm_uport->rx.wake_lock, HZ / 2); |
| 1017 | msm_uport->rx.flush = FLUSH_SHUTDOWN; |
| 1018 | wake_up(&msm_uport->rx.wait); |
| 1019 | } |
| 1020 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1021 | /* |
| 1022 | * Standard API, Stop receiver as soon as possible. |
| 1023 | * |
| 1024 | * Function immediately terminates the operation of the |
| 1025 | * channel receiver and any incoming characters are lost. None |
| 1026 | * of the receiver status bits are affected by this command and |
| 1027 | * characters that are already in the receive FIFO there. |
| 1028 | */ |
| 1029 | static void msm_hs_stop_rx_locked(struct uart_port *uport) |
| 1030 | { |
| 1031 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1032 | unsigned int data; |
| 1033 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1034 | /* disable dlink */ |
| 1035 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1036 | if (is_blsp_uart(msm_uport)) |
| 1037 | data &= ~UARTDM_RX_BAM_ENABLE_BMSK; |
| 1038 | else |
| 1039 | data &= ~UARTDM_RX_DM_EN_BMSK; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1040 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); |
| 1041 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1042 | /* calling DMOV or CLOCK API. Hence mb() */ |
| 1043 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1044 | /* Disable the receiver */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1045 | if (msm_uport->rx.flush == FLUSH_NONE) { |
| 1046 | wake_lock(&msm_uport->rx.wake_lock); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1047 | if (is_blsp_uart(msm_uport)) { |
| 1048 | msm_uport->rx.flush = FLUSH_STOP; |
| 1049 | /* workqueue for BAM rx endpoint disconnect */ |
| 1050 | queue_work(msm_uport->hsuart_wq, |
| 1051 | &msm_uport->disconnect_rx_endpoint); |
| 1052 | } else { |
| 1053 | /* do discard flush */ |
| 1054 | msm_dmov_flush(msm_uport->dma_rx_channel, 0); |
| 1055 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1056 | } |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1057 | if (!is_blsp_uart(msm_uport) && msm_uport->rx.flush != FLUSH_SHUTDOWN) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1058 | msm_uport->rx.flush = FLUSH_STOP; |
Saket Saurabh | 8b6b6af | 2013-02-19 16:04:16 +0530 | [diff] [blame] | 1059 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1060 | } |
| 1061 | |
| 1062 | /* Transmit the next chunk of data */ |
| 1063 | static void msm_hs_submit_tx_locked(struct uart_port *uport) |
| 1064 | { |
| 1065 | int left; |
| 1066 | int tx_count; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1067 | int aligned_tx_count; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1068 | dma_addr_t src_addr; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1069 | dma_addr_t aligned_src_addr; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1070 | u32 flags = SPS_IOVEC_FLAG_EOT; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1071 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1072 | struct msm_hs_tx *tx = &msm_uport->tx; |
| 1073 | struct circ_buf *tx_buf = &msm_uport->uport.state->xmit; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1074 | struct sps_pipe *sps_pipe_handle; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1075 | |
| 1076 | if (uart_circ_empty(tx_buf) || uport->state->port.tty->stopped) { |
| 1077 | msm_hs_stop_tx_locked(uport); |
| 1078 | return; |
| 1079 | } |
| 1080 | |
| 1081 | tx->dma_in_flight = 1; |
| 1082 | |
| 1083 | tx_count = uart_circ_chars_pending(tx_buf); |
| 1084 | |
| 1085 | if (UARTDM_TX_BUF_SIZE < tx_count) |
| 1086 | tx_count = UARTDM_TX_BUF_SIZE; |
| 1087 | |
| 1088 | left = UART_XMIT_SIZE - tx_buf->tail; |
| 1089 | |
| 1090 | if (tx_count > left) |
| 1091 | tx_count = left; |
| 1092 | |
| 1093 | src_addr = tx->dma_base + tx_buf->tail; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1094 | /* Mask the src_addr to align on a cache |
| 1095 | * and add those bytes to tx_count */ |
| 1096 | aligned_src_addr = src_addr & ~(dma_get_cache_alignment() - 1); |
| 1097 | aligned_tx_count = tx_count + src_addr - aligned_src_addr; |
| 1098 | |
| 1099 | dma_sync_single_for_device(uport->dev, aligned_src_addr, |
| 1100 | aligned_tx_count, DMA_TO_DEVICE); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1101 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1102 | if (is_blsp_uart(msm_uport)) { |
| 1103 | /* Issue TX BAM Start IFC command */ |
| 1104 | msm_hs_write(uport, UARTDM_CR_ADDR, START_TX_BAM_IFC); |
| 1105 | } else { |
| 1106 | tx->command_ptr->num_rows = |
| 1107 | (((tx_count + 15) >> 4) << 16) | |
| 1108 | ((tx_count + 15) >> 4); |
| 1109 | tx->command_ptr->src_row_addr = src_addr; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1110 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1111 | dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr, |
| 1112 | sizeof(dmov_box), DMA_TO_DEVICE); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1113 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1114 | *tx->command_ptr_ptr = CMD_PTR_LP | |
| 1115 | DMOV_CMD_ADDR(tx->mapped_cmd_ptr); |
| 1116 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1117 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1118 | /* Save tx_count to use in Callback */ |
| 1119 | tx->tx_count = tx_count; |
| 1120 | msm_hs_write(uport, UARTDM_NCF_TX_ADDR, tx_count); |
| 1121 | |
| 1122 | /* Disable the tx_ready interrupt */ |
| 1123 | msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK; |
| 1124 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1125 | /* Calling next DMOV API. Hence mb() here. */ |
| 1126 | mb(); |
| 1127 | |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 1128 | msm_uport->tx.flush = FLUSH_NONE; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1129 | |
| 1130 | if (is_blsp_uart(msm_uport)) { |
| 1131 | sps_pipe_handle = tx->cons.pipe_handle; |
| 1132 | /* Queue transfer request to SPS */ |
| 1133 | sps_transfer_one(sps_pipe_handle, src_addr, tx_count, |
| 1134 | msm_uport, flags); |
| 1135 | } else { |
| 1136 | dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr, |
| 1137 | sizeof(u32), DMA_TO_DEVICE); |
| 1138 | |
| 1139 | msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer); |
| 1140 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1141 | } |
| 1142 | |
| 1143 | /* Start to receive the next chunk of data */ |
| 1144 | static void msm_hs_start_rx_locked(struct uart_port *uport) |
| 1145 | { |
| 1146 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1147 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 1148 | struct sps_pipe *sps_pipe_handle; |
| 1149 | u32 flags = SPS_IOVEC_FLAG_EOT; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1150 | unsigned int buffer_pending = msm_uport->rx.buffer_pending; |
Mayank Rana | 2d4d2f6 | 2011-07-21 17:31:31 +0530 | [diff] [blame] | 1151 | unsigned int data; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1152 | |
| 1153 | msm_uport->rx.buffer_pending = 0; |
| 1154 | if (buffer_pending && hs_serial_debug_mask) |
| 1155 | printk(KERN_ERR "Error: rx started in buffer state = %x", |
| 1156 | buffer_pending); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1157 | |
| 1158 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT); |
| 1159 | msm_hs_write(uport, UARTDM_DMRX_ADDR, UARTDM_RX_BUF_SIZE); |
| 1160 | msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_ENABLE); |
| 1161 | msm_uport->imr_reg |= UARTDM_ISR_RXLEV_BMSK; |
Mayank Rana | 2d4d2f6 | 2011-07-21 17:31:31 +0530 | [diff] [blame] | 1162 | |
| 1163 | /* |
| 1164 | * Enable UARTDM Rx Interface as previously it has been |
| 1165 | * disable in set_termios before configuring baud rate. |
| 1166 | */ |
| 1167 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1168 | if (is_blsp_uart(msm_uport)) { |
| 1169 | /* Enable UARTDM Rx BAM Interface */ |
| 1170 | data |= UARTDM_RX_BAM_ENABLE_BMSK; |
| 1171 | } else { |
| 1172 | data |= UARTDM_RX_DM_EN_BMSK; |
| 1173 | } |
| 1174 | |
Mayank Rana | 2d4d2f6 | 2011-07-21 17:31:31 +0530 | [diff] [blame] | 1175 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1176 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1177 | /* Calling next DMOV API. Hence mb() here. */ |
| 1178 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1179 | |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1180 | if (is_blsp_uart(msm_uport)) { |
| 1181 | /* |
| 1182 | * RX-transfer will be automatically re-activated |
| 1183 | * after last data of previous transfer was read. |
| 1184 | */ |
| 1185 | data = (RX_STALE_AUTO_RE_EN | RX_TRANS_AUTO_RE_ACTIVATE | |
| 1186 | RX_DMRX_CYCLIC_EN); |
| 1187 | msm_hs_write(uport, UARTDM_RX_TRANS_CTRL_ADDR, data); |
| 1188 | /* Issue RX BAM Start IFC command */ |
| 1189 | msm_hs_write(uport, UARTDM_CR_ADDR, START_RX_BAM_IFC); |
| 1190 | mb(); |
| 1191 | } |
| 1192 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1193 | msm_uport->rx.flush = FLUSH_NONE; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1194 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1195 | if (is_blsp_uart(msm_uport)) { |
| 1196 | sps_pipe_handle = rx->prod.pipe_handle; |
| 1197 | /* Queue transfer request to SPS */ |
| 1198 | sps_transfer_one(sps_pipe_handle, rx->rbuffer, |
| 1199 | UARTDM_RX_BUF_SIZE, msm_uport, flags); |
| 1200 | } else { |
| 1201 | msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel, |
| 1202 | &msm_uport->rx.xfer); |
| 1203 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1204 | } |
| 1205 | |
| 1206 | static void flip_insert_work(struct work_struct *work) |
| 1207 | { |
| 1208 | unsigned long flags; |
| 1209 | int retval; |
| 1210 | struct msm_hs_port *msm_uport = |
| 1211 | container_of(work, struct msm_hs_port, |
| 1212 | rx.flip_insert_work.work); |
| 1213 | struct tty_struct *tty = msm_uport->uport.state->port.tty; |
| 1214 | |
| 1215 | spin_lock_irqsave(&msm_uport->uport.lock, flags); |
| 1216 | if (msm_uport->rx.buffer_pending == NONE_PENDING) { |
| 1217 | if (hs_serial_debug_mask) |
| 1218 | printk(KERN_ERR "Error: No buffer pending in %s", |
| 1219 | __func__); |
| 1220 | return; |
| 1221 | } |
| 1222 | if (msm_uport->rx.buffer_pending & FIFO_OVERRUN) { |
| 1223 | retval = tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
| 1224 | if (retval) |
| 1225 | msm_uport->rx.buffer_pending &= ~FIFO_OVERRUN; |
| 1226 | } |
| 1227 | if (msm_uport->rx.buffer_pending & PARITY_ERROR) { |
| 1228 | retval = tty_insert_flip_char(tty, 0, TTY_PARITY); |
| 1229 | if (retval) |
| 1230 | msm_uport->rx.buffer_pending &= ~PARITY_ERROR; |
| 1231 | } |
| 1232 | if (msm_uport->rx.buffer_pending & CHARS_NORMAL) { |
| 1233 | int rx_count, rx_offset; |
| 1234 | rx_count = (msm_uport->rx.buffer_pending & 0xFFFF0000) >> 16; |
| 1235 | rx_offset = (msm_uport->rx.buffer_pending & 0xFFD0) >> 5; |
| 1236 | retval = tty_insert_flip_string(tty, msm_uport->rx.buffer + |
| 1237 | rx_offset, rx_count); |
| 1238 | msm_uport->rx.buffer_pending &= (FIFO_OVERRUN | |
| 1239 | PARITY_ERROR); |
| 1240 | if (retval != rx_count) |
| 1241 | msm_uport->rx.buffer_pending |= CHARS_NORMAL | |
| 1242 | retval << 8 | (rx_count - retval) << 16; |
| 1243 | } |
| 1244 | if (msm_uport->rx.buffer_pending) |
| 1245 | schedule_delayed_work(&msm_uport->rx.flip_insert_work, |
| 1246 | msecs_to_jiffies(RETRY_TIMEOUT)); |
| 1247 | else |
| 1248 | if ((msm_uport->clk_state == MSM_HS_CLK_ON) && |
| 1249 | (msm_uport->rx.flush <= FLUSH_IGNORE)) { |
| 1250 | if (hs_serial_debug_mask) |
| 1251 | printk(KERN_WARNING |
| 1252 | "msm_serial_hs: " |
| 1253 | "Pending buffers cleared. " |
| 1254 | "Restarting\n"); |
| 1255 | msm_hs_start_rx_locked(&msm_uport->uport); |
| 1256 | } |
| 1257 | spin_unlock_irqrestore(&msm_uport->uport.lock, flags); |
| 1258 | tty_flip_buffer_push(tty); |
| 1259 | } |
| 1260 | |
| 1261 | static void msm_serial_hs_rx_tlet(unsigned long tlet_ptr) |
| 1262 | { |
| 1263 | int retval; |
| 1264 | int rx_count; |
| 1265 | unsigned long status; |
| 1266 | unsigned long flags; |
| 1267 | unsigned int error_f = 0; |
| 1268 | struct uart_port *uport; |
| 1269 | struct msm_hs_port *msm_uport; |
| 1270 | unsigned int flush; |
| 1271 | struct tty_struct *tty; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1272 | struct sps_event_notify *notify; |
| 1273 | struct msm_hs_rx *rx; |
| 1274 | struct sps_pipe *sps_pipe_handle; |
| 1275 | u32 sps_flags = SPS_IOVEC_FLAG_EOT; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1276 | |
| 1277 | msm_uport = container_of((struct tasklet_struct *)tlet_ptr, |
| 1278 | struct msm_hs_port, rx.tlet); |
| 1279 | uport = &msm_uport->uport; |
| 1280 | tty = uport->state->port.tty; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1281 | notify = &msm_uport->notify; |
| 1282 | rx = &msm_uport->rx; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1283 | |
| 1284 | status = msm_hs_read(uport, UARTDM_SR_ADDR); |
| 1285 | |
| 1286 | spin_lock_irqsave(&uport->lock, flags); |
| 1287 | |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1288 | if (!is_blsp_uart(msm_uport)) |
| 1289 | msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1290 | |
| 1291 | /* overflow is not connect to data in a FIFO */ |
| 1292 | if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) && |
| 1293 | (uport->read_status_mask & CREAD))) { |
| 1294 | retval = tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
| 1295 | if (!retval) |
| 1296 | msm_uport->rx.buffer_pending |= TTY_OVERRUN; |
| 1297 | uport->icount.buf_overrun++; |
| 1298 | error_f = 1; |
| 1299 | } |
| 1300 | |
| 1301 | if (!(uport->ignore_status_mask & INPCK)) |
| 1302 | status = status & ~(UARTDM_SR_PAR_FRAME_BMSK); |
| 1303 | |
| 1304 | if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) { |
| 1305 | /* Can not tell difference between parity & frame error */ |
Mayank Rana | 85aeee1 | 2012-11-27 14:49:46 +0530 | [diff] [blame] | 1306 | if (hs_serial_debug_mask) |
| 1307 | printk(KERN_WARNING "msm_serial_hs: parity error\n"); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1308 | uport->icount.parity++; |
| 1309 | error_f = 1; |
Mayank Rana | 85aeee1 | 2012-11-27 14:49:46 +0530 | [diff] [blame] | 1310 | if (!(uport->ignore_status_mask & IGNPAR)) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1311 | retval = tty_insert_flip_char(tty, 0, TTY_PARITY); |
| 1312 | if (!retval) |
| 1313 | msm_uport->rx.buffer_pending |= TTY_PARITY; |
| 1314 | } |
| 1315 | } |
| 1316 | |
Mayank Rana | 85aeee1 | 2012-11-27 14:49:46 +0530 | [diff] [blame] | 1317 | if (unlikely(status & UARTDM_SR_RX_BREAK_BMSK)) { |
| 1318 | if (hs_serial_debug_mask) |
| 1319 | printk(KERN_WARNING "msm_serial_hs: Rx break\n"); |
| 1320 | uport->icount.brk++; |
| 1321 | error_f = 1; |
| 1322 | if (!(uport->ignore_status_mask & IGNBRK)) { |
| 1323 | retval = tty_insert_flip_char(tty, 0, TTY_BREAK); |
| 1324 | if (!retval) |
| 1325 | msm_uport->rx.buffer_pending |= TTY_BREAK; |
| 1326 | } |
| 1327 | } |
| 1328 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1329 | if (error_f) |
| 1330 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS); |
| 1331 | |
| 1332 | if (msm_uport->clk_req_off_state == CLK_REQ_OFF_FLUSH_ISSUED) |
| 1333 | msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_FLUSHED; |
| 1334 | flush = msm_uport->rx.flush; |
| 1335 | if (flush == FLUSH_IGNORE) |
| 1336 | if (!msm_uport->rx.buffer_pending) |
| 1337 | msm_hs_start_rx_locked(uport); |
| 1338 | |
| 1339 | if (flush == FLUSH_STOP) { |
| 1340 | msm_uport->rx.flush = FLUSH_SHUTDOWN; |
| 1341 | wake_up(&msm_uport->rx.wait); |
| 1342 | } |
| 1343 | if (flush >= FLUSH_DATA_INVALID) |
| 1344 | goto out; |
| 1345 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1346 | if (is_blsp_uart(msm_uport)) { |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1347 | rx_count = msm_uport->rx_count_callback; |
| 1348 | } else { |
| 1349 | rx_count = msm_hs_read(uport, UARTDM_RX_TOTAL_SNAP_ADDR); |
| 1350 | /* order the read of rx.buffer */ |
| 1351 | rmb(); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1352 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1353 | |
| 1354 | if (0 != (uport->read_status_mask & CREAD)) { |
| 1355 | retval = tty_insert_flip_string(tty, msm_uport->rx.buffer, |
| 1356 | rx_count); |
| 1357 | if (retval != rx_count) { |
| 1358 | msm_uport->rx.buffer_pending |= CHARS_NORMAL | |
| 1359 | retval << 5 | (rx_count - retval) << 16; |
| 1360 | } |
| 1361 | } |
| 1362 | |
| 1363 | /* order the read of rx.buffer and the start of next rx xfer */ |
| 1364 | wmb(); |
| 1365 | |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1366 | if (!msm_uport->rx.buffer_pending) { |
| 1367 | if (is_blsp_uart(msm_uport)) { |
| 1368 | msm_uport->rx.flush = FLUSH_NONE; |
| 1369 | sps_pipe_handle = rx->prod.pipe_handle; |
| 1370 | /* Queue transfer request to SPS */ |
| 1371 | sps_transfer_one(sps_pipe_handle, rx->rbuffer, |
| 1372 | UARTDM_RX_BUF_SIZE, msm_uport, sps_flags); |
| 1373 | } else { |
| 1374 | msm_hs_start_rx_locked(uport); |
| 1375 | } |
| 1376 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1377 | out: |
| 1378 | if (msm_uport->rx.buffer_pending) { |
| 1379 | if (hs_serial_debug_mask) |
| 1380 | printk(KERN_WARNING |
| 1381 | "msm_serial_hs: " |
| 1382 | "tty buffer exhausted. " |
| 1383 | "Stalling\n"); |
| 1384 | schedule_delayed_work(&msm_uport->rx.flip_insert_work |
| 1385 | , msecs_to_jiffies(RETRY_TIMEOUT)); |
| 1386 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1387 | /* release wakelock in 500ms, not immediately, because higher layers |
| 1388 | * don't always take wakelocks when they should */ |
| 1389 | wake_lock_timeout(&msm_uport->rx.wake_lock, HZ / 2); |
| 1390 | /* tty_flip_buffer_push() might call msm_hs_start(), so unlock */ |
| 1391 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1392 | if (flush < FLUSH_DATA_INVALID) |
| 1393 | tty_flip_buffer_push(tty); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1394 | } |
| 1395 | |
| 1396 | /* Enable the transmitter Interrupt */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1397 | static void msm_hs_start_tx_locked(struct uart_port *uport ) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1398 | { |
| 1399 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1400 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1401 | if (msm_uport->tx.tx_ready_int_en == 0) { |
| 1402 | msm_uport->tx.tx_ready_int_en = 1; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1403 | if (msm_uport->tx.dma_in_flight == 0) |
| 1404 | msm_hs_submit_tx_locked(uport); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1405 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1406 | } |
| 1407 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1408 | /** |
| 1409 | * Callback notification from SPS driver |
| 1410 | * |
| 1411 | * This callback function gets triggered called from |
| 1412 | * SPS driver when requested SPS data transfer is |
| 1413 | * completed. |
| 1414 | * |
| 1415 | */ |
| 1416 | |
| 1417 | static void msm_hs_sps_tx_callback(struct sps_event_notify *notify) |
| 1418 | { |
| 1419 | struct msm_hs_port *msm_uport = |
| 1420 | (struct msm_hs_port *) |
| 1421 | ((struct sps_event_notify *)notify)->user; |
| 1422 | |
| 1423 | msm_uport->notify = *notify; |
| 1424 | pr_debug("%s: sps ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x\n", |
| 1425 | __func__, notify->event_id, |
| 1426 | notify->data.transfer.iovec.addr, |
| 1427 | notify->data.transfer.iovec.size, |
| 1428 | notify->data.transfer.iovec.flags); |
| 1429 | |
| 1430 | tasklet_schedule(&msm_uport->tx.tlet); |
| 1431 | } |
| 1432 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1433 | /* |
| 1434 | * This routine is called when we are done with a DMA transfer |
| 1435 | * |
| 1436 | * This routine is registered with Data mover when we set |
| 1437 | * up a Data Mover transfer. It is called from Data mover ISR |
| 1438 | * when the DMA transfer is done. |
| 1439 | */ |
| 1440 | static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr, |
| 1441 | unsigned int result, |
| 1442 | struct msm_dmov_errdata *err) |
| 1443 | { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1444 | struct msm_hs_port *msm_uport; |
| 1445 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1446 | msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer); |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 1447 | if (msm_uport->tx.flush == FLUSH_STOP) |
| 1448 | /* DMA FLUSH unsuccesfful */ |
| 1449 | WARN_ON(!(result & DMOV_RSLT_FLUSH)); |
| 1450 | else |
| 1451 | /* DMA did not finish properly */ |
| 1452 | WARN_ON(!(result & DMOV_RSLT_DONE)); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1453 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1454 | tasklet_schedule(&msm_uport->tx.tlet); |
| 1455 | } |
| 1456 | |
| 1457 | static void msm_serial_hs_tx_tlet(unsigned long tlet_ptr) |
| 1458 | { |
| 1459 | unsigned long flags; |
| 1460 | struct msm_hs_port *msm_uport = container_of((struct tasklet_struct *) |
| 1461 | tlet_ptr, struct msm_hs_port, tx.tlet); |
| 1462 | |
| 1463 | spin_lock_irqsave(&(msm_uport->uport.lock), flags); |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 1464 | if (msm_uport->tx.flush == FLUSH_STOP) { |
| 1465 | msm_uport->tx.flush = FLUSH_SHUTDOWN; |
| 1466 | wake_up(&msm_uport->tx.wait); |
| 1467 | spin_unlock_irqrestore(&(msm_uport->uport.lock), flags); |
| 1468 | return; |
| 1469 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1470 | |
| 1471 | msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1472 | msm_hs_write(&(msm_uport->uport), UARTDM_IMR_ADDR, msm_uport->imr_reg); |
| 1473 | /* Calling clk API. Hence mb() requires. */ |
| 1474 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1475 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1476 | spin_unlock_irqrestore(&(msm_uport->uport.lock), flags); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1477 | } |
| 1478 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1479 | /** |
| 1480 | * Callback notification from SPS driver |
| 1481 | * |
| 1482 | * This callback function gets triggered called from |
| 1483 | * SPS driver when requested SPS data transfer is |
| 1484 | * completed. |
| 1485 | * |
| 1486 | */ |
| 1487 | |
| 1488 | static void msm_hs_sps_rx_callback(struct sps_event_notify *notify) |
| 1489 | { |
| 1490 | |
| 1491 | struct msm_hs_port *msm_uport = |
| 1492 | (struct msm_hs_port *) |
| 1493 | ((struct sps_event_notify *)notify)->user; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1494 | struct uart_port *uport; |
| 1495 | unsigned long flags; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1496 | |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1497 | uport = &(msm_uport->uport); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1498 | msm_uport->notify = *notify; |
| 1499 | pr_debug("%s: sps ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x\n", |
| 1500 | __func__, notify->event_id, |
| 1501 | notify->data.transfer.iovec.addr, |
| 1502 | notify->data.transfer.iovec.size, |
| 1503 | notify->data.transfer.iovec.flags); |
| 1504 | |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1505 | if (msm_uport->rx.flush == FLUSH_NONE) { |
| 1506 | spin_lock_irqsave(&uport->lock, flags); |
| 1507 | msm_uport->rx_count_callback = notify->data.transfer.iovec.size; |
| 1508 | spin_unlock_irqrestore(&uport->lock, flags); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1509 | tasklet_schedule(&msm_uport->rx.tlet); |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1510 | } |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1511 | } |
| 1512 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1513 | /* |
| 1514 | * This routine is called when we are done with a DMA transfer or the |
| 1515 | * a flush has been sent to the data mover driver. |
| 1516 | * |
| 1517 | * This routine is registered with Data mover when we set up a Data Mover |
| 1518 | * transfer. It is called from Data mover ISR when the DMA transfer is done. |
| 1519 | */ |
| 1520 | static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr, |
| 1521 | unsigned int result, |
| 1522 | struct msm_dmov_errdata *err) |
| 1523 | { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1524 | struct msm_hs_port *msm_uport; |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 1525 | struct uart_port *uport; |
| 1526 | unsigned long flags; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1527 | |
| 1528 | msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer); |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 1529 | uport = &(msm_uport->uport); |
| 1530 | |
| 1531 | pr_debug("%s(): called result:%x\n", __func__, result); |
| 1532 | if (!(result & DMOV_RSLT_ERROR)) { |
| 1533 | if (result & DMOV_RSLT_FLUSH) { |
| 1534 | if (msm_uport->rx_discard_flush_issued) { |
| 1535 | spin_lock_irqsave(&uport->lock, flags); |
| 1536 | msm_uport->rx_discard_flush_issued = false; |
| 1537 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1538 | wake_up(&msm_uport->rx.wait); |
| 1539 | } |
| 1540 | } |
| 1541 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1542 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1543 | tasklet_schedule(&msm_uport->rx.tlet); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1544 | } |
| 1545 | |
| 1546 | /* |
| 1547 | * Standard API, Current states of modem control inputs |
| 1548 | * |
| 1549 | * Since CTS can be handled entirely by HARDWARE we always |
| 1550 | * indicate clear to send and count on the TX FIFO to block when |
| 1551 | * it fills up. |
| 1552 | * |
| 1553 | * - TIOCM_DCD |
| 1554 | * - TIOCM_CTS |
| 1555 | * - TIOCM_DSR |
| 1556 | * - TIOCM_RI |
| 1557 | * (Unsupported) DCD and DSR will return them high. RI will return low. |
| 1558 | */ |
| 1559 | static unsigned int msm_hs_get_mctrl_locked(struct uart_port *uport) |
| 1560 | { |
| 1561 | return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS; |
| 1562 | } |
| 1563 | |
| 1564 | /* |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1565 | * Standard API, Set or clear RFR_signal |
| 1566 | * |
| 1567 | * Set RFR high, (Indicate we are not ready for data), we disable auto |
| 1568 | * ready for receiving and then set RFR_N high. To set RFR to low we just turn |
| 1569 | * back auto ready for receiving and it should lower RFR signal |
| 1570 | * when hardware is ready |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1571 | */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1572 | void msm_hs_set_mctrl_locked(struct uart_port *uport, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1573 | unsigned int mctrl) |
| 1574 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1575 | unsigned int set_rts; |
| 1576 | unsigned int data; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1577 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1578 | /* RTS is active low */ |
| 1579 | set_rts = TIOCM_RTS & mctrl ? 0 : 1; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1580 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1581 | data = msm_hs_read(uport, UARTDM_MR1_ADDR); |
| 1582 | if (set_rts) { |
| 1583 | /*disable auto ready-for-receiving */ |
| 1584 | data &= ~UARTDM_MR1_RX_RDY_CTL_BMSK; |
| 1585 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); |
| 1586 | /* set RFR_N to high */ |
| 1587 | msm_hs_write(uport, UARTDM_CR_ADDR, RFR_HIGH); |
| 1588 | } else { |
| 1589 | /* Enable auto ready-for-receiving */ |
| 1590 | data |= UARTDM_MR1_RX_RDY_CTL_BMSK; |
| 1591 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); |
| 1592 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1593 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1594 | } |
| 1595 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1596 | void msm_hs_set_mctrl(struct uart_port *uport, |
| 1597 | unsigned int mctrl) |
| 1598 | { |
| 1599 | unsigned long flags; |
| 1600 | |
| 1601 | spin_lock_irqsave(&uport->lock, flags); |
| 1602 | msm_hs_set_mctrl_locked(uport, mctrl); |
| 1603 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1604 | } |
| 1605 | EXPORT_SYMBOL(msm_hs_set_mctrl); |
| 1606 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1607 | /* Standard API, Enable modem status (CTS) interrupt */ |
| 1608 | static void msm_hs_enable_ms_locked(struct uart_port *uport) |
| 1609 | { |
| 1610 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1611 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1612 | /* Enable DELTA_CTS Interrupt */ |
| 1613 | msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK; |
| 1614 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1615 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1616 | |
| 1617 | } |
| 1618 | |
Saket Saurabh | ce39410 | 2012-10-29 19:51:28 +0530 | [diff] [blame] | 1619 | static void msm_hs_flush_buffer(struct uart_port *uport) |
| 1620 | { |
| 1621 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1622 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1623 | if (msm_uport->tx.dma_in_flight) |
| 1624 | msm_uport->tty_flush_receive = true; |
Saket Saurabh | ce39410 | 2012-10-29 19:51:28 +0530 | [diff] [blame] | 1625 | } |
| 1626 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1627 | /* |
| 1628 | * Standard API, Break Signal |
| 1629 | * |
| 1630 | * Control the transmission of a break signal. ctl eq 0 => break |
| 1631 | * signal terminate ctl ne 0 => start break signal |
| 1632 | */ |
| 1633 | static void msm_hs_break_ctl(struct uart_port *uport, int ctl) |
| 1634 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1635 | unsigned long flags; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1636 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1637 | spin_lock_irqsave(&uport->lock, flags); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1638 | msm_hs_write(uport, UARTDM_CR_ADDR, ctl ? START_BREAK : STOP_BREAK); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1639 | mb(); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1640 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1641 | } |
| 1642 | |
| 1643 | static void msm_hs_config_port(struct uart_port *uport, int cfg_flags) |
| 1644 | { |
| 1645 | unsigned long flags; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1646 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1647 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1648 | if (cfg_flags & UART_CONFIG_TYPE) { |
| 1649 | uport->type = PORT_MSM; |
| 1650 | msm_hs_request_port(uport); |
| 1651 | } |
Mayank Rana | bbfd269 | 2011-09-20 08:51:17 +0530 | [diff] [blame] | 1652 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1653 | if (is_gsbi_uart(msm_uport)) { |
Mayank Rana | 00b6bff | 2011-08-17 08:33:42 +0530 | [diff] [blame] | 1654 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1655 | clk_prepare_enable(msm_uport->pclk); |
| 1656 | spin_lock_irqsave(&uport->lock, flags); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1657 | iowrite32(GSBI_PROTOCOL_UART, msm_uport->mapped_gsbi + |
| 1658 | GSBI_CONTROL_ADDR); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1659 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | 00b6bff | 2011-08-17 08:33:42 +0530 | [diff] [blame] | 1660 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1661 | clk_disable_unprepare(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1662 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1663 | } |
| 1664 | |
| 1665 | /* Handle CTS changes (Called from interrupt handler) */ |
Mayank Rana | ee815f3 | 2011-12-08 09:06:09 +0530 | [diff] [blame] | 1666 | static void msm_hs_handle_delta_cts_locked(struct uart_port *uport) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1667 | { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1668 | /* clear interrupt */ |
| 1669 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1670 | /* Calling CLOCK API. Hence mb() requires here. */ |
| 1671 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1672 | uport->icount.cts++; |
| 1673 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1674 | /* clear the IOCTL TIOCMIWAIT if called */ |
| 1675 | wake_up_interruptible(&uport->state->port.delta_msr_wait); |
| 1676 | } |
| 1677 | |
| 1678 | /* check if the TX path is flushed, and if so clock off |
| 1679 | * returns 0 did not clock off, need to retry (still sending final byte) |
| 1680 | * -1 did not clock off, do not retry |
| 1681 | * 1 if we clocked off |
| 1682 | */ |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1683 | static int msm_hs_check_clock_off(struct uart_port *uport) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1684 | { |
| 1685 | unsigned long sr_status; |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1686 | unsigned long flags; |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 1687 | int ret; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1688 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1689 | struct circ_buf *tx_buf = &uport->state->xmit; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1690 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 1691 | struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1692 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1693 | mutex_lock(&msm_uport->clk_mutex); |
| 1694 | spin_lock_irqsave(&uport->lock, flags); |
| 1695 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1696 | /* Cancel if tx tty buffer is not empty, dma is in flight, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1697 | * or tx fifo is not empty */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1698 | if (msm_uport->clk_state != MSM_HS_CLK_REQUEST_OFF || |
| 1699 | !uart_circ_empty(tx_buf) || msm_uport->tx.dma_in_flight || |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1700 | msm_uport->imr_reg & UARTDM_ISR_TXLEV_BMSK) { |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1701 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1702 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1703 | return -1; |
| 1704 | } |
| 1705 | |
| 1706 | /* Make sure the uart is finished with the last byte */ |
| 1707 | sr_status = msm_hs_read(uport, UARTDM_SR_ADDR); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1708 | if (!(sr_status & UARTDM_SR_TXEMT_BMSK)) { |
| 1709 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1710 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1711 | return 0; /* retry */ |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1712 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1713 | |
| 1714 | /* Make sure forced RXSTALE flush complete */ |
| 1715 | switch (msm_uport->clk_req_off_state) { |
| 1716 | case CLK_REQ_OFF_START: |
| 1717 | msm_uport->clk_req_off_state = CLK_REQ_OFF_RXSTALE_ISSUED; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1718 | |
| 1719 | if (!is_blsp_uart(msm_uport)) { |
| 1720 | msm_hs_write(uport, UARTDM_CR_ADDR, FORCE_STALE_EVENT); |
| 1721 | /* |
| 1722 | * Before returning make sure that device writel |
| 1723 | * completed. Hence mb() requires here. |
| 1724 | */ |
| 1725 | mb(); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1726 | } |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1727 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1728 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1729 | return 0; /* RXSTALE flush not complete - retry */ |
| 1730 | case CLK_REQ_OFF_RXSTALE_ISSUED: |
| 1731 | case CLK_REQ_OFF_FLUSH_ISSUED: |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1732 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1733 | if (is_blsp_uart(msm_uport)) { |
| 1734 | msm_uport->clk_req_off_state = |
| 1735 | CLK_REQ_OFF_RXSTALE_FLUSHED; |
| 1736 | sps_disconnect(sps_pipe_handle); |
| 1737 | } |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1738 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1739 | return 0; /* RXSTALE flush not complete - retry */ |
| 1740 | case CLK_REQ_OFF_RXSTALE_FLUSHED: |
| 1741 | break; /* continue */ |
| 1742 | } |
| 1743 | |
| 1744 | if (msm_uport->rx.flush != FLUSH_SHUTDOWN) { |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 1745 | if (msm_uport->rx.flush == FLUSH_NONE) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1746 | msm_hs_stop_rx_locked(uport); |
Saket Saurabh | 467614f | 2013-03-16 17:24:12 +0530 | [diff] [blame] | 1747 | if (!is_blsp_uart(msm_uport)) |
| 1748 | msm_uport->rx_discard_flush_issued = true; |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 1749 | } |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1750 | |
| 1751 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | 9c8bda9 | 2013-02-28 11:58:04 +0530 | [diff] [blame] | 1752 | if (msm_uport->rx_discard_flush_issued) { |
| 1753 | pr_debug("%s(): wainting for flush completion.\n", |
| 1754 | __func__); |
| 1755 | ret = wait_event_timeout(msm_uport->rx.wait, |
| 1756 | msm_uport->rx_discard_flush_issued == false, |
| 1757 | RX_FLUSH_COMPLETE_TIMEOUT); |
| 1758 | if (!ret) |
| 1759 | pr_err("%s(): Flush complete pending.\n", |
| 1760 | __func__); |
| 1761 | } |
| 1762 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1763 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1764 | return 0; /* come back later to really clock off */ |
| 1765 | } |
| 1766 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1767 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1768 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1769 | /* we really want to clock off */ |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1770 | clk_disable_unprepare(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1771 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1772 | clk_disable_unprepare(msm_uport->pclk); |
| 1773 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1774 | msm_uport->clk_state = MSM_HS_CLK_OFF; |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1775 | |
| 1776 | spin_lock_irqsave(&uport->lock, flags); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1777 | if (use_low_power_wakeup(msm_uport)) { |
| 1778 | msm_uport->wakeup.ignore = 1; |
| 1779 | enable_irq(msm_uport->wakeup.irq); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1780 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1781 | wake_unlock(&msm_uport->dma_wake_lock); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1782 | |
| 1783 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 1784 | |
| 1785 | /* Reset PNOC Bus Scaling */ |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 1786 | msm_hs_bus_voting(msm_uport, BUS_RESET); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1787 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 1788 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1789 | return 1; |
| 1790 | } |
| 1791 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1792 | static void hsuart_clock_off_work(struct work_struct *w) |
| 1793 | { |
| 1794 | struct msm_hs_port *msm_uport = container_of(w, struct msm_hs_port, |
| 1795 | clock_off_w); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1796 | struct uart_port *uport = &msm_uport->uport; |
| 1797 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1798 | if (!msm_hs_check_clock_off(uport)) { |
| 1799 | hrtimer_start(&msm_uport->clk_off_timer, |
| 1800 | msm_uport->clk_off_delay, |
| 1801 | HRTIMER_MODE_REL); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1802 | } |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1803 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1804 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1805 | static enum hrtimer_restart msm_hs_clk_off_retry(struct hrtimer *timer) |
| 1806 | { |
| 1807 | struct msm_hs_port *msm_uport = container_of(timer, struct msm_hs_port, |
| 1808 | clk_off_timer); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1809 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1810 | queue_work(msm_uport->hsuart_wq, &msm_uport->clock_off_w); |
| 1811 | return HRTIMER_NORESTART; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1812 | } |
| 1813 | |
| 1814 | static irqreturn_t msm_hs_isr(int irq, void *dev) |
| 1815 | { |
| 1816 | unsigned long flags; |
| 1817 | unsigned long isr_status; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1818 | struct msm_hs_port *msm_uport = (struct msm_hs_port *)dev; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1819 | struct uart_port *uport = &msm_uport->uport; |
| 1820 | struct circ_buf *tx_buf = &uport->state->xmit; |
| 1821 | struct msm_hs_tx *tx = &msm_uport->tx; |
| 1822 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 1823 | |
| 1824 | spin_lock_irqsave(&uport->lock, flags); |
| 1825 | |
| 1826 | isr_status = msm_hs_read(uport, UARTDM_MISR_ADDR); |
| 1827 | |
| 1828 | /* Uart RX starting */ |
| 1829 | if (isr_status & UARTDM_ISR_RXLEV_BMSK) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1830 | wake_lock(&rx->wake_lock); /* hold wakelock while rx dma */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1831 | msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK; |
| 1832 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1833 | /* Complete device write for IMR. Hence mb() requires. */ |
| 1834 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1835 | } |
| 1836 | /* Stale rx interrupt */ |
| 1837 | if (isr_status & UARTDM_ISR_RXSTALE_BMSK) { |
| 1838 | msm_hs_write(uport, UARTDM_CR_ADDR, STALE_EVENT_DISABLE); |
| 1839 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1840 | /* |
| 1841 | * Complete device write before calling DMOV API. Hence |
| 1842 | * mb() requires here. |
| 1843 | */ |
| 1844 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1845 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1846 | if (msm_uport->clk_req_off_state == |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1847 | CLK_REQ_OFF_RXSTALE_ISSUED) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1848 | msm_uport->clk_req_off_state = |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1849 | CLK_REQ_OFF_FLUSH_ISSUED; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1850 | |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1851 | if (!is_blsp_uart(msm_uport) && (rx->flush == FLUSH_NONE)) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1852 | rx->flush = FLUSH_DATA_READY; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1853 | msm_dmov_flush(msm_uport->dma_rx_channel, 1); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1854 | } |
| 1855 | } |
| 1856 | /* tx ready interrupt */ |
| 1857 | if (isr_status & UARTDM_ISR_TX_READY_BMSK) { |
| 1858 | /* Clear TX Ready */ |
| 1859 | msm_hs_write(uport, UARTDM_CR_ADDR, CLEAR_TX_READY); |
| 1860 | |
| 1861 | if (msm_uport->clk_state == MSM_HS_CLK_REQUEST_OFF) { |
| 1862 | msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK; |
| 1863 | msm_hs_write(uport, UARTDM_IMR_ADDR, |
| 1864 | msm_uport->imr_reg); |
| 1865 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1866 | /* |
| 1867 | * Complete both writes before starting new TX. |
| 1868 | * Hence mb() requires here. |
| 1869 | */ |
| 1870 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1871 | /* Complete DMA TX transactions and submit new transactions */ |
Saket Saurabh | ce39410 | 2012-10-29 19:51:28 +0530 | [diff] [blame] | 1872 | |
| 1873 | /* Do not update tx_buf.tail if uart_flush_buffer already |
| 1874 | called in serial core */ |
| 1875 | if (!msm_uport->tty_flush_receive) |
| 1876 | tx_buf->tail = (tx_buf->tail + |
| 1877 | tx->tx_count) & ~UART_XMIT_SIZE; |
| 1878 | else |
| 1879 | msm_uport->tty_flush_receive = false; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1880 | |
| 1881 | tx->dma_in_flight = 0; |
| 1882 | |
| 1883 | uport->icount.tx += tx->tx_count; |
| 1884 | if (tx->tx_ready_int_en) |
| 1885 | msm_hs_submit_tx_locked(uport); |
| 1886 | |
| 1887 | if (uart_circ_chars_pending(tx_buf) < WAKEUP_CHARS) |
| 1888 | uart_write_wakeup(uport); |
| 1889 | } |
| 1890 | if (isr_status & UARTDM_ISR_TXLEV_BMSK) { |
| 1891 | /* TX FIFO is empty */ |
| 1892 | msm_uport->imr_reg &= ~UARTDM_ISR_TXLEV_BMSK; |
| 1893 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1894 | /* |
| 1895 | * Complete device write before starting clock_off request. |
| 1896 | * Hence mb() requires here. |
| 1897 | */ |
| 1898 | mb(); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1899 | queue_work(msm_uport->hsuart_wq, &msm_uport->clock_off_w); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1900 | } |
| 1901 | |
| 1902 | /* Change in CTS interrupt */ |
| 1903 | if (isr_status & UARTDM_ISR_DELTA_CTS_BMSK) |
Mayank Rana | ee815f3 | 2011-12-08 09:06:09 +0530 | [diff] [blame] | 1904 | msm_hs_handle_delta_cts_locked(uport); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1905 | |
| 1906 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1907 | |
| 1908 | return IRQ_HANDLED; |
| 1909 | } |
| 1910 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1911 | /* request to turn off uart clock once pending TX is flushed */ |
| 1912 | void msm_hs_request_clock_off(struct uart_port *uport) { |
| 1913 | unsigned long flags; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1914 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 1915 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1916 | spin_lock_irqsave(&uport->lock, flags); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1917 | if (msm_uport->clk_state == MSM_HS_CLK_ON) { |
| 1918 | msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF; |
| 1919 | msm_uport->clk_req_off_state = CLK_REQ_OFF_START; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1920 | msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK; |
| 1921 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1922 | /* |
| 1923 | * Complete device write before retuning back. |
| 1924 | * Hence mb() requires here. |
| 1925 | */ |
| 1926 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1927 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1928 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1929 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1930 | EXPORT_SYMBOL(msm_hs_request_clock_off); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1931 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1932 | void msm_hs_request_clock_on(struct uart_port *uport) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1933 | { |
| 1934 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1935 | unsigned long flags; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1936 | unsigned int data; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1937 | int ret = 0; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1938 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1939 | mutex_lock(&msm_uport->clk_mutex); |
| 1940 | spin_lock_irqsave(&uport->lock, flags); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1941 | |
| 1942 | switch (msm_uport->clk_state) { |
| 1943 | case MSM_HS_CLK_OFF: |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1944 | wake_lock(&msm_uport->dma_wake_lock); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1945 | disable_irq_nosync(msm_uport->wakeup.irq); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1946 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 1947 | |
| 1948 | /* Vote for PNOC BUS Scaling */ |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 1949 | msm_hs_bus_voting(msm_uport, BUS_SCALING); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 1950 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1951 | ret = clk_prepare_enable(msm_uport->clk); |
| 1952 | if (ret) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1953 | dev_err(uport->dev, "Clock ON Failure" |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1954 | "For UART CLK Stalling HSUART\n"); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1955 | break; |
| 1956 | } |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 1957 | |
| 1958 | if (msm_uport->pclk) { |
| 1959 | ret = clk_prepare_enable(msm_uport->pclk); |
| 1960 | if (unlikely(ret)) { |
| 1961 | clk_disable_unprepare(msm_uport->clk); |
| 1962 | dev_err(uport->dev, "Clock ON Failure" |
| 1963 | "For UART Pclk Stalling HSUART\n"); |
| 1964 | break; |
| 1965 | } |
| 1966 | } |
| 1967 | spin_lock_irqsave(&uport->lock, flags); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1968 | /* else fall-through */ |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1969 | case MSM_HS_CLK_REQUEST_OFF: |
| 1970 | if (msm_uport->rx.flush == FLUSH_STOP || |
| 1971 | msm_uport->rx.flush == FLUSH_SHUTDOWN) { |
| 1972 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); |
| 1973 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 1974 | if (is_blsp_uart(msm_uport)) |
| 1975 | data |= UARTDM_RX_BAM_ENABLE_BMSK; |
| 1976 | else |
| 1977 | data |= UARTDM_RX_DM_EN_BMSK; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1978 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1979 | /* Complete above device write. Hence mb() here. */ |
| 1980 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1981 | } |
| 1982 | hrtimer_try_to_cancel(&msm_uport->clk_off_timer); |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1983 | if (msm_uport->rx.flush == FLUSH_SHUTDOWN) { |
| 1984 | if (is_blsp_uart(msm_uport)) { |
| 1985 | spin_unlock_irqrestore(&uport->lock, flags); |
| 1986 | msm_hs_spsconnect_rx(uport); |
| 1987 | spin_lock_irqsave(&uport->lock, flags); |
| 1988 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1989 | msm_hs_start_rx_locked(uport); |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 1990 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 1991 | if (msm_uport->rx.flush == FLUSH_STOP) |
| 1992 | msm_uport->rx.flush = FLUSH_IGNORE; |
| 1993 | msm_uport->clk_state = MSM_HS_CLK_ON; |
| 1994 | break; |
| 1995 | case MSM_HS_CLK_ON: |
| 1996 | break; |
| 1997 | case MSM_HS_CLK_PORT_OFF: |
| 1998 | break; |
| 1999 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2000 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2001 | spin_unlock_irqrestore(&uport->lock, flags); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2002 | mutex_unlock(&msm_uport->clk_mutex); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2003 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2004 | EXPORT_SYMBOL(msm_hs_request_clock_on); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2005 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2006 | static irqreturn_t msm_hs_wakeup_isr(int irq, void *dev) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2007 | { |
| 2008 | unsigned int wakeup = 0; |
| 2009 | unsigned long flags; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2010 | struct msm_hs_port *msm_uport = (struct msm_hs_port *)dev; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2011 | struct uart_port *uport = &msm_uport->uport; |
| 2012 | struct tty_struct *tty = NULL; |
| 2013 | |
| 2014 | spin_lock_irqsave(&uport->lock, flags); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2015 | if (msm_uport->clk_state == MSM_HS_CLK_OFF) { |
| 2016 | /* ignore the first irq - it is a pending irq that occured |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2017 | * before enable_irq() */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2018 | if (msm_uport->wakeup.ignore) |
| 2019 | msm_uport->wakeup.ignore = 0; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2020 | else |
| 2021 | wakeup = 1; |
| 2022 | } |
| 2023 | |
| 2024 | if (wakeup) { |
| 2025 | /* the uart was clocked off during an rx, wake up and |
| 2026 | * optionally inject char into tty rx */ |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2027 | spin_unlock_irqrestore(&uport->lock, flags); |
| 2028 | msm_hs_request_clock_on(uport); |
| 2029 | spin_lock_irqsave(&uport->lock, flags); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2030 | if (msm_uport->wakeup.inject_rx) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2031 | tty = uport->state->port.tty; |
| 2032 | tty_insert_flip_char(tty, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2033 | msm_uport->wakeup.rx_to_inject, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2034 | TTY_NORMAL); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2035 | } |
| 2036 | } |
| 2037 | |
| 2038 | spin_unlock_irqrestore(&uport->lock, flags); |
| 2039 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2040 | if (wakeup && msm_uport->wakeup.inject_rx) |
| 2041 | tty_flip_buffer_push(tty); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2042 | return IRQ_HANDLED; |
| 2043 | } |
| 2044 | |
| 2045 | static const char *msm_hs_type(struct uart_port *port) |
| 2046 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2047 | return ("MSM HS UART"); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2048 | } |
| 2049 | |
Saket Saurabh | fe3b93b | 2013-02-04 18:44:12 +0530 | [diff] [blame] | 2050 | /** |
| 2051 | * msm_hs_unconfig_uart_gpios: Unconfigures UART GPIOs |
| 2052 | * @uport: uart port |
| 2053 | */ |
| 2054 | static void msm_hs_unconfig_uart_gpios(struct uart_port *uport) |
| 2055 | { |
| 2056 | struct platform_device *pdev = to_platform_device(uport->dev); |
| 2057 | const struct msm_serial_hs_platform_data *pdata = |
| 2058 | pdev->dev.platform_data; |
| 2059 | |
| 2060 | if (pdata) { |
| 2061 | if (gpio_is_valid(pdata->uart_tx_gpio)) |
| 2062 | gpio_free(pdata->uart_tx_gpio); |
| 2063 | if (gpio_is_valid(pdata->uart_rx_gpio)) |
| 2064 | gpio_free(pdata->uart_rx_gpio); |
| 2065 | if (gpio_is_valid(pdata->uart_cts_gpio)) |
| 2066 | gpio_free(pdata->uart_cts_gpio); |
| 2067 | if (gpio_is_valid(pdata->uart_rfr_gpio)) |
| 2068 | gpio_free(pdata->uart_rfr_gpio); |
| 2069 | } else { |
| 2070 | pr_err("Error:Pdata is NULL.\n"); |
| 2071 | } |
| 2072 | } |
| 2073 | |
| 2074 | /** |
| 2075 | * msm_hs_config_uart_gpios - Configures UART GPIOs |
| 2076 | * @uport: uart port |
| 2077 | */ |
| 2078 | static int msm_hs_config_uart_gpios(struct uart_port *uport) |
| 2079 | { |
| 2080 | struct platform_device *pdev = to_platform_device(uport->dev); |
| 2081 | const struct msm_serial_hs_platform_data *pdata = |
| 2082 | pdev->dev.platform_data; |
| 2083 | int ret = 0; |
| 2084 | |
| 2085 | if (pdata) { |
| 2086 | if (gpio_is_valid(pdata->uart_tx_gpio)) { |
| 2087 | ret = gpio_request(pdata->uart_tx_gpio, |
| 2088 | "UART_TX_GPIO"); |
| 2089 | if (unlikely(ret)) { |
| 2090 | pr_err("gpio request failed for:%d\n", |
| 2091 | pdata->uart_tx_gpio); |
| 2092 | goto exit_uart_config; |
| 2093 | } |
| 2094 | } |
| 2095 | |
| 2096 | if (gpio_is_valid(pdata->uart_rx_gpio)) { |
| 2097 | ret = gpio_request(pdata->uart_rx_gpio, |
| 2098 | "UART_RX_GPIO"); |
| 2099 | if (unlikely(ret)) { |
| 2100 | pr_err("gpio request failed for:%d\n", |
| 2101 | pdata->uart_rx_gpio); |
| 2102 | goto uart_tx_unconfig; |
| 2103 | } |
| 2104 | } |
| 2105 | |
| 2106 | if (gpio_is_valid(pdata->uart_cts_gpio)) { |
| 2107 | ret = gpio_request(pdata->uart_cts_gpio, |
| 2108 | "UART_CTS_GPIO"); |
| 2109 | if (unlikely(ret)) { |
| 2110 | pr_err("gpio request failed for:%d\n", |
| 2111 | pdata->uart_cts_gpio); |
| 2112 | goto uart_rx_unconfig; |
| 2113 | } |
| 2114 | } |
| 2115 | |
| 2116 | if (gpio_is_valid(pdata->uart_rfr_gpio)) { |
| 2117 | ret = gpio_request(pdata->uart_rfr_gpio, |
| 2118 | "UART_RFR_GPIO"); |
| 2119 | if (unlikely(ret)) { |
| 2120 | pr_err("gpio request failed for:%d\n", |
| 2121 | pdata->uart_rfr_gpio); |
| 2122 | goto uart_cts_unconfig; |
| 2123 | } |
| 2124 | } |
| 2125 | } else { |
| 2126 | pr_err("Pdata is NULL.\n"); |
| 2127 | ret = -EINVAL; |
| 2128 | } |
| 2129 | return ret; |
| 2130 | |
| 2131 | uart_cts_unconfig: |
| 2132 | if (gpio_is_valid(pdata->uart_cts_gpio)) |
| 2133 | gpio_free(pdata->uart_cts_gpio); |
| 2134 | uart_rx_unconfig: |
| 2135 | if (gpio_is_valid(pdata->uart_rx_gpio)) |
| 2136 | gpio_free(pdata->uart_rx_gpio); |
| 2137 | uart_tx_unconfig: |
| 2138 | if (gpio_is_valid(pdata->uart_tx_gpio)) |
| 2139 | gpio_free(pdata->uart_tx_gpio); |
| 2140 | exit_uart_config: |
| 2141 | return ret; |
| 2142 | } |
| 2143 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2144 | /* Called when port is opened */ |
| 2145 | static int msm_hs_startup(struct uart_port *uport) |
| 2146 | { |
| 2147 | int ret; |
| 2148 | int rfr_level; |
| 2149 | unsigned long flags; |
| 2150 | unsigned int data; |
| 2151 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
Mayank Rana | 4083678 | 2012-11-16 14:45:47 +0530 | [diff] [blame] | 2152 | struct platform_device *pdev = to_platform_device(uport->dev); |
| 2153 | const struct msm_serial_hs_platform_data *pdata = |
| 2154 | pdev->dev.platform_data; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2155 | struct circ_buf *tx_buf = &uport->state->xmit; |
| 2156 | struct msm_hs_tx *tx = &msm_uport->tx; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2157 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 2158 | struct sps_pipe *sps_pipe_handle_tx = tx->cons.pipe_handle; |
| 2159 | struct sps_pipe *sps_pipe_handle_rx = rx->prod.pipe_handle; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2160 | |
| 2161 | rfr_level = uport->fifosize; |
| 2162 | if (rfr_level > 16) |
| 2163 | rfr_level -= 16; |
| 2164 | |
| 2165 | tx->dma_base = dma_map_single(uport->dev, tx_buf->buf, UART_XMIT_SIZE, |
| 2166 | DMA_TO_DEVICE); |
| 2167 | |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2168 | wake_lock(&msm_uport->dma_wake_lock); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2169 | /* turn on uart clk */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2170 | ret = msm_hs_init_clk(uport); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2171 | if (unlikely(ret)) { |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2172 | pr_err("Turning ON uartclk error\n"); |
| 2173 | wake_unlock(&msm_uport->dma_wake_lock); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2174 | return ret; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2175 | } |
| 2176 | |
Saket Saurabh | fe3b93b | 2013-02-04 18:44:12 +0530 | [diff] [blame] | 2177 | if (is_blsp_uart(msm_uport)) { |
| 2178 | ret = msm_hs_config_uart_gpios(uport); |
| 2179 | if (ret) { |
| 2180 | pr_err("Uart GPIO request failed\n"); |
| 2181 | goto deinit_uart_clk; |
| 2182 | } |
| 2183 | } else { |
| 2184 | if (pdata && pdata->gpio_config) |
| 2185 | if (unlikely(pdata->gpio_config(1))) |
| 2186 | dev_err(uport->dev, "Cannot configure gpios\n"); |
| 2187 | } |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2188 | |
| 2189 | /* SPS Connect for BAM endpoints */ |
| 2190 | if (is_blsp_uart(msm_uport)) { |
| 2191 | /* SPS connect for TX */ |
| 2192 | ret = msm_hs_spsconnect_tx(uport); |
| 2193 | if (ret) { |
| 2194 | pr_err("msm_serial_hs: SPS connect failed for TX"); |
Saket Saurabh | fe3b93b | 2013-02-04 18:44:12 +0530 | [diff] [blame] | 2195 | goto unconfig_uart_gpios; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2196 | } |
| 2197 | |
| 2198 | /* SPS connect for RX */ |
| 2199 | ret = msm_hs_spsconnect_rx(uport); |
| 2200 | if (ret) { |
| 2201 | pr_err("msm_serial_hs: SPS connect failed for RX"); |
| 2202 | goto sps_disconnect_tx; |
| 2203 | } |
| 2204 | } |
| 2205 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2206 | /* Set auto RFR Level */ |
| 2207 | data = msm_hs_read(uport, UARTDM_MR1_ADDR); |
| 2208 | data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK; |
| 2209 | data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK; |
| 2210 | data |= (UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2)); |
| 2211 | data |= (UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level); |
| 2212 | msm_hs_write(uport, UARTDM_MR1_ADDR, data); |
| 2213 | |
| 2214 | /* Make sure RXSTALE count is non-zero */ |
| 2215 | data = msm_hs_read(uport, UARTDM_IPR_ADDR); |
| 2216 | if (!data) { |
| 2217 | data |= 0x1f & UARTDM_IPR_STALE_LSB_BMSK; |
| 2218 | msm_hs_write(uport, UARTDM_IPR_ADDR, data); |
| 2219 | } |
| 2220 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2221 | if (is_blsp_uart(msm_uport)) { |
| 2222 | /* Enable BAM mode */ |
| 2223 | data = UARTDM_TX_BAM_ENABLE_BMSK | UARTDM_RX_BAM_ENABLE_BMSK; |
| 2224 | } else { |
| 2225 | /* Enable Data Mover Mode */ |
| 2226 | data = UARTDM_TX_DM_EN_BMSK | UARTDM_RX_DM_EN_BMSK; |
| 2227 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2228 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); |
| 2229 | |
| 2230 | /* Reset TX */ |
| 2231 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX); |
| 2232 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_RX); |
| 2233 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_ERROR_STATUS); |
| 2234 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_BREAK_INT); |
| 2235 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_STALE_INT); |
| 2236 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_CTS); |
| 2237 | msm_hs_write(uport, UARTDM_CR_ADDR, RFR_LOW); |
| 2238 | /* Turn on Uart Receiver */ |
| 2239 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_EN_BMSK); |
| 2240 | |
| 2241 | /* Turn on Uart Transmitter */ |
| 2242 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_EN_BMSK); |
| 2243 | |
| 2244 | /* Initialize the tx */ |
| 2245 | tx->tx_ready_int_en = 0; |
| 2246 | tx->dma_in_flight = 0; |
| 2247 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2248 | if (!is_blsp_uart(msm_uport)) { |
| 2249 | tx->xfer.complete_func = msm_hs_dmov_tx_callback; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2250 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2251 | tx->command_ptr->cmd = CMD_LC | |
| 2252 | CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2253 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2254 | tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2255 | | (MSM_UARTDM_BURST_SIZE); |
| 2256 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2257 | tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2258 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2259 | tx->command_ptr->dst_row_addr = |
| 2260 | msm_uport->uport.mapbase + UARTDM_TF_ADDR; |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 2261 | |
| 2262 | msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2263 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2264 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2265 | /* Enable reading the current CTS, no harm even if CTS is ignored */ |
| 2266 | msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK; |
| 2267 | |
| 2268 | msm_hs_write(uport, UARTDM_TFWR_ADDR, 0); /* TXLEV on empty TX fifo */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2269 | /* |
| 2270 | * Complete all device write related configuration before |
| 2271 | * queuing RX request. Hence mb() requires here. |
| 2272 | */ |
| 2273 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2274 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2275 | if (use_low_power_wakeup(msm_uport)) { |
| 2276 | ret = irq_set_irq_wake(msm_uport->wakeup.irq, 1); |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2277 | if (unlikely(ret)) { |
| 2278 | pr_err("%s():Err setting wakeup irq\n", __func__); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2279 | goto sps_disconnect_rx; |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2280 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2281 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2282 | |
| 2283 | ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH, |
| 2284 | "msm_hs_uart", msm_uport); |
| 2285 | if (unlikely(ret)) { |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2286 | pr_err("%s():Error getting uart irq\n", __func__); |
| 2287 | goto free_wake_irq; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2288 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2289 | if (use_low_power_wakeup(msm_uport)) { |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2290 | |
| 2291 | ret = request_threaded_irq(msm_uport->wakeup.irq, NULL, |
| 2292 | msm_hs_wakeup_isr, |
| 2293 | IRQF_TRIGGER_FALLING, |
| 2294 | "msm_hs_wakeup", msm_uport); |
| 2295 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2296 | if (unlikely(ret)) { |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2297 | pr_err("%s():Err getting uart wakeup_irq\n", __func__); |
| 2298 | goto free_uart_irq; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2299 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2300 | disable_irq(msm_uport->wakeup.irq); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2301 | } |
| 2302 | |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 2303 | /* Vote for PNOC BUS Scaling */ |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 2304 | msm_hs_bus_voting(msm_uport, BUS_SCALING); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 2305 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2306 | spin_lock_irqsave(&uport->lock, flags); |
| 2307 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2308 | msm_hs_start_rx_locked(uport); |
| 2309 | |
| 2310 | spin_unlock_irqrestore(&uport->lock, flags); |
| 2311 | ret = pm_runtime_set_active(uport->dev); |
| 2312 | if (ret) |
| 2313 | dev_err(uport->dev, "set active error:%d\n", ret); |
| 2314 | pm_runtime_enable(uport->dev); |
| 2315 | |
| 2316 | return 0; |
| 2317 | |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2318 | free_uart_irq: |
| 2319 | free_irq(uport->irq, msm_uport); |
| 2320 | free_wake_irq: |
| 2321 | irq_set_irq_wake(msm_uport->wakeup.irq, 0); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2322 | sps_disconnect_rx: |
| 2323 | if (is_blsp_uart(msm_uport)) |
| 2324 | sps_disconnect(sps_pipe_handle_rx); |
| 2325 | sps_disconnect_tx: |
| 2326 | if (is_blsp_uart(msm_uport)) |
| 2327 | sps_disconnect(sps_pipe_handle_tx); |
Saket Saurabh | fe3b93b | 2013-02-04 18:44:12 +0530 | [diff] [blame] | 2328 | unconfig_uart_gpios: |
| 2329 | if (is_blsp_uart(msm_uport)) |
| 2330 | msm_hs_unconfig_uart_gpios(uport); |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2331 | deinit_uart_clk: |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2332 | clk_disable_unprepare(msm_uport->clk); |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2333 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2334 | clk_disable_unprepare(msm_uport->pclk); |
Mayank Rana | 679436e | 2012-03-31 05:41:14 +0530 | [diff] [blame] | 2335 | wake_unlock(&msm_uport->dma_wake_lock); |
| 2336 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2337 | return ret; |
| 2338 | } |
| 2339 | |
| 2340 | /* Initialize tx and rx data structures */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2341 | static int uartdm_init_port(struct uart_port *uport) |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2342 | { |
| 2343 | int ret = 0; |
| 2344 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
| 2345 | struct msm_hs_tx *tx = &msm_uport->tx; |
| 2346 | struct msm_hs_rx *rx = &msm_uport->rx; |
| 2347 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2348 | init_waitqueue_head(&rx->wait); |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 2349 | init_waitqueue_head(&tx->wait); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2350 | wake_lock_init(&rx->wake_lock, WAKE_LOCK_SUSPEND, "msm_serial_hs_rx"); |
| 2351 | wake_lock_init(&msm_uport->dma_wake_lock, WAKE_LOCK_SUSPEND, |
| 2352 | "msm_serial_hs_dma"); |
| 2353 | |
| 2354 | tasklet_init(&rx->tlet, msm_serial_hs_rx_tlet, |
| 2355 | (unsigned long) &rx->tlet); |
| 2356 | tasklet_init(&tx->tlet, msm_serial_hs_tx_tlet, |
| 2357 | (unsigned long) &tx->tlet); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2358 | |
| 2359 | rx->pool = dma_pool_create("rx_buffer_pool", uport->dev, |
| 2360 | UARTDM_RX_BUF_SIZE, 16, 0); |
| 2361 | if (!rx->pool) { |
| 2362 | pr_err("%s(): cannot allocate rx_buffer_pool", __func__); |
| 2363 | ret = -ENOMEM; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2364 | goto exit_tasket_init; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2365 | } |
| 2366 | |
| 2367 | rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer); |
| 2368 | if (!rx->buffer) { |
| 2369 | pr_err("%s(): cannot allocate rx->buffer", __func__); |
| 2370 | ret = -ENOMEM; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2371 | goto free_pool; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2372 | } |
| 2373 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2374 | /* Set up Uart Receive */ |
Mayank Rana | 05396b2 | 2013-03-16 19:10:11 +0530 | [diff] [blame] | 2375 | if (is_blsp_uart(msm_uport)) |
| 2376 | msm_hs_write(uport, UARTDM_RFWR_ADDR, 32); |
| 2377 | else |
| 2378 | msm_hs_write(uport, UARTDM_RFWR_ADDR, 0); |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2379 | |
| 2380 | INIT_DELAYED_WORK(&rx->flip_insert_work, flip_insert_work); |
| 2381 | |
| 2382 | if (is_blsp_uart(msm_uport)) |
| 2383 | return ret; |
| 2384 | |
| 2385 | /* Allocate the command pointer. Needs to be 64 bit aligned */ |
| 2386 | tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA); |
| 2387 | if (!tx->command_ptr) { |
| 2388 | return -ENOMEM; |
| 2389 | goto free_rx_buffer; |
| 2390 | } |
| 2391 | |
| 2392 | tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA); |
| 2393 | if (!tx->command_ptr_ptr) { |
| 2394 | ret = -ENOMEM; |
| 2395 | goto free_tx_command_ptr; |
| 2396 | } |
| 2397 | |
| 2398 | tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr, |
| 2399 | sizeof(dmov_box), DMA_TO_DEVICE); |
| 2400 | tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev, |
| 2401 | tx->command_ptr_ptr, |
| 2402 | sizeof(u32), DMA_TO_DEVICE); |
| 2403 | tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr); |
| 2404 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2405 | /* Allocate the command pointer. Needs to be 64 bit aligned */ |
| 2406 | rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA); |
| 2407 | if (!rx->command_ptr) { |
| 2408 | pr_err("%s(): cannot allocate rx->command_ptr", __func__); |
| 2409 | ret = -ENOMEM; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2410 | goto free_tx_command_ptr_ptr; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2411 | } |
| 2412 | |
Mayank Rana | 8431de8 | 2011-12-08 09:06:08 +0530 | [diff] [blame] | 2413 | rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2414 | if (!rx->command_ptr_ptr) { |
| 2415 | pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__); |
| 2416 | ret = -ENOMEM; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2417 | goto free_rx_command_ptr; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2418 | } |
| 2419 | |
| 2420 | rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) | |
| 2421 | (UARTDM_RX_BUF_SIZE >> 4); |
| 2422 | |
| 2423 | rx->command_ptr->dst_row_addr = rx->rbuffer; |
| 2424 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2425 | rx->xfer.complete_func = msm_hs_dmov_rx_callback; |
| 2426 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2427 | rx->command_ptr->cmd = CMD_LC | |
| 2428 | CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX; |
| 2429 | |
| 2430 | rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16) |
| 2431 | | (MSM_UARTDM_BURST_SIZE); |
| 2432 | rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE; |
| 2433 | rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR; |
| 2434 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2435 | rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr, |
| 2436 | sizeof(dmov_box), DMA_TO_DEVICE); |
| 2437 | |
| 2438 | *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr); |
| 2439 | |
| 2440 | rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr, |
Mayank Rana | 8431de8 | 2011-12-08 09:06:08 +0530 | [diff] [blame] | 2441 | sizeof(u32), DMA_TO_DEVICE); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2442 | rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr); |
| 2443 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2444 | return ret; |
| 2445 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2446 | free_rx_command_ptr: |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2447 | kfree(rx->command_ptr); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2448 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2449 | free_tx_command_ptr_ptr: |
| 2450 | kfree(msm_uport->tx.command_ptr_ptr); |
| 2451 | dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr, |
| 2452 | sizeof(u32), DMA_TO_DEVICE); |
| 2453 | dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr, |
| 2454 | sizeof(dmov_box), DMA_TO_DEVICE); |
| 2455 | |
| 2456 | free_tx_command_ptr: |
| 2457 | kfree(msm_uport->tx.command_ptr); |
| 2458 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2459 | free_rx_buffer: |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2460 | dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2461 | msm_uport->rx.rbuffer); |
| 2462 | |
| 2463 | free_pool: |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2464 | dma_pool_destroy(msm_uport->rx.pool); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2465 | |
| 2466 | exit_tasket_init: |
| 2467 | wake_lock_destroy(&msm_uport->rx.wake_lock); |
| 2468 | wake_lock_destroy(&msm_uport->dma_wake_lock); |
| 2469 | tasklet_kill(&msm_uport->tx.tlet); |
| 2470 | tasklet_kill(&msm_uport->rx.tlet); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2471 | return ret; |
| 2472 | } |
| 2473 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2474 | struct msm_serial_hs_platform_data |
| 2475 | *msm_hs_dt_to_pdata(struct platform_device *pdev) |
| 2476 | { |
| 2477 | struct device_node *node = pdev->dev.of_node; |
| 2478 | struct msm_serial_hs_platform_data *pdata; |
| 2479 | int rx_to_inject, ret; |
| 2480 | |
| 2481 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 2482 | if (!pdata) { |
| 2483 | pr_err("unable to allocate memory for platform data\n"); |
| 2484 | return ERR_PTR(-ENOMEM); |
| 2485 | } |
| 2486 | |
| 2487 | /* UART TX GPIO */ |
| 2488 | pdata->uart_tx_gpio = of_get_named_gpio(node, |
| 2489 | "qcom,tx-gpio", 0); |
| 2490 | if (pdata->uart_tx_gpio < 0) |
| 2491 | pr_debug("uart_tx_gpio is not available\n"); |
| 2492 | |
| 2493 | /* UART RX GPIO */ |
| 2494 | pdata->uart_rx_gpio = of_get_named_gpio(node, |
| 2495 | "qcom,rx-gpio", 0); |
| 2496 | if (pdata->uart_rx_gpio < 0) |
| 2497 | pr_debug("uart_rx_gpio is not available\n"); |
| 2498 | |
| 2499 | /* UART CTS GPIO */ |
| 2500 | pdata->uart_cts_gpio = of_get_named_gpio(node, |
| 2501 | "qcom,cts-gpio", 0); |
| 2502 | if (pdata->uart_cts_gpio < 0) |
| 2503 | pr_debug("uart_cts_gpio is not available\n"); |
| 2504 | |
| 2505 | /* UART RFR GPIO */ |
| 2506 | pdata->uart_rfr_gpio = of_get_named_gpio(node, |
| 2507 | "qcom,rfr-gpio", 0); |
| 2508 | if (pdata->uart_rfr_gpio < 0) |
| 2509 | pr_debug("uart_rfr_gpio is not available\n"); |
| 2510 | |
| 2511 | pdata->inject_rx_on_wakeup = of_property_read_bool(node, |
| 2512 | "qcom,inject-rx-on-wakeup"); |
| 2513 | |
| 2514 | if (pdata->inject_rx_on_wakeup) { |
| 2515 | ret = of_property_read_u32(node, "qcom,rx-char-to-inject", |
| 2516 | &rx_to_inject); |
| 2517 | if (ret < 0) { |
| 2518 | pr_err("Error: Rx_char_to_inject not specified.\n"); |
| 2519 | return ERR_PTR(ret); |
| 2520 | } |
| 2521 | pdata->rx_to_inject = (char)rx_to_inject; |
| 2522 | } |
| 2523 | |
| 2524 | ret = of_property_read_u32(node, "qcom,bam-tx-ep-pipe-index", |
| 2525 | &pdata->bam_tx_ep_pipe_index); |
| 2526 | if (ret < 0) { |
| 2527 | pr_err("Error: Getting UART BAM TX EP Pipe Index.\n"); |
| 2528 | return ERR_PTR(ret); |
| 2529 | } |
| 2530 | |
| 2531 | if (!(pdata->bam_tx_ep_pipe_index >= BAM_PIPE_MIN && |
| 2532 | pdata->bam_tx_ep_pipe_index <= BAM_PIPE_MAX)) { |
| 2533 | pr_err("Error: Invalid UART BAM TX EP Pipe Index.\n"); |
| 2534 | return ERR_PTR(-EINVAL); |
| 2535 | } |
| 2536 | |
| 2537 | ret = of_property_read_u32(node, "qcom,bam-rx-ep-pipe-index", |
| 2538 | &pdata->bam_rx_ep_pipe_index); |
| 2539 | if (ret < 0) { |
| 2540 | pr_err("Error: Getting UART BAM RX EP Pipe Index.\n"); |
| 2541 | return ERR_PTR(ret); |
| 2542 | } |
| 2543 | |
| 2544 | if (!(pdata->bam_rx_ep_pipe_index >= BAM_PIPE_MIN && |
| 2545 | pdata->bam_rx_ep_pipe_index <= BAM_PIPE_MAX)) { |
| 2546 | pr_err("Error: Invalid UART BAM RX EP Pipe Index.\n"); |
| 2547 | return ERR_PTR(-EINVAL); |
| 2548 | } |
| 2549 | |
| 2550 | pr_debug("tx_ep_pipe_index:%d rx_ep_pipe_index:%d\n" |
| 2551 | "tx_gpio:%d rx_gpio:%d rfr_gpio:%d cts_gpio:%d", |
| 2552 | pdata->bam_tx_ep_pipe_index, pdata->bam_rx_ep_pipe_index, |
| 2553 | pdata->uart_tx_gpio, pdata->uart_rx_gpio, pdata->uart_cts_gpio, |
| 2554 | pdata->uart_rfr_gpio); |
| 2555 | |
| 2556 | return pdata; |
| 2557 | } |
| 2558 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2559 | |
| 2560 | /** |
| 2561 | * Deallocate UART peripheral's SPS endpoint |
| 2562 | * @msm_uport - Pointer to msm_hs_port structure |
| 2563 | * @ep - Pointer to sps endpoint data structure |
| 2564 | */ |
| 2565 | |
| 2566 | static void msm_hs_exit_ep_conn(struct msm_hs_port *msm_uport, |
| 2567 | struct msm_hs_sps_ep_conn_data *ep) |
| 2568 | { |
| 2569 | struct sps_pipe *sps_pipe_handle = ep->pipe_handle; |
| 2570 | struct sps_connect *sps_config = &ep->config; |
| 2571 | |
| 2572 | dma_free_coherent(msm_uport->uport.dev, |
| 2573 | sps_config->desc.size, |
| 2574 | &sps_config->desc.phys_base, |
| 2575 | GFP_KERNEL); |
| 2576 | sps_free_endpoint(sps_pipe_handle); |
| 2577 | } |
| 2578 | |
| 2579 | |
| 2580 | /** |
| 2581 | * Allocate UART peripheral's SPS endpoint |
| 2582 | * |
| 2583 | * This function allocates endpoint context |
| 2584 | * by calling appropriate SPS driver APIs. |
| 2585 | * |
| 2586 | * @msm_uport - Pointer to msm_hs_port structure |
| 2587 | * @ep - Pointer to sps endpoint data structure |
| 2588 | * @is_produce - 1 means Producer endpoint |
| 2589 | * - 0 means Consumer endpoint |
| 2590 | * |
| 2591 | * @return - 0 if successful else negative value |
| 2592 | */ |
| 2593 | |
| 2594 | static int msm_hs_sps_init_ep_conn(struct msm_hs_port *msm_uport, |
| 2595 | struct msm_hs_sps_ep_conn_data *ep, |
| 2596 | bool is_producer) |
| 2597 | { |
| 2598 | int rc = 0; |
| 2599 | struct sps_pipe *sps_pipe_handle; |
| 2600 | struct sps_connect *sps_config = &ep->config; |
| 2601 | struct sps_register_event *sps_event = &ep->event; |
| 2602 | |
| 2603 | /* Allocate endpoint context */ |
| 2604 | sps_pipe_handle = sps_alloc_endpoint(); |
| 2605 | if (!sps_pipe_handle) { |
| 2606 | pr_err("msm_serial_hs: sps_alloc_endpoint() failed!!\n" |
| 2607 | "is_producer=%d", is_producer); |
| 2608 | rc = -ENOMEM; |
| 2609 | goto out; |
| 2610 | } |
| 2611 | |
| 2612 | /* Get default connection configuration for an endpoint */ |
| 2613 | rc = sps_get_config(sps_pipe_handle, sps_config); |
| 2614 | if (rc) { |
| 2615 | pr_err("msm_serial_hs: sps_get_config() failed!!\n" |
| 2616 | "pipe_handle=0x%x rc=%d", (u32)sps_pipe_handle, rc); |
| 2617 | goto get_config_err; |
| 2618 | } |
| 2619 | |
| 2620 | /* Modify the default connection configuration */ |
| 2621 | if (is_producer) { |
| 2622 | /* For UART producer transfer, source is UART peripheral |
| 2623 | where as destination is system memory */ |
| 2624 | sps_config->source = msm_uport->bam_handle; |
| 2625 | sps_config->destination = SPS_DEV_HANDLE_MEM; |
| 2626 | sps_config->mode = SPS_MODE_SRC; |
| 2627 | sps_config->src_pipe_index = msm_uport->bam_rx_ep_pipe_index; |
| 2628 | sps_config->dest_pipe_index = 0; |
| 2629 | sps_config->options = SPS_O_EOT; |
| 2630 | } else { |
| 2631 | /* For UART consumer transfer, source is system memory |
| 2632 | where as destination is UART peripheral */ |
| 2633 | sps_config->source = SPS_DEV_HANDLE_MEM; |
| 2634 | sps_config->destination = msm_uport->bam_handle; |
| 2635 | sps_config->mode = SPS_MODE_DEST; |
| 2636 | sps_config->src_pipe_index = 0; |
| 2637 | sps_config->dest_pipe_index = msm_uport->bam_tx_ep_pipe_index; |
| 2638 | sps_config->options = SPS_O_EOT; |
| 2639 | } |
| 2640 | |
| 2641 | sps_config->event_thresh = 0x10; |
| 2642 | |
| 2643 | /* Allocate maximum descriptor fifo size */ |
| 2644 | sps_config->desc.size = 65532; |
| 2645 | sps_config->desc.base = dma_alloc_coherent(msm_uport->uport.dev, |
| 2646 | sps_config->desc.size, |
| 2647 | &sps_config->desc.phys_base, |
| 2648 | GFP_KERNEL); |
| 2649 | if (!sps_config->desc.base) { |
| 2650 | rc = -ENOMEM; |
| 2651 | pr_err("msm_serial_hs: dma_alloc_coherent() failed!!\n"); |
| 2652 | goto get_config_err; |
| 2653 | } |
| 2654 | memset(sps_config->desc.base, 0x00, sps_config->desc.size); |
| 2655 | |
| 2656 | sps_event->mode = SPS_TRIGGER_CALLBACK; |
| 2657 | sps_event->options = SPS_O_EOT; |
| 2658 | if (is_producer) |
| 2659 | sps_event->callback = msm_hs_sps_rx_callback; |
| 2660 | else |
| 2661 | sps_event->callback = msm_hs_sps_tx_callback; |
| 2662 | |
| 2663 | sps_event->user = (void *)msm_uport; |
| 2664 | |
| 2665 | /* Now save the sps pipe handle */ |
| 2666 | ep->pipe_handle = sps_pipe_handle; |
| 2667 | pr_debug("msm_serial_hs: success !! %s: pipe_handle=0x%x\n" |
| 2668 | "desc_fifo.phys_base=0x%x\n", |
| 2669 | is_producer ? "READ" : "WRITE", |
| 2670 | (u32)sps_pipe_handle, sps_config->desc.phys_base); |
| 2671 | return 0; |
| 2672 | |
| 2673 | get_config_err: |
| 2674 | sps_free_endpoint(sps_pipe_handle); |
| 2675 | out: |
| 2676 | return rc; |
| 2677 | } |
| 2678 | |
| 2679 | /** |
| 2680 | * Initialize SPS HW connected with UART core |
| 2681 | * |
| 2682 | * This function register BAM HW resources with |
| 2683 | * SPS driver and then initialize 2 SPS endpoints |
| 2684 | * |
| 2685 | * msm_uport - Pointer to msm_hs_port structure |
| 2686 | * |
| 2687 | * @return - 0 if successful else negative value |
| 2688 | */ |
| 2689 | |
| 2690 | static int msm_hs_sps_init(struct msm_hs_port *msm_uport) |
| 2691 | { |
| 2692 | int rc = 0; |
| 2693 | struct sps_bam_props bam = {0}; |
| 2694 | u32 bam_handle; |
| 2695 | |
| 2696 | rc = sps_phy2h(msm_uport->bam_mem, &bam_handle); |
| 2697 | if (rc || !bam_handle) { |
| 2698 | bam.phys_addr = msm_uport->bam_mem; |
| 2699 | bam.virt_addr = msm_uport->bam_base; |
| 2700 | /* |
| 2701 | * This event thresold value is only significant for BAM-to-BAM |
| 2702 | * transfer. It's ignored for BAM-to-System mode transfer. |
| 2703 | */ |
| 2704 | bam.event_threshold = 0x10; /* Pipe event threshold */ |
| 2705 | bam.summing_threshold = 1; /* BAM event threshold */ |
| 2706 | |
| 2707 | /* SPS driver wll handle the UART BAM IRQ */ |
| 2708 | bam.irq = (u32)msm_uport->bam_irq; |
| 2709 | bam.manage = SPS_BAM_MGR_LOCAL; |
| 2710 | |
| 2711 | pr_debug("msm_serial_hs: bam physical base=0x%x\n", |
| 2712 | (u32)bam.phys_addr); |
| 2713 | pr_debug("msm_serial_hs: bam virtual base=0x%x\n", |
| 2714 | (u32)bam.virt_addr); |
| 2715 | |
| 2716 | /* Register UART Peripheral BAM device to SPS driver */ |
| 2717 | rc = sps_register_bam_device(&bam, &bam_handle); |
| 2718 | if (rc) { |
| 2719 | pr_err("msm_serial_hs: BAM device register failed\n"); |
| 2720 | return rc; |
| 2721 | } |
| 2722 | pr_info("msm_serial_hs: BAM device registered. bam_handle=0x%x", |
| 2723 | msm_uport->bam_handle); |
| 2724 | } |
| 2725 | msm_uport->bam_handle = bam_handle; |
| 2726 | |
| 2727 | rc = msm_hs_sps_init_ep_conn(msm_uport, &msm_uport->rx.prod, |
| 2728 | UART_SPS_PROD_PERIPHERAL); |
| 2729 | if (rc) { |
| 2730 | pr_err("%s: Failed to Init Producer BAM-pipe", __func__); |
| 2731 | goto deregister_bam; |
| 2732 | } |
| 2733 | |
| 2734 | rc = msm_hs_sps_init_ep_conn(msm_uport, &msm_uport->tx.cons, |
| 2735 | UART_SPS_CONS_PERIPHERAL); |
| 2736 | if (rc) { |
| 2737 | pr_err("%s: Failed to Init Consumer BAM-pipe", __func__); |
| 2738 | goto deinit_ep_conn_prod; |
| 2739 | } |
| 2740 | return 0; |
| 2741 | |
| 2742 | deinit_ep_conn_prod: |
| 2743 | msm_hs_exit_ep_conn(msm_uport, &msm_uport->rx.prod); |
| 2744 | deregister_bam: |
| 2745 | sps_deregister_bam_device(msm_uport->bam_handle); |
| 2746 | return rc; |
| 2747 | } |
| 2748 | |
Saket Saurabh | 10e88b3 | 2013-02-04 15:26:34 +0530 | [diff] [blame] | 2749 | #define BLSP_UART_NR 12 |
| 2750 | static int deviceid[BLSP_UART_NR] = {0}; |
| 2751 | static atomic_t msm_serial_hs_next_id = ATOMIC_INIT(0); |
| 2752 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2753 | static int __devinit msm_hs_probe(struct platform_device *pdev) |
| 2754 | { |
Saket Saurabh | 10e88b3 | 2013-02-04 15:26:34 +0530 | [diff] [blame] | 2755 | int ret = 0, alias_num = -1; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2756 | struct uart_port *uport; |
| 2757 | struct msm_hs_port *msm_uport; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2758 | struct resource *core_resource; |
| 2759 | struct resource *bam_resource; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2760 | struct resource *resource; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2761 | int core_irqres, bam_irqres; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2762 | struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2763 | |
| 2764 | if (pdev->dev.of_node) { |
| 2765 | dev_dbg(&pdev->dev, "device tree enabled\n"); |
| 2766 | pdata = msm_hs_dt_to_pdata(pdev); |
| 2767 | if (IS_ERR(pdata)) |
| 2768 | return PTR_ERR(pdata); |
| 2769 | |
Saket Saurabh | 10e88b3 | 2013-02-04 15:26:34 +0530 | [diff] [blame] | 2770 | if (pdev->id == -1) { |
| 2771 | pdev->id = atomic_inc_return(&msm_serial_hs_next_id)-1; |
| 2772 | deviceid[pdev->id] = 1; |
| 2773 | } |
| 2774 | |
| 2775 | /* Use alias from device tree if present |
| 2776 | * Alias is used as an optional property |
| 2777 | */ |
| 2778 | alias_num = of_alias_get_id(pdev->dev.of_node, "uart"); |
| 2779 | if (alias_num >= 0) { |
| 2780 | /* If alias_num is between 0 and 11, check that it not |
| 2781 | * equal to previous incremented pdev-ids. If it is |
| 2782 | * equal to previous pdev.ids , fail deviceprobe. |
| 2783 | */ |
| 2784 | if (alias_num < BLSP_UART_NR) { |
| 2785 | if (deviceid[alias_num] == 0) { |
| 2786 | pdev->id = alias_num; |
| 2787 | } else { |
| 2788 | pr_err("alias_num=%d already used\n", |
| 2789 | alias_num); |
| 2790 | return -EINVAL; |
| 2791 | } |
| 2792 | } else { |
| 2793 | pdev->id = alias_num; |
| 2794 | } |
| 2795 | } |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2796 | |
| 2797 | pdev->dev.platform_data = pdata; |
| 2798 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2799 | |
| 2800 | if (pdev->id < 0 || pdev->id >= UARTDM_NR) { |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2801 | pr_err("Invalid plaform device ID = %d\n", pdev->id); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2802 | return -EINVAL; |
| 2803 | } |
| 2804 | |
| 2805 | msm_uport = &q_uart_port[pdev->id]; |
| 2806 | uport = &msm_uport->uport; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2807 | uport->dev = &pdev->dev; |
| 2808 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2809 | if (pdev->dev.of_node) |
| 2810 | msm_uport->uart_type = BLSP_HSUART; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2811 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2812 | /* Get required resources for BAM HSUART */ |
| 2813 | if (is_blsp_uart(msm_uport)) { |
| 2814 | core_resource = platform_get_resource_byname(pdev, |
| 2815 | IORESOURCE_MEM, "core_mem"); |
| 2816 | bam_resource = platform_get_resource_byname(pdev, |
| 2817 | IORESOURCE_MEM, "bam_mem"); |
| 2818 | core_irqres = platform_get_irq_byname(pdev, "core_irq"); |
| 2819 | bam_irqres = platform_get_irq_byname(pdev, "bam_irq"); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2820 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2821 | if (!core_resource) { |
| 2822 | pr_err("Invalid core HSUART Resources.\n"); |
| 2823 | return -ENXIO; |
| 2824 | } |
| 2825 | |
| 2826 | if (!bam_resource) { |
| 2827 | pr_err("Invalid BAM HSUART Resources.\n"); |
| 2828 | return -ENXIO; |
| 2829 | } |
| 2830 | |
| 2831 | if (!core_irqres) { |
| 2832 | pr_err("Invalid core irqres Resources.\n"); |
| 2833 | return -ENXIO; |
| 2834 | } |
| 2835 | if (!bam_irqres) { |
| 2836 | pr_err("Invalid bam irqres Resources.\n"); |
| 2837 | return -ENXIO; |
| 2838 | } |
| 2839 | |
| 2840 | uport->mapbase = core_resource->start; |
| 2841 | |
| 2842 | uport->membase = ioremap(uport->mapbase, |
| 2843 | resource_size(core_resource)); |
| 2844 | if (unlikely(!uport->membase)) { |
| 2845 | pr_err("UART Resource ioremap Failed.\n"); |
| 2846 | return -ENOMEM; |
| 2847 | } |
| 2848 | msm_uport->bam_mem = bam_resource->start; |
| 2849 | msm_uport->bam_base = ioremap(msm_uport->bam_mem, |
| 2850 | resource_size(bam_resource)); |
| 2851 | if (unlikely(!msm_uport->bam_base)) { |
| 2852 | pr_err("UART BAM Resource ioremap Failed.\n"); |
| 2853 | iounmap(uport->membase); |
| 2854 | return -ENOMEM; |
| 2855 | } |
| 2856 | |
| 2857 | uport->irq = core_irqres; |
| 2858 | msm_uport->bam_irq = bam_irqres; |
| 2859 | |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 2860 | msm_uport->bus_scale_table = msm_bus_cl_get_pdata(pdev); |
| 2861 | if (!msm_uport->bus_scale_table) { |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 2862 | pr_err("BLSP UART: Bus scaling is disabled.\n"); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 2863 | } else { |
| 2864 | msm_uport->bus_perf_client = |
| 2865 | msm_bus_scale_register_client |
| 2866 | (msm_uport->bus_scale_table); |
| 2867 | if (IS_ERR(&msm_uport->bus_perf_client)) { |
| 2868 | pr_err("%s(): Bus client register failed.\n", |
| 2869 | __func__); |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 2870 | ret = -EINVAL; |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 2871 | goto unmap_memory; |
| 2872 | } |
| 2873 | } |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2874 | } else { |
| 2875 | |
| 2876 | resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 2877 | if (unlikely(!resource)) |
| 2878 | return -ENXIO; |
| 2879 | uport->mapbase = resource->start; |
| 2880 | uport->membase = ioremap(uport->mapbase, |
| 2881 | resource_size(resource)); |
| 2882 | if (unlikely(!uport->membase)) |
| 2883 | return -ENOMEM; |
| 2884 | |
| 2885 | uport->irq = platform_get_irq(pdev, 0); |
| 2886 | if (unlikely((int)uport->irq < 0)) { |
| 2887 | pr_err("UART IRQ Failed.\n"); |
| 2888 | iounmap(uport->membase); |
| 2889 | return -ENXIO; |
| 2890 | } |
| 2891 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2892 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2893 | if (pdata == NULL) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2894 | msm_uport->wakeup.irq = -1; |
| 2895 | else { |
| 2896 | msm_uport->wakeup.irq = pdata->wakeup_irq; |
| 2897 | msm_uport->wakeup.ignore = 1; |
| 2898 | msm_uport->wakeup.inject_rx = pdata->inject_rx_on_wakeup; |
| 2899 | msm_uport->wakeup.rx_to_inject = pdata->rx_to_inject; |
| 2900 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2901 | if (unlikely(msm_uport->wakeup.irq < 0)) { |
| 2902 | ret = -ENXIO; |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2903 | goto deregister_bus_client; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2904 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2905 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2906 | if (is_blsp_uart(msm_uport)) { |
| 2907 | msm_uport->bam_tx_ep_pipe_index = |
| 2908 | pdata->bam_tx_ep_pipe_index; |
| 2909 | msm_uport->bam_rx_ep_pipe_index = |
| 2910 | pdata->bam_rx_ep_pipe_index; |
| 2911 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2912 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2913 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2914 | if (!is_blsp_uart(msm_uport)) { |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2915 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2916 | resource = platform_get_resource_byname(pdev, |
| 2917 | IORESOURCE_DMA, "uartdm_channels"); |
| 2918 | if (unlikely(!resource)) { |
| 2919 | ret = -ENXIO; |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2920 | goto deregister_bus_client; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2921 | } |
| 2922 | |
| 2923 | msm_uport->dma_tx_channel = resource->start; |
| 2924 | msm_uport->dma_rx_channel = resource->end; |
| 2925 | |
| 2926 | resource = platform_get_resource_byname(pdev, |
| 2927 | IORESOURCE_DMA, "uartdm_crci"); |
| 2928 | if (unlikely(!resource)) { |
| 2929 | ret = -ENXIO; |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2930 | goto deregister_bus_client; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2931 | } |
| 2932 | |
| 2933 | msm_uport->dma_tx_crci = resource->start; |
| 2934 | msm_uport->dma_rx_crci = resource->end; |
| 2935 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2936 | |
| 2937 | uport->iotype = UPIO_MEM; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2938 | uport->fifosize = 64; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2939 | uport->ops = &msm_hs_ops; |
| 2940 | uport->flags = UPF_BOOT_AUTOCONF; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2941 | uport->uartclk = 7372800; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2942 | msm_uport->imr_reg = 0x0; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2943 | |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 2944 | msm_uport->clk = clk_get(&pdev->dev, "core_clk"); |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2945 | if (IS_ERR(msm_uport->clk)) { |
| 2946 | ret = PTR_ERR(msm_uport->clk); |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2947 | goto deregister_bus_client; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2948 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2949 | |
Matt Wagantall | e252237 | 2011-08-17 14:52:21 -0700 | [diff] [blame] | 2950 | msm_uport->pclk = clk_get(&pdev->dev, "iface_clk"); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2951 | /* |
| 2952 | * Some configurations do not require explicit pclk control so |
| 2953 | * do not flag error on pclk get failure. |
| 2954 | */ |
| 2955 | if (IS_ERR(msm_uport->pclk)) |
| 2956 | msm_uport->pclk = NULL; |
| 2957 | |
| 2958 | ret = clk_set_rate(msm_uport->clk, uport->uartclk); |
| 2959 | if (ret) { |
| 2960 | printk(KERN_WARNING "Error setting clock rate on UART\n"); |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2961 | goto put_clk; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 2962 | } |
| 2963 | |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2964 | msm_uport->hsuart_wq = alloc_workqueue("k_hsuart", |
| 2965 | WQ_UNBOUND | WQ_MEM_RECLAIM, 1); |
| 2966 | if (!msm_uport->hsuart_wq) { |
| 2967 | pr_err("%s(): Unable to create workqueue hsuart_wq\n", |
| 2968 | __func__); |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 2969 | ret = -ENOMEM; |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2970 | goto put_clk; |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2971 | } |
| 2972 | |
| 2973 | INIT_WORK(&msm_uport->clock_off_w, hsuart_clock_off_work); |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2974 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2975 | /* Init work for sps_disconnect in stop_rx_locked */ |
| 2976 | INIT_WORK(&msm_uport->disconnect_rx_endpoint, |
| 2977 | hsuart_disconnect_rx_endpoint_work); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 2978 | mutex_init(&msm_uport->clk_mutex); |
| 2979 | |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2980 | /* Initialize SPS HW connected with UART core */ |
| 2981 | if (is_blsp_uart(msm_uport)) { |
| 2982 | ret = msm_hs_sps_init(msm_uport); |
| 2983 | if (unlikely(ret)) { |
| 2984 | pr_err("SPS Initialization failed ! err=%d", ret); |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 2985 | goto destroy_mutex; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 2986 | } |
| 2987 | } |
| 2988 | |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 2989 | msm_hs_bus_voting(msm_uport, BUS_SCALING); |
| 2990 | |
Matt Wagantall | 7f32d2a | 2012-05-17 15:48:04 -0700 | [diff] [blame] | 2991 | clk_prepare_enable(msm_uport->clk); |
| 2992 | if (msm_uport->pclk) |
| 2993 | clk_prepare_enable(msm_uport->pclk); |
| 2994 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2995 | ret = uartdm_init_port(uport); |
Matt Wagantall | 7f32d2a | 2012-05-17 15:48:04 -0700 | [diff] [blame] | 2996 | if (unlikely(ret)) { |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 2997 | goto err_clock; |
Matt Wagantall | 7f32d2a | 2012-05-17 15:48:04 -0700 | [diff] [blame] | 2998 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 2999 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3000 | /* configure the CR Protection to Enable */ |
| 3001 | msm_hs_write(uport, UARTDM_CR_ADDR, CR_PROTECTION_EN); |
Matt Wagantall | 7f32d2a | 2012-05-17 15:48:04 -0700 | [diff] [blame] | 3002 | |
Matt Wagantall | 7f32d2a | 2012-05-17 15:48:04 -0700 | [diff] [blame] | 3003 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3004 | /* |
| 3005 | * Enable Command register protection before going ahead as this hw |
| 3006 | * configuration makes sure that issued cmd to CR register gets complete |
| 3007 | * before next issued cmd start. Hence mb() requires here. |
| 3008 | */ |
| 3009 | mb(); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3010 | |
| 3011 | msm_uport->clk_state = MSM_HS_CLK_PORT_OFF; |
| 3012 | hrtimer_init(&msm_uport->clk_off_timer, CLOCK_MONOTONIC, |
| 3013 | HRTIMER_MODE_REL); |
| 3014 | msm_uport->clk_off_timer.function = msm_hs_clk_off_retry; |
| 3015 | msm_uport->clk_off_delay = ktime_set(0, 1000000); /* 1ms */ |
| 3016 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3017 | ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_clock.attr); |
| 3018 | if (unlikely(ret)) |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3019 | goto err_clock; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3020 | |
| 3021 | msm_serial_debugfs_init(msm_uport, pdev->id); |
| 3022 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3023 | uport->line = pdev->id; |
Saket Saurabh | 51690e5 | 2012-08-17 14:17:46 +0530 | [diff] [blame] | 3024 | if (pdata != NULL && pdata->userid && pdata->userid <= UARTDM_NR) |
| 3025 | uport->line = pdata->userid; |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 3026 | ret = uart_add_one_port(&msm_hs_driver, uport); |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3027 | if (!ret) { |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 3028 | msm_hs_bus_voting(msm_uport, BUS_RESET); |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3029 | clk_disable_unprepare(msm_uport->clk); |
| 3030 | if (msm_uport->pclk) |
| 3031 | clk_disable_unprepare(msm_uport->pclk); |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 3032 | return ret; |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3033 | } |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 3034 | |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3035 | err_clock: |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 3036 | |
| 3037 | msm_hs_bus_voting(msm_uport, BUS_RESET); |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3038 | clk_disable_unprepare(msm_uport->clk); |
| 3039 | if (msm_uport->pclk) |
| 3040 | clk_disable_unprepare(msm_uport->pclk); |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 3041 | |
| 3042 | destroy_mutex: |
| 3043 | mutex_destroy(&msm_uport->clk_mutex); |
Saket Saurabh | 2c3f0b9 | 2013-01-16 15:06:39 +0530 | [diff] [blame] | 3044 | destroy_workqueue(msm_uport->hsuart_wq); |
Mayank Rana | 43c8baa | 2013-02-23 14:57:14 +0530 | [diff] [blame] | 3045 | |
| 3046 | put_clk: |
| 3047 | if (msm_uport->pclk) |
| 3048 | clk_put(msm_uport->pclk); |
| 3049 | |
| 3050 | if (msm_uport->clk) |
| 3051 | clk_put(msm_uport->clk); |
| 3052 | |
| 3053 | deregister_bus_client: |
| 3054 | if (is_blsp_uart(msm_uport)) |
| 3055 | msm_bus_scale_unregister_client(msm_uport->bus_perf_client); |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 3056 | unmap_memory: |
| 3057 | iounmap(uport->membase); |
| 3058 | if (is_blsp_uart(msm_uport)) |
| 3059 | iounmap(msm_uport->bam_base); |
| 3060 | |
| 3061 | return ret; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3062 | } |
| 3063 | |
| 3064 | static int __init msm_serial_hs_init(void) |
| 3065 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3066 | int ret; |
| 3067 | int i; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3068 | |
| 3069 | /* Init all UARTS as non-configured */ |
| 3070 | for (i = 0; i < UARTDM_NR; i++) |
| 3071 | q_uart_port[i].uport.type = PORT_UNKNOWN; |
| 3072 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3073 | ret = uart_register_driver(&msm_hs_driver); |
| 3074 | if (unlikely(ret)) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3075 | printk(KERN_ERR "%s failed to load\n", __FUNCTION__); |
| 3076 | return ret; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3077 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3078 | debug_base = debugfs_create_dir("msm_serial_hs", NULL); |
| 3079 | if (IS_ERR_OR_NULL(debug_base)) |
| 3080 | pr_info("msm_serial_hs: Cannot create debugfs dir\n"); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3081 | |
| 3082 | ret = platform_driver_register(&msm_serial_hs_platform_driver); |
| 3083 | if (ret) { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3084 | printk(KERN_ERR "%s failed to load\n", __FUNCTION__); |
| 3085 | debugfs_remove_recursive(debug_base); |
| 3086 | uart_unregister_driver(&msm_hs_driver); |
| 3087 | return ret; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3088 | } |
| 3089 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3090 | printk(KERN_INFO "msm_serial_hs module loaded\n"); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3091 | return ret; |
| 3092 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3093 | |
| 3094 | /* |
| 3095 | * Called by the upper layer when port is closed. |
| 3096 | * - Disables the port |
| 3097 | * - Unhook the ISR |
| 3098 | */ |
| 3099 | static void msm_hs_shutdown(struct uart_port *uport) |
| 3100 | { |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 3101 | int ret; |
| 3102 | unsigned int data; |
| 3103 | unsigned long flags; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3104 | struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); |
Mayank Rana | 4083678 | 2012-11-16 14:45:47 +0530 | [diff] [blame] | 3105 | struct platform_device *pdev = to_platform_device(uport->dev); |
| 3106 | const struct msm_serial_hs_platform_data *pdata = |
| 3107 | pdev->dev.platform_data; |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 3108 | struct msm_hs_tx *tx = &msm_uport->tx; |
| 3109 | struct sps_pipe *sps_pipe_handle = tx->cons.pipe_handle; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3110 | |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 3111 | if (msm_uport->tx.dma_in_flight) { |
Saket Saurabh | cbf6c52 | 2013-01-07 16:30:37 +0530 | [diff] [blame] | 3112 | if (!is_blsp_uart(msm_uport)) { |
| 3113 | spin_lock_irqsave(&uport->lock, flags); |
| 3114 | /* disable UART TX interface to DM */ |
| 3115 | data = msm_hs_read(uport, UARTDM_DMEN_ADDR); |
| 3116 | data &= ~UARTDM_TX_DM_EN_BMSK; |
| 3117 | msm_hs_write(uport, UARTDM_DMEN_ADDR, data); |
| 3118 | /* turn OFF UART Transmitter */ |
| 3119 | msm_hs_write(uport, UARTDM_CR_ADDR, |
| 3120 | UARTDM_CR_TX_DISABLE_BMSK); |
| 3121 | /* reset UART TX */ |
| 3122 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX); |
| 3123 | /* reset UART TX Error */ |
| 3124 | msm_hs_write(uport, UARTDM_CR_ADDR, RESET_TX_ERROR); |
| 3125 | msm_uport->tx.flush = FLUSH_STOP; |
| 3126 | spin_unlock_irqrestore(&uport->lock, flags); |
| 3127 | /* discard flush */ |
| 3128 | msm_dmov_flush(msm_uport->dma_tx_channel, 0); |
| 3129 | ret = wait_event_timeout(msm_uport->tx.wait, |
| 3130 | msm_uport->tx.flush == FLUSH_SHUTDOWN, 100); |
| 3131 | if (!ret) |
| 3132 | pr_err("%s():HSUART TX Stalls.\n", __func__); |
| 3133 | } else { |
| 3134 | /* BAM Disconnect for TX */ |
| 3135 | sps_disconnect(sps_pipe_handle); |
| 3136 | } |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 3137 | } |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3138 | tasklet_kill(&msm_uport->tx.tlet); |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 3139 | BUG_ON(msm_uport->rx.flush < FLUSH_STOP); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3140 | wait_event(msm_uport->rx.wait, msm_uport->rx.flush == FLUSH_SHUTDOWN); |
| 3141 | tasklet_kill(&msm_uport->rx.tlet); |
| 3142 | cancel_delayed_work_sync(&msm_uport->rx.flip_insert_work); |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 3143 | flush_workqueue(msm_uport->hsuart_wq); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3144 | pm_runtime_disable(uport->dev); |
| 3145 | pm_runtime_set_suspended(uport->dev); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3146 | |
| 3147 | /* Disable the transmitter */ |
| 3148 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_TX_DISABLE_BMSK); |
| 3149 | /* Disable the receiver */ |
| 3150 | msm_hs_write(uport, UARTDM_CR_ADDR, UARTDM_CR_RX_DISABLE_BMSK); |
| 3151 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3152 | msm_uport->imr_reg = 0; |
| 3153 | msm_hs_write(uport, UARTDM_IMR_ADDR, msm_uport->imr_reg); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3154 | /* |
| 3155 | * Complete all device write before actually disabling uartclk. |
| 3156 | * Hence mb() requires here. |
| 3157 | */ |
| 3158 | mb(); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 3159 | |
| 3160 | /* Reset PNOC Bus Scaling */ |
Mayank Rana | e4bc7de | 2013-01-22 12:51:16 +0530 | [diff] [blame] | 3161 | msm_hs_bus_voting(msm_uport, BUS_RESET); |
Mayank Rana | 88d4914 | 2013-01-16 17:28:53 +0530 | [diff] [blame] | 3162 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3163 | if (msm_uport->clk_state != MSM_HS_CLK_OFF) { |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 3164 | /* to balance clk_state */ |
| 3165 | clk_disable_unprepare(msm_uport->clk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3166 | if (msm_uport->pclk) |
Mayank Rana | cb589d8 | 2012-03-01 11:50:03 +0530 | [diff] [blame] | 3167 | clk_disable_unprepare(msm_uport->pclk); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3168 | wake_unlock(&msm_uport->dma_wake_lock); |
| 3169 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3170 | |
Mayank Rana | af2f008 | 2012-05-22 10:16:02 +0530 | [diff] [blame] | 3171 | msm_uport->clk_state = MSM_HS_CLK_PORT_OFF; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3172 | dma_unmap_single(uport->dev, msm_uport->tx.dma_base, |
| 3173 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
| 3174 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3175 | if (use_low_power_wakeup(msm_uport)) |
| 3176 | irq_set_irq_wake(msm_uport->wakeup.irq, 0); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3177 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3178 | /* Free the interrupt */ |
| 3179 | free_irq(uport->irq, msm_uport); |
| 3180 | if (use_low_power_wakeup(msm_uport)) |
| 3181 | free_irq(msm_uport->wakeup.irq, msm_uport); |
Mayank Rana | 4083678 | 2012-11-16 14:45:47 +0530 | [diff] [blame] | 3182 | |
Saket Saurabh | fe3b93b | 2013-02-04 18:44:12 +0530 | [diff] [blame] | 3183 | if (is_blsp_uart(msm_uport)) { |
| 3184 | msm_hs_unconfig_uart_gpios(uport); |
| 3185 | } else { |
| 3186 | if (pdata && pdata->gpio_config) |
| 3187 | if (pdata->gpio_config(0)) |
| 3188 | dev_err(uport->dev, "GPIO config error\n"); |
| 3189 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3190 | } |
| 3191 | |
| 3192 | static void __exit msm_serial_hs_exit(void) |
| 3193 | { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3194 | printk(KERN_INFO "msm_serial_hs module removed\n"); |
Mayank Rana | 17e0e1a | 2012-04-07 02:10:33 +0530 | [diff] [blame] | 3195 | debugfs_remove_recursive(debug_base); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3196 | platform_driver_unregister(&msm_serial_hs_platform_driver); |
| 3197 | uart_unregister_driver(&msm_hs_driver); |
| 3198 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3199 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3200 | static int msm_hs_runtime_idle(struct device *dev) |
| 3201 | { |
| 3202 | /* |
| 3203 | * returning success from idle results in runtime suspend to be |
| 3204 | * called |
| 3205 | */ |
| 3206 | return 0; |
| 3207 | } |
| 3208 | |
| 3209 | static int msm_hs_runtime_resume(struct device *dev) |
| 3210 | { |
| 3211 | struct platform_device *pdev = container_of(dev, struct |
| 3212 | platform_device, dev); |
| 3213 | struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3214 | msm_hs_request_clock_on(&msm_uport->uport); |
| 3215 | return 0; |
| 3216 | } |
| 3217 | |
| 3218 | static int msm_hs_runtime_suspend(struct device *dev) |
| 3219 | { |
| 3220 | struct platform_device *pdev = container_of(dev, struct |
| 3221 | platform_device, dev); |
| 3222 | struct msm_hs_port *msm_uport = &q_uart_port[pdev->id]; |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3223 | msm_hs_request_clock_off(&msm_uport->uport); |
| 3224 | return 0; |
| 3225 | } |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3226 | |
| 3227 | static const struct dev_pm_ops msm_hs_dev_pm_ops = { |
| 3228 | .runtime_suspend = msm_hs_runtime_suspend, |
| 3229 | .runtime_resume = msm_hs_runtime_resume, |
| 3230 | .runtime_idle = msm_hs_runtime_idle, |
| 3231 | }; |
| 3232 | |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 3233 | static struct of_device_id msm_hs_match_table[] = { |
| 3234 | { .compatible = "qcom,msm-hsuart-v14" }, |
| 3235 | {} |
| 3236 | }; |
| 3237 | |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3238 | static struct platform_driver msm_serial_hs_platform_driver = { |
Mayank Rana | 17e0e1a | 2012-04-07 02:10:33 +0530 | [diff] [blame] | 3239 | .probe = msm_hs_probe, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3240 | .remove = __devexit_p(msm_hs_remove), |
| 3241 | .driver = { |
| 3242 | .name = "msm_serial_hs", |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3243 | .pm = &msm_hs_dev_pm_ops, |
Mayank Rana | ff398d0 | 2012-12-18 10:22:50 +0530 | [diff] [blame] | 3244 | .of_match_table = msm_hs_match_table, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3245 | }, |
| 3246 | }; |
| 3247 | |
| 3248 | static struct uart_driver msm_hs_driver = { |
| 3249 | .owner = THIS_MODULE, |
| 3250 | .driver_name = "msm_serial_hs", |
| 3251 | .dev_name = "ttyHS", |
| 3252 | .nr = UARTDM_NR, |
| 3253 | .cons = 0, |
| 3254 | }; |
| 3255 | |
| 3256 | static struct uart_ops msm_hs_ops = { |
| 3257 | .tx_empty = msm_hs_tx_empty, |
| 3258 | .set_mctrl = msm_hs_set_mctrl_locked, |
| 3259 | .get_mctrl = msm_hs_get_mctrl_locked, |
| 3260 | .stop_tx = msm_hs_stop_tx_locked, |
| 3261 | .start_tx = msm_hs_start_tx_locked, |
| 3262 | .stop_rx = msm_hs_stop_rx_locked, |
| 3263 | .enable_ms = msm_hs_enable_ms_locked, |
| 3264 | .break_ctl = msm_hs_break_ctl, |
| 3265 | .startup = msm_hs_startup, |
| 3266 | .shutdown = msm_hs_shutdown, |
| 3267 | .set_termios = msm_hs_set_termios, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3268 | .type = msm_hs_type, |
| 3269 | .config_port = msm_hs_config_port, |
| 3270 | .release_port = msm_hs_release_port, |
| 3271 | .request_port = msm_hs_request_port, |
Saket Saurabh | ce39410 | 2012-10-29 19:51:28 +0530 | [diff] [blame] | 3272 | .flush_buffer = msm_hs_flush_buffer, |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3273 | }; |
| 3274 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 3275 | module_init(msm_serial_hs_init); |
| 3276 | module_exit(msm_serial_hs_exit); |
Mayank Rana | 5504623 | 2011-03-07 10:28:42 +0530 | [diff] [blame] | 3277 | MODULE_DESCRIPTION("High Speed UART Driver for the MSM chipset"); |
| 3278 | MODULE_VERSION("1.2"); |
| 3279 | MODULE_LICENSE("GPL v2"); |