blob: 34b313955af5fc715a26d182c0e5357cb809b2fd [file] [log] [blame]
Kevin Chan1d5fd4a2013-01-11 14:08:14 -08001#ifndef __MSMB_ISP__
2#define __MSMB_ISP__
3
4#include <linux/videodev2.h>
5
6#define MAX_PLANES_PER_STREAM 3
7#define MAX_NUM_STREAM 7
8
9#define ISP_VERSION_40 40
10#define ISP_VERSION_32 32
Mingcheng Zhu503a6f92013-01-06 13:23:24 -080011#define ISP_NATIVE_BUF_BIT 0x10000
12#define ISP_STATS_STREAM_BIT 0x80000000
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080013
14enum ISP_START_PIXEL_PATTERN {
15 ISP_BAYER_RGRGRG,
16 ISP_BAYER_GRGRGR,
17 ISP_BAYER_BGBGBG,
18 ISP_BAYER_GBGBGB,
19 ISP_YUV_YCbYCr,
20 ISP_YUV_YCrYCb,
21 ISP_YUV_CbYCrY,
22 ISP_YUV_CrYCbY,
23 ISP_PIX_PATTERN_MAX
24};
25
26enum msm_vfe_plane_fmt {
27 Y_PLANE,
28 CB_PLANE,
29 CR_PLANE,
30 CRCB_PLANE,
31 CBCR_PLANE,
32 VFE_PLANE_FMT_MAX
33};
34
35enum msm_vfe_input_src {
36 VFE_PIX_0,
37 VFE_RAW_0,
38 VFE_RAW_1,
39 VFE_RAW_2,
40 VFE_SRC_MAX,
41};
42
43enum msm_vfe_axi_stream_src {
44 PIX_ENCODER,
45 PIX_VIEWFINDER,
46 CAMIF_RAW,
47 IDEAL_RAW,
Kevin Chan80b7b6d2013-01-31 16:08:35 -080048 RDI_INTF_0,
49 RDI_INTF_1,
50 RDI_INTF_2,
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080051 VFE_AXI_SRC_MAX
52};
53
54enum msm_vfe_frame_skip_pattern {
55 NO_SKIP,
56 EVERY_2FRAME,
Kevin Chan1fe7fb72013-02-12 19:33:38 -080057 EVERY_3FRAME,
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080058 EVERY_4FRAME,
Kevin Chan1fe7fb72013-02-12 19:33:38 -080059 EVERY_5FRAME,
60 EVERY_6FRAME,
61 EVERY_7FRAME,
Kevin Chan1d5fd4a2013-01-11 14:08:14 -080062 EVERY_8FRAME,
63 EVERY_16FRAME,
64 EVERY_32FRAME,
65 MAX_SKIP,
66};
67
68enum msm_vfe_camif_input {
69 CAMIF_DISABLED,
70 CAMIF_PAD_REG_INPUT,
71 CAMIF_MIDDI_INPUT,
72 CAMIF_MIPI_INPUT,
73};
74
75struct msm_vfe_camif_cfg {
76 uint32_t lines_per_frame;
77 uint32_t pixels_per_line;
78 uint32_t first_pixel;
79 uint32_t last_pixel;
80 uint32_t first_line;
81 uint32_t last_line;
82 uint32_t epoch_line0;
83 uint32_t epoch_line1;
84 enum msm_vfe_camif_input camif_input;
85};
86
87enum msm_vfe_inputmux {
88 CAMIF,
89 TESTGEN,
90 EXTERNAL_READ,
91};
92
93struct msm_vfe_pix_cfg {
94 struct msm_vfe_camif_cfg camif_cfg;
95 enum msm_vfe_inputmux input_mux;
96 enum ISP_START_PIXEL_PATTERN pixel_pattern;
97};
98
Kevin Chan80b7b6d2013-01-31 16:08:35 -080099struct msm_vfe_rdi_cfg {
100 uint8_t cid;
101 uint8_t frame_based;
102};
103
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800104struct msm_vfe_input_cfg {
105 union {
106 struct msm_vfe_pix_cfg pix_cfg;
Kevin Chan80b7b6d2013-01-31 16:08:35 -0800107 struct msm_vfe_rdi_cfg rdi_cfg;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800108 } d;
109 enum msm_vfe_input_src input_src;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800110};
111
112struct msm_vfe_axi_plane_cfg {
113 uint32_t output_width; /*Include padding*/
114 uint32_t output_height;
115 uint32_t output_stride;
116 uint32_t output_scan_lines;
117 uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
118
119 uint8_t csid_src; /*RDI 0-2*/
120 uint8_t rdi_cid;/*CID 1-16*/
121};
122
123struct msm_vfe_axi_stream_request_cmd {
124 uint32_t session_id;
125 uint32_t stream_id;
126 uint32_t output_format;/*Planar/RAW/Misc*/
127 enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
128 struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
129
130 uint32_t burst_count;
131 uint32_t hfr_mode;
132 uint8_t frame_base;
133
134 uint32_t init_frame_drop; /*MAX 31 Frames*/
135 enum msm_vfe_frame_skip_pattern frame_skip_pattern;
136 uint8_t buf_divert; /* if TRUE no vb2 buf done. */
137 /*Return values*/
138 uint32_t axi_stream_handle;
139};
140
141struct msm_vfe_axi_stream_release_cmd {
142 uint32_t stream_handle;
143};
144
145enum msm_vfe_axi_stream_cmd {
146 STOP_STREAM,
147 START_STREAM,
148};
149
150struct msm_vfe_axi_stream_cfg_cmd {
151 uint8_t num_streams;
152 uint32_t stream_handle[MAX_NUM_STREAM];
153 enum msm_vfe_axi_stream_cmd cmd;
154};
155
Kevin Chan5bebd2e2013-01-30 20:25:05 -0800156enum msm_vfe_axi_stream_update_type {
157 ENABLE_STREAM_BUF_DIVERT,
158 DISABLE_STREAM_BUF_DIVERT,
159 UPDATE_STREAM_FRAMEDROP_PATTERN,
160};
161
162struct msm_vfe_axi_stream_update_cmd {
163 uint32_t stream_handle;
164 enum msm_vfe_axi_stream_update_type update_type;
165 enum msm_vfe_frame_skip_pattern skip_pattern;
166};
167
Kevin Chan3454e2b2013-01-17 19:18:57 -0800168enum msm_vfe_stats_pipeline_policy {
169 STATS_COMP_ALL,
170 STATS_COMP_NONE,
171 MAX_STATS_POLICY,
172};
173
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800174enum msm_isp_stats_type {
175 MSM_ISP_STATS_AEC, /* legacy based AEC */
176 MSM_ISP_STATS_AF, /* legacy based AF */
177 MSM_ISP_STATS_AWB, /* legacy based AWB */
178 MSM_ISP_STATS_RS, /* legacy based RS */
179 MSM_ISP_STATS_CS, /* legacy based CS */
180 MSM_ISP_STATS_IHIST, /* legacy based HIST */
181 MSM_ISP_STATS_SKIN, /* legacy based SKIN */
182 MSM_ISP_STATS_BG, /* Bayer Grids */
183 MSM_ISP_STATS_BF, /* Bayer Focus */
184 MSM_ISP_STATS_BE, /* Bayer Exposure*/
185 MSM_ISP_STATS_BHIST, /* Bayer Hist */
186 MSM_ISP_STATS_MAX /* MAX */
187};
188
189struct msm_vfe_stats_stream_request_cmd {
190 uint32_t session_id;
191 uint32_t stream_id;
192 enum msm_isp_stats_type stats_type;
Mingcheng Zhu503a6f92013-01-06 13:23:24 -0800193 uint32_t framedrop_pattern;
Kevin Chan3454e2b2013-01-17 19:18:57 -0800194 uint32_t irq_subsample_pattern;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800195 uint32_t stream_handle;
Kevin Chan3454e2b2013-01-17 19:18:57 -0800196 uint8_t comp_flag;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800197};
Kevin Chan3454e2b2013-01-17 19:18:57 -0800198
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800199struct msm_vfe_stats_stream_release_cmd {
200 uint32_t stream_handle;
201};
202struct msm_vfe_stats_stream_cfg_cmd {
203 uint8_t num_streams;
204 uint32_t stream_handle[MSM_ISP_STATS_MAX];
205 uint8_t enable;
206};
Kevin Chan3454e2b2013-01-17 19:18:57 -0800207
208struct msm_vfe_stats_comp_policy_cfg {
209 enum msm_vfe_stats_pipeline_policy stats_pipeline_policy;
210 uint32_t comp_framedrop_pattern;
211 uint32_t comp_irq_subsample_pattern;
212};
213
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800214enum msm_vfe_reg_cfg_type {
215 VFE_WRITE,
216 VFE_WRITE_MB,
217 VFE_READ,
Kevin Chan7672ef32013-01-21 22:10:53 -0800218 VFE_CFG_MASK,
219 VFE_WRITE_DMI_16BIT,
220 VFE_WRITE_DMI_32BIT,
221 VFE_WRITE_DMI_64BIT,
222 VFE_READ_DMI_16BIT,
223 VFE_READ_DMI_32BIT,
224 VFE_READ_DMI_64BIT,
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800225};
226
227struct msm_vfe_cfg_cmd2 {
228 uint16_t num_cfg;
229 uint16_t cmd_len;
230 void __user *cfg_data;
231 void __user *cfg_cmd;
232};
233
Kevin Chan7672ef32013-01-21 22:10:53 -0800234struct msm_vfe_reg_rw_info {
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800235 uint32_t reg_offset;
Kevin Chan7672ef32013-01-21 22:10:53 -0800236 uint32_t cmd_data_offset;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800237 uint32_t len;
Kevin Chan7672ef32013-01-21 22:10:53 -0800238};
239
240struct msm_vfe_reg_mask_info {
241 uint32_t reg_offset;
242 uint32_t mask;
243 uint32_t val;
244};
245
246struct msm_vfe_reg_dmi_info {
247 uint32_t hi_tbl_offset; /*Optional*/
248 uint32_t lo_tbl_offset; /*Required*/
249 uint32_t len;
250};
251
252struct msm_vfe_reg_cfg_cmd {
253 union {
254 struct msm_vfe_reg_rw_info rw_info;
255 struct msm_vfe_reg_mask_info mask_info;
256 struct msm_vfe_reg_dmi_info dmi_info;
257 } u;
258
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800259 enum msm_vfe_reg_cfg_type cmd_type;
260};
261
262struct msm_isp_buf_request {
263 uint32_t session_id;
264 uint32_t stream_id;
265 uint8_t num_buf;
266 uint32_t handle;
267};
268
269struct msm_isp_qbuf_info {
270 uint32_t handle;
271 int buf_idx;
272 /*Only used for prepare buffer*/
273 struct v4l2_buffer buffer;
Kevin Chan5bebd2e2013-01-30 20:25:05 -0800274 /*Only used for diverted buffer*/
275 uint32_t dirty_buf;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800276};
277
278struct msm_vfe_axi_src_state {
279 enum msm_vfe_input_src input_src;
280 uint32_t src_active;
281};
282
283enum msm_isp_event_idx {
284 ISP_REG_UPDATE = 0,
285 ISP_START_ACK = 1,
286 ISP_STOP_ACK = 2,
287 ISP_IRQ_VIOLATION = 3,
288 ISP_WM_BUS_OVERFLOW = 4,
289 ISP_STATS_OVERFLOW = 5,
290 ISP_CAMIF_ERROR = 6,
Kevin Chan9c74c522013-02-06 22:27:47 -0800291 ISP_SOF = 7,
292 ISP_EOF = 8,
293 ISP_EVENT_MAX = 9
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800294};
295
Kevin Chan9c74c522013-02-06 22:27:47 -0800296#define ISP_EVENT_OFFSET 8
297#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
298#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
299#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800300#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
301#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
302#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
303#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
304#define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW)
305#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
306#define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR)
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800307#define ISP_EVENT_SOF (ISP_EVENT_BASE + ISP_SOF)
308#define ISP_EVENT_EOF (ISP_EVENT_BASE + ISP_EOF)
Kevin Chan9c74c522013-02-06 22:27:47 -0800309#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
310#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800311
312/* The msm_v4l2_event_data structure should match the
313 * v4l2_event.u.data field.
314 * should not exceed 64 bytes */
315
316struct msm_isp_buf_event {
317 uint32_t session_id;
318 uint32_t stream_id;
319 uint32_t handle;
320 int8_t buf_idx;
321};
322struct msm_isp_stats_event {
323 uint32_t stats_mask; /* 4 bytes */
324 uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */
325};
326
327struct msm_isp_stream_ack {
328 uint32_t session_id;
329 uint32_t stream_id;
330 uint32_t handle;
331};
332
333struct msm_isp_event_data {
Kevin Chan9f7785c2013-02-22 22:09:57 -0800334 /*Wall clock except for buffer divert events
335 *which use monotonic clock
336 */
337 struct timeval timestamp;
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800338 /* if pix is a src frame_id is from camif */
339 uint32_t frame_id;
340 union {
341 /* START_ACK, STOP_ACK */
342 struct msm_isp_stream_ack stream_ack;
343 /* REG_UPDATE_TRIGGER, bus over flow */
344 enum msm_vfe_input_src input_src;
345 /* stats notify */
346 struct msm_isp_stats_event stats;
347 /* IRQ_VIOLATION, STATS_OVER_FLOW, WM_OVER_FLOW */
348 uint32_t irq_status_mask;
349 struct msm_isp_buf_event buf_done;
350 } u; /* union can have max 52 bytes */
351};
352
Kevin Chan80b7b6d2013-01-31 16:08:35 -0800353#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
354#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
355#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
356#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
357#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
358#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
359#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
360#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
361#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
362#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
363#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
364#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
365
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800366#define VIDIOC_MSM_VFE_REG_CFG \
367 _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
368
369#define VIDIOC_MSM_ISP_REQUEST_BUF \
370 _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
371
372#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
373 _IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
374
375#define VIDIOC_MSM_ISP_RELEASE_BUF \
376 _IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
377
378#define VIDIOC_MSM_ISP_REQUEST_STREAM \
379 _IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
380
381#define VIDIOC_MSM_ISP_CFG_STREAM \
382 _IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
383
384#define VIDIOC_MSM_ISP_RELEASE_STREAM \
385 _IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
386
387#define VIDIOC_MSM_ISP_INPUT_CFG \
388 _IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
389
390#define VIDIOC_MSM_ISP_SET_SRC_STATE \
391 _IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
392
393#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
394 _IOWR('V', BASE_VIDIOC_PRIVATE+9, \
395 struct msm_vfe_stats_stream_request_cmd)
396
397#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
398 _IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
399
400#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
401 _IOWR('V', BASE_VIDIOC_PRIVATE+11, \
402 struct msm_vfe_stats_stream_release_cmd)
403
Kevin Chan3454e2b2013-01-17 19:18:57 -0800404#define VIDIOC_MSM_ISP_CFG_STATS_COMP_POLICY \
405 _IOWR('V', BASE_VIDIOC_PRIVATE+12, \
406 struct msm_vfe_stats_comp_policy_cfg)
407
Kevin Chan5bebd2e2013-01-30 20:25:05 -0800408#define VIDIOC_MSM_ISP_UPDATE_STREAM \
409 _IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
410
Kevin Chan1d5fd4a2013-01-11 14:08:14 -0800411#endif /* __MSMB_ISP__ */