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gerrit-public.fairphone.software / kernel / msm / ec9686c4a57ea46c97126660936f66e8a5eb87eb / . / arch / powerpc / boot / dts / mpc8572ds.dts
blob: 91d15e8de9b5d51666317fe711c9ac8d457f21fc [file] [log] [blame]
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]1/*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,8572@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <8000>; // L1, 32K
28 i-cache-size = <8000>; // L1, 32K
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <00000000 00000000>; // Filled by U-Boot
38 };
39
40 soc8572@ffe00000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 device_type = "soc";
44 ranges = <00000000 ffe00000 00100000>;
45 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
46 bus-frequency = <0>; // Filled out by uboot.
47
48 memory-controller@2000 {
49 compatible = "fsl,mpc8572-memory-controller";
50 reg = <2000 1000>;
51 interrupt-parent = <&mpic>;
52 interrupts = <12 2>;
53 };
54
55 memory-controller@6000 {
56 compatible = "fsl,mpc8572-memory-controller";
57 reg = <6000 1000>;
58 interrupt-parent = <&mpic>;
59 interrupts = <12 2>;
60 };
61
62 l2-cache-controller@20000 {
63 compatible = "fsl,mpc8572-l2-cache-controller";
64 reg = <20000 1000>;
65 cache-line-size = <20>; // 32 bytes
66 cache-size = <80000>; // L2, 512K
67 interrupt-parent = <&mpic>;
68 interrupts = <10 2>;
69 };
70
71 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame^]72 #address-cells = <1>;
73 #size-cells = <0>;
74 cell-index = <0>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]75 compatible = "fsl-i2c";
76 reg = <3000 100>;
77 interrupts = <2b 2>;
78 interrupt-parent = <&mpic>;
79 dfsrr;
80 };
81
82 i2c@3100 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame^]83 #address-cells = <1>;
84 #size-cells = <0>;
85 cell-index = <1>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]86 compatible = "fsl-i2c";
87 reg = <3100 100>;
88 interrupts = <2b 2>;
89 interrupt-parent = <&mpic>;
90 dfsrr;
91 };
92
93 mdio@24520 {
94 #address-cells = <1>;
95 #size-cells = <0>;
96 device_type = "mdio";
97 compatible = "gianfar";
98 reg = <24520 20>;
99 phy0: ethernet-phy@0 {
100 interrupt-parent = <&mpic>;
101 interrupts = <a 1>;
102 reg = <0>;
103 };
104 phy1: ethernet-phy@1 {
105 interrupt-parent = <&mpic>;
106 interrupts = <a 1>;
107 reg = <1>;
108 };
109 phy2: ethernet-phy@2 {
110 interrupt-parent = <&mpic>;
111 interrupts = <a 1>;
112 reg = <2>;
113 };
114 phy3: ethernet-phy@3 {
115 interrupt-parent = <&mpic>;
116 interrupts = <a 1>;
117 reg = <3>;
118 };
119 };
120
121 ethernet@24000 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 device_type = "network";
125 model = "eTSEC";
126 compatible = "gianfar";
127 reg = <24000 1000>;
128 local-mac-address = [ 00 00 00 00 00 00 ];
129 interrupts = <1d 2 1e 2 22 2>;
130 interrupt-parent = <&mpic>;
131 phy-handle = <&phy0>;
132 phy-connection-type = "rgmii-id";
133 };
134
135 ethernet@25000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 device_type = "network";
139 model = "eTSEC";
140 compatible = "gianfar";
141 reg = <25000 1000>;
142 local-mac-address = [ 00 00 00 00 00 00 ];
143 interrupts = <23 2 24 2 28 2>;
144 interrupt-parent = <&mpic>;
145 phy-handle = <&phy1>;
146 phy-connection-type = "rgmii-id";
147 };
148
149 ethernet@26000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 device_type = "network";
153 model = "eTSEC";
154 compatible = "gianfar";
155 reg = <26000 1000>;
156 local-mac-address = [ 00 00 00 00 00 00 ];
157 interrupts = <1f 2 20 2 21 2>;
158 interrupt-parent = <&mpic>;
159 phy-handle = <&phy2>;
160 phy-connection-type = "rgmii-id";
161 };
162
163 ethernet@27000 {
164 #address-cells = <1>;
165 #size-cells = <0>;
166 device_type = "network";
167 model = "eTSEC";
168 compatible = "gianfar";
169 reg = <27000 1000>;
170 local-mac-address = [ 00 00 00 00 00 00 ];
171 interrupts = <25 2 26 2 27 2>;
172 interrupt-parent = <&mpic>;
173 phy-handle = <&phy3>;
174 phy-connection-type = "rgmii-id";
175 };
176
177 serial@4500 {
178 device_type = "serial";
179 compatible = "ns16550";
180 reg = <4500 100>;
181 clock-frequency = <0>;
182 interrupts = <2a 2>;
183 interrupt-parent = <&mpic>;
184 };
185
186 serial@4600 {
187 device_type = "serial";
188 compatible = "ns16550";
189 reg = <4600 100>;
190 clock-frequency = <0>;
191 interrupts = <2a 2>;
192 interrupt-parent = <&mpic>;
193 };
194
195 global-utilities@e0000 { //global utilities block
196 compatible = "fsl,mpc8572-guts";
197 reg = <e0000 1000>;
198 fsl,has-rstcr;
199 };
200
201 mpic: pic@40000 {
202 clock-frequency = <0>;
203 interrupt-controller;
204 #address-cells = <0>;
205 #interrupt-cells = <2>;
206 reg = <40000 40000>;
207 compatible = "chrp,open-pic";
208 device_type = "open-pic";
209 big-endian;
210 };
211 };
212
213 pcie@ffe08000 {
214 compatible = "fsl,mpc8548-pcie";
215 device_type = "pci";
216 #interrupt-cells = <1>;
217 #size-cells = <2>;
218 #address-cells = <3>;
219 reg = <ffe08000 1000>;
220 bus-range = <0 ff>;
221 ranges = <02000000 0 80000000 80000000 0 20000000
222 01000000 0 00000000 ffc00000 0 00010000>;
223 clock-frequency = <1fca055>;
224 interrupt-parent = <&mpic>;
225 interrupts = <18 2>;
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]226 interrupt-map-mask = <ff00 0 0 7>;
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]227 interrupt-map = <
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]228 /* IDSEL 0x11 func 0 - PCI slot 1 */
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]229 8800 0 0 1 &mpic 2 1
230 8800 0 0 2 &mpic 3 1
231 8800 0 0 3 &mpic 4 1
232 8800 0 0 4 &mpic 1 1
233
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]234 /* IDSEL 0x11 func 1 - PCI slot 1 */
235 8900 0 0 1 &mpic 2 1
236 8900 0 0 2 &mpic 3 1
237 8900 0 0 3 &mpic 4 1
238 8900 0 0 4 &mpic 1 1
239
240 /* IDSEL 0x11 func 2 - PCI slot 1 */
241 8a00 0 0 1 &mpic 2 1
242 8a00 0 0 2 &mpic 3 1
243 8a00 0 0 3 &mpic 4 1
244 8a00 0 0 4 &mpic 1 1
245
246 /* IDSEL 0x11 func 3 - PCI slot 1 */
247 8b00 0 0 1 &mpic 2 1
248 8b00 0 0 2 &mpic 3 1
249 8b00 0 0 3 &mpic 4 1
250 8b00 0 0 4 &mpic 1 1
251
252 /* IDSEL 0x11 func 4 - PCI slot 1 */
253 8c00 0 0 1 &mpic 2 1
254 8c00 0 0 2 &mpic 3 1
255 8c00 0 0 3 &mpic 4 1
256 8c00 0 0 4 &mpic 1 1
257
258 /* IDSEL 0x11 func 5 - PCI slot 1 */
259 8d00 0 0 1 &mpic 2 1
260 8d00 0 0 2 &mpic 3 1
261 8d00 0 0 3 &mpic 4 1
262 8d00 0 0 4 &mpic 1 1
263
264 /* IDSEL 0x11 func 6 - PCI slot 1 */
265 8e00 0 0 1 &mpic 2 1
266 8e00 0 0 2 &mpic 3 1
267 8e00 0 0 3 &mpic 4 1
268 8e00 0 0 4 &mpic 1 1
269
270 /* IDSEL 0x11 func 7 - PCI slot 1 */
271 8f00 0 0 1 &mpic 2 1
272 8f00 0 0 2 &mpic 3 1
273 8f00 0 0 3 &mpic 4 1
274 8f00 0 0 4 &mpic 1 1
275
276 /* IDSEL 0x12 func 0 - PCI slot 2 */
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]277 9000 0 0 1 &mpic 3 1
278 9000 0 0 2 &mpic 4 1
279 9000 0 0 3 &mpic 1 1
280 9000 0 0 4 &mpic 2 1
281
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]282 /* IDSEL 0x12 func 1 - PCI slot 2 */
283 9100 0 0 1 &mpic 3 1
284 9100 0 0 2 &mpic 4 1
285 9100 0 0 3 &mpic 1 1
286 9100 0 0 4 &mpic 2 1
287
288 /* IDSEL 0x12 func 2 - PCI slot 2 */
289 9200 0 0 1 &mpic 3 1
290 9200 0 0 2 &mpic 4 1
291 9200 0 0 3 &mpic 1 1
292 9200 0 0 4 &mpic 2 1
293
294 /* IDSEL 0x12 func 3 - PCI slot 2 */
295 9300 0 0 1 &mpic 3 1
296 9300 0 0 2 &mpic 4 1
297 9300 0 0 3 &mpic 1 1
298 9300 0 0 4 &mpic 2 1
299
300 /* IDSEL 0x12 func 4 - PCI slot 2 */
301 9400 0 0 1 &mpic 3 1
302 9400 0 0 2 &mpic 4 1
303 9400 0 0 3 &mpic 1 1
304 9400 0 0 4 &mpic 2 1
305
306 /* IDSEL 0x12 func 5 - PCI slot 2 */
307 9500 0 0 1 &mpic 3 1
308 9500 0 0 2 &mpic 4 1
309 9500 0 0 3 &mpic 1 1
310 9500 0 0 4 &mpic 2 1
311
312 /* IDSEL 0x12 func 6 - PCI slot 2 */
313 9600 0 0 1 &mpic 3 1
314 9600 0 0 2 &mpic 4 1
315 9600 0 0 3 &mpic 1 1
316 9600 0 0 4 &mpic 2 1
317
318 /* IDSEL 0x12 func 7 - PCI slot 2 */
319 9700 0 0 1 &mpic 3 1
320 9700 0 0 2 &mpic 4 1
321 9700 0 0 3 &mpic 1 1
322 9700 0 0 4 &mpic 2 1
323
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]324 // IDSEL 0x1c USB
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]325 e000 0 0 1 &i8259 c 2
326 e100 0 0 1 &i8259 9 2
327 e200 0 0 1 &i8259 a 2
328 e300 0 0 1 &i8259 b 2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]329
330 // IDSEL 0x1d Audio
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]331 e800 0 0 1 &i8259 6 2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]332
333 // IDSEL 0x1e Legacy
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]334 f000 0 0 1 &i8259 7 2
335 f100 0 0 1 &i8259 7 2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]336
337 // IDSEL 0x1f IDE/SATA
Kumar Galabebfa062007-11-19 23:36:23 -0600[diff] [blame]338 f800 0 0 1 &i8259 e 2
339 f900 0 0 1 &i8259 5 2
Kumar Gala5d54ddc2007-09-11 01:25:43 -0500[diff] [blame]340
341 >;
342
343 pcie@0 {
344 reg = <0 0 0 0 0>;
345 #size-cells = <2>;
346 #address-cells = <3>;
347 device_type = "pci";
348 ranges = <02000000 0 80000000
349 02000000 0 80000000
350 0 20000000
351
352 01000000 0 00000000
353 01000000 0 00000000
354 0 00100000>;
355 uli1575@0 {
356 reg = <0 0 0 0 0>;
357 #size-cells = <2>;
358 #address-cells = <3>;
359 ranges = <02000000 0 80000000
360 02000000 0 80000000
361 0 20000000
362
363 01000000 0 00000000
364 01000000 0 00000000
365 0 00100000>;
366 isa@1e {
367 device_type = "isa";
368 #interrupt-cells = <2>;
369 #size-cells = <1>;
370 #address-cells = <2>;
371 reg = <f000 0 0 0 0>;
372 ranges = <1 0 01000000 0 0
373 00001000>;
374 interrupt-parent = <&i8259>;
375
376 i8259: interrupt-controller@20 {
377 reg = <1 20 2
378 1 a0 2
379 1 4d0 2>;
380 interrupt-controller;
381 device_type = "interrupt-controller";
382 #address-cells = <0>;
383 #interrupt-cells = <2>;
384 compatible = "chrp,iic";
385 interrupts = <9 2>;
386 interrupt-parent = <&mpic>;
387 };
388
389 i8042@60 {
390 #size-cells = <0>;
391 #address-cells = <1>;
392 reg = <1 60 1 1 64 1>;
393 interrupts = <1 3 c 3>;
394 interrupt-parent =
395 <&i8259>;
396
397 keyboard@0 {
398 reg = <0>;
399 compatible = "pnpPNP,303";
400 };
401
402 mouse@1 {
403 reg = <1>;
404 compatible = "pnpPNP,f03";
405 };
406 };
407
408 rtc@70 {
409 compatible = "pnpPNP,b00";
410 reg = <1 70 2>;
411 };
412
413 gpio@400 {
414 reg = <1 400 80>;
415 };
416 };
417 };
418 };
419
420 };
421
422 pcie@ffe09000 {
423 compatible = "fsl,mpc8548-pcie";
424 device_type = "pci";
425 #interrupt-cells = <1>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 reg = <ffe09000 1000>;
429 bus-range = <0 ff>;
430 ranges = <02000000 0 a0000000 a0000000 0 20000000
431 01000000 0 00000000 ffc10000 0 00010000>;
432 clock-frequency = <1fca055>;
433 interrupt-parent = <&mpic>;
434 interrupts = <1a 2>;
435 interrupt-map-mask = <f800 0 0 7>;
436 interrupt-map = <
437 /* IDSEL 0x0 */
438 0000 0 0 1 &mpic 4 1
439 0000 0 0 2 &mpic 5 1
440 0000 0 0 3 &mpic 6 1
441 0000 0 0 4 &mpic 7 1
442 >;
443 pcie@0 {
444 reg = <0 0 0 0 0>;
445 #size-cells = <2>;
446 #address-cells = <3>;
447 device_type = "pci";
448 ranges = <02000000 0 a0000000
449 02000000 0 a0000000
450 0 20000000
451
452 01000000 0 00000000
453 01000000 0 00000000
454 0 00100000>;
455 };
456 };
457
458 pcie@ffe0a000 {
459 compatible = "fsl,mpc8548-pcie";
460 device_type = "pci";
461 #interrupt-cells = <1>;
462 #size-cells = <2>;
463 #address-cells = <3>;
464 reg = <ffe0a000 1000>;
465 bus-range = <0 ff>;
466 ranges = <02000000 0 c0000000 c0000000 0 20000000
467 01000000 0 00000000 ffc20000 0 00010000>;
468 clock-frequency = <1fca055>;
469 interrupt-parent = <&mpic>;
470 interrupts = <1b 2>;
471 interrupt-map = <
472 /* IDSEL 0x0 */
473 0000 0 0 1 &mpic 0 1
474 0000 0 0 2 &mpic 1 1
475 0000 0 0 3 &mpic 2 1
476 0000 0 0 4 &mpic 3 1
477 >;
478 pcie@0 {
479 reg = <0 0 0 0 0>;
480 #size-cells = <2>;
481 #address-cells = <3>;
482 device_type = "pci";
483 ranges = <02000000 0 c0000000
484 02000000 0 c0000000
485 0 20000000
486
487 01000000 0 00000000
488 01000000 0 00000000
489 0 00100000>;
490 };
491 };
492};