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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparded2145cd2011-03-16 08:20:46 +00002 * Copyright (C) 2005 - 2011 Emulex
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
Ajit Khaparded2145cd2011-03-16 08:20:46 +000011 * linux-drivers@emulex.com
Sathya Perla6b7c5b92009-03-11 23:32:03 -070012 *
Ajit Khaparded2145cd2011-03-16 08:20:46 +000013 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
Sathya Perla6b7c5b92009-03-11 23:32:03 -070016 */
17
18#ifndef BE_H
19#define BE_H
20
21#include <linux/pci.h>
22#include <linux/etherdevice.h>
23#include <linux/version.h>
24#include <linux/delay.h>
25#include <net/tcp.h>
26#include <net/ip.h>
27#include <net/ipv6.h>
28#include <linux/if_vlan.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h>
Ajit Khaparde84517482009-09-04 03:12:16 +000031#include <linux/firmware.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Sathya Perla6b7c5b92009-03-11 23:32:03 -070033
34#include "be_hw.h"
35
Ajit Khapardec8883852011-03-16 08:21:00 +000036#define DRV_VER "4.0.100u"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070037#define DRV_NAME "be2net"
38#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070039#define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
Ajit Khapardec4ca2372009-05-18 15:38:55 -070040#define OC_NAME "Emulex OneConnect 10Gbps NIC"
Sathya Perlafe6d2a32010-11-21 23:25:50 +000041#define OC_NAME_BE OC_NAME "(be3)"
42#define OC_NAME_LANCER OC_NAME "(Lancer)"
Ajit Khaparde35ecf032010-02-09 01:38:06 +000043#define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
Sathya Perla6b7c5b92009-03-11 23:32:03 -070044
Ajit Khapardec4ca2372009-05-18 15:38:55 -070045#define BE_VENDOR_ID 0x19a2
Sathya Perlafe6d2a32010-11-21 23:25:50 +000046#define EMULEX_VENDOR_ID 0x10df
Ajit Khapardec4ca2372009-05-18 15:38:55 -070047#define BE_DEVICE_ID1 0x211
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070048#define BE_DEVICE_ID2 0x221
Sathya Perlafe6d2a32010-11-21 23:25:50 +000049#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */
50#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */
51#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */
Ajit Khapardec4ca2372009-05-18 15:38:55 -070052
53static inline char *nic_name(struct pci_dev *pdev)
54{
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070055 switch (pdev->device) {
56 case OC_DEVICE_ID1:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070057 return OC_NAME;
Ajit Khapardee254f6e2010-02-09 01:28:35 +000058 case OC_DEVICE_ID2:
Sathya Perlafe6d2a32010-11-21 23:25:50 +000059 return OC_NAME_BE;
60 case OC_DEVICE_ID3:
61 return OC_NAME_LANCER;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070062 case BE_DEVICE_ID2:
63 return BE3_NAME;
64 default:
Ajit Khapardec4ca2372009-05-18 15:38:55 -070065 return BE_NAME;
Ajit Khaparde12d7ea22009-10-16 18:02:12 -070066 }
Ajit Khapardec4ca2372009-05-18 15:38:55 -070067}
68
Sathya Perla6b7c5b92009-03-11 23:32:03 -070069/* Number of bytes of an RX frame that are copied to skb->data */
Sathya Perla2e588f82011-03-11 02:49:26 +000070#define BE_HDR_LEN ((u16) 64)
Sathya Perla6b7c5b92009-03-11 23:32:03 -070071#define BE_MAX_JUMBO_FRAME_SIZE 9018
72#define BE_MIN_MTU 256
73
74#define BE_NUM_VLANS_SUPPORTED 64
75#define BE_MAX_EQD 96
76#define BE_MAX_TX_FRAG_COUNT 30
77
78#define EVNT_Q_LEN 1024
79#define TX_Q_LEN 2048
80#define TX_CQ_LEN 1024
81#define RX_Q_LEN 1024 /* Does not support any other value */
82#define RX_CQ_LEN 1024
Sathya Perla5fb379e2009-06-18 00:02:59 +000083#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070084#define MCC_CQ_LEN 256
85
Sathya Perla3abcded2010-10-03 22:12:27 -070086#define MAX_RSS_QS 4 /* BE limit is 4 queues/port */
87#define BE_MAX_MSIX_VECTORS (MAX_RSS_QS + 1 + 1)/* RSS qs + 1 def Rx + Tx */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070088#define BE_NAPI_WEIGHT 64
89#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
90#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
91
Sathya Perla8788fdc2009-07-27 22:52:03 +000092#define FW_VER_LEN 32
93
Sarveshwar Bandiba343c72010-03-31 02:56:12 +000094#define BE_MAX_VF 32
95
Sathya Perla6b7c5b92009-03-11 23:32:03 -070096struct be_dma_mem {
97 void *va;
98 dma_addr_t dma;
99 u32 size;
100};
101
102struct be_queue_info {
103 struct be_dma_mem dma_mem;
104 u16 len;
105 u16 entry_size; /* Size of an element in the queue */
106 u16 id;
107 u16 tail, head;
108 bool created;
109 atomic_t used; /* Number of valid elements in the queue */
110};
111
Sathya Perla5fb379e2009-06-18 00:02:59 +0000112static inline u32 MODULO(u16 val, u16 limit)
113{
114 BUG_ON(limit & (limit - 1));
115 return val & (limit - 1);
116}
117
118static inline void index_adv(u16 *index, u16 val, u16 limit)
119{
120 *index = MODULO((*index + val), limit);
121}
122
123static inline void index_inc(u16 *index, u16 limit)
124{
125 *index = MODULO((*index + 1), limit);
126}
127
128static inline void *queue_head_node(struct be_queue_info *q)
129{
130 return q->dma_mem.va + q->head * q->entry_size;
131}
132
133static inline void *queue_tail_node(struct be_queue_info *q)
134{
135 return q->dma_mem.va + q->tail * q->entry_size;
136}
137
138static inline void queue_head_inc(struct be_queue_info *q)
139{
140 index_inc(&q->head, q->len);
141}
142
143static inline void queue_tail_inc(struct be_queue_info *q)
144{
145 index_inc(&q->tail, q->len);
146}
147
Sathya Perla5fb379e2009-06-18 00:02:59 +0000148struct be_eq_obj {
149 struct be_queue_info q;
150 char desc[32];
151
152 /* Adaptive interrupt coalescing (AIC) info */
153 bool enable_aic;
154 u16 min_eqd; /* in usecs */
155 u16 max_eqd; /* in usecs */
156 u16 cur_eqd; /* in usecs */
Padmanabh Ratnakarecd62102011-04-03 01:54:11 +0000157 u8 eq_idx;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000158
159 struct napi_struct napi;
160};
161
162struct be_mcc_obj {
163 struct be_queue_info q;
164 struct be_queue_info cq;
Sathya Perla7a1e9b22010-02-17 01:35:11 +0000165 bool rearm_cq;
Sathya Perla5fb379e2009-06-18 00:02:59 +0000166};
167
Sathya Perla3abcded2010-10-03 22:12:27 -0700168struct be_tx_stats {
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700169 u32 be_tx_reqs; /* number of TX requests initiated */
170 u32 be_tx_stops; /* number of times TX Q was stopped */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700171 u32 be_tx_wrbs; /* number of tx WRBs used */
172 u32 be_tx_events; /* number of tx completion events */
173 u32 be_tx_compl; /* number of tx completion entries processed */
Sathya Perla4097f662009-03-24 16:40:13 -0700174 ulong be_tx_jiffies;
175 u64 be_tx_bytes;
176 u64 be_tx_bytes_prev;
Ajit Khaparde91992e42010-02-19 13:57:12 +0000177 u64 be_tx_pkts;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700178 u32 be_tx_rate;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700179};
180
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700181struct be_tx_obj {
182 struct be_queue_info q;
183 struct be_queue_info cq;
184 /* Remember the skbs that were transmitted */
185 struct sk_buff *sent_skb_list[TX_Q_LEN];
186};
187
188/* Struct to remember the pages posted for rx frags */
189struct be_rx_page_info {
190 struct page *page;
FUJITA Tomonorifac6da52010-04-01 16:53:22 +0000191 DEFINE_DMA_UNMAP_ADDR(bus);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700192 u16 page_offset;
193 bool last_page_user;
194};
195
Sathya Perla3abcded2010-10-03 22:12:27 -0700196struct be_rx_stats {
197 u32 rx_post_fail;/* number of ethrx buffer alloc failures */
198 u32 rx_polls; /* number of times NAPI called poll function */
199 u32 rx_events; /* number of ucast rx completion events */
200 u32 rx_compl; /* number of rx completion entries processed */
201 ulong rx_jiffies;
202 u64 rx_bytes;
203 u64 rx_bytes_prev;
204 u64 rx_pkts;
205 u32 rx_rate;
206 u32 rx_mcast_pkts;
207 u32 rxcp_err; /* Num rx completion entries w/ err set. */
208 ulong rx_fps_jiffies; /* jiffies at last FPS calc */
209 u32 rx_frags;
210 u32 prev_rx_frags;
211 u32 rx_fps; /* Rx frags per second */
212};
213
Sathya Perla2e588f82011-03-11 02:49:26 +0000214struct be_rx_compl_info {
215 u32 rss_hash;
216 u16 vid;
217 u16 pkt_size;
218 u16 rxq_idx;
219 u16 mac_id;
220 u8 vlanf;
221 u8 num_rcvd;
222 u8 err;
223 u8 ipf;
224 u8 tcpf;
225 u8 udpf;
226 u8 ip_csum;
227 u8 l4_csum;
228 u8 ipv6;
229 u8 vtm;
230 u8 pkt_type;
231};
232
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700233struct be_rx_obj {
Sathya Perla3abcded2010-10-03 22:12:27 -0700234 struct be_adapter *adapter;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700235 struct be_queue_info q;
236 struct be_queue_info cq;
Sathya Perla2e588f82011-03-11 02:49:26 +0000237 struct be_rx_compl_info rxcp;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700238 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
Sathya Perla3abcded2010-10-03 22:12:27 -0700239 struct be_eq_obj rx_eq;
240 struct be_rx_stats stats;
241 u8 rss_id;
242 bool rx_post_starved; /* Zero rx frags have been posted to BE */
Padmanabh Ratnakare80d9da2011-03-07 03:07:58 +0000243 u32 cache_line_barrier[16];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700244};
245
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000246struct be_drv_stats {
247 u8 be_on_die_temperature;
248};
249
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000250struct be_vf_cfg {
251 unsigned char vf_mac_addr[ETH_ALEN];
252 u32 vf_if_handle;
253 u32 vf_pmac_id;
Ajit Khaparde1da87b72010-07-23 01:51:22 +0000254 u16 vf_vlan_tag;
Ajit Khapardee1d18732010-07-23 01:52:13 +0000255 u32 vf_tx_rate;
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000256};
257
Ajit Khaparde9cd90002010-07-23 01:49:04 +0000258#define BE_INVALID_PMAC_ID 0xffffffff
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000259
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700260struct be_adapter {
261 struct pci_dev *pdev;
262 struct net_device *netdev;
263
Sathya Perla8788fdc2009-07-27 22:52:03 +0000264 u8 __iomem *csr;
265 u8 __iomem *db; /* Door Bell */
266 u8 __iomem *pcicfg; /* PCI config space */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000267
Ivan Vecera29849612010-12-14 05:43:19 +0000268 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
Sathya Perla8788fdc2009-07-27 22:52:03 +0000269 struct be_dma_mem mbox_mem;
270 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
271 * is stored for freeing purpose */
272 struct be_dma_mem mbox_mem_alloced;
273
274 struct be_mcc_obj mcc_obj;
275 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
276 spinlock_t mcc_cq_lock;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700277
Sathya Perla3abcded2010-10-03 22:12:27 -0700278 struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700279 bool msix_enabled;
280 bool isr_registered;
281
282 /* TX Rings */
283 struct be_eq_obj tx_eq;
284 struct be_tx_obj tx_obj;
Sathya Perla3abcded2010-10-03 22:12:27 -0700285 struct be_tx_stats tx_stats;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700286
287 u32 cache_line_break[8];
288
289 /* Rx rings */
Sathya Perla3abcded2010-10-03 22:12:27 -0700290 struct be_rx_obj rx_obj[MAX_RSS_QS + 1]; /* one default non-rss Q */
291 u32 num_rx_qs;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700292 u32 big_page_size; /* Compounded page size shared by rx wrbs */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700293
Padmanabh Ratnakarecd62102011-04-03 01:54:11 +0000294 u8 eq_next_idx;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000295 struct be_drv_stats drv_stats;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000296
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700297 struct vlan_group *vlan_grp;
Ajit Khaparde82903e42010-02-09 01:34:57 +0000298 u16 vlans_added;
299 u16 max_vlans; /* Number of vlans supported */
Jesse Grossb7381272010-10-20 13:56:02 +0000300 u8 vlan_tag[VLAN_N_VID];
Somnath Koturcc4ce022010-10-21 07:11:14 -0700301 u8 vlan_prio_bmap; /* Available Priority BitMap */
302 u16 recommended_prio; /* Recommended Priority */
Sathya Perlae7b909a2009-11-22 22:01:10 +0000303 struct be_dma_mem mc_cmd_mem;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700304
Sathya Perla3abcded2010-10-03 22:12:27 -0700305 struct be_dma_mem stats_cmd;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700306 /* Work queue used to perform periodic tasks like getting statistics */
307 struct delayed_work work;
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000308 u16 work_counter;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700309
310 /* Ethtool knobs and info */
311 bool rx_csum; /* BE card must perform rx-checksumming */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700312 char fw_ver[FW_VER_LEN];
313 u32 if_handle; /* Used to configure filtering */
314 u32 pmac_id; /* MAC addr handle used by BE card */
315
Sathya Perlacf588472010-02-14 21:22:01 +0000316 bool eeh_err;
Sathya Perlaa8f447b2009-06-18 00:10:27 +0000317 bool link_up;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700318 u32 port_num;
Sathya Perla24307ee2009-06-18 00:09:25 +0000319 bool promiscuous;
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000320 bool wol;
Ajit Khaparde3486be22010-07-23 02:04:54 +0000321 u32 function_mode;
Sathya Perla3abcded2010-10-03 22:12:27 -0700322 u32 function_caps;
Ajit Khaparde9e90c962009-11-06 02:06:59 +0000323 u32 rx_fc; /* Rx flow control */
324 u32 tx_fc; /* Tx flow control */
Ajit Khaparde7c185272010-07-29 06:16:33 +0000325 bool ue_detected;
Ajit Khapardeb2aebe62011-02-20 11:41:39 +0000326 bool stats_cmd_sent;
Ajit Khaparde0dffc832009-11-29 17:57:46 +0000327 int link_speed;
328 u8 port_type;
Sarveshwar Bandi16c02142009-12-23 04:42:51 +0000329 u8 transceiver;
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000330 u8 autoneg;
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000331 u8 generation; /* BladeEngine ASIC generation */
Sarveshwar Bandidd131e72010-05-25 16:16:32 -0700332 u32 flash_status;
333 struct completion flash_compl;
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000334
Sathya Perla2e588f82011-03-11 02:49:26 +0000335 bool be3_native;
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000336 bool sriov_enabled;
Ajit Khaparde64600ea2010-07-23 01:50:34 +0000337 struct be_vf_cfg vf_cfg[BE_MAX_VF];
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000338 u8 is_virtfn;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000339 u32 sli_family;
Ajit Khaparde9e1453c2011-02-20 11:42:22 +0000340 u8 hba_port_num;
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000341 u16 pvid;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700342};
343
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000344#define be_physfn(adapter) (!adapter->is_virtfn)
Sarveshwar Bandiba343c72010-03-31 02:56:12 +0000345
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000346/* BladeEngine Generation numbers */
347#define BE_GEN2 2
348#define BE_GEN3 3
349
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000350#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3)
351
Stephen Hemminger0fc0b732009-09-02 01:03:33 -0700352extern const struct ethtool_ops be_ethtool_ops;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700353
Sathya Perla3abcded2010-10-03 22:12:27 -0700354#define tx_stats(adapter) (&adapter->tx_stats)
355#define rx_stats(rxo) (&rxo->stats)
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700356
357#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
358
Sathya Perla3abcded2010-10-03 22:12:27 -0700359#define for_all_rx_queues(adapter, rxo, i) \
360 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \
361 i++, rxo++)
362
363/* Just skip the first default non-rss queue */
364#define for_all_rss_queues(adapter, rxo, i) \
365 for (i = 0, rxo = &adapter->rx_obj[i+1]; i < (adapter->num_rx_qs - 1);\
366 i++, rxo++)
367
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700368#define PAGE_SHIFT_4K 12
369#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
370
371/* Returns number of pages spanned by the data starting at the given addr */
372#define PAGES_4K_SPANNED(_address, size) \
373 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
374 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
375
376/* Byte offset into the page corresponding to given address */
377#define OFFSET_IN_PAGE(addr) \
378 ((size_t)(addr) & (PAGE_SIZE_4K-1))
379
380/* Returns bit offset within a DWORD of a bitfield */
381#define AMAP_BIT_OFFSET(_struct, field) \
382 (((size_t)&(((_struct *)0)->field))%32)
383
384/* Returns the bit mask of the field that is NOT shifted into location. */
385static inline u32 amap_mask(u32 bitsize)
386{
387 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
388}
389
390static inline void
391amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
392{
393 u32 *dw = (u32 *) ptr + dw_offset;
394 *dw &= ~(mask << offset);
395 *dw |= (mask & value) << offset;
396}
397
398#define AMAP_SET_BITS(_struct, field, ptr, val) \
399 amap_set(ptr, \
400 offsetof(_struct, field)/32, \
401 amap_mask(sizeof(((_struct *)0)->field)), \
402 AMAP_BIT_OFFSET(_struct, field), \
403 val)
404
405static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
406{
407 u32 *dw = (u32 *) ptr;
408 return mask & (*(dw + dw_offset) >> offset);
409}
410
411#define AMAP_GET_BITS(_struct, field, ptr) \
412 amap_get(ptr, \
413 offsetof(_struct, field)/32, \
414 amap_mask(sizeof(((_struct *)0)->field)), \
415 AMAP_BIT_OFFSET(_struct, field))
416
417#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
418#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
419static inline void swap_dws(void *wrb, int len)
420{
421#ifdef __BIG_ENDIAN
422 u32 *dw = wrb;
423 BUG_ON(len % 4);
424 do {
425 *dw = cpu_to_le32(*dw);
426 dw++;
427 len -= 4;
428 } while (len);
429#endif /* __BIG_ENDIAN */
430}
431
432static inline u8 is_tcp_pkt(struct sk_buff *skb)
433{
434 u8 val = 0;
435
436 if (ip_hdr(skb)->version == 4)
437 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
438 else if (ip_hdr(skb)->version == 6)
439 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
440
441 return val;
442}
443
444static inline u8 is_udp_pkt(struct sk_buff *skb)
445{
446 u8 val = 0;
447
448 if (ip_hdr(skb)->version == 4)
449 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
450 else if (ip_hdr(skb)->version == 6)
451 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
452
453 return val;
454}
455
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000456static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
457{
458 u8 data;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000459 u32 sli_intf;
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000460
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000461 if (lancer_chip(adapter)) {
462 pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET,
463 &sli_intf);
464 adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0;
465 } else {
466 pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
467 pci_read_config_byte(adapter->pdev, 0xFE, &data);
468 adapter->is_virtfn = (data != 0xAA);
469 }
Sarveshwar Bandi344dbf12010-07-09 01:43:55 +0000470}
471
Ajit Khaparde6d87f5c2010-08-25 00:32:33 +0000472static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
473{
474 u32 addr;
475
476 addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
477
478 mac[5] = (u8)(addr & 0xFF);
479 mac[4] = (u8)((addr >> 8) & 0xFF);
480 mac[3] = (u8)((addr >> 16) & 0xFF);
Ajit Khaparde7a2414a2011-02-11 13:36:18 +0000481 /* Use the OUI from the current MAC address */
482 memcpy(mac, adapter->netdev->dev_addr, 3);
Ajit Khaparde6d87f5c2010-08-25 00:32:33 +0000483}
484
Sathya Perla8788fdc2009-07-27 22:52:03 +0000485extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000486 u16 num_popped);
Sathya Perla8788fdc2009-07-27 22:52:03 +0000487extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
Sathya Perlab31c50a2009-09-17 10:30:13 -0700488extern void netdev_stats_update(struct be_adapter *adapter);
Ajit Khaparde84517482009-09-04 03:12:16 +0000489extern int be_load_fw(struct be_adapter *adapter, u8 *func);
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700490#endif /* BE_H */