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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* linux/arch/arm/mach-msm/board-sapphire-panel.c
2 * Copyright (C) 2007-2009 HTC Corporation.
3 * Author: Thomas Tsai <thomas_tsai@htc.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/leds.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22
23#include <linux/io.h>
24#include <linux/gpio.h>
25#include <asm/mach-types.h>
26
27#include <mach/msm_fb.h>
28#include <mach/vreg.h>
29#include <mach/htc_pwrsink.h>
Steve Mucklef132c6c2012-06-06 18:30:57 -070030#include <mach/proc_comm.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070031
32#include "gpio_chip.h"
33#include "board-sapphire.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070034#include "devices.h"
35
36#define DEBUG_SAPPHIRE_PANEL 0
37#define userid 0xD10
38
39#define VSYNC_GPIO 97
40
41enum sapphire_panel_type {
42 SAPPHIRE_PANEL_SHARP = 0,
43 SAPPHIRE_PANEL_TOPPOLY,
44 NUM_OF_SAPPHIRE_PANELS,
45};
46static int g_panel_id = -1 ;
47static int g_panel_inited = 0 ;
48
49#define SAPPHIRE_DEFAULT_BACKLIGHT_BRIGHTNESS 132
50#define GOOGLE_DEFAULT_BACKLIGHT_BRIGHTNESS 102
51#define SDBB SAPPHIRE_DEFAULT_BACKLIGHT_BRIGHTNESS
52#define GDBB GOOGLE_DEFAULT_BACKLIGHT_BRIGHTNESS
53
54static int sapphire_backlight_off;
55static int sapphire_backlight_brightness =
56 SAPPHIRE_DEFAULT_BACKLIGHT_BRIGHTNESS;
57
58static uint8_t sapphire_backlight_last_level = 33;
59static DEFINE_MUTEX(sapphire_backlight_lock);
60
61/* Divide dimming level into 12 sections, and restrict maximum level to 27 */
62#define DIMMING_STEPS 12
63static unsigned dimming_levels[NUM_OF_SAPPHIRE_PANELS][DIMMING_STEPS] = {
64 {0, 1, 2, 3, 6, 9, 11, 13, 16, 19, 22, 25}, /* Sharp */
65 {0, 1, 2, 4, 7, 10, 13, 15, 18, 21, 24, 27}, /* Toppolly */
66};
67static unsigned pwrsink_percents[] = {0, 6, 8, 15, 26, 34, 46, 54, 65, 77, 87,
68 100};
69
70static void sapphire_set_backlight_level(uint8_t level)
71{
72 unsigned dimming_factor = 255/DIMMING_STEPS + 1;
73 int index, new_level ;
74 unsigned percent;
75 unsigned long flags;
76 int i = 0;
77
78 /* Non-linear transform for the difference between two
79 * kind of default backlight settings.
80 */
81 new_level = level<=GDBB ?
82 level*SDBB/GDBB : (SDBB + (level-GDBB)*(255-SDBB) / (255-GDBB)) ;
83 index = new_level/dimming_factor ;
84
85#if DEBUG_SAPPHIRE_PANEL
86 printk(KERN_INFO "level=%d, new level=%d, dimming_levels[%d]=%d\n",
87 level, new_level, index, dimming_levels[g_panel_id][index]);
88#endif
89 percent = pwrsink_percents[index];
90 level = dimming_levels[g_panel_id][index];
91
92 if (sapphire_backlight_last_level == level)
93 return;
94
95 if (level == 0) {
96 gpio_set_value(27, 0);
97 msleep(2);
98 } else {
99 local_irq_save(flags);
100 if (sapphire_backlight_last_level == 0) {
101 gpio_set_value(27, 1);
102 udelay(40);
103 sapphire_backlight_last_level = 33;
104 }
105 i = (sapphire_backlight_last_level - level + 33) % 33;
106 while (i-- > 0) {
107 gpio_set_value(27, 0);
108 udelay(1);
109 gpio_set_value(27, 1);
110 udelay(1);
111 }
112 local_irq_restore(flags);
113 }
114 sapphire_backlight_last_level = level;
115 htc_pwrsink_set(PWRSINK_BACKLIGHT, percent);
116}
117
118#define MDDI_CLIENT_CORE_BASE 0x108000
119#define LCD_CONTROL_BLOCK_BASE 0x110000
120#define SPI_BLOCK_BASE 0x120000
121#define I2C_BLOCK_BASE 0x130000
122#define PWM_BLOCK_BASE 0x140000
123#define GPIO_BLOCK_BASE 0x150000
124#define SYSTEM_BLOCK1_BASE 0x160000
125#define SYSTEM_BLOCK2_BASE 0x170000
126
127
128#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
129#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
130#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
131
132#define V_VDDE2E_VDD2_GPIO 0
133#define V_VDDE2E_VDD2_GPIO_5M 89
134#define MDDI_RST_N 82
135
136#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
137#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
138#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
139#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
140#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
141#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
142#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
143#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
144#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
145#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
146#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
147#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
148#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
149#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
150#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
151#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
152#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
153#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
154#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
155#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
156#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
157#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
158
159#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
160#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
161#define START (LCD_CONTROL_BLOCK_BASE|0x08)
162#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
163#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
164#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
165#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
166#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
167#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
168#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
169#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
170#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
171#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
172#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
173#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
174#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
175#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
176#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
177#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
178#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
179#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
180#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
181#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
182#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
183#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
184#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
185#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
186#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
187#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
188#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
189#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
190#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
191#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
192#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
193#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
194
195#define SSICTL (SPI_BLOCK_BASE|0x00)
196#define SSITIME (SPI_BLOCK_BASE|0x04)
197#define SSITX (SPI_BLOCK_BASE|0x08)
198#define SSIRX (SPI_BLOCK_BASE|0x0C)
199#define SSIINTC (SPI_BLOCK_BASE|0x10)
200#define SSIINTS (SPI_BLOCK_BASE|0x14)
201#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
202#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
203#define SSIID (SPI_BLOCK_BASE|0x20)
204
205#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
206#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
207#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
208#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
209#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
210
211#define GPIODATA (GPIO_BLOCK_BASE|0x00)
212#define GPIODIR (GPIO_BLOCK_BASE|0x04)
213#define GPIOIS (GPIO_BLOCK_BASE|0x08)
214#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
215#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
216#define GPIOIE (GPIO_BLOCK_BASE|0x14)
217#define GPIORIS (GPIO_BLOCK_BASE|0x18)
218#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
219#define GPIOIC (GPIO_BLOCK_BASE|0x20)
220#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
221#define GPIOPC (GPIO_BLOCK_BASE|0x28)
222#define GPIOID (GPIO_BLOCK_BASE|0x30)
223
224#define SPI_WRITE(reg, val) \
225 { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
226 { 0, 5 },
227
228#define SPI_WRITE1(reg) \
229 { SSITX, (reg) & 0xff }, \
230 { 0, 5 },
231
232struct mddi_table {
233 uint32_t reg;
234 uint32_t value;
235};
236static struct mddi_table mddi_toshiba_init_table[] = {
237 { DPSET0, 0x09e90046 },
238 { DPSET1, 0x00000118 },
239 { DPSUS, 0x00000000 },
240 { DPRUN, 0x00000001 },
241 { 1, 14 }, /* msleep 14 */
242 { SYSCKENA, 0x00000001 },
243 /*{ CLKENB, 0x000000EF } */
244 { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
245 /*{ CLKENB, 0x000025CB }, Clock enable register */
246
247 { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
248 { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
249 { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
250 { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
251 { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
252
253 { GPIOIBE, 0x000003FF },
254 { GPIOIS, 0x00000000 },
255 { GPIOIC, 0x000003FF },
256 { GPIOIE, 0x00000000 },
257
258 { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
259 { 1, 1 }, /* msleep 1 */
260 { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
261 { DRAMPWR, 0x00000001 }, /* eDRAM power */
262};
263
264static struct mddi_table mddi_toshiba_panel_init_table[] = {
265 { SRST, 0x00000003 }, /* FIFO/LCDC not reset */
266 { PORT_ENB, 0x00000001 }, /* Enable sync. Port */
267 { START, 0x00000000 }, /* To stop operation */
268 /*{ START, 0x00000001 }, To start operation */
269 { PORT, 0x00000004 }, /* Polarity of VS/HS/DE. */
270 { CMN, 0x00000000 },
271 { GAMMA, 0x00000000 }, /* No Gamma correction */
272 { INTFLG, 0x00000000 }, /* VSYNC interrupt flag clear/status */
273 { INTMSK, 0x00000000 }, /* VSYNC interrupt mask is off. */
274 { MPLFBUF, 0x00000000 }, /* Select frame buffer's base address. */
275 { HDE_LEFT, 0x00000000 }, /* The value of HDE_LEFT. */
276 { VDE_TOP, 0x00000000 }, /* The value of VDE_TPO. */
277 { PXL, 0x00000001 }, /* 1. RGB666 */
278 /* 2. Data is valid from 1st frame of beginning. */
279 { HDE_START, 0x00000006 }, /* HDE_START= 14 PCLK */
280 { HDE_SIZE, 0x0000009F }, /* HDE_SIZE=320 PCLK */
281 { HSW, 0x00000004 }, /* HSW= 10 PCLK */
282 { VSW, 0x00000001 }, /* VSW=2 HCYCLE */
283 { VDE_START, 0x00000003 }, /* VDE_START=4 HCYCLE */
284 { VDE_SIZE, 0x000001DF }, /* VDE_SIZE=480 HCYCLE */
285 { WAKEUP, 0x000001e2 }, /* Wakeup position in VSYNC mode. */
286 { WSYN_DLY, 0x00000000 }, /* Wakeup position in VSIN mode. */
287 { REGENB, 0x00000001 }, /* Set 1 to enable to change the value of registers. */
288 { CLKENB, 0x000025CB }, /* Clock enable register */
289
290 { SSICTL, 0x00000170 }, /* SSI control register */
291 { SSITIME, 0x00000250 }, /* SSI timing control register */
292 { SSICTL, 0x00000172 }, /* SSI control register */
293};
294
295
296static struct mddi_table mddi_sharp_init_table[] = {
297 { VCYCLE, 0x000001eb },
298 { HCYCLE, 0x000000ae },
299 { REGENB, 0x00000001 }, /* Set 1 to enable to change the value of registers. */
300 { GPIODATA, 0x00040000 }, /* GPIO2 low */
301 { GPIODIR, 0x00000004 }, /* GPIO2 out */
302 { 1, 1 }, /* msleep 1 */
303 { GPIODATA, 0x00040004 }, /* GPIO2 high */
304 { 1, 10 }, /* msleep 10 */
305 SPI_WRITE(0x5f, 0x01)
306 SPI_WRITE1(0x11)
307 { 1, 200 }, /* msleep 200 */
308 SPI_WRITE1(0x29)
309 SPI_WRITE1(0xde)
310 { START, 0x00000001 }, /* To start operation */
311};
312
313static struct mddi_table mddi_sharp_deinit_table[] = {
314 { 1, 200 }, /* msleep 200 */
315 SPI_WRITE(0x10, 0x1)
316 { 1, 100 }, /* msleep 100 */
317 { GPIODATA, 0x00040004 }, /* GPIO2 high */
318 { GPIODIR, 0x00000004 }, /* GPIO2 out */
319 { GPIODATA, 0x00040000 }, /* GPIO2 low */
320 { 1, 10 }, /* msleep 10 */
321};
322
323static struct mddi_table mddi_tpo_init_table[] = {
324 { VCYCLE, 0x000001e5 },
325 { HCYCLE, 0x000000ac },
326 { REGENB, 0x00000001 }, /* Set 1 to enable to change the value of registers. */
327 { 0, 20 }, /* udelay 20 */
328 { GPIODATA, 0x00000004 }, /* GPIO2 high */
329 { GPIODIR, 0x00000004 }, /* GPIO2 out */
330 { 0, 20 }, /* udelay 20 */
331
332 SPI_WRITE(0x08, 0x01)
333 { 0, 500 }, /* udelay 500 */
334 SPI_WRITE(0x08, 0x00)
335 SPI_WRITE(0x02, 0x00)
336 SPI_WRITE(0x03, 0x04)
337 SPI_WRITE(0x04, 0x0e)
338 SPI_WRITE(0x09, 0x02)
339 SPI_WRITE(0x0b, 0x08)
340 SPI_WRITE(0x0c, 0x53)
341 SPI_WRITE(0x0d, 0x01)
342 SPI_WRITE(0x0e, 0xe0)
343 SPI_WRITE(0x0f, 0x01)
344 SPI_WRITE(0x10, 0x58)
345 SPI_WRITE(0x20, 0x1e)
346 SPI_WRITE(0x21, 0x0a)
347 SPI_WRITE(0x22, 0x0a)
348 SPI_WRITE(0x23, 0x1e)
349 SPI_WRITE(0x25, 0x32)
350 SPI_WRITE(0x26, 0x00)
351 SPI_WRITE(0x27, 0xac)
352 SPI_WRITE(0x29, 0x06)
353 SPI_WRITE(0x2a, 0xa4)
354 SPI_WRITE(0x2b, 0x45)
355 SPI_WRITE(0x2c, 0x45)
356 SPI_WRITE(0x2d, 0x15)
357 SPI_WRITE(0x2e, 0x5a)
358 SPI_WRITE(0x2f, 0xff)
359 SPI_WRITE(0x30, 0x6b)
360 SPI_WRITE(0x31, 0x0d)
361 SPI_WRITE(0x32, 0x48)
362 SPI_WRITE(0x33, 0x82)
363 SPI_WRITE(0x34, 0xbd)
364 SPI_WRITE(0x35, 0xe7)
365 SPI_WRITE(0x36, 0x18)
366 SPI_WRITE(0x37, 0x94)
367 SPI_WRITE(0x38, 0x01)
368 SPI_WRITE(0x39, 0x5d)
369 SPI_WRITE(0x3a, 0xae)
370 SPI_WRITE(0x3b, 0xff)
371 SPI_WRITE(0x07, 0x09)
372 { 0, 10 }, /* udelay 10 */
373 { START, 0x00000001 }, /* To start operation */
374};
375
376static struct mddi_table mddi_tpo_deinit_table[] = {
377 SPI_WRITE(0x07, 0x19)
378 { START, 0x00000000 }, /* To stop operation */
379 { GPIODATA, 0x00040004 }, /* GPIO2 high */
380 { GPIODIR, 0x00000004 }, /* GPIO2 out */
381 { GPIODATA, 0x00040000 }, /* GPIO2 low */
382 { 0, 5 }, /* usleep 5 */
383};
384
385
386#define GPIOSEL_VWAKEINT (1U << 0)
387#define INTMASK_VWAKEOUT (1U << 0)
388
389static void sapphire_process_mddi_table(
390 struct msm_mddi_client_data *client_data,
391 const struct mddi_table *table,
392 size_t count)
393{
394 int i;
395 for (i = 0; i < count; i++) {
396 uint32_t reg = table[i].reg;
397 uint32_t value = table[i].value;
398
399 if (reg == 0)
400 udelay(value);
401 else if (reg == 1)
402 msleep(value);
403 else
404 client_data->remote_write(client_data, value, reg);
405 }
406}
407
408static struct vreg *vreg_lcm_2v85;
409
410static void sapphire_mddi_power_client(struct msm_mddi_client_data *client_data,
411 int on)
412{
413 unsigned id, on_off;
414#if DEBUG_SAPPHIRE_PANEL
415 printk(KERN_INFO "sapphire_mddi_client_power:%d\r\n", on);
416#endif
417 if (on) {
418 on_off = 0;
419 id = PM_VREG_PDOWN_MDDI_ID;
420 msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id);
421
422 gpio_set_value(SAPPHIRE_MDDI_1V5_EN, 1);
423 mdelay(5); /* delay time >5ms and <10ms */
424
425 if (is_12pin_camera())
426 gpio_set_value(V_VDDE2E_VDD2_GPIO_5M, 1);
427 else
428 gpio_set_value(V_VDDE2E_VDD2_GPIO, 1);
429
430 gpio_set_value(SAPPHIRE_GPIO_MDDI_32K_EN, 1);
431 msleep(3);
432 id = PM_VREG_PDOWN_AUX_ID;
433 msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id);
434 vreg_enable(vreg_lcm_2v85);
435 msleep(3);
436 } else {
437 gpio_set_value(SAPPHIRE_GPIO_MDDI_32K_EN, 0);
438 gpio_set_value(MDDI_RST_N, 0);
439 msleep(10);
440 vreg_disable(vreg_lcm_2v85);
441 on_off = 1;
442 id = PM_VREG_PDOWN_AUX_ID;
443 msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id);
444 msleep(5);
445 if (is_12pin_camera())
446 gpio_set_value(V_VDDE2E_VDD2_GPIO_5M, 0);
447 else
448 gpio_set_value(V_VDDE2E_VDD2_GPIO, 0);
449
450 msleep(200);
451 gpio_set_value(SAPPHIRE_MDDI_1V5_EN, 0);
452 id = PM_VREG_PDOWN_MDDI_ID;
453 msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id);
454 }
455}
456
457static int sapphire_mddi_toshiba_client_init(
458 struct msm_mddi_bridge_platform_data *bridge_data,
459 struct msm_mddi_client_data *client_data)
460{
461 int panel_id;
462
463 /* Set the MDDI_RST_N accroding to MDDI client repectively(
464 * been set in sapphire_mddi_power_client() originally)
465 */
466 gpio_set_value(MDDI_RST_N, 1);
467 msleep(10);
468
469 client_data->auto_hibernate(client_data, 0);
470 sapphire_process_mddi_table(client_data, mddi_toshiba_init_table,
471 ARRAY_SIZE(mddi_toshiba_init_table));
472 client_data->auto_hibernate(client_data, 1);
473 g_panel_id = panel_id =
474 (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
475 if (panel_id > 1) {
476#if DEBUG_SAPPHIRE_PANEL
477 printk(KERN_ERR "unknown panel id at mddi_enable\n");
478#endif
479 return -1;
480 }
481 return 0;
482}
483
484static int sapphire_mddi_toshiba_client_uninit(
485 struct msm_mddi_bridge_platform_data *bridge_data,
486 struct msm_mddi_client_data *client_data)
487{
488 gpio_set_value(MDDI_RST_N, 0);
489 msleep(10);
490
491 return 0;
492}
493
494static int sapphire_mddi_panel_unblank(
495 struct msm_mddi_bridge_platform_data *bridge_data,
496 struct msm_mddi_client_data *client_data)
497{
498 int panel_id, ret = 0;
499
500 sapphire_set_backlight_level(0);
501 client_data->auto_hibernate(client_data, 0);
502 sapphire_process_mddi_table(client_data, mddi_toshiba_panel_init_table,
503 ARRAY_SIZE(mddi_toshiba_panel_init_table));
504 panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
505 switch (panel_id) {
506 case 0:
507#if DEBUG_SAPPHIRE_PANEL
508 printk(KERN_DEBUG "init sharp panel\n");
509#endif
510 sapphire_process_mddi_table(client_data,
511 mddi_sharp_init_table,
512 ARRAY_SIZE(mddi_sharp_init_table));
513 break;
514 case 1:
515#if DEBUG_SAPPHIRE_PANEL
516 printk(KERN_DEBUG "init tpo panel\n");
517#endif
518 sapphire_process_mddi_table(client_data,
519 mddi_tpo_init_table,
520 ARRAY_SIZE(mddi_tpo_init_table));
521 break;
522 default:
523
524 printk(KERN_DEBUG "unknown panel_id: %d\n", panel_id);
525 ret = -1;
526 };
527 mutex_lock(&sapphire_backlight_lock);
528 sapphire_set_backlight_level(sapphire_backlight_brightness);
529 sapphire_backlight_off = 0;
530 mutex_unlock(&sapphire_backlight_lock);
531 client_data->auto_hibernate(client_data, 1);
532 /* reenable vsync */
533 client_data->remote_write(client_data, GPIOSEL_VWAKEINT,
534 GPIOSEL);
535 client_data->remote_write(client_data, INTMASK_VWAKEOUT,
536 INTMASK);
537 return ret;
538
539}
540
541static int sapphire_mddi_panel_blank(
542 struct msm_mddi_bridge_platform_data *bridge_data,
543 struct msm_mddi_client_data *client_data)
544{
545 int panel_id, ret = 0;
546
547 panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
548 client_data->auto_hibernate(client_data, 0);
549 switch (panel_id) {
550 case 0:
551 printk(KERN_DEBUG "deinit sharp panel\n");
552 sapphire_process_mddi_table(client_data,
553 mddi_sharp_deinit_table,
554 ARRAY_SIZE(mddi_sharp_deinit_table));
555 break;
556 case 1:
557 printk(KERN_DEBUG "deinit tpo panel\n");
558 sapphire_process_mddi_table(client_data,
559 mddi_tpo_deinit_table,
560 ARRAY_SIZE(mddi_tpo_deinit_table));
561 break;
562 default:
563 printk(KERN_DEBUG "unknown panel_id: %d\n", panel_id);
564 ret = -1;
565 };
566 client_data->auto_hibernate(client_data, 1);
567 mutex_lock(&sapphire_backlight_lock);
568 sapphire_set_backlight_level(0);
569 sapphire_backlight_off = 1;
570 mutex_unlock(&sapphire_backlight_lock);
571 client_data->remote_write(client_data, 0, SYSCLKENA);
572 client_data->remote_write(client_data, 1, DPSUS);
573
574 return ret;
575}
576
577
578/* Initial sequence of sharp panel with Novatek NT35399 MDDI client */
579static const struct mddi_table sharp2_init_table[] = {
580 { 0x02A0, 0x00 },
581 { 0x02A1, 0x00 },
582 { 0x02A2, 0x3F },
583 { 0x02A3, 0x01 },
584 { 0x02B0, 0x00 },
585 { 0x02B1, 0x00 },
586 { 0x02B2, 0xDF },
587 { 0x02B3, 0x01 },
588 { 0x02D0, 0x00 },
589 { 0x02D1, 0x00 },
590 { 0x02D2, 0x00 },
591 { 0x02D3, 0x00 },
592 { 0x0350, 0x80 }, /* Set frame tearing effect(FTE) position */
593 { 0x0351, 0x00 },
594 { 0x0360, 0x30 },
595 { 0x0361, 0xC1 },
596 { 0x0362, 0x00 },
597 { 0x0370, 0x00 },
598 { 0x0371, 0xEF },
599 { 0x0372, 0x01 },
600
601 { 0x0B00, 0x10 },
602
603 { 0x0B10, 0x00 },
604 { 0x0B20, 0x22 },
605 { 0x0B30, 0x46 },
606 { 0x0B40, 0x07 },
607 { 0x0B41, 0x1C },
608 { 0x0B50, 0x0F },
609 { 0x0B51, 0x7A },
610 { 0x0B60, 0x16 },
611 { 0x0B70, 0x0D },
612 { 0x0B80, 0x04 },
613 { 0x0B90, 0x07 },
614 { 0x0BA0, 0x04 },
615 { 0x0BA1, 0x86 },
616 { 0x0BB0, 0xFF },
617 { 0x0BB1, 0x01 },
618 { 0x0BB2, 0xF7 },
619 { 0x0BB3, 0x01 },
620 { 0x0BC0, 0x00 },
621 { 0x0BC1, 0x00 },
622 { 0x0BC2, 0x00 },
623 { 0x0BC3, 0x00 },
624 { 0x0BE0, 0x01 },
625 { 0x0BE1, 0x3F },
626
627 { 0x0BF0, 0x03 },
628
629 { 0x0C10, 0x02 },
630
631 { 0x0C30, 0x22 },
632 { 0x0C31, 0x20 },
633 { 0x0C40, 0x48 },
634 { 0x0C41, 0x06 },
635
636 { 0xE00, 0x0028},
637 { 0xE01, 0x002F},
638 { 0xE02, 0x0032},
639 { 0xE03, 0x000A},
640 { 0xE04, 0x0023},
641 { 0xE05, 0x0024},
642 { 0xE06, 0x0022},
643 { 0xE07, 0x0012},
644 { 0xE08, 0x000D},
645 { 0xE09, 0x0035},
646 { 0xE0A, 0x000E},
647 { 0xE0B, 0x001A},
648 { 0xE0C, 0x003C},
649 { 0xE0D, 0x003A},
650 { 0xE0E, 0x0050},
651 { 0xE0F, 0x0069},
652 { 0xE10, 0x0006},
653 { 0xE11, 0x001F},
654 { 0xE12, 0x0035},
655 { 0xE13, 0x0020},
656 { 0xE14, 0x0043},
657 { 0xE15, 0x0030},
658 { 0xE16, 0x003C},
659 { 0xE17, 0x0010},
660 { 0xE18, 0x0009},
661 { 0xE19, 0x0051},
662 { 0xE1A, 0x001D},
663 { 0xE1B, 0x003C},
664 { 0xE1C, 0x0053},
665 { 0xE1D, 0x0041},
666 { 0xE1E, 0x0045},
667 { 0xE1F, 0x004B},
668 { 0xE20, 0x000A},
669 { 0xE21, 0x0014},
670 { 0xE22, 0x001C},
671 { 0xE23, 0x0013},
672 { 0xE24, 0x002E},
673 { 0xE25, 0x0029},
674 { 0xE26, 0x001B},
675 { 0xE27, 0x0014},
676 { 0xE28, 0x000E},
677 { 0xE29, 0x0032},
678 { 0xE2A, 0x000D},
679 { 0xE2B, 0x001B},
680 { 0xE2C, 0x0033},
681 { 0xE2D, 0x0033},
682 { 0xE2E, 0x005B},
683 { 0xE2F, 0x0069},
684 { 0xE30, 0x0006},
685 { 0xE31, 0x0014},
686 { 0xE32, 0x003D},
687 { 0xE33, 0x0029},
688 { 0xE34, 0x0042},
689 { 0xE35, 0x0032},
690 { 0xE36, 0x003F},
691 { 0xE37, 0x000E},
692 { 0xE38, 0x0008},
693 { 0xE39, 0x0059},
694 { 0xE3A, 0x0015},
695 { 0xE3B, 0x002E},
696 { 0xE3C, 0x0049},
697 { 0xE3D, 0x0058},
698 { 0xE3E, 0x0061},
699 { 0xE3F, 0x006B},
700 { 0xE40, 0x000A},
701 { 0xE41, 0x001A},
702 { 0xE42, 0x0022},
703 { 0xE43, 0x0014},
704 { 0xE44, 0x002F},
705 { 0xE45, 0x002A},
706 { 0xE46, 0x001A},
707 { 0xE47, 0x0014},
708 { 0xE48, 0x000E},
709 { 0xE49, 0x002F},
710 { 0xE4A, 0x000F},
711 { 0xE4B, 0x001B},
712 { 0xE4C, 0x0030},
713 { 0xE4D, 0x002C},
714 { 0xE4E, 0x0051},
715 { 0xE4F, 0x0069},
716 { 0xE50, 0x0006},
717 { 0xE51, 0x001E},
718 { 0xE52, 0x0043},
719 { 0xE53, 0x002F},
720 { 0xE54, 0x0043},
721 { 0xE55, 0x0032},
722 { 0xE56, 0x0043},
723 { 0xE57, 0x000D},
724 { 0xE58, 0x0008},
725 { 0xE59, 0x0059},
726 { 0xE5A, 0x0016},
727 { 0xE5B, 0x0030},
728 { 0xE5C, 0x004B},
729 { 0xE5D, 0x0051},
730 { 0xE5E, 0x005A},
731 { 0xE5F, 0x006B},
732
733 { 0x0290, 0x01 },
734};
735
736#undef TPO2_ONE_GAMMA
737/* Initial sequence of TPO panel with Novatek NT35399 MDDI client */
738
739static const struct mddi_table tpo2_init_table[] = {
740 /* Panel interface control */
741 { 0xB30, 0x44 },
742 { 0xB40, 0x00 },
743 { 0xB41, 0x87 },
744 { 0xB50, 0x06 },
745 { 0xB51, 0x7B },
746 { 0xB60, 0x0E },
747 { 0xB70, 0x0F },
748 { 0xB80, 0x03 },
749 { 0xB90, 0x00 },
750 { 0x350, 0x70 }, /* FTE is at line 0x70 */
751
752 /* Entry Mode */
753 { 0x360, 0x30 },
754 { 0x361, 0xC1 },
755 { 0x362, 0x04 },
756
757/* 0x2 for gray scale gamma correction, 0x12 for RGB gamma correction */
758#ifdef TPO2_ONE_GAMMA
759 { 0xB00, 0x02 },
760#else
761 { 0xB00, 0x12 },
762#endif
763 /* Driver output control */
764 { 0x371, 0xEF },
765 { 0x372, 0x03 },
766
767 /* DCDC on glass control */
768 { 0xC31, 0x10 },
769 { 0xBA0, 0x00 },
770 { 0xBA1, 0x86 },
771
772 /* VCOMH voltage control */
773 { 0xC50, 0x3b },
774
775 /* Special function control */
776 { 0xC10, 0x82 },
777
778 /* Power control */
779 { 0xC40, 0x44 },
780 { 0xC41, 0x02 },
781
782 /* Source output control */
783 { 0xBE0, 0x01 },
784 { 0xBE1, 0x00 },
785
786 /* Windows address setting */
787 { 0x2A0, 0x00 },
788 { 0x2A1, 0x00 },
789 { 0x2A2, 0x3F },
790 { 0x2A3, 0x01 },
791 { 0x2B0, 0x00 },
792 { 0x2B1, 0x00 },
793 { 0x2B2, 0xDF },
794 { 0x2B3, 0x01 },
795
796 /* RAM address setting */
797 { 0x2D0, 0x00 },
798 { 0x2D1, 0x00 },
799 { 0x2D2, 0x00 },
800 { 0x2D3, 0x00 },
801
802 { 0xF20, 0x55 },
803 { 0xF21, 0xAA },
804 { 0xF22, 0x66 },
805 { 0xF57, 0x45 },
806
807/*
808 * The NT35399 provides gray or RGB gamma correction table,
809 * which determinated by register-0xb00, and following table
810 */
811#ifdef TPO2_ONE_GAMMA
812 /* Positive Gamma setting */
813 { 0xE00, 0x04 },
814 { 0xE01, 0x12 },
815 { 0xE02, 0x18 },
816 { 0xE03, 0x10 },
817 { 0xE04, 0x29 },
818 { 0xE05, 0x26 },
819 { 0xE06, 0x1f },
820 { 0xE07, 0x11 },
821 { 0xE08, 0x0c },
822 { 0xE09, 0x3a },
823 { 0xE0A, 0x0d },
824 { 0xE0B, 0x28 },
825 { 0xE0C, 0x40 },
826 { 0xE0D, 0x4e },
827 { 0xE0E, 0x6f },
828 { 0xE0F, 0x5E },
829
830 /* Negative Gamma setting */
831 { 0xE10, 0x0B },
832 { 0xE11, 0x00 },
833 { 0xE12, 0x00 },
834 { 0xE13, 0x1F },
835 { 0xE14, 0x4b },
836 { 0xE15, 0x33 },
837 { 0xE16, 0x13 },
838 { 0xE17, 0x12 },
839 { 0xE18, 0x0d },
840 { 0xE19, 0x2f },
841 { 0xE1A, 0x16 },
842 { 0xE1B, 0x2e },
843 { 0xE1C, 0x49 },
844 { 0xE1D, 0x41 },
845 { 0xE1E, 0x46 },
846 { 0xE1F, 0x55 },
847#else
848 /* Red Positive Gamma */
849 { 0xE00, 0x0f },
850 { 0xE01, 0x19 },
851 { 0xE02, 0x22 },
852 { 0xE03, 0x0b },
853 { 0xE04, 0x23 },
854 { 0xE05, 0x23 },
855 { 0xE06, 0x14 },
856 { 0xE07, 0x13 },
857 { 0xE08, 0x0f },
858 { 0xE09, 0x2a },
859 { 0xE0A, 0x0d },
860 { 0xE0B, 0x26 },
861 { 0xE0C, 0x43 },
862 { 0xE0D, 0x20 },
863 { 0xE0E, 0x2a },
864 { 0xE0F, 0x5c },
865
866 /* Red Negative Gamma */
867 { 0xE10, 0x0d },
868 { 0xE11, 0x45 },
869 { 0xE12, 0x4c },
870 { 0xE13, 0x1c },
871 { 0xE14, 0x4d },
872 { 0xE15, 0x33 },
873 { 0xE16, 0x23 },
874 { 0xE17, 0x0f },
875 { 0xE18, 0x0b },
876 { 0xE19, 0x3a },
877 { 0xE1A, 0x19 },
878 { 0xE1B, 0x32 },
879 { 0xE1C, 0x4e },
880 { 0xE1D, 0x37 },
881 { 0xE1E, 0x38 },
882 { 0xE1F, 0x3b },
883
884 /* Green Positive Gamma */
885 { 0xE20, 0x00 },
886 { 0xE21, 0x09 },
887 { 0xE22, 0x10 },
888 { 0xE23, 0x0f },
889 { 0xE24, 0x29 },
890 { 0xE25, 0x23 },
891 { 0xE26, 0x0b },
892 { 0xE27, 0x14 },
893 { 0xE28, 0x12 },
894 { 0xE29, 0x25 },
895 { 0xE2A, 0x12 },
896 { 0xE2B, 0x2f },
897 { 0xE2C, 0x43 },
898 { 0xE2D, 0x2d },
899 { 0xE2E, 0x52 },
900 { 0xE2F, 0x61 },
901
902 /* Green Negative Gamma */
903 { 0xE30, 0x08 },
904 { 0xE31, 0x1d },
905 { 0xE32, 0x3f },
906 { 0xE33, 0x1c },
907 { 0xE34, 0x44 },
908 { 0xE35, 0x2e },
909 { 0xE36, 0x28 },
910 { 0xE37, 0x0c },
911 { 0xE38, 0x0a },
912 { 0xE39, 0x42 },
913 { 0xE3A, 0x17 },
914 { 0xE3B, 0x30 },
915 { 0xE3C, 0x4b },
916 { 0xE3D, 0x3f },
917 { 0xE3E, 0x43 },
918 { 0xE3F, 0x45 },
919
920 /* Blue Positive Gamma */
921 { 0xE40, 0x32 },
922 { 0xE41, 0x32 },
923 { 0xE42, 0x31 },
924 { 0xE43, 0x06 },
925 { 0xE44, 0x08 },
926 { 0xE45, 0x0d },
927 { 0xE46, 0x04 },
928 { 0xE47, 0x14 },
929 { 0xE48, 0x0f },
930 { 0xE49, 0x1d },
931 { 0xE4A, 0x1a },
932 { 0xE4B, 0x39 },
933 { 0xE4C, 0x4c },
934 { 0xE4D, 0x1e },
935 { 0xE4E, 0x43 },
936 { 0xE4F, 0x61 },
937
938 /* Blue Negative Gamma */
939 { 0xE50, 0x08 },
940 { 0xE51, 0x2c },
941 { 0xE52, 0x4e },
942 { 0xE53, 0x13 },
943 { 0xE54, 0x3a },
944 { 0xE55, 0x26 },
945 { 0xE56, 0x30 },
946 { 0xE57, 0x0f },
947 { 0xE58, 0x0a },
948 { 0xE59, 0x49 },
949 { 0xE5A, 0x34 },
950 { 0xE5B, 0x4a },
951 { 0xE5C, 0x53 },
952 { 0xE5D, 0x28 },
953 { 0xE5E, 0x26 },
954 { 0xE5F, 0x27 },
955
956#endif
957 /* Sleep in mode */
958 { 0x110, 0x00 },
959 { 0x1, 0x23 },
960 /* Display on mode */
961 { 0x290, 0x00 },
962 { 0x1, 0x27 },
963 /* Driver output control */
964 { 0x372, 0x01 },
965 { 0x1, 0x40 },
966 /* Display on mode */
967 { 0x290, 0x01 },
968};
969
970static const struct mddi_table tpo2_display_on[] = {
971 { 0x290, 0x01 },
972};
973
974static const struct mddi_table tpo2_display_off[] = {
975 { 0x110, 0x01 },
976 { 0x290, 0x00 },
977 { 0x1, 100 },
978};
979
980static const struct mddi_table tpo2_power_off[] = {
981 { 0x0110, 0x01 },
982};
983
984static int nt35399_detect_panel(struct msm_mddi_client_data *client_data)
985{
986 int id = -1, i ;
987
988 /* If the MDDI client is failed to report the panel ID,
989 * perform retrial 5 times.
990 */
991 for( i=0; i < 5; i++ ) {
992 client_data->remote_write(client_data, 0, 0x110);
993 msleep(5);
994 id = client_data->remote_read(client_data, userid) ;
995 if( id == 0 || id == 1 ) {
996 if(i==0) {
997 printk(KERN_ERR "%s: got valid panel ID=%d, "
998 "without retry\n",
999 __FUNCTION__, id);
1000 }
1001 else {
1002 printk(KERN_ERR "%s: got valid panel ID=%d, "
1003 "after %d retry\n",
1004 __FUNCTION__, id, i+1);
1005 }
1006 break ;
1007 }
1008 printk(KERN_ERR "%s: got invalid panel ID:%d, trial #%d\n",
1009 __FUNCTION__, id, i+1);
1010
1011 gpio_set_value(MDDI_RST_N, 0);
1012 msleep(5);
1013
1014 gpio_set_value(MDDI_RST_N, 1);
1015 msleep(10);
1016 gpio_set_value(MDDI_RST_N, 0);
1017 udelay(100);
1018 gpio_set_value(MDDI_RST_N, 1);
1019 mdelay(10);
1020 }
1021 printk(KERN_INFO "%s: final panel id=%d\n", __FUNCTION__, id);
1022
1023 switch(id) {
1024 case 0:
1025 return SAPPHIRE_PANEL_TOPPOLY;
1026 case 1:
1027 return SAPPHIRE_PANEL_SHARP;
1028 default :
1029 printk(KERN_ERR "%s(): Invalid panel ID: %d, "
1030 "treat as sharp panel.", __FUNCTION__, id);
1031 return SAPPHIRE_PANEL_SHARP;
1032 }
1033}
1034
1035static int nt35399_client_init(
1036 struct msm_mddi_bridge_platform_data *bridge_data,
1037 struct msm_mddi_client_data *client_data)
1038{
1039 int panel_id;
1040
1041 if (g_panel_inited == 0) {
1042 g_panel_id = panel_id = nt35399_detect_panel(client_data);
1043 g_panel_inited = 1 ;
1044 } else {
1045 gpio_set_value(MDDI_RST_N, 1);
1046 msleep(10);
1047 gpio_set_value(MDDI_RST_N, 0);
1048 udelay(100);
1049 gpio_set_value(MDDI_RST_N, 1);
1050 mdelay(10);
1051
1052 g_panel_id = panel_id = nt35399_detect_panel(client_data);
1053 if (panel_id == -1) {
1054 printk("Invalid panel id\n");
1055 return -1;
1056 }
1057
1058 client_data->auto_hibernate(client_data, 0);
1059 if (panel_id == SAPPHIRE_PANEL_TOPPOLY) {
1060 sapphire_process_mddi_table(client_data, tpo2_init_table,
1061 ARRAY_SIZE(tpo2_init_table));
1062 } else if(panel_id == SAPPHIRE_PANEL_SHARP) {
1063 sapphire_process_mddi_table(client_data, sharp2_init_table,
1064 ARRAY_SIZE(sharp2_init_table));
1065 }
1066
1067 client_data->auto_hibernate(client_data, 1);
1068 }
1069
1070 return 0;
1071}
1072
1073static int nt35399_client_uninit(
1074 struct msm_mddi_bridge_platform_data *bridge_data,
1075 struct msm_mddi_client_data *cdata)
1076{
1077 return 0;
1078}
1079
1080static int nt35399_panel_unblank(
1081 struct msm_mddi_bridge_platform_data *bridge_data,
1082 struct msm_mddi_client_data *client_data)
1083{
1084 int ret = 0;
1085
1086 mdelay(20);
1087 sapphire_set_backlight_level(0);
1088 client_data->auto_hibernate(client_data, 0);
1089
1090 mutex_lock(&sapphire_backlight_lock);
1091 sapphire_set_backlight_level(sapphire_backlight_brightness);
1092 sapphire_backlight_off = 0;
1093 mutex_unlock(&sapphire_backlight_lock);
1094
1095 client_data->auto_hibernate(client_data, 1);
1096
1097 return ret;
1098}
1099
1100static int nt35399_panel_blank(
1101 struct msm_mddi_bridge_platform_data *bridge_data,
1102 struct msm_mddi_client_data *client_data)
1103{
1104 int ret = 0;
1105
1106 client_data->auto_hibernate(client_data, 0);
1107 sapphire_process_mddi_table(client_data, tpo2_display_off,
1108 ARRAY_SIZE(tpo2_display_off));
1109 client_data->auto_hibernate(client_data, 1);
1110
1111 mutex_lock(&sapphire_backlight_lock);
1112 sapphire_set_backlight_level(0);
1113 sapphire_backlight_off = 1;
1114 mutex_unlock(&sapphire_backlight_lock);
1115
1116 return ret;
1117}
1118
1119static void sapphire_brightness_set(struct led_classdev *led_cdev, enum led_brightness value)
1120{
1121 mutex_lock(&sapphire_backlight_lock);
1122 sapphire_backlight_brightness = value;
1123 if (!sapphire_backlight_off)
1124 sapphire_set_backlight_level(sapphire_backlight_brightness);
1125 mutex_unlock(&sapphire_backlight_lock);
1126}
1127
1128static struct led_classdev sapphire_backlight_led = {
1129 .name = "lcd-backlight",
1130 .brightness = SAPPHIRE_DEFAULT_BACKLIGHT_BRIGHTNESS,
1131 .brightness_set = sapphire_brightness_set,
1132};
1133
1134static int sapphire_backlight_probe(struct platform_device *pdev)
1135{
1136 led_classdev_register(&pdev->dev, &sapphire_backlight_led);
1137 return 0;
1138}
1139
1140static int sapphire_backlight_remove(struct platform_device *pdev)
1141{
1142 led_classdev_unregister(&sapphire_backlight_led);
1143 return 0;
1144}
1145
1146static struct platform_driver sapphire_backlight_driver = {
1147 .probe = sapphire_backlight_probe,
1148 .remove = sapphire_backlight_remove,
1149 .driver = {
1150 .name = "sapphire-backlight",
1151 .owner = THIS_MODULE,
1152 },
1153};
1154
1155static struct resource resources_msm_fb[] = {
1156 {
1157 .start = SMI64_MSM_FB_BASE,
1158 .end = SMI64_MSM_FB_BASE + SMI64_MSM_FB_SIZE - 1,
1159 .flags = IORESOURCE_MEM,
1160 },
1161};
1162
1163static struct msm_mddi_bridge_platform_data toshiba_client_data = {
1164 .init = sapphire_mddi_toshiba_client_init,
1165 .uninit = sapphire_mddi_toshiba_client_uninit,
1166 .blank = sapphire_mddi_panel_blank,
1167 .unblank = sapphire_mddi_panel_unblank,
1168 .fb_data = {
1169 .xres = 320,
1170 .yres = 480,
1171 .width = 45,
1172 .height = 67,
1173 .output_format = 0,
1174 },
1175};
1176
1177#define NT35399_MFR_NAME 0x0bda
1178#define NT35399_PRODUCT_CODE 0x8a47
1179
1180static void nt35399_fixup(uint16_t * mfr_name, uint16_t * product_code)
1181{
1182 printk(KERN_DEBUG "%s: enter.\n", __func__);
1183 *mfr_name = NT35399_MFR_NAME ;
1184 *product_code= NT35399_PRODUCT_CODE ;
1185}
1186
1187static struct msm_mddi_bridge_platform_data nt35399_client_data = {
1188
1189 .init = nt35399_client_init,
1190 .uninit = nt35399_client_uninit,
1191 .blank = nt35399_panel_blank,
1192 .unblank = nt35399_panel_unblank,
1193 .fb_data = {
1194 .xres = 320,
1195 .yres = 480,
1196 .output_format = 0,
1197 },
1198};
1199
1200static struct msm_mddi_platform_data mddi_pdata = {
1201 .clk_rate = 122880000,
1202 .power_client = sapphire_mddi_power_client,
1203 .fixup = nt35399_fixup,
1204 .vsync_irq = MSM_GPIO_TO_INT(VSYNC_GPIO),
1205 .fb_resource = resources_msm_fb,
1206 .num_clients = 2,
1207 .client_platform_data = {
1208 {
1209 .product_id = (0xd263 << 16 | 0),
1210 .name = "mddi_c_d263_0000",
1211 .id = 0,
1212 .client_data = &toshiba_client_data,
1213 .clk_rate = 0,
1214 },
1215 {
1216 .product_id =
1217 (NT35399_MFR_NAME << 16 | NT35399_PRODUCT_CODE),
1218 .name = "mddi_c_simple" ,
1219 .id = 0,
1220 .client_data = &nt35399_client_data,
1221 .clk_rate = 0,
1222 },
1223 },
1224};
1225
1226static struct platform_device sapphire_backlight = {
1227 .name = "sapphire-backlight",
1228};
1229
1230int __init sapphire_init_panel(void)
1231{
1232 int rc = -1;
1233 uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA); /* GPIO27 */
1234
1235 if (!machine_is_sapphire())
1236 return 0;
1237
1238 /* checking board as soon as possible */
1239 printk("sapphire_init_panel:machine_is_sapphire=%d, machine_arch_type=%d, MACH_TYPE_SAPPHIRE=%d\r\n", machine_is_sapphire(), machine_arch_type, MACH_TYPE_SAPPHIRE);
1240 if (!machine_is_sapphire())
1241 return 0;
1242
1243 vreg_lcm_2v85 = vreg_get(0, "gp4");
1244 if (IS_ERR(vreg_lcm_2v85))
1245 return PTR_ERR(vreg_lcm_2v85);
1246
1247 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
1248
1249 /* setup FB by SMI size */
1250 if (sapphire_get_smi_size() == 32) {
1251 resources_msm_fb[0].start = SMI32_MSM_FB_BASE;
1252 resources_msm_fb[0].end = SMI32_MSM_FB_BASE + SMI32_MSM_FB_SIZE - 1;
1253 }
1254
1255 rc = gpio_request(VSYNC_GPIO, "vsync");
1256 if (rc)
1257 return rc;
1258 rc = gpio_direction_input(VSYNC_GPIO);
1259 if (rc)
1260 return rc;
1261 rc = platform_device_register(&msm_device_mdp);
1262 if (rc)
1263 return rc;
1264 msm_device_mddi0.dev.platform_data = &mddi_pdata;
1265 rc = platform_device_register(&msm_device_mddi0);
1266 if (rc)
1267 return rc;
1268 platform_device_register(&sapphire_backlight);
1269 return platform_driver_register(&sapphire_backlight_driver);
1270}
1271
1272device_initcall(sapphire_init_panel);