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gerrit-public.fairphone.software / kernel / msm / edd98336b35d36d8d871d78e16da4fe33b0d4df6 / . / arch / arm / mach-msm / msm_bus / msm_bus_board_8974.c
blob: 1f6e50830f43bf5fb7361795f28aeb6f0feeba7e [file] [log] [blame]
Gagan Macca0254a2013-01-11 14:01:11 -0700[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/module.h>
18#include <mach/msm_bus.h>
19#include <mach/msm_bus_board.h>
20#include <mach/board.h>
21#include <mach/rpm.h>
22#include "msm_bus_core.h"
23#include "msm_bus_noc.h"
24#include "msm_bus_bimc.h"
25
26#define NMASTERS 120
27#define NSLAVES 150
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]28#define NFAB_8974 7
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]29
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]30enum msm_bus_8974_master_ports_type {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]31 /* System NOC Masters */
32 MASTER_PORT_LPASS_AHB = 0,
33 MASTER_PORT_QDSS_BAM,
34 MASTER_PORT_SNOC_CFG,
35 MASTER_PORT_GW_BIMC_SNOC,
36 MASTER_PORT_GW_CNOC_SNOC,
37 MASTER_PORT_CRYPTO_CORE0,
38 MASTER_PORT_CRYPTO_CORE1,
39 MASTER_PORT_LPASS_PROC,
40 MASTER_PORT_MSS,
41 MASTER_PORT_MSS_NAV,
42 MASTER_PORT_OCMEM_DMA,
43 MASTER_PORT_GW_PNOC_SNOC,
44 MASTER_PORT_WCSS,
45 MASTER_PORT_QDSS_ETR,
46 MASTER_PORT_USB3,
47
48 /* MMSS NOC Masters */
49 MASTER_PORT_GW_CNOC_MNOC_MMSS_CFG = 0,
50 MASTER_PORT_GW_CNOC_MNOC_CFG,
51 MASTER_PORT_GFX3D_PORT0,
52 MASTER_PORT_GFX3D_PORT1,
53 MASTER_PORT_JPEG,
54 MASTER_PORT_MDP,
55 /* Venus video core */
56 MASTER_PORT_VIDEO_PORT0,
57 MASTER_PORT_VIDEO_PORT1,
58 MASTER_PORT_VFE = 16,
59
60 /* BIMC Masters */
61 MASTER_PORT_KMPSS_M0 = 0,
62 MASTER_PORT_KMPSS_M1,
63 MASTER_PORT_MSS_PROC,
64 MASTER_PORT_GW_MNOC_BIMC_0,
65 MASTER_PORT_GW_MNOC_BIMC_1,
66 MASTER_PORT_GW_SNOC_BIMC_0,
67 MASTER_PORT_GW_SNOC_BIMC_1,
68
69 /* OCMEM NOC Masters */
70 MASTER_PORT_CNOC_ONOC_CFG = 0,
71 MASTER_PORT_JPEG_OCMEM,
72 MASTER_PORT_MDP_OCMEM,
73 MASTER_PORT_VIDEO_P0_OCMEM,
74 MASTER_PORT_VIDEO_P1_OCMEM,
75 MASTER_PORT_VFE_OCMEM,
76
77 /* Peripheral NOC Masters */
78 MASTER_PORT_SDCC_1 = 0,
79 MASTER_PORT_SDCC_3,
80 MASTER_PORT_SDCC_2,
81 MASTER_PORT_SDCC_4,
82 MASTER_PORT_TSIF,
83 MASTER_PORT_BAM_DMA,
84 MASTER_PORT_BLSP_2,
85 MASTER_PORT_USB_HSIC,
86 MASTER_PORT_BLSP_1,
87 MASTER_PORT_USB_HS,
88 MASTER_PORT_PNOC_CFG,
89 MASTER_PORT_GW_SNOC_PNOC,
90
91 /* Config NOC Masters */
92 MASTER_PORT_RPM_INST = 0,
93 MASTER_PORT_RPM_DATA,
94 MASTER_PORT_RPM_SYS,
95 MASTER_PORT_DEHR,
96 MASTER_PORT_QDSS_DAP,
97 MASTER_PORT_SPDM,
98 MASTER_PORT_TIC,
99 MASTER_PORT_GW_SNOC_CNOC,
100};
101
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]102enum msm_bus_8974_slave_ports_type {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]103 /* System NOC Slaves */
104 SLAVE_PORT_KMPSS = 1,
105 SLAVE_PORT_LPASS,
106 SLAVE_PORT_USB3 = 4,
107 SLAVE_PORT_WCSS = 6,
108 SLAVE_PORT_GW_SNOC_BIMC_P0,
109 SLAVE_PORT_GW_SNOC_BIMC_P1,
110 SLAVE_PORT_GW_SNOC_CNOC,
111 SLAVE_PORT_OCIMEM,
112 SLAVE_PORT_SNOC_OCMEM,
113 SLAVE_PORT_GW_SNOC_PNOC,
114 SLAVE_PORT_SERVICE_SNOC,
115 SLAVE_PORT_QDSS_STM,
116
117 /* MMSS NOC Slaves */
118 SLAVE_PORT_CAMERA_CFG = 0,
119 SLAVE_PORT_DISPLAY_CFG,
120 SLAVE_PORT_OCMEM_CFG,
121 SLAVE_PORT_CPR_CFG,
122 SLAVE_PORT_CPR_XPU_CFG,
123 SLAVE_PORT_MISC_CFG = 6,
124 SLAVE_PORT_MISC_XPU_CFG,
125 SLAVE_PORT_VENUS_CFG,
126 SLAVE_PORT_GFX3D_CFG,
127 SLAVE_PORT_MMSS_CLK_CFG = 11,
128 SLAVE_PORT_MMSS_CLK_XPU_CFG,
129 SLAVE_PORT_MNOC_MPU_CFG,
130 SLAVE_PORT_ONOC_MPU_CFG,
131 SLAVE_PORT_GW_MMSS_BIMC_P0 = 16,
132 SLAVE_PORT_GW_MMSS_BIMC_P1,
133 SLAVE_PORT_SERVICE_MNOC,
134
135 /* BIMC Slaves */
136 SLAVE_PORT_EBI1_CH0 = 0,
137 SLAVE_PORT_EBI1_CH1,
138 SLAVE_PORT_KMPSS_L2,
139 SLAVE_PORT_GW_BIMC_SNOC,
140
141 /* OCMEM NOC Slaves */
142 SLAVE_PORT_OCMEM_P0 = 0,
143 SLAVE_PORT_OCMEM_P1,
144 SLAVE_PORT_SERVICE_ONOC,
145
146 /*Peripheral NOC Slaves */
147 SLAVE_PORT_SDCC_1 = 0,
148 SLAVE_PORT_SDCC_3,
149 SLAVE_PORT_SDCC_2,
150 SLAVE_PORT_SDCC_4,
151 SLAVE_PORT_TSIF,
152 SLAVE_PORT_BAM_DMA,
153 SLAVE_PORT_BLSP_2,
154 SLAVE_PORT_USB_HSIC,
155 SLAVE_PORT_BLSP_1,
156 SLAVE_PORT_USB_HS,
157 SLAVE_PORT_PDM,
158 SLAVE_PORT_PERIPH_APU_CFG,
159 SLAVE_PORT_PNOC_MPU_CFG,
160 SLAVE_PORT_PRNG,
161 SLAVE_PORT_GW_PNOC_SNOC,
162 SLAVE_PORT_SERVICE_PNOC,
163
164 /* Config NOC slaves */
165 SLAVE_PORT_CLK_CTL = 1,
166 SLAVE_PORT_CNOC_MSS,
167 SLAVE_PORT_SECURITY,
168 SLAVE_PORT_TCSR,
169 SLAVE_PORT_TLMM,
170 SLAVE_PORT_CRYPTO_0_CFG,
171 SLAVE_PORT_CRYPTO_1_CFG,
172 SLAVE_PORT_IMEM_CFG,
173 SLAVE_PORT_MESSAGE_RAM,
174 SLAVE_PORT_BIMC_CFG,
175 SLAVE_PORT_BOOT_ROM,
176 SLAVE_PORT_CNOC_MNOC_MMSS_CFG,
177 SLAVE_PORT_PMIC_ARB,
178 SLAVE_PORT_SPDM_WRAPPER,
179 SLAVE_PORT_DEHR_CFG,
180 SLAVE_PORT_MPM,
181 SLAVE_PORT_QDSS_CFG,
182 SLAVE_PORT_RBCPR_CFG,
183 SLAVE_PORT_RBCPR_QDSS_APU_CFG,
184 SLAVE_PORT_CNOC_MNOC_CFG,
185 SLAVE_PORT_SNOC_MPU_CFG,
186 SLAVE_PORT_CNOC_ONOC_CFG,
187 SLAVE_PORT_PNOC_CFG,
188 SLAVE_PORT_SNOC_CFG,
189 SLAVE_PORT_EBI1_DLL_CFG,
190 SLAVE_PORT_PHY_APU_CFG,
191 SLAVE_PORT_EBI1_PHY_CFG,
192 SLAVE_PORT_RPM,
193 SLAVE_PORT_GW_CNOC_SNOC,
194 SLAVE_PORT_SERVICE_CNOC,
195};
196
197/* Hardware IDs for RPM */
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]198enum msm_bus_8974_mas_hw_id {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]199 MAS_APPSS_PROC = 0,
200 MAS_AMSS_PROC,
201 MAS_MNOC_BIMC,
202 MAS_SNOC_BIMC,
203 MAS_CNOC_MNOC_MMSS_CFG,
204 MAS_CNOC_MNOC_CFG,
205 MAS_GFX3D,
206 MAS_JPEG,
207 MAS_MDP,
208 MAS_VIDEO_P0,
209 MAS_VIDEO_P1,
210 MAS_VFE,
211 MAS_CNOC_ONOC_CFG,
212 MAS_JPEG_OCMEM,
213 MAS_MDP_OCMEM,
214 MAS_VIDEO_P0_OCMEM,
215 MAS_VIDEO_P1_OCMEM,
216 MAS_VFE_OCMEM,
217 MAS_LPASS_AHB,
218 MAS_QDSS_BAM,
219 MAS_SNOC_CFG,
220 MAS_BIMC_SNOC,
221 MAS_CNOC_SNOC,
222 MAS_CRYPTO_CORE0,
223 MAS_CRYPTO_CORE1,
224 MAS_LPASS_PROC,
225 MAS_MSS,
226 MAS_MSS_NAV,
227 MAS_OCMEM_DMA,
228 MAS_PNOC_SNOC,
229 MAS_WCSS,
230 MAS_QDSS_ETR,
231 MAS_USB3,
232 MAS_SDCC_1,
233 MAS_SDCC_3,
234 MAS_SDCC_2,
235 MAS_SDCC_4,
236 MAS_TSIF,
237 MAS_BAM_DMA,
238 MAS_BLSP_2,
239 MAS_USB_HSIC,
240 MAS_BLSP_1,
241 MAS_USB_HS,
242 MAS_PNOC_CFG,
243 MAS_SNOC_PNOC,
244 MAS_RPM_INST,
245 MAS_RPM_DATA,
246 MAS_RPM_SYS,
247 MAS_DEHR,
248 MAS_QDSS_DAP,
249 MAS_SPDM,
250 MAS_TIC,
251 MAS_SNOC_CNOC,
252 MAS_OVNOC_SNOC,
253 MAS_OVNOC_ONOC,
254 MAS_V_OCMEM_GFX3D,
255 MAS_ONOC_OVNOC,
256 MAS_SNOC_OVNOC,
257};
258
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]259enum msm_bus_8974_slv_hw_id {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]260 SLV_EBI = 0,
261 SLV_APSS_L2,
262 SLV_BIMC_SNOC,
263 SLV_CAMERA_CFG,
264 SLV_DISPLAY_CFG,
265 SLV_OCMEM_CFG,
266 SLV_CPR_CFG,
267 SLV_CPR_XPU_CFG,
268 SLV_MISC_CFG,
269 SLV_MISC_XPU_CFG,
270 SLV_VENUS_CFG,
271 SLV_GFX3D_CFG,
272 SLV_MMSS_CLK_CFG,
273 SLV_MMSS_CLK_XPU_CFG,
274 SLV_MNOC_MPU_CFG,
275 SLV_ONOC_MPU_CFG,
276 SLV_MMSS_BIMC,
277 SLV_SERVICE_MNOC,
278 SLV_OCMEM,
279 SLV_SERVICE_ONOC,
280 SLV_APPSS,
281 SLV_LPASS,
282 SLV_USB3,
283 SLV_WCSS,
284 SLV_SNOC_BIMC,
285 SLV_SNOC_CNOC,
286 SLV_OCIMEM,
287 SLV_SNOC_OCMEM,
288 SLV_SNOC_PNOC,
289 SLV_SERVICE_SNOC,
290 SLV_QDSS_STM,
291 SLV_SDCC_1,
292 SLV_SDCC_3,
293 SLV_SDCC_2,
294 SLV_SDCC_4,
295 SLV_TSIF,
296 SLV_BAM_DMA,
297 SLV_BLSP_2,
298 SLV_USB_HSIC,
299 SLV_BLSP_1,
300 SLV_USB_HS,
301 SLV_PDM,
302 SLV_PERIPH_APU_CFG,
303 SLV_MPU_CFG,
304 SLV_PRNG,
305 SLV_PNOC_SNOC,
306 SLV_SERVICE_PNOC,
307 SLV_CLK_CTL,
308 SLV_CNOC_MSS,
309 SLV_SECURITY,
310 SLV_TCSR,
311 SLV_TLMM,
312 SLV_CRYPTO_0_CFG,
313 SLV_CRYPTO_1_CFG,
314 SLV_IMEM_CFG,
315 SLV_MESSAGE_RAM,
316 SLV_BIMC_CFG,
317 SLV_BOOT_ROM,
318 SLV_CNOC_MNOC_MMSS_CFG,
319 SLV_PMIC_ARB,
320 SLV_SPDM_WRAPPER,
321 SLV_DEHR_CFG,
322 SLV_MPM,
323 SLV_QDSS_CFG,
324 SLV_RBCPR_CFG,
325 SLV_RBCPR_QDSS_APU_CFG,
326 SLV_CNOC_MNOC_CFG,
327 SLV_SNOC_MPU_CFG,
328 SLV_CNOC_ONOC_CFG,
329 SLV_PNOC_CFG,
330 SLV_SNOC_CFG,
331 SLV_EBI1_DLL_CFG,
332 SLV_PHY_APU_CFG,
333 SLV_EBI1_PHY_CFG,
334 SLV_RPM,
335 SLV_CNOC_SNOC,
336 SLV_SERVICE_CNOC,
337 SLV_SNOC_OVNOC,
338 SLV_ONOC_OVNOC,
339 SLV_OVNOC_ONOC,
340 SLV_OVNOC_SNOC,
341};
342
343static uint32_t master_iids[NMASTERS];
344static uint32_t slave_iids[NSLAVES];
345
346/* System NOC nodes */
347static int mport_lpass_ahb[] = {MASTER_PORT_LPASS_AHB,};
348static int mport_qdss_bam[] = {MASTER_PORT_QDSS_BAM,};
349static int mport_snoc_cfg[] = {MASTER_PORT_SNOC_CFG,};
350static int mport_gw_bimc_snoc[] = {MASTER_PORT_GW_BIMC_SNOC,};
351static int mport_gw_cnoc_snoc[] = {MASTER_PORT_GW_CNOC_SNOC,};
352static int mport_crypto_core0[] = {MASTER_PORT_CRYPTO_CORE0,};
353static int mport_crypto_core1[] = {MASTER_PORT_CRYPTO_CORE1};
354static int mport_lpass_proc[] = {MASTER_PORT_LPASS_PROC};
355static int mport_mss[] = {MASTER_PORT_MSS};
356static int mport_mss_nav[] = {MASTER_PORT_MSS_NAV};
357static int mport_ocmem_dma[] = {MASTER_PORT_OCMEM_DMA};
358static int mport_gw_pnoc_snoc[] = {MASTER_PORT_GW_PNOC_SNOC};
359static int mport_wcss[] = {MASTER_PORT_WCSS};
360static int mport_qdss_etr[] = {MASTER_PORT_QDSS_ETR};
361static int mport_usb3[] = {MASTER_PORT_USB3};
362
363static int sport_kmpss[] = {SLAVE_PORT_KMPSS};
364static int sport_lpass[] = {SLAVE_PORT_LPASS};
365static int sport_usb3[] = {SLAVE_PORT_USB3};
366static int sport_wcss[] = {SLAVE_PORT_WCSS};
367static int sport_gw_snoc_bimc[] = {
368 SLAVE_PORT_GW_SNOC_BIMC_P0,
369 SLAVE_PORT_GW_SNOC_BIMC_P1,
370 };
371static int sport_gw_snoc_cnoc[] = {SLAVE_PORT_GW_SNOC_CNOC};
372static int sport_ocimem[] = {SLAVE_PORT_OCIMEM};
373static int sport_snoc_ocmem[] = {SLAVE_PORT_SNOC_OCMEM};
374static int sport_gw_snoc_pnoc[] = {SLAVE_PORT_GW_SNOC_PNOC};
375static int sport_service_snoc[] = {SLAVE_PORT_SERVICE_SNOC};
376static int sport_qdss_stm[] = {SLAVE_PORT_QDSS_STM};
377
378
379/* MMSS NOC nodes */
380static int mport_gw_cnoc_mnoc_cfg[] = {
381 MASTER_PORT_GW_CNOC_MNOC_MMSS_CFG,
382 MASTER_PORT_GW_CNOC_MNOC_CFG,
383};
384static int mport_gfx3d[] = {
385 MASTER_PORT_GFX3D_PORT0,
386 MASTER_PORT_GFX3D_PORT1,
387};
388static int mport_jpeg[] = {MASTER_PORT_JPEG};
389static int mport_mdp[] = {MASTER_PORT_MDP};
390static int mport_video_port0[] = {MASTER_PORT_VIDEO_PORT0};
391static int mport_video_port1[] = {MASTER_PORT_VIDEO_PORT1};
392static int mport_vfe[] = {MASTER_PORT_VFE};
393
394static int sport_camera_cfg[] = {SLAVE_PORT_CAMERA_CFG};
395static int sport_display_cfg[] = {SLAVE_PORT_DISPLAY_CFG};
396static int sport_ocmem_cfg[] = {SLAVE_PORT_OCMEM_CFG};
397static int sport_cpr_cfg[] = {SLAVE_PORT_CPR_CFG};
398static int sport_cpr_xpu_cfg[] = {SLAVE_PORT_CPR_XPU_CFG,};
399static int sport_misc_cfg[] = {SLAVE_PORT_MISC_CFG};
400static int sport_misc_xpu_cfg[] = {SLAVE_PORT_MISC_XPU_CFG};
401static int sport_venus_cfg[] = {SLAVE_PORT_VENUS_CFG};
402static int sport_gfx3d_cfg[] = {SLAVE_PORT_GFX3D_CFG};
403static int sport_mmss_clk_cfg[] = {SLAVE_PORT_MMSS_CLK_CFG};
404static int sport_mmss_clk_xpu_cfg[] = {
405 SLAVE_PORT_MMSS_CLK_XPU_CFG
406};
407static int sport_mnoc_mpu_cfg[] = {SLAVE_PORT_MNOC_MPU_CFG};
408static int sport_onoc_mpu_cfg[] = {SLAVE_PORT_ONOC_MPU_CFG};
409static int sport_gw_mmss_bimc[] = {
410 SLAVE_PORT_GW_MMSS_BIMC_P0,
411 SLAVE_PORT_GW_MMSS_BIMC_P1,
412};
413static int sport_service_mnoc[] = {SLAVE_PORT_SERVICE_MNOC};
414
415/* BIMC Nodes */
416
417static int mport_kmpss_m0[] = {MASTER_PORT_KMPSS_M0,};
418static int mport_kmpss_m1[] = {MASTER_PORT_KMPSS_M1};
419static int mport_mss_proc[] = {MASTER_PORT_MSS_PROC};
420static int mport_gw_mnoc_bimc[] = {
421 MASTER_PORT_GW_MNOC_BIMC_0,
422 MASTER_PORT_GW_MNOC_BIMC_1,
423};
424static int mport_gw_snoc_bimc[] = {
425 MASTER_PORT_GW_SNOC_BIMC_0,
426 MASTER_PORT_GW_SNOC_BIMC_1,
427};
428
429static int sport_ebi1[] = {
430 SLAVE_PORT_EBI1_CH0,
431 SLAVE_PORT_EBI1_CH1,
432};
433static int sport_kmpss_l2[] = {SLAVE_PORT_KMPSS_L2,};
434static int sport_gw_bimc_snoc[] = {SLAVE_PORT_GW_BIMC_SNOC,};
435
436/* OCMEM NOC Nodes */
437static int mport_cnoc_onoc_cfg[] = {
438 MASTER_PORT_CNOC_ONOC_CFG,
439};
440static int mport_jpeg_ocmem[] = {MASTER_PORT_JPEG_OCMEM,};
441static int mport_mdp_ocmem[] = {MASTER_PORT_MDP_OCMEM,};
442static int mport_video_p0_ocmem[] = {
443 MASTER_PORT_VIDEO_P0_OCMEM,
444};
445static int mport_video_p1_ocmem[] = {
446 MASTER_PORT_VIDEO_P1_OCMEM,
447};
448static int mport_vfe_ocmem[] = {MASTER_PORT_VFE_OCMEM,};
449static int sport_ocmem[] = {
450 SLAVE_PORT_OCMEM_P0,
451 SLAVE_PORT_OCMEM_P1,
452};
453
454static int sport_service_onoc[] = {SLAVE_PORT_SERVICE_ONOC,};
455
456/* Peripheral NOC Nodes */
457static int mport_sdcc_1[] = {MASTER_PORT_SDCC_1,};
458static int mport_sdcc_3[] = {MASTER_PORT_SDCC_3,};
459static int mport_sdcc_2[] = {MASTER_PORT_SDCC_2,};
460static int mport_sdcc_4[] = {MASTER_PORT_SDCC_4,};
461static int mport_tsif[] = {MASTER_PORT_TSIF,};
462static int mport_bam_dma[] = {MASTER_PORT_BAM_DMA,};
463static int mport_blsp_2[] = {MASTER_PORT_BLSP_2,};
464static int mport_usb_hsic[] = {MASTER_PORT_USB_HSIC,};
465static int mport_blsp_1[] = {MASTER_PORT_BLSP_1,};
466static int mport_usb_hs[] = {MASTER_PORT_USB_HS,};
467static int mport_pnoc_cfg[] = {MASTER_PORT_PNOC_CFG,};
468static int mport_gw_snoc_pnoc[] = {MASTER_PORT_GW_SNOC_PNOC,};
469
470static int sport_sdcc_1[] = {SLAVE_PORT_SDCC_1,};
471static int sport_sdcc_3[] = {SLAVE_PORT_SDCC_3,};
472static int sport_sdcc_2[] = {SLAVE_PORT_SDCC_2,};
473static int sport_sdcc_4[] = {SLAVE_PORT_SDCC_4,};
474static int sport_tsif[] = {SLAVE_PORT_TSIF,};
475static int sport_bam_dma[] = {SLAVE_PORT_BAM_DMA,};
476static int sport_blsp_2[] = {SLAVE_PORT_BLSP_2,};
477static int sport_usb_hsic[] = {SLAVE_PORT_USB_HSIC,};
478static int sport_blsp_1[] = {SLAVE_PORT_BLSP_1,};
479static int sport_usb_hs[] = {SLAVE_PORT_USB_HS,};
480static int sport_pdm[] = {SLAVE_PORT_PDM,};
481static int sport_periph_apu_cfg[] = {
482 SLAVE_PORT_PERIPH_APU_CFG,
483};
484static int sport_pnoc_mpu_cfg[] = {SLAVE_PORT_PNOC_MPU_CFG,};
485static int sport_prng[] = {SLAVE_PORT_PRNG,};
486static int sport_gw_pnoc_snoc[] = {SLAVE_PORT_GW_PNOC_SNOC,};
487static int sport_service_pnoc[] = {SLAVE_PORT_SERVICE_PNOC,};
488
489/* Config NOC Nodes */
490static int mport_rpm_inst[] = {MASTER_PORT_RPM_INST,};
491static int mport_rpm_data[] = {MASTER_PORT_RPM_DATA,};
492static int mport_rpm_sys[] = {MASTER_PORT_RPM_SYS,};
493static int mport_dehr[] = {MASTER_PORT_DEHR,};
494static int mport_qdss_dap[] = {MASTER_PORT_QDSS_DAP,};
495static int mport_spdm[] = {MASTER_PORT_SPDM,};
496static int mport_tic[] = {MASTER_PORT_TIC,};
497static int mport_gw_snoc_cnoc[] = {MASTER_PORT_GW_SNOC_CNOC,};
498
499static int sport_clk_ctl[] = {SLAVE_PORT_CLK_CTL,};
500static int sport_cnoc_mss[] = {SLAVE_PORT_CNOC_MSS,};
501static int sport_security[] = {SLAVE_PORT_SECURITY,};
502static int sport_tcsr[] = {SLAVE_PORT_TCSR,};
503static int sport_tlmm[] = {SLAVE_PORT_TLMM,};
504static int sport_crypto_0_cfg[] = {SLAVE_PORT_CRYPTO_0_CFG,};
505static int sport_crypto_1_cfg[] = {SLAVE_PORT_CRYPTO_1_CFG,};
506static int sport_imem_cfg[] = {SLAVE_PORT_IMEM_CFG,};
507static int sport_message_ram[] = {SLAVE_PORT_MESSAGE_RAM,};
508static int sport_bimc_cfg[] = {SLAVE_PORT_BIMC_CFG,};
509static int sport_boot_rom[] = {SLAVE_PORT_BOOT_ROM,};
510static int sport_cnoc_mnoc_mmss_cfg[] = {SLAVE_PORT_CNOC_MNOC_MMSS_CFG,};
511static int sport_cnoc_mnoc_cfg[] = {SLAVE_PORT_CNOC_MNOC_CFG,};
512static int sport_pmic_arb[] = {SLAVE_PORT_PMIC_ARB,};
513static int sport_spdm_wrapper[] = {SLAVE_PORT_SPDM_WRAPPER,};
514static int sport_dehr_cfg[] = {SLAVE_PORT_DEHR_CFG,};
515static int sport_mpm[] = {SLAVE_PORT_MPM,};
516static int sport_qdss_cfg[] = {SLAVE_PORT_QDSS_CFG,};
517static int sport_rbcpr_cfg[] = {SLAVE_PORT_RBCPR_CFG,};
518static int sport_rbcpr_qdss_apu_cfg[] = {SLAVE_PORT_RBCPR_QDSS_APU_CFG,};
519static int sport_snoc_mpu_cfg[] = {SLAVE_PORT_SNOC_MPU_CFG,};
520static int sport_cnoc_onoc_cfg[] = {SLAVE_PORT_CNOC_ONOC_CFG,};
521static int sport_pnoc_cfg[] = {SLAVE_PORT_PNOC_CFG,};
522static int sport_snoc_cfg[] = {SLAVE_PORT_SNOC_CFG,};
523static int sport_ebi1_dll_cfg[] = {SLAVE_PORT_EBI1_DLL_CFG,};
524static int sport_phy_apu_cfg[] = {SLAVE_PORT_PHY_APU_CFG,};
525static int sport_ebi1_phy_cfg[] = {SLAVE_PORT_EBI1_PHY_CFG,};
526static int sport_rpm[] = {SLAVE_PORT_RPM,};
527static int sport_gw_cnoc_snoc[] = {SLAVE_PORT_GW_CNOC_SNOC,};
528static int sport_service_cnoc[] = {SLAVE_PORT_SERVICE_CNOC,};
529
530static int tier2[] = {MSM_BUS_BW_TIER2,};
531
532/*
533 * QOS Ports defined only when qos ports are different than
534 * master ports
535 **/
536static int qports_gemini[] = {0};
537static int qports_mdp[] = {1};
538static int qports_venus_p0[] = {4};
539static int qports_venus_p1[] = {5};
540static int qports_vfe[] = {6};
541static int qports_gemini_ocmem[] = {0};
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]542static int qports_venus_p0_ocmem[] = {2};
543static int qports_venus_p1_ocmem[] = {3};
544static int qports_vfe_ocmem[] = {4};
545static int qports_crypto_c0[] = {2};
546static int qports_crypto_c1[] = {3};
547static int qports_lpass_proc[] = {4};
548static int qports_ocmem_dma[] = {7};
549static int qports_gw_snoc_bimc[] = {5, 6};
550static int qports_kmpss[] = {0, 1};
551static int qports_lpass_ahb[] = {0};
552static int qports_qdss_bam[] = {1};
553static int qports_gw_pnoc_snoc[] = {8};
554static int qports_qdss_etr[] = {10};
555static int qports_usb3[] = {11};
556static int qports_oxili[] = {2, 3};
557static int qports_gw_mnoc_bimc[] = {3, 4};
558
559static struct msm_bus_node_info sys_noc_info[] = {
560 {
561 .id = MSM_BUS_MASTER_LPASS_AHB,
562 .masterp = mport_lpass_ahb,
563 .num_mports = ARRAY_SIZE(mport_lpass_ahb),
564 .tier = tier2,
565 .num_tiers = ARRAY_SIZE(tier2),
566 .qport = qports_lpass_ahb,
567 .mas_hw_id = MAS_LPASS_AHB,
568 .mode = NOC_QOS_MODE_FIXED,
569 .prio_rd = 2,
570 .prio_wr = 2,
571 },
572 {
573 .id = MSM_BUS_MASTER_QDSS_BAM,
574 .masterp = mport_qdss_bam,
575 .num_mports = ARRAY_SIZE(mport_qdss_bam),
576 .tier = tier2,
577 .num_tiers = ARRAY_SIZE(tier2),
578 .mode = NOC_QOS_MODE_FIXED,
579 .qport = qports_qdss_bam,
580 .mas_hw_id = MAS_QDSS_BAM,
581 },
582 {
583 .id = MSM_BUS_MASTER_SNOC_CFG,
584 .masterp = mport_snoc_cfg,
585 .num_mports = ARRAY_SIZE(mport_snoc_cfg),
586 .tier = tier2,
587 .num_tiers = ARRAY_SIZE(tier2),
588 .mas_hw_id = MAS_SNOC_CFG,
589 },
590 {
591 .id = MSM_BUS_FAB_BIMC,
592 .gateway = 1,
593 .slavep = sport_gw_snoc_bimc,
594 .num_sports = ARRAY_SIZE(sport_gw_snoc_bimc),
595 .masterp = mport_gw_bimc_snoc,
596 .num_mports = ARRAY_SIZE(mport_gw_bimc_snoc),
597 .buswidth = 8,
598 .mas_hw_id = MAS_BIMC_SNOC,
599 .slv_hw_id = SLV_SNOC_BIMC,
600 },
601 {
602 .id = MSM_BUS_FAB_CONFIG_NOC,
603 .gateway = 1,
604 .slavep = sport_gw_snoc_cnoc,
605 .num_sports = ARRAY_SIZE(sport_gw_snoc_cnoc),
606 .masterp = mport_gw_cnoc_snoc,
607 .num_mports = ARRAY_SIZE(mport_gw_cnoc_snoc),
608 .buswidth = 8,
609 .mas_hw_id = MAS_CNOC_SNOC,
610 .slv_hw_id = SLV_SNOC_CNOC,
611 },
612 {
613 .id = MSM_BUS_FAB_PERIPH_NOC,
614 .gateway = 1,
615 .slavep = sport_gw_snoc_pnoc,
616 .num_sports = ARRAY_SIZE(sport_gw_snoc_pnoc),
617 .masterp = mport_gw_pnoc_snoc,
618 .num_mports = ARRAY_SIZE(mport_gw_pnoc_snoc),
619 .buswidth = 8,
620 .qport = qports_gw_pnoc_snoc,
621 .mas_hw_id = MAS_PNOC_SNOC,
622 .slv_hw_id = SLV_SNOC_PNOC,
623 .mode = NOC_QOS_MODE_FIXED,
624 .prio_rd = 2,
625 .prio_wr = 2,
626 },
627 {
628 .id = MSM_BUS_FAB_OCMEM_VNOC,
629 .gateway = 1,
630 .buswidth = 8,
631 .mas_hw_id = MAS_OVNOC_SNOC,
632 .slv_hw_id = SLV_SNOC_OVNOC,
633 },
634 {
635 .id = MSM_BUS_MASTER_CRYPTO_CORE0,
636 .masterp = mport_crypto_core0,
637 .num_mports = ARRAY_SIZE(mport_crypto_core0),
638 .tier = tier2,
639 .num_tiers = ARRAY_SIZE(tier2),
640 .mode = NOC_QOS_MODE_FIXED,
641 .qport = qports_crypto_c0,
642 .mas_hw_id = MAS_CRYPTO_CORE0,
Gagan Macc38e38d2012-10-03 17:36:14 -0600[diff] [blame]643 .hw_sel = MSM_BUS_NOC,
Gagan Mac4f87c502012-11-07 19:45:13 -0700[diff] [blame]644 .prio_rd = 1,
645 .prio_wr = 1,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]646 },
647 {
648 .id = MSM_BUS_MASTER_CRYPTO_CORE1,
649 .masterp = mport_crypto_core1,
650 .num_mports = ARRAY_SIZE(mport_crypto_core1),
651 .tier = tier2,
652 .num_tiers = ARRAY_SIZE(tier2),
653 .mode = NOC_QOS_MODE_FIXED,
654 .qport = qports_crypto_c1,
655 .mas_hw_id = MAS_CRYPTO_CORE1,
Gagan Macc38e38d2012-10-03 17:36:14 -0600[diff] [blame]656 .hw_sel = MSM_BUS_NOC,
Gagan Mac4f87c502012-11-07 19:45:13 -0700[diff] [blame]657 .prio_rd = 1,
658 .prio_wr = 1,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]659 },
660 {
661 .id = MSM_BUS_MASTER_LPASS_PROC,
662 .masterp = mport_lpass_proc,
663 .num_mports = ARRAY_SIZE(mport_lpass_proc),
664 .tier = tier2,
665 .num_tiers = ARRAY_SIZE(tier2),
666 .qport = qports_lpass_proc,
667 .mas_hw_id = MAS_LPASS_PROC,
668 .mode = NOC_QOS_MODE_FIXED,
669 .prio_rd = 2,
670 .prio_wr = 2,
671 },
672 {
673 .id = MSM_BUS_MASTER_MSS,
674 .masterp = mport_mss,
675 .num_mports = ARRAY_SIZE(mport_mss),
676 .tier = tier2,
677 .num_tiers = ARRAY_SIZE(tier2),
678 .mas_hw_id = MAS_MSS,
679 },
680 {
681 .id = MSM_BUS_MASTER_MSS_NAV,
682 .masterp = mport_mss_nav,
683 .num_mports = ARRAY_SIZE(mport_mss_nav),
684 .tier = tier2,
685 .num_tiers = ARRAY_SIZE(tier2),
686 .mas_hw_id = MAS_MSS_NAV,
687 },
688 {
689 .id = MSM_BUS_MASTER_OCMEM_DMA,
690 .masterp = mport_ocmem_dma,
691 .num_mports = ARRAY_SIZE(mport_ocmem_dma),
692 .tier = tier2,
693 .num_tiers = ARRAY_SIZE(tier2),
694 .mode = NOC_QOS_MODE_FIXED,
695 .qport = qports_ocmem_dma,
696 .mas_hw_id = MAS_OCMEM_DMA,
697 },
698 {
699 .id = MSM_BUS_MASTER_WCSS,
700 .masterp = mport_wcss,
701 .num_mports = ARRAY_SIZE(mport_wcss),
702 .tier = tier2,
703 .num_tiers = ARRAY_SIZE(tier2),
704 .mas_hw_id = MAS_WCSS,
705 },
706 {
707 .id = MSM_BUS_MASTER_QDSS_ETR,
708 .masterp = mport_qdss_etr,
709 .num_mports = ARRAY_SIZE(mport_qdss_etr),
710 .tier = tier2,
711 .num_tiers = ARRAY_SIZE(tier2),
712 .qport = qports_qdss_etr,
713 .mode = NOC_QOS_MODE_FIXED,
714 .mas_hw_id = MAS_QDSS_ETR,
715 },
716 {
717 .id = MSM_BUS_MASTER_USB3,
718 .masterp = mport_usb3,
719 .num_mports = ARRAY_SIZE(mport_usb3),
720 .tier = tier2,
721 .num_tiers = ARRAY_SIZE(tier2),
722 .mode = NOC_QOS_MODE_FIXED,
723 .qport = qports_usb3,
724 .mas_hw_id = MAS_USB3,
725 .prio_rd = 2,
726 .prio_wr = 2,
Gagan Macc38e38d2012-10-03 17:36:14 -0600[diff] [blame]727 .hw_sel = MSM_BUS_NOC,
Gagan Macf095ded2012-10-16 16:37:39 -0600[diff] [blame]728 .iface_clk_node = "msm_usb3",
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]729 },
730 {
731 .id = MSM_BUS_SLAVE_AMPSS,
732 .slavep = sport_kmpss,
733 .num_sports = ARRAY_SIZE(sport_kmpss),
734 .tier = tier2,
735 .num_tiers = ARRAY_SIZE(tier2),
736 .buswidth = 8,
737 .slv_hw_id = SLV_APPSS,
738 },
739 {
740 .id = MSM_BUS_SLAVE_LPASS,
741 .slavep = sport_lpass,
742 .num_sports = ARRAY_SIZE(sport_lpass),
743 .tier = tier2,
744 .num_tiers = ARRAY_SIZE(tier2),
745 .buswidth = 8,
746 .slv_hw_id = SLV_LPASS,
747 },
748 {
749 .id = MSM_BUS_SLAVE_USB3,
750 .slavep = sport_usb3,
751 .num_sports = ARRAY_SIZE(sport_usb3),
752 .tier = tier2,
753 .num_tiers = ARRAY_SIZE(tier2),
754 .buswidth = 8,
755 .slv_hw_id = SLV_USB3,
756 },
757 {
758 .id = MSM_BUS_SLAVE_WCSS,
759 .slavep = sport_wcss,
760 .num_sports = ARRAY_SIZE(sport_wcss),
761 .tier = tier2,
762 .num_tiers = ARRAY_SIZE(tier2),
763 .buswidth = 8,
764 .slv_hw_id = SLV_WCSS,
765 },
766 {
767 .id = MSM_BUS_SLAVE_OCIMEM,
768 .slavep = sport_ocimem,
769 .num_sports = ARRAY_SIZE(sport_ocimem),
770 .tier = tier2,
771 .num_tiers = ARRAY_SIZE(tier2),
772 .buswidth = 8,
773 .slv_hw_id = SLV_OCIMEM,
774 },
775 {
776 .id = MSM_BUS_SLAVE_SNOC_OCMEM,
777 .slavep = sport_snoc_ocmem,
778 .num_sports = ARRAY_SIZE(sport_snoc_ocmem),
779 .tier = tier2,
780 .num_tiers = ARRAY_SIZE(tier2),
781 .buswidth = 8,
782 .slv_hw_id = SLV_SNOC_OCMEM,
783 },
784 {
785 .id = MSM_BUS_SLAVE_SERVICE_SNOC,
786 .slavep = sport_service_snoc,
787 .num_sports = ARRAY_SIZE(sport_service_snoc),
788 .tier = tier2,
789 .num_tiers = ARRAY_SIZE(tier2),
790 .buswidth = 8,
791 .slv_hw_id = SLV_SERVICE_SNOC,
792 },
793 {
794 .id = MSM_BUS_SLAVE_QDSS_STM,
795 .slavep = sport_qdss_stm,
796 .num_sports = ARRAY_SIZE(sport_qdss_stm),
797 .tier = tier2,
798 .num_tiers = ARRAY_SIZE(tier2),
799 .buswidth = 8,
800 .slv_hw_id = SLV_QDSS_STM,
801 },
802};
803
804
805static struct msm_bus_node_info mmss_noc_info[] = {
806 {
807 .id = MSM_BUS_MASTER_GRAPHICS_3D,
808 .masterp = mport_gfx3d,
809 .num_mports = ARRAY_SIZE(mport_gfx3d),
810 .tier = tier2,
811 .num_tiers = ARRAY_SIZE(tier2),
812 .hw_sel = MSM_BUS_NOC,
Gagan Mac9addee02012-11-06 16:40:42 -0700[diff] [blame]813 .perm_mode = NOC_QOS_PERM_MODE_BYPASS,
Gagan Macf5465612012-08-29 12:20:48 -0600[diff] [blame]814 .mode = NOC_QOS_MODE_BYPASS,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]815 .ws = 10000,
816 .qport = qports_oxili,
817 .mas_hw_id = MAS_GFX3D,
818 },
819 {
820 .id = MSM_BUS_MASTER_JPEG,
821 .masterp = mport_jpeg,
822 .num_mports = ARRAY_SIZE(mport_jpeg),
823 .tier = tier2,
824 .num_tiers = ARRAY_SIZE(tier2),
825 .hw_sel = MSM_BUS_NOC,
Gagan Mac9addee02012-11-06 16:40:42 -0700[diff] [blame]826 .perm_mode = NOC_QOS_PERM_MODE_BYPASS,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]827 .mode = NOC_QOS_MODE_BYPASS,
828 .qport = qports_gemini,
829 .ws = 10000,
830 .mas_hw_id = MAS_JPEG,
831 },
832 {
833 .id = MSM_BUS_MASTER_MDP_PORT0,
834 .masterp = mport_mdp,
835 .num_mports = ARRAY_SIZE(mport_mdp),
836 .tier = tier2,
837 .num_tiers = ARRAY_SIZE(tier2),
838 .hw_sel = MSM_BUS_NOC,
Gagan Mac9addee02012-11-06 16:40:42 -0700[diff] [blame]839 .perm_mode = NOC_QOS_PERM_MODE_BYPASS,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]840 .mode = NOC_QOS_MODE_BYPASS,
841 .qport = qports_mdp,
842 .ws = 10000,
843 .mas_hw_id = MAS_MDP,
844 },
845 {
846 .id = MSM_BUS_MASTER_VIDEO_P0,
847 .masterp = mport_video_port0,
848 .num_mports = ARRAY_SIZE(mport_video_port0),
849 .tier = tier2,
850 .num_tiers = ARRAY_SIZE(tier2),
851 .hw_sel = MSM_BUS_NOC,
Gagan Mac9addee02012-11-06 16:40:42 -0700[diff] [blame]852 .perm_mode = NOC_QOS_PERM_MODE_BYPASS,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]853 .mode = NOC_QOS_MODE_BYPASS,
854 .ws = 10000,
855 .qport = qports_venus_p0,
856 .mas_hw_id = MAS_VIDEO_P0,
857 },
858 {
859 .id = MSM_BUS_MASTER_VIDEO_P1,
860 .masterp = mport_video_port1,
861 .num_mports = ARRAY_SIZE(mport_video_port1),
862 .tier = tier2,
863 .num_tiers = ARRAY_SIZE(tier2),
864 .hw_sel = MSM_BUS_NOC,
Gagan Mac9addee02012-11-06 16:40:42 -0700[diff] [blame]865 .perm_mode = NOC_QOS_PERM_MODE_BYPASS,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]866 .mode = NOC_QOS_MODE_BYPASS,
867 .ws = 10000,
868 .qport = qports_venus_p1,
869 .mas_hw_id = MAS_VIDEO_P1,
870 },
871 {
872 .id = MSM_BUS_MASTER_VFE,
873 .masterp = mport_vfe,
874 .num_mports = ARRAY_SIZE(mport_vfe),
875 .tier = tier2,
876 .num_tiers = ARRAY_SIZE(tier2),
877 .hw_sel = MSM_BUS_NOC,
Gagan Mac9addee02012-11-06 16:40:42 -0700[diff] [blame]878 .perm_mode = NOC_QOS_PERM_MODE_BYPASS,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]879 .mode = NOC_QOS_MODE_BYPASS,
880 .ws = 10000,
881 .qport = qports_vfe,
882 .mas_hw_id = MAS_VFE,
883 },
884 {
885 .id = MSM_BUS_FAB_CONFIG_NOC,
886 .gateway = 1,
887 .masterp = mport_gw_cnoc_mnoc_cfg,
888 .num_mports = ARRAY_SIZE(mport_gw_cnoc_mnoc_cfg),
889 .buswidth = 16,
890 .hw_sel = MSM_BUS_RPM,
891 .mas_hw_id = MAS_CNOC_MNOC_MMSS_CFG,
892 },
893 {
894 .id = MSM_BUS_FAB_BIMC,
895 .gateway = 1,
896 .slavep = sport_gw_mmss_bimc,
897 .num_sports = ARRAY_SIZE(sport_gw_mmss_bimc),
898 .buswidth = 16,
899 .hw_sel = MSM_BUS_NOC,
900 .slv_hw_id = SLV_MMSS_BIMC,
901 },
902 {
903 .id = MSM_BUS_SLAVE_CAMERA_CFG,
904 .slavep = sport_camera_cfg,
905 .num_sports = ARRAY_SIZE(sport_camera_cfg),
906 .tier = tier2,
907 .num_tiers = ARRAY_SIZE(tier2),
908 .buswidth = 16,
909 .hw_sel = MSM_BUS_NOC,
910 .slv_hw_id = SLV_CAMERA_CFG,
911 },
912 {
913 .id = MSM_BUS_SLAVE_DISPLAY_CFG,
914 .slavep = sport_display_cfg,
915 .num_sports = ARRAY_SIZE(sport_display_cfg),
916 .tier = tier2,
917 .num_tiers = ARRAY_SIZE(tier2),
918 .buswidth = 16,
919 .hw_sel = MSM_BUS_NOC,
920 .slv_hw_id = SLV_DISPLAY_CFG,
921 },
922 {
923 .id = MSM_BUS_SLAVE_OCMEM_CFG,
924 .slavep = sport_ocmem_cfg,
925 .num_sports = ARRAY_SIZE(sport_ocmem_cfg),
926 .tier = tier2,
927 .num_tiers = ARRAY_SIZE(tier2),
928 .buswidth = 16,
929 .hw_sel = MSM_BUS_NOC,
930 .slv_hw_id = SLV_OCMEM_CFG,
931 },
932 {
933 .id = MSM_BUS_SLAVE_CPR_CFG,
934 .slavep = sport_cpr_cfg,
935 .num_sports = ARRAY_SIZE(sport_cpr_cfg),
936 .tier = tier2,
937 .num_tiers = ARRAY_SIZE(tier2),
938 .buswidth = 16,
939 .hw_sel = MSM_BUS_NOC,
940 .slv_hw_id = SLV_CPR_CFG,
941 },
942 {
943 .id = MSM_BUS_SLAVE_CPR_XPU_CFG,
944 .slavep = sport_cpr_xpu_cfg,
945 .num_sports = ARRAY_SIZE(sport_cpr_xpu_cfg),
946 .tier = tier2,
947 .num_tiers = ARRAY_SIZE(tier2),
948 .buswidth = 16,
949 .hw_sel = MSM_BUS_NOC,
950 .slv_hw_id = SLV_CPR_XPU_CFG,
951 },
952 {
953 .id = MSM_BUS_SLAVE_MISC_CFG,
954 .slavep = sport_misc_cfg,
955 .num_sports = ARRAY_SIZE(sport_misc_cfg),
956 .tier = tier2,
957 .num_tiers = ARRAY_SIZE(tier2),
958 .buswidth = 16,
959 .hw_sel = MSM_BUS_NOC,
960 .slv_hw_id = SLV_MISC_CFG,
961 },
962 {
963 .id = MSM_BUS_SLAVE_MISC_XPU_CFG,
964 .slavep = sport_misc_xpu_cfg,
965 .num_sports = ARRAY_SIZE(sport_misc_xpu_cfg),
966 .tier = tier2,
967 .num_tiers = ARRAY_SIZE(tier2),
968 .buswidth = 16,
969 .hw_sel = MSM_BUS_NOC,
970 .slv_hw_id = SLV_MISC_XPU_CFG,
971 },
972 {
973 .id = MSM_BUS_SLAVE_VENUS_CFG,
974 .slavep = sport_venus_cfg,
975 .num_sports = ARRAY_SIZE(sport_venus_cfg),
976 .tier = tier2,
977 .num_tiers = ARRAY_SIZE(tier2),
978 .buswidth = 16,
979 .hw_sel = MSM_BUS_NOC,
980 .slv_hw_id = SLV_VENUS_CFG,
981 },
982 {
983 .id = MSM_BUS_SLAVE_GRAPHICS_3D_CFG,
984 .slavep = sport_gfx3d_cfg,
985 .num_sports = ARRAY_SIZE(sport_gfx3d_cfg),
986 .tier = tier2,
987 .num_tiers = ARRAY_SIZE(tier2),
988 .buswidth = 16,
989 .hw_sel = MSM_BUS_NOC,
990 .slv_hw_id = SLV_GFX3D_CFG,
991 },
992 {
993 .id = MSM_BUS_SLAVE_MMSS_CLK_CFG,
994 .slavep = sport_mmss_clk_cfg,
995 .num_sports = ARRAY_SIZE(sport_mmss_clk_cfg),
996 .tier = tier2,
997 .num_tiers = ARRAY_SIZE(tier2),
998 .buswidth = 16,
999 .hw_sel = MSM_BUS_NOC,
1000 .slv_hw_id = SLV_MMSS_CLK_CFG,
1001 },
1002 {
1003 .id = MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG,
1004 .slavep = sport_mmss_clk_xpu_cfg,
1005 .num_sports = ARRAY_SIZE(sport_mmss_clk_xpu_cfg),
1006 .tier = tier2,
1007 .num_tiers = ARRAY_SIZE(tier2),
1008 .buswidth = 16,
1009 .hw_sel = MSM_BUS_NOC,
1010 .slv_hw_id = SLV_MMSS_CLK_XPU_CFG,
1011 },
1012 {
1013 .id = MSM_BUS_SLAVE_MNOC_MPU_CFG,
1014 .slavep = sport_mnoc_mpu_cfg,
1015 .num_sports = ARRAY_SIZE(sport_mnoc_mpu_cfg),
1016 .tier = tier2,
1017 .num_tiers = ARRAY_SIZE(tier2),
1018 .buswidth = 16,
1019 .hw_sel = MSM_BUS_NOC,
1020 .slv_hw_id = SLV_MNOC_MPU_CFG,
1021 },
1022 {
1023 .id = MSM_BUS_SLAVE_ONOC_MPU_CFG,
1024 .slavep = sport_onoc_mpu_cfg,
1025 .num_sports = ARRAY_SIZE(sport_onoc_mpu_cfg),
1026 .tier = tier2,
1027 .num_tiers = ARRAY_SIZE(tier2),
1028 .buswidth = 16,
1029 .hw_sel = MSM_BUS_NOC,
1030 .slv_hw_id = SLV_ONOC_MPU_CFG,
1031 },
1032 {
1033 .id = MSM_BUS_SLAVE_SERVICE_MNOC,
1034 .slavep = sport_service_mnoc,
1035 .num_sports = ARRAY_SIZE(sport_service_mnoc),
1036 .tier = tier2,
1037 .num_tiers = ARRAY_SIZE(tier2),
1038 .buswidth = 16,
1039 .hw_sel = MSM_BUS_NOC,
1040 .slv_hw_id = SLV_SERVICE_MNOC,
1041 },
1042};
1043
1044static struct msm_bus_node_info bimc_info[] = {
1045 {
1046 .id = MSM_BUS_MASTER_AMPSS_M0,
1047 .masterp = mport_kmpss_m0,
1048 .num_mports = ARRAY_SIZE(mport_kmpss_m0),
1049 .tier = tier2,
1050 .num_tiers = ARRAY_SIZE(tier2),
1051 .hw_sel = MSM_BUS_BIMC,
1052 .mode = NOC_QOS_MODE_FIXED,
1053 .qport = qports_kmpss,
1054 .ws = 10000,
1055 .mas_hw_id = MAS_APPSS_PROC,
Gagan Macd5e87ac2012-09-17 10:51:25 -0600[diff] [blame]1056 .prio_rd = 1,
1057 .prio_wr = 1,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1058 },
1059 {
1060 .id = MSM_BUS_MASTER_AMPSS_M1,
1061 .masterp = mport_kmpss_m1,
1062 .num_mports = ARRAY_SIZE(mport_kmpss_m1),
1063 .tier = tier2,
1064 .num_tiers = ARRAY_SIZE(tier2),
1065 .hw_sel = MSM_BUS_BIMC,
1066 .mode = NOC_QOS_MODE_FIXED,
1067 .qport = qports_kmpss,
1068 .ws = 10000,
1069 .mas_hw_id = MAS_APPSS_PROC,
Gagan Macd5e87ac2012-09-17 10:51:25 -0600[diff] [blame]1070 .prio_rd = 1,
1071 .prio_wr = 1,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1072 },
1073 {
1074 .id = MSM_BUS_MASTER_MSS_PROC,
1075 .masterp = mport_mss_proc,
1076 .num_mports = ARRAY_SIZE(mport_mss_proc),
1077 .tier = tier2,
1078 .num_tiers = ARRAY_SIZE(tier2),
1079 .hw_sel = MSM_BUS_RPM,
1080 .mas_hw_id = MAS_AMSS_PROC,
1081 },
1082 {
1083 .id = MSM_BUS_FAB_MMSS_NOC,
1084 .gateway = 1,
1085 .masterp = mport_gw_mnoc_bimc,
1086 .num_mports = ARRAY_SIZE(mport_gw_mnoc_bimc),
1087 .qport = qports_gw_mnoc_bimc,
1088 .buswidth = 8,
1089 .ws = 10000,
1090 .mas_hw_id = MAS_MNOC_BIMC,
1091 .hw_sel = MSM_BUS_BIMC,
1092 .mode = NOC_QOS_MODE_BYPASS,
1093 },
1094 {
1095 .id = MSM_BUS_FAB_SYS_NOC,
1096 .gateway = 1,
1097 .slavep = sport_gw_bimc_snoc,
1098 .num_sports = ARRAY_SIZE(sport_gw_bimc_snoc),
1099 .masterp = mport_gw_snoc_bimc,
1100 .num_mports = ARRAY_SIZE(mport_gw_snoc_bimc),
1101 .qport = qports_gw_snoc_bimc,
1102 .buswidth = 8,
1103 .ws = 10000,
1104 .mas_hw_id = MAS_SNOC_BIMC,
1105 .slv_hw_id = SLV_BIMC_SNOC,
1106 },
1107 {
1108 .id = MSM_BUS_SLAVE_EBI_CH0,
1109 .slavep = sport_ebi1,
1110 .num_sports = ARRAY_SIZE(sport_ebi1),
1111 .tier = tier2,
1112 .num_tiers = ARRAY_SIZE(tier2),
1113 .buswidth = 8,
1114 .slv_hw_id = SLV_EBI,
1115 .mode = NOC_QOS_MODE_BYPASS,
1116 },
1117 {
1118 .id = MSM_BUS_SLAVE_AMPSS_L2,
1119 .slavep = sport_kmpss_l2,
1120 .num_sports = ARRAY_SIZE(sport_kmpss_l2),
1121 .tier = tier2,
1122 .num_tiers = ARRAY_SIZE(tier2),
1123 .buswidth = 8,
1124 .slv_hw_id = SLV_APSS_L2,
1125 },
1126};
1127
1128static struct msm_bus_node_info ocmem_noc_info[] = {
1129 {
1130 .id = MSM_BUS_FAB_OCMEM_VNOC,
1131 .gateway = 1,
1132 .buswidth = 16,
1133 .mas_hw_id = MAS_OVNOC_ONOC,
1134 .slv_hw_id = SLV_ONOC_OVNOC,
1135 },
1136 {
1137 .id = MSM_BUS_MASTER_JPEG_OCMEM,
1138 .masterp = mport_jpeg_ocmem,
1139 .num_mports = ARRAY_SIZE(mport_jpeg_ocmem),
1140 .tier = tier2,
1141 .num_tiers = ARRAY_SIZE(tier2),
1142 .perm_mode = NOC_QOS_PERM_MODE_FIXED,
1143 .mode = NOC_QOS_MODE_FIXED,
1144 .qport = qports_gemini_ocmem,
1145 .mas_hw_id = MAS_JPEG_OCMEM,
1146 .hw_sel = MSM_BUS_NOC,
1147 },
1148 {
1149 .id = MSM_BUS_MASTER_MDP_OCMEM,
1150 .masterp = mport_mdp_ocmem,
1151 .num_mports = ARRAY_SIZE(mport_mdp_ocmem),
1152 .tier = tier2,
1153 .num_tiers = ARRAY_SIZE(tier2),
1154 .perm_mode = NOC_QOS_PERM_MODE_FIXED,
1155 .mode = NOC_QOS_MODE_FIXED,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1156 .mas_hw_id = MAS_MDP_OCMEM,
1157 .hw_sel = MSM_BUS_NOC,
1158 },
1159 {
1160 .id = MSM_BUS_MASTER_VIDEO_P0_OCMEM,
1161 .masterp = mport_video_p0_ocmem,
1162 .num_mports = ARRAY_SIZE(mport_video_p0_ocmem),
1163 .tier = tier2,
1164 .num_tiers = ARRAY_SIZE(tier2),
1165 .perm_mode = NOC_QOS_PERM_MODE_FIXED,
1166 .mode = NOC_QOS_MODE_FIXED,
1167 .qport = qports_venus_p0_ocmem,
1168 .mas_hw_id = MAS_VIDEO_P0_OCMEM,
1169 .hw_sel = MSM_BUS_NOC,
1170 },
1171 {
1172 .id = MSM_BUS_MASTER_VIDEO_P1_OCMEM,
1173 .masterp = mport_video_p1_ocmem,
1174 .num_mports = ARRAY_SIZE(mport_video_p1_ocmem),
1175 .tier = tier2,
1176 .num_tiers = ARRAY_SIZE(tier2),
1177 .perm_mode = NOC_QOS_PERM_MODE_FIXED,
1178 .mode = NOC_QOS_MODE_FIXED,
1179 .qport = qports_venus_p1_ocmem,
1180 .mas_hw_id = MAS_VIDEO_P1_OCMEM,
1181 .hw_sel = MSM_BUS_NOC,
1182 },
1183 {
1184 .id = MSM_BUS_MASTER_VFE_OCMEM,
1185 .masterp = mport_vfe_ocmem,
1186 .num_mports = ARRAY_SIZE(mport_vfe_ocmem),
1187 .tier = tier2,
1188 .num_tiers = ARRAY_SIZE(tier2),
1189 .perm_mode = NOC_QOS_PERM_MODE_FIXED,
1190 .mode = NOC_QOS_MODE_FIXED,
1191 .qport = qports_vfe_ocmem,
1192 .mas_hw_id = MAS_VFE_OCMEM,
1193 .hw_sel = MSM_BUS_NOC,
1194 .prio_rd = 1,
1195 .prio_wr = 1,
1196 },
1197 {
1198 .id = MSM_BUS_MASTER_CNOC_ONOC_CFG,
1199 .masterp = mport_cnoc_onoc_cfg,
1200 .num_mports = ARRAY_SIZE(mport_cnoc_onoc_cfg),
1201 .tier = tier2,
1202 .num_tiers = ARRAY_SIZE(tier2),
1203 .buswidth = 16,
1204 .mas_hw_id = MAS_CNOC_ONOC_CFG,
1205 .hw_sel = MSM_BUS_NOC,
1206 },
1207 {
1208 .id = MSM_BUS_SLAVE_SERVICE_ONOC,
1209 .slavep = sport_service_onoc,
1210 .num_sports = ARRAY_SIZE(sport_service_onoc),
1211 .tier = tier2,
1212 .num_tiers = ARRAY_SIZE(tier2),
1213 .buswidth = 16,
1214 .slv_hw_id = SLV_SERVICE_ONOC,
1215 },
1216};
1217
1218static struct msm_bus_node_info periph_noc_info[] = {
1219 {
1220 .id = MSM_BUS_MASTER_PNOC_CFG,
1221 .masterp = mport_pnoc_cfg,
1222 .num_mports = ARRAY_SIZE(mport_pnoc_cfg),
1223 .tier = tier2,
1224 .num_tiers = ARRAY_SIZE(tier2),
1225 .buswidth = 8,
1226 .mas_hw_id = MAS_PNOC_CFG,
1227 },
1228 {
1229 .id = MSM_BUS_MASTER_SDCC_1,
1230 .masterp = mport_sdcc_1,
1231 .num_mports = ARRAY_SIZE(mport_sdcc_1),
1232 .tier = tier2,
1233 .num_tiers = ARRAY_SIZE(tier2),
1234 .buswidth = 8,
1235 .mas_hw_id = MAS_SDCC_1,
1236 },
1237 {
1238 .id = MSM_BUS_MASTER_SDCC_3,
1239 .masterp = mport_sdcc_3,
1240 .num_mports = ARRAY_SIZE(mport_sdcc_3),
1241 .tier = tier2,
1242 .num_tiers = ARRAY_SIZE(tier2),
1243 .buswidth = 8,
1244 .mas_hw_id = MAS_SDCC_3,
1245 },
1246 {
1247 .id = MSM_BUS_MASTER_SDCC_4,
1248 .masterp = mport_sdcc_4,
1249 .num_mports = ARRAY_SIZE(mport_sdcc_4),
1250 .tier = tier2,
1251 .num_tiers = ARRAY_SIZE(tier2),
1252 .buswidth = 8,
1253 .mas_hw_id = MAS_SDCC_4,
1254 },
1255 {
1256 .id = MSM_BUS_MASTER_SDCC_2,
1257 .masterp = mport_sdcc_2,
1258 .num_mports = ARRAY_SIZE(mport_sdcc_2),
1259 .tier = tier2,
1260 .num_tiers = ARRAY_SIZE(tier2),
1261 .buswidth = 8,
1262 .mas_hw_id = MAS_SDCC_2,
1263 },
1264 {
1265 .id = MSM_BUS_MASTER_TSIF,
1266 .masterp = mport_tsif,
1267 .num_mports = ARRAY_SIZE(mport_tsif),
1268 .tier = tier2,
1269 .num_tiers = ARRAY_SIZE(tier2),
1270 .buswidth = 8,
1271 .mas_hw_id = MAS_TSIF,
1272 },
1273 {
1274 .id = MSM_BUS_MASTER_BAM_DMA,
1275 .masterp = mport_bam_dma,
1276 .num_mports = ARRAY_SIZE(mport_bam_dma),
1277 .tier = tier2,
1278 .num_tiers = ARRAY_SIZE(tier2),
1279 .buswidth = 8,
1280 .mas_hw_id = MAS_BAM_DMA,
1281 },
1282 {
1283 .id = MSM_BUS_MASTER_BLSP_2,
1284 .masterp = mport_blsp_2,
1285 .num_mports = ARRAY_SIZE(mport_blsp_2),
1286 .tier = tier2,
1287 .num_tiers = ARRAY_SIZE(tier2),
1288 .buswidth = 8,
1289 .mas_hw_id = MAS_BLSP_2,
1290 },
1291 {
1292 .id = MSM_BUS_MASTER_USB_HSIC,
1293 .masterp = mport_usb_hsic,
1294 .num_mports = ARRAY_SIZE(mport_usb_hsic),
1295 .tier = tier2,
1296 .num_tiers = ARRAY_SIZE(tier2),
1297 .buswidth = 8,
1298 .mas_hw_id = MAS_USB_HSIC,
1299 },
1300 {
1301 .id = MSM_BUS_MASTER_BLSP_1,
1302 .masterp = mport_blsp_1,
1303 .num_mports = ARRAY_SIZE(mport_blsp_1),
1304 .tier = tier2,
1305 .num_tiers = ARRAY_SIZE(tier2),
1306 .buswidth = 8,
1307 .mas_hw_id = MAS_BLSP_1,
1308 },
1309 {
1310 .id = MSM_BUS_MASTER_USB_HS,
1311 .masterp = mport_usb_hs,
1312 .num_mports = ARRAY_SIZE(mport_usb_hs),
1313 .tier = tier2,
1314 .num_tiers = ARRAY_SIZE(tier2),
1315 .buswidth = 8,
1316 .mas_hw_id = MAS_USB_HS,
1317 },
1318 {
1319 .id = MSM_BUS_FAB_SYS_NOC,
1320 .gateway = 1,
1321 .slavep = sport_gw_pnoc_snoc,
1322 .num_sports = ARRAY_SIZE(sport_gw_pnoc_snoc),
1323 .masterp = mport_gw_snoc_pnoc,
1324 .num_mports = ARRAY_SIZE(mport_gw_snoc_pnoc),
1325 .tier = tier2,
1326 .num_tiers = ARRAY_SIZE(tier2),
1327 .buswidth = 8,
1328 .slv_hw_id = SLV_PNOC_SNOC,
1329 .mas_hw_id = MAS_SNOC_PNOC,
1330 },
1331 {
1332 .id = MSM_BUS_SLAVE_SDCC_1,
1333 .slavep = sport_sdcc_1,
1334 .num_sports = ARRAY_SIZE(sport_sdcc_1),
1335 .tier = tier2,
1336 .num_tiers = ARRAY_SIZE(tier2),
1337 .buswidth = 8,
1338 .slv_hw_id = SLV_SDCC_1,
1339 },
1340 {
1341 .id = MSM_BUS_SLAVE_SDCC_3,
1342 .slavep = sport_sdcc_3,
1343 .num_sports = ARRAY_SIZE(sport_sdcc_3),
1344 .tier = tier2,
1345 .num_tiers = ARRAY_SIZE(tier2),
1346 .buswidth = 8,
1347 .slv_hw_id = SLV_SDCC_3,
1348 },
1349 {
1350 .id = MSM_BUS_SLAVE_SDCC_2,
1351 .slavep = sport_sdcc_2,
1352 .num_sports = ARRAY_SIZE(sport_sdcc_2),
1353 .tier = tier2,
1354 .num_tiers = ARRAY_SIZE(tier2),
1355 .buswidth = 8,
1356 .slv_hw_id = SLV_SDCC_2,
1357 },
1358 {
1359 .id = MSM_BUS_SLAVE_SDCC_4,
1360 .slavep = sport_sdcc_4,
1361 .num_sports = ARRAY_SIZE(sport_sdcc_4),
1362 .tier = tier2,
1363 .num_tiers = ARRAY_SIZE(tier2),
1364 .buswidth = 8,
1365 .slv_hw_id = SLV_SDCC_4,
1366 },
1367 {
1368 .id = MSM_BUS_SLAVE_TSIF,
1369 .slavep = sport_tsif,
1370 .num_sports = ARRAY_SIZE(sport_tsif),
1371 .tier = tier2,
1372 .num_tiers = ARRAY_SIZE(tier2),
1373 .buswidth = 8,
1374 .slv_hw_id = SLV_TSIF,
1375 },
1376 {
1377 .id = MSM_BUS_SLAVE_BAM_DMA,
1378 .slavep = sport_bam_dma,
1379 .num_sports = ARRAY_SIZE(sport_bam_dma),
1380 .tier = tier2,
1381 .num_tiers = ARRAY_SIZE(tier2),
1382 .buswidth = 8,
1383 .slv_hw_id = SLV_BAM_DMA,
1384 },
1385 {
1386 .id = MSM_BUS_SLAVE_BLSP_2,
1387 .slavep = sport_blsp_2,
1388 .num_sports = ARRAY_SIZE(sport_blsp_2),
1389 .tier = tier2,
1390 .num_tiers = ARRAY_SIZE(tier2),
1391 .buswidth = 8,
1392 .slv_hw_id = SLV_BLSP_2,
1393 },
1394 {
1395 .id = MSM_BUS_SLAVE_USB_HSIC,
1396 .slavep = sport_usb_hsic,
1397 .num_sports = ARRAY_SIZE(sport_usb_hsic),
1398 .tier = tier2,
1399 .num_tiers = ARRAY_SIZE(tier2),
1400 .buswidth = 8,
1401 .slv_hw_id = SLV_USB_HSIC,
1402 },
1403 {
1404 .id = MSM_BUS_SLAVE_BLSP_1,
1405 .slavep = sport_blsp_1,
1406 .num_sports = ARRAY_SIZE(sport_blsp_1),
1407 .tier = tier2,
1408 .num_tiers = ARRAY_SIZE(tier2),
1409 .buswidth = 8,
1410 .slv_hw_id = SLV_BLSP_1,
1411 },
1412 {
1413 .id = MSM_BUS_SLAVE_USB_HS,
1414 .slavep = sport_usb_hs,
1415 .num_sports = ARRAY_SIZE(sport_usb_hs),
1416 .tier = tier2,
1417 .num_tiers = ARRAY_SIZE(tier2),
1418 .buswidth = 8,
1419 .slv_hw_id = SLV_USB_HS,
1420 },
1421 {
1422 .id = MSM_BUS_SLAVE_PDM,
1423 .slavep = sport_pdm,
1424 .num_sports = ARRAY_SIZE(sport_pdm),
1425 .tier = tier2,
1426 .num_tiers = ARRAY_SIZE(tier2),
1427 .buswidth = 8,
1428 .slv_hw_id = SLV_PDM,
1429 },
1430 {
1431 .id = MSM_BUS_SLAVE_PERIPH_APU_CFG,
1432 .slavep = sport_periph_apu_cfg,
1433 .num_sports = ARRAY_SIZE(sport_periph_apu_cfg),
1434 .tier = tier2,
1435 .num_tiers = ARRAY_SIZE(tier2),
1436 .buswidth = 8,
1437 .slv_hw_id = SLV_PERIPH_APU_CFG,
1438 },
1439 {
1440 .id = MSM_BUS_SLAVE_PNOC_MPU_CFG,
1441 .slavep = sport_pnoc_mpu_cfg,
1442 .num_sports = ARRAY_SIZE(sport_pnoc_mpu_cfg),
1443 .tier = tier2,
1444 .num_tiers = ARRAY_SIZE(tier2),
1445 .buswidth = 8,
1446 .slv_hw_id = SLV_MPU_CFG,
1447 },
1448 {
1449 .id = MSM_BUS_SLAVE_PRNG,
1450 .slavep = sport_prng,
1451 .num_sports = ARRAY_SIZE(sport_prng),
1452 .tier = tier2,
1453 .num_tiers = ARRAY_SIZE(tier2),
1454 .buswidth = 8,
1455 .slv_hw_id = SLV_PRNG,
1456 },
1457 {
1458 .id = MSM_BUS_SLAVE_SERVICE_PNOC,
1459 .slavep = sport_service_pnoc,
1460 .num_sports = ARRAY_SIZE(sport_service_pnoc),
1461 .tier = tier2,
1462 .num_tiers = ARRAY_SIZE(tier2),
1463 .buswidth = 8,
1464 .slv_hw_id = SLV_SERVICE_PNOC,
1465 },
1466};
1467
1468static struct msm_bus_node_info config_noc_info[] = {
1469 {
1470 .id = MSM_BUS_MASTER_RPM_INST,
1471 .masterp = mport_rpm_inst,
1472 .num_mports = ARRAY_SIZE(mport_rpm_inst),
1473 .tier = tier2,
1474 .num_tiers = ARRAY_SIZE(tier2),
1475 .buswidth = 8,
1476 .mas_hw_id = MAS_RPM_INST,
1477 },
1478 {
1479 .id = MSM_BUS_MASTER_RPM_DATA,
1480 .masterp = mport_rpm_data,
1481 .num_mports = ARRAY_SIZE(mport_rpm_data),
1482 .tier = tier2,
1483 .num_tiers = ARRAY_SIZE(tier2),
1484 .buswidth = 8,
1485 .mas_hw_id = MAS_RPM_DATA,
1486 },
1487 {
1488 .id = MSM_BUS_MASTER_RPM_SYS,
1489 .masterp = mport_rpm_sys,
1490 .num_mports = ARRAY_SIZE(mport_rpm_sys),
1491 .tier = tier2,
1492 .num_tiers = ARRAY_SIZE(tier2),
1493 .buswidth = 8,
1494 .mas_hw_id = MAS_RPM_SYS,
1495 },
1496 {
1497 .id = MSM_BUS_MASTER_DEHR,
1498 .masterp = mport_dehr,
1499 .num_mports = ARRAY_SIZE(mport_dehr),
1500 .tier = tier2,
1501 .num_tiers = ARRAY_SIZE(tier2),
1502 .buswidth = 8,
1503 .mas_hw_id = MAS_DEHR,
1504 },
1505 {
1506 .id = MSM_BUS_MASTER_QDSS_DAP,
1507 .masterp = mport_qdss_dap,
1508 .num_mports = ARRAY_SIZE(mport_qdss_dap),
1509 .tier = tier2,
1510 .num_tiers = ARRAY_SIZE(tier2),
1511 .buswidth = 8,
1512 .mas_hw_id = MAS_QDSS_DAP,
1513 },
1514 {
1515 .id = MSM_BUS_MASTER_SPDM,
1516 .masterp = mport_spdm,
1517 .num_mports = ARRAY_SIZE(mport_spdm),
1518 .tier = tier2,
1519 .num_tiers = ARRAY_SIZE(tier2),
1520 .buswidth = 8,
1521 .mas_hw_id = MAS_SPDM,
1522 },
1523 {
1524 .id = MSM_BUS_MASTER_TIC,
1525 .masterp = mport_tic,
1526 .num_mports = ARRAY_SIZE(mport_tic),
1527 .tier = tier2,
1528 .num_tiers = ARRAY_SIZE(tier2),
1529 .buswidth = 8,
1530 .mas_hw_id = MAS_TIC,
1531 },
1532 {
1533 .id = MSM_BUS_SLAVE_CLK_CTL,
1534 .slavep = sport_clk_ctl,
1535 .num_sports = ARRAY_SIZE(sport_clk_ctl),
1536 .tier = tier2,
1537 .num_tiers = ARRAY_SIZE(tier2),
1538 .buswidth = 8,
1539 .slv_hw_id = SLV_CLK_CTL,
1540 },
1541 {
1542 .id = MSM_BUS_SLAVE_CNOC_MSS,
1543 .slavep = sport_cnoc_mss,
1544 .num_sports = ARRAY_SIZE(sport_cnoc_mss),
1545 .tier = tier2,
1546 .num_tiers = ARRAY_SIZE(tier2),
1547 .buswidth = 8,
1548 .slv_hw_id = SLV_CNOC_MSS,
1549 },
1550 {
1551 .id = MSM_BUS_SLAVE_SECURITY,
1552 .slavep = sport_security,
1553 .num_sports = ARRAY_SIZE(sport_security),
1554 .tier = tier2,
1555 .num_tiers = ARRAY_SIZE(tier2),
1556 .buswidth = 8,
1557 .slv_hw_id = SLV_SECURITY,
1558 },
1559 {
1560 .id = MSM_BUS_SLAVE_TCSR,
1561 .slavep = sport_tcsr,
1562 .num_sports = ARRAY_SIZE(sport_tcsr),
1563 .tier = tier2,
1564 .num_tiers = ARRAY_SIZE(tier2),
1565 .buswidth = 8,
1566 .slv_hw_id = SLV_TCSR,
1567 },
1568 {
1569 .id = MSM_BUS_SLAVE_TLMM,
1570 .slavep = sport_tlmm,
1571 .num_sports = ARRAY_SIZE(sport_tlmm),
1572 .tier = tier2,
1573 .num_tiers = ARRAY_SIZE(tier2),
1574 .buswidth = 8,
1575 .slv_hw_id = SLV_TLMM,
1576 },
1577 {
1578 .id = MSM_BUS_SLAVE_CRYPTO_0_CFG,
1579 .slavep = sport_crypto_0_cfg,
1580 .num_sports = ARRAY_SIZE(sport_crypto_0_cfg),
1581 .tier = tier2,
1582 .num_tiers = ARRAY_SIZE(tier2),
1583 .buswidth = 8,
1584 .slv_hw_id = SLV_CRYPTO_0_CFG,
1585 },
1586 {
1587 .id = MSM_BUS_SLAVE_CRYPTO_1_CFG,
1588 .slavep = sport_crypto_1_cfg,
1589 .num_sports = ARRAY_SIZE(sport_crypto_1_cfg),
1590 .tier = tier2,
1591 .num_tiers = ARRAY_SIZE(tier2),
1592 .buswidth = 8,
1593 .slv_hw_id = SLV_CRYPTO_1_CFG,
1594 },
1595 {
1596 .id = MSM_BUS_SLAVE_IMEM_CFG,
1597 .slavep = sport_imem_cfg,
1598 .num_sports = ARRAY_SIZE(sport_imem_cfg),
1599 .tier = tier2,
1600 .num_tiers = ARRAY_SIZE(tier2),
1601 .buswidth = 8,
1602 .slv_hw_id = SLV_IMEM_CFG,
1603 },
1604 {
1605 .id = MSM_BUS_SLAVE_MESSAGE_RAM,
1606 .slavep = sport_message_ram,
1607 .num_sports = ARRAY_SIZE(sport_message_ram),
1608 .tier = tier2,
1609 .num_tiers = ARRAY_SIZE(tier2),
1610 .buswidth = 8,
1611 .slv_hw_id = SLV_MESSAGE_RAM,
1612 },
1613 {
1614 .id = MSM_BUS_SLAVE_BIMC_CFG,
1615 .slavep = sport_bimc_cfg,
1616 .num_sports = ARRAY_SIZE(sport_bimc_cfg),
1617 .tier = tier2,
1618 .num_tiers = ARRAY_SIZE(tier2),
1619 .buswidth = 8,
1620 .slv_hw_id = SLV_BIMC_CFG,
1621 },
1622 {
1623 .id = MSM_BUS_SLAVE_BOOT_ROM,
1624 .slavep = sport_boot_rom,
1625 .num_sports = ARRAY_SIZE(sport_boot_rom),
1626 .tier = tier2,
1627 .num_tiers = ARRAY_SIZE(tier2),
1628 .buswidth = 8,
1629 .slv_hw_id = SLV_BOOT_ROM,
1630 },
1631 {
1632 .id = MSM_BUS_SLAVE_PMIC_ARB,
1633 .slavep = sport_pmic_arb,
1634 .num_sports = ARRAY_SIZE(sport_pmic_arb),
1635 .tier = tier2,
1636 .num_tiers = ARRAY_SIZE(tier2),
1637 .buswidth = 8,
1638 .slv_hw_id = SLV_PMIC_ARB,
1639 },
1640 {
1641 .id = MSM_BUS_SLAVE_SPDM_WRAPPER,
1642 .slavep = sport_spdm_wrapper,
1643 .num_sports = ARRAY_SIZE(sport_spdm_wrapper),
1644 .tier = tier2,
1645 .num_tiers = ARRAY_SIZE(tier2),
1646 .buswidth = 8,
1647 .slv_hw_id = SLV_SPDM_WRAPPER,
1648 },
1649 {
1650 .id = MSM_BUS_SLAVE_DEHR_CFG,
1651 .slavep = sport_dehr_cfg,
1652 .num_sports = ARRAY_SIZE(sport_dehr_cfg),
1653 .tier = tier2,
1654 .num_tiers = ARRAY_SIZE(tier2),
1655 .buswidth = 8,
1656 .slv_hw_id = SLV_DEHR_CFG,
1657 },
1658 {
1659 .id = MSM_BUS_SLAVE_MPM,
1660 .slavep = sport_mpm,
1661 .num_sports = ARRAY_SIZE(sport_mpm),
1662 .tier = tier2,
1663 .num_tiers = ARRAY_SIZE(tier2),
1664 .buswidth = 8,
1665 .slv_hw_id = SLV_MPM,
1666 },
1667 {
1668 .id = MSM_BUS_SLAVE_QDSS_CFG,
1669 .slavep = sport_qdss_cfg,
1670 .num_sports = ARRAY_SIZE(sport_qdss_cfg),
1671 .tier = tier2,
1672 .num_tiers = ARRAY_SIZE(tier2),
1673 .buswidth = 8,
1674 .slv_hw_id = SLV_QDSS_CFG,
1675 },
1676 {
1677 .id = MSM_BUS_SLAVE_RBCPR_CFG,
1678 .slavep = sport_rbcpr_cfg,
1679 .num_sports = ARRAY_SIZE(sport_rbcpr_cfg),
1680 .tier = tier2,
1681 .num_tiers = ARRAY_SIZE(tier2),
1682 .buswidth = 8,
1683 .slv_hw_id = SLV_RBCPR_CFG,
1684 },
1685 {
1686 .id = MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG,
1687 .slavep = sport_rbcpr_qdss_apu_cfg,
1688 .num_sports = ARRAY_SIZE(sport_rbcpr_qdss_apu_cfg),
1689 .tier = tier2,
1690 .num_tiers = ARRAY_SIZE(tier2),
1691 .buswidth = 8,
1692 .slv_hw_id = SLV_RBCPR_QDSS_APU_CFG,
1693 },
1694 {
1695 .id = MSM_BUS_FAB_SYS_NOC,
1696 .gateway = 1,
1697 .slavep = sport_gw_cnoc_snoc,
1698 .num_sports = ARRAY_SIZE(sport_gw_cnoc_snoc),
1699 .masterp = mport_gw_snoc_cnoc,
1700 .num_mports = ARRAY_SIZE(mport_gw_snoc_cnoc),
1701 .tier = tier2,
1702 .num_tiers = ARRAY_SIZE(tier2),
1703 .buswidth = 8,
1704 .mas_hw_id = MAS_SNOC_CNOC,
1705 .slv_hw_id = SLV_CNOC_SNOC,
1706 },
1707 {
1708 .id = MSM_BUS_SLAVE_CNOC_ONOC_CFG,
1709 .slavep = sport_cnoc_onoc_cfg,
1710 .num_sports = ARRAY_SIZE(sport_cnoc_onoc_cfg),
1711 .tier = tier2,
1712 .num_tiers = ARRAY_SIZE(tier2),
1713 .buswidth = 8,
1714 .slv_hw_id = SLV_CNOC_ONOC_CFG,
1715 },
1716 {
1717 .id = MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG,
1718 .slavep = sport_cnoc_mnoc_mmss_cfg,
1719 .num_sports = ARRAY_SIZE(sport_cnoc_mnoc_mmss_cfg),
1720 .tier = tier2,
1721 .num_tiers = ARRAY_SIZE(tier2),
1722 .buswidth = 8,
1723 .slv_hw_id = SLV_CNOC_MNOC_MMSS_CFG,
1724 },
1725 {
1726 .id = MSM_BUS_SLAVE_CNOC_MNOC_CFG,
1727 .slavep = sport_cnoc_mnoc_cfg,
1728 .num_sports = ARRAY_SIZE(sport_cnoc_mnoc_cfg),
1729 .tier = tier2,
1730 .num_tiers = ARRAY_SIZE(tier2),
1731 .buswidth = 8,
1732 .slv_hw_id = SLV_CNOC_MNOC_CFG,
1733 },
1734 {
1735 .id = MSM_BUS_SLAVE_PNOC_CFG,
1736 .slavep = sport_pnoc_cfg,
1737 .num_sports = ARRAY_SIZE(sport_pnoc_cfg),
1738 .tier = tier2,
1739 .num_tiers = ARRAY_SIZE(tier2),
1740 .buswidth = 8,
1741 .slv_hw_id = SLV_PNOC_CFG,
1742 },
1743 {
1744 .id = MSM_BUS_SLAVE_SNOC_MPU_CFG,
1745 .slavep = sport_snoc_mpu_cfg,
1746 .num_sports = ARRAY_SIZE(sport_snoc_mpu_cfg),
1747 .tier = tier2,
1748 .num_tiers = ARRAY_SIZE(tier2),
1749 .buswidth = 8,
1750 .slv_hw_id = SLV_SNOC_MPU_CFG,
1751 },
1752 {
1753 .id = MSM_BUS_SLAVE_SNOC_CFG,
1754 .slavep = sport_snoc_cfg,
1755 .num_sports = ARRAY_SIZE(sport_snoc_cfg),
1756 .tier = tier2,
1757 .num_tiers = ARRAY_SIZE(tier2),
1758 .buswidth = 8,
1759 .slv_hw_id = SLV_SNOC_CFG,
1760 },
1761 {
1762 .id = MSM_BUS_SLAVE_EBI1_DLL_CFG,
1763 .slavep = sport_ebi1_dll_cfg,
1764 .num_sports = ARRAY_SIZE(sport_ebi1_dll_cfg),
1765 .tier = tier2,
1766 .num_tiers = ARRAY_SIZE(tier2),
1767 .buswidth = 8,
1768 .slv_hw_id = SLV_EBI1_DLL_CFG,
1769 },
1770 {
1771 .id = MSM_BUS_SLAVE_PHY_APU_CFG,
1772 .slavep = sport_phy_apu_cfg,
1773 .num_sports = ARRAY_SIZE(sport_phy_apu_cfg),
1774 .tier = tier2,
1775 .num_tiers = ARRAY_SIZE(tier2),
1776 .buswidth = 8,
1777 .slv_hw_id = SLV_PHY_APU_CFG,
1778 },
1779 {
1780 .id = MSM_BUS_SLAVE_EBI1_PHY_CFG,
1781 .slavep = sport_ebi1_phy_cfg,
1782 .num_sports = ARRAY_SIZE(sport_ebi1_phy_cfg),
1783 .tier = tier2,
1784 .num_tiers = ARRAY_SIZE(tier2),
1785 .buswidth = 8,
1786 .slv_hw_id = SLV_EBI1_PHY_CFG,
1787 },
1788 {
1789 .id = MSM_BUS_SLAVE_RPM,
1790 .slavep = sport_rpm,
1791 .num_sports = ARRAY_SIZE(sport_rpm),
1792 .tier = tier2,
1793 .num_tiers = ARRAY_SIZE(tier2),
1794 .buswidth = 8,
1795 .slv_hw_id = SLV_RPM,
1796 },
1797 {
1798 .id = MSM_BUS_SLAVE_SERVICE_CNOC,
1799 .slavep = sport_service_cnoc,
1800 .num_sports = ARRAY_SIZE(sport_service_cnoc),
1801 .tier = tier2,
1802 .num_tiers = ARRAY_SIZE(tier2),
1803 .buswidth = 8,
1804 .slv_hw_id = SLV_SERVICE_CNOC,
1805 },
1806};
1807
1808/* A virtual NoC is needed for connection to OCMEM */
1809static struct msm_bus_node_info ocmem_vnoc_info[] = {
1810 {
1811 .id = MSM_BUS_MASTER_V_OCMEM_GFX3D,
1812 .tier = tier2,
1813 .num_tiers = ARRAY_SIZE(tier2),
1814 .buswidth = 8,
1815 .mas_hw_id = MAS_V_OCMEM_GFX3D,
1816 },
1817 {
1818 .id = MSM_BUS_SLAVE_OCMEM,
1819 .slavep = sport_ocmem,
1820 .num_sports = ARRAY_SIZE(sport_ocmem),
1821 .tier = tier2,
1822 .num_tiers = ARRAY_SIZE(tier2),
1823 .buswidth = 16,
1824 .slv_hw_id = SLV_OCMEM,
1825 .tier = tier2,
1826 .slaveclk[DUAL_CTX] = "ocmem_clk",
1827 .slaveclk[ACTIVE_CTX] = "ocmem_a_clk",
1828 },
1829 {
1830 .id = MSM_BUS_FAB_SYS_NOC,
1831 .gateway = 1,
1832 .buswidth = 8,
1833 .ws = 10000,
1834 .mas_hw_id = MAS_SNOC_OVNOC,
1835 .slv_hw_id = SLV_OVNOC_SNOC,
1836 },
1837 {
1838 .id = MSM_BUS_FAB_OCMEM_NOC,
1839 .gateway = 1,
1840 .buswidth = 16,
1841 .ws = 10000,
1842 .mas_hw_id = MAS_ONOC_OVNOC,
1843 .slv_hw_id = SLV_OVNOC_ONOC,
1844 },
1845};
1846
1847static void msm_bus_board_assign_iids(struct msm_bus_fabric_registration
1848 *fabreg, int fabid)
1849{
1850 int i;
1851 for (i = 0; i < fabreg->len; i++) {
1852 if (!fabreg->info[i].gateway) {
1853 fabreg->info[i].priv_id = fabid + fabreg->info[i].id;
1854 if (fabreg->info[i].id < SLAVE_ID_KEY) {
1855 WARN(fabreg->info[i].id >= NMASTERS,
1856 "id %d exceeds array size!\n",
1857 fabreg->info[i].id);
1858 master_iids[fabreg->info[i].id] =
1859 fabreg->info[i].priv_id;
1860 } else {
1861 WARN((fabreg->info[i].id - SLAVE_ID_KEY) >=
1862 NSLAVES, "id %d exceeds array size!\n",
1863 fabreg->info[i].id);
1864 slave_iids[fabreg->info[i].id - (SLAVE_ID_KEY)]
1865 = fabreg->info[i].priv_id;
1866 }
1867 } else {
1868 fabreg->info[i].priv_id = fabreg->info[i].id;
1869 }
1870 }
1871}
1872
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1873static int msm_bus_board_8974_get_iid(int id)
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1874{
1875 if ((id < SLAVE_ID_KEY && id >= NMASTERS) ||
1876 id >= (SLAVE_ID_KEY + NSLAVES)) {
1877 MSM_BUS_ERR("Cannot get iid. Invalid id %d passed\n", id);
1878 return -EINVAL;
1879 }
1880
1881 return CHECK_ID(((id < SLAVE_ID_KEY) ? master_iids[id] :
1882 slave_iids[id - SLAVE_ID_KEY]), id);
1883}
1884
1885int msm_bus_board_rpm_get_il_ids(uint16_t *id)
1886{
1887 return -ENXIO;
1888}
1889
1890static struct msm_bus_board_algorithm msm_bus_board_algo = {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1891 .board_nfab = NFAB_8974,
1892 .get_iid = msm_bus_board_8974_get_iid,
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1893 .assign_iids = msm_bus_board_assign_iids,
1894};
1895
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1896struct msm_bus_fabric_registration msm_bus_8974_sys_noc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1897 .id = MSM_BUS_FAB_SYS_NOC,
1898 .name = "msm_sys_noc",
1899 .info = sys_noc_info,
1900 .len = ARRAY_SIZE(sys_noc_info),
1901 .ahb = 0,
1902 .fabclk[DUAL_CTX] = "bus_clk",
1903 .fabclk[ACTIVE_CTX] = "bus_a_clk",
1904 .nmasters = 15,
1905 .nslaves = 12,
1906 .ntieredslaves = 0,
1907 .board_algo = &msm_bus_board_algo,
1908 .qos_freq = 4800,
1909 .hw_sel = MSM_BUS_NOC,
1910 .rpm_enabled = 1,
1911};
1912
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1913struct msm_bus_fabric_registration msm_bus_8974_mmss_noc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1914 .id = MSM_BUS_FAB_MMSS_NOC,
1915 .name = "msm_mmss_noc",
1916 .info = mmss_noc_info,
1917 .len = ARRAY_SIZE(mmss_noc_info),
1918 .ahb = 0,
1919 .fabclk[DUAL_CTX] = "bus_clk",
1920 .fabclk[ACTIVE_CTX] = "bus_a_clk",
1921 .nmasters = 9,
1922 .nslaves = 16,
1923 .ntieredslaves = 0,
1924 .board_algo = &msm_bus_board_algo,
1925 .qos_freq = 4800,
1926 .hw_sel = MSM_BUS_NOC,
1927 .rpm_enabled = 1,
1928};
1929
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1930struct msm_bus_fabric_registration msm_bus_8974_bimc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1931 .id = MSM_BUS_FAB_BIMC,
1932 .name = "msm_bimc",
1933 .info = bimc_info,
1934 .len = ARRAY_SIZE(bimc_info),
1935 .ahb = 0,
1936 .fabclk[DUAL_CTX] = "mem_clk",
1937 .fabclk[ACTIVE_CTX] = "mem_a_clk",
1938 .nmasters = 7,
1939 .nslaves = 4,
1940 .ntieredslaves = 0,
1941 .board_algo = &msm_bus_board_algo,
1942 .qos_freq = 4800,
1943 .hw_sel = MSM_BUS_BIMC,
1944 .rpm_enabled = 1,
1945};
1946
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1947struct msm_bus_fabric_registration msm_bus_8974_ocmem_noc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1948 .id = MSM_BUS_FAB_OCMEM_NOC,
1949 .name = "msm_ocmem_noc",
1950 .info = ocmem_noc_info,
1951 .len = ARRAY_SIZE(ocmem_noc_info),
1952 .ahb = 0,
1953 .fabclk[DUAL_CTX] = "bus_clk",
1954 .fabclk[ACTIVE_CTX] = "bus_a_clk",
1955 .nmasters = 6,
1956 .nslaves = 3,
1957 .ntieredslaves = 0,
1958 .board_algo = &msm_bus_board_algo,
1959 .qos_freq = 4800,
1960 .hw_sel = MSM_BUS_NOC,
1961 .rpm_enabled = 1,
1962};
1963
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1964struct msm_bus_fabric_registration msm_bus_8974_periph_noc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1965 .id = MSM_BUS_FAB_PERIPH_NOC,
1966 .name = "msm_periph_noc",
1967 .info = periph_noc_info,
1968 .len = ARRAY_SIZE(periph_noc_info),
1969 .ahb = 0,
1970 .fabclk[DUAL_CTX] = "bus_clk",
1971 .fabclk[ACTIVE_CTX] = "bus_a_clk",
1972 .nmasters = 12,
1973 .nslaves = 16,
1974 .ntieredslaves = 0,
1975 .board_algo = &msm_bus_board_algo,
1976 .hw_sel = MSM_BUS_NOC,
1977 .rpm_enabled = 1,
1978};
1979
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1980struct msm_bus_fabric_registration msm_bus_8974_config_noc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1981 .id = MSM_BUS_FAB_CONFIG_NOC,
1982 .name = "msm_config_noc",
1983 .info = config_noc_info,
1984 .len = ARRAY_SIZE(config_noc_info),
1985 .ahb = 0,
1986 .fabclk[DUAL_CTX] = "bus_clk",
1987 .fabclk[ACTIVE_CTX] = "bus_a_clk",
1988 .nmasters = 8,
1989 .nslaves = 30,
1990 .ntieredslaves = 0,
1991 .board_algo = &msm_bus_board_algo,
1992 .hw_sel = MSM_BUS_NOC,
1993 .rpm_enabled = 1,
1994};
1995
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]1996struct msm_bus_fabric_registration msm_bus_8974_ocmem_vnoc_pdata = {
Gagan Mac4eba8b92012-02-13 17:45:28 -0700[diff] [blame]1997 .id = MSM_BUS_FAB_OCMEM_VNOC,
1998 .name = "msm_ocmem_vnoc",
1999 .info = ocmem_vnoc_info,
2000 .len = ARRAY_SIZE(ocmem_vnoc_info),
2001 .ahb = 0,
2002 .nmasters = 5,
2003 .nslaves = 4,
2004 .ntieredslaves = 0,
2005 .board_algo = &msm_bus_board_algo,
2006 .hw_sel = MSM_BUS_NOC,
2007 .virt = 1,
2008 .rpm_enabled = 1,
2009};
Gagan Mac7c7e5542012-12-19 19:28:47 -0700[diff] [blame]2010
2011void msm_bus_board_init(struct msm_bus_fabric_registration *pdata)
2012{
2013 pdata->board_algo = &msm_bus_board_algo;
2014}