blob: 503ac777a2ba8682b35f0798eccd80f3f8621763 [file] [log] [blame]
Santosh Shilimkar367cd312009-04-28 20:51:52 +05301/*
2 * Secondary CPU startup routine source file.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software,you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/linkage.h>
19#include <linux/init.h>
20
Russell King45176f42012-02-07 10:34:01 +000021 __CPUINIT
Santosh Shilimkar367cd312009-04-28 20:51:52 +053022/*
23 * OMAP4 specific entry point for secondary CPU to jump from ROM
24 * code. This routine also provides a holding flag into which
25 * secondary core is held until we're ready for it to initialise.
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080026 * The primary core will update this flag using a hardware
27 * register AuxCoreBoot0.
Santosh Shilimkar367cd312009-04-28 20:51:52 +053028 */
29ENTRY(omap_secondary_startup)
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080030hold: ldr r12,=0x103
31 dsb
Richard Woodruffdf571c42010-04-07 07:47:21 +000032 smc #0 @ read from AuxCoreBoot0
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080033 mov r0, r0, lsr #9
34 mrc p15, 0, r4, c0, c0, 5
35 and r4, r4, #0x0f
36 cmp r0, r4
Santosh Shilimkar367cd312009-04-28 20:51:52 +053037 bne hold
38
39 /*
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080040 * we've been released from the wait loop,secondary_stack
Santosh Shilimkar367cd312009-04-28 20:51:52 +053041 * should now contain the SVC stack for this core
42 */
43 b secondary_startup
Dave Martinf96bdfa2011-03-04 15:33:54 +000044ENDPROC(omap_secondary_startup)
Santosh Shilimkar367cd312009-04-28 20:51:52 +053045