blob: 95442b69ae27111fc4bf5dba66eaaa8e01c6547a [file] [log] [blame]
Kevin Hilman8bd22942009-05-28 10:56:16 -07001/*
2 * OMAP2 Power Management Routines
3 *
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
6 *
7 * Written by:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Tony Lindgren
10 * Juha Yrjola
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/suspend.h>
22#include <linux/sched.h>
23#include <linux/proc_fs.h>
24#include <linux/interrupt.h>
25#include <linux/sysfs.h>
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070029#include <linux/irq.h>
30#include <linux/time.h>
31#include <linux/gpio.h>
32
33#include <asm/mach/time.h>
34#include <asm/mach/irq.h>
35#include <asm/mach-types.h>
David Howells9f97da72012-03-28 18:30:01 +010036#include <asm/system_misc.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070037
Tony Lindgrence491cf2009-10-20 09:40:47 -070038#include <plat/clock.h>
39#include <plat/sram.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070040#include <plat/dma.h>
41#include <plat/board.h>
Kevin Hilman8bd22942009-05-28 10:56:16 -070042
Tony Lindgrenee0839c2012-02-24 10:34:35 -080043#include <mach/irqs.h>
44
Tony Lindgren4e653312011-11-10 22:45:17 +010045#include "common.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070046#include "prm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070047#include "prm-regbits-24xx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070048#include "cm2xxx_3xxx.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070049#include "cm-regbits-24xx.h"
50#include "sdrc.h"
51#include "pm.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060052#include "control.h"
Paul Walmsley72e06d02010-12-21 21:05:16 -070053#include "powerdomain.h"
Paul Walmsley1540f2142010-12-21 21:05:15 -070054#include "clockdomain.h"
Kevin Hilman8bd22942009-05-28 10:56:16 -070055
56static void (*omap2_sram_idle)(void);
57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
58 void __iomem *sdrc_power);
59
Paul Walmsley369d5612010-01-26 20:13:01 -070060static struct powerdomain *mpu_pwrdm, *core_pwrdm;
61static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
Kevin Hilman8bd22942009-05-28 10:56:16 -070062
63static struct clk *osc_ck, *emul_ck;
64
65static int omap2_fclks_active(void)
66{
67 u32 f1, f2;
68
Paul Walmsleyc4d7e582010-12-21 21:05:14 -070069 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
70 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
Kevin Hilman4af40162009-02-04 10:51:40 -080071
Paul Walmsley1e056dd2012-02-09 18:24:03 -070072 return (f1 | f2) ? 1 : 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -070073}
74
Paul Walmsley14164082012-02-02 02:30:50 -070075static int omap2_enter_full_retention(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -070076{
77 u32 l;
Kevin Hilman8bd22942009-05-28 10:56:16 -070078
79 /* There is 1 reference hold for all children of the oscillator
80 * clock, the following will remove it. If no one else uses the
81 * oscillator itself it will be disabled if/when we enter retention
82 * mode.
83 */
84 clk_disable(osc_ck);
85
86 /* Clear old wake-up events */
87 /* REVISIT: These write to reserved bits? */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -070088 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
89 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
90 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
Kevin Hilman8bd22942009-05-28 10:56:16 -070091
92 /*
93 * Set MPU powerdomain's next power state to RETENTION;
94 * preserve logic state during retention
95 */
96 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
97 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
98
99 /* Workaround to kill USB */
100 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
101 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
102
Paul Walmsley72e06d02010-12-21 21:05:16 -0700103 omap2_gpio_prepare_for_idle(0);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700104
Kevin Hilman8bd22942009-05-28 10:56:16 -0700105 /* One last check for pending IRQs to avoid extra latency due
106 * to sleeping unnecessarily. */
Jouni Hogander94434532009-02-03 15:49:04 -0800107 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700108 goto no_sleep;
109
110 /* Jump to SRAM suspend code */
111 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
112 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
113 OMAP_SDRC_REGADDR(SDRC_POWER));
Kevin Hilman8bd22942009-05-28 10:56:16 -0700114
Kevin Hilman4af40162009-02-04 10:51:40 -0800115no_sleep:
Kevin Hilman43ffcd92009-01-27 11:09:24 -0800116 omap2_gpio_resume_after_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700117
118 clk_enable(osc_ck);
119
120 /* clear CORE wake-up events */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700121 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
122 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700123
124 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700125 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700126
127 /* MPU domain wake events */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700128 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700129 if (l & 0x01)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700130 omap2_prm_write_mod_reg(0x01, OCP_MOD,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700131 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
132 if (l & 0x20)
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700133 omap2_prm_write_mod_reg(0x20, OCP_MOD,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700134 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
135
136 /* Mask future PRCM-to-MPU interrupts */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700137 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
Paul Walmsley14164082012-02-02 02:30:50 -0700138
139 return 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700140}
141
142static int omap2_i2c_active(void)
143{
144 u32 l;
145
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700146 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsleyf38ca102010-05-20 12:31:04 -0600147 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700148}
149
150static int sti_console_enabled;
151
152static int omap2_allow_mpu_retention(void)
153{
154 u32 l;
155
156 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700157 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600158 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
159 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
160 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
Kevin Hilman8bd22942009-05-28 10:56:16 -0700161 return 0;
162 /* Check for UART3. */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700163 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600164 if (l & OMAP24XX_EN_UART3_MASK)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700165 return 0;
166 if (sti_console_enabled)
167 return 0;
168
169 return 1;
170}
171
172static void omap2_enter_mpu_retention(void)
173{
174 int only_idle = 0;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700175
176 /* Putting MPU into the WFI state while a transfer is active
177 * seems to cause the I2C block to timeout. Why? Good question. */
178 if (omap2_i2c_active())
179 return;
180
181 /* The peripherals seem not to be able to wake up the MPU when
182 * it is in retention mode. */
183 if (omap2_allow_mpu_retention()) {
184 /* REVISIT: These write to reserved bits? */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700185 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
186 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
187 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700188
189 /* Try to enter MPU retention */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700190 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600191 OMAP_LOGICRETSTATE_MASK,
Abhijit Pagare37903002010-01-26 20:12:51 -0700192 MPU_MOD, OMAP2_PM_PWSTCTRL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700193 } else {
194 /* Block MPU retention */
195
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700196 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
Abhijit Pagare37903002010-01-26 20:12:51 -0700197 OMAP2_PM_PWSTCTRL);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700198 only_idle = 1;
199 }
200
Kevin Hilman8bd22942009-05-28 10:56:16 -0700201 omap2_sram_idle();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700202}
203
204static int omap2_can_sleep(void)
205{
206 if (omap2_fclks_active())
207 return 0;
208 if (osc_ck->usecount > 1)
209 return 0;
210 if (omap_dma_running())
211 return 0;
212
213 return 1;
214}
215
216static void omap2_pm_idle(void)
217{
Kevin Hilman8bd22942009-05-28 10:56:16 -0700218 local_fiq_disable();
219
220 if (!omap2_can_sleep()) {
Jouni Hogander94434532009-02-03 15:49:04 -0800221 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700222 goto out;
223 omap2_enter_mpu_retention();
224 goto out;
225 }
226
Jouni Hogander94434532009-02-03 15:49:04 -0800227 if (omap_irq_pending())
Kevin Hilman8bd22942009-05-28 10:56:16 -0700228 goto out;
229
230 omap2_enter_full_retention();
231
232out:
233 local_fiq_enable();
Kevin Hilman8bd22942009-05-28 10:56:16 -0700234}
235
Kevin Hilman8bd22942009-05-28 10:56:16 -0700236static void __init prcm_setup_regs(void)
237{
238 int i, num_mem_banks;
239 struct powerdomain *pwrdm;
240
Paul Walmsley4ef70c02011-02-25 15:39:30 -0700241 /*
242 * Enable autoidle
243 * XXX This should be handled by hwmod code or PRCM init code
244 */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700245 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
Kevin Hilman8bd22942009-05-28 10:56:16 -0700246 OMAP2_PRCM_SYSCONFIG_OFFSET);
247
Kevin Hilman8bd22942009-05-28 10:56:16 -0700248 /*
249 * Set CORE powerdomain memory banks to retain their contents
250 * during RETENTION
251 */
252 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
253 for (i = 0; i < num_mem_banks; i++)
254 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
255
256 /* Set CORE powerdomain's next power state to RETENTION */
257 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
258
259 /*
260 * Set MPU powerdomain's next power state to RETENTION;
261 * preserve logic state during retention
262 */
263 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
264 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
265
266 /* Force-power down DSP, GFX powerdomains */
267
268 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
269 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700270 clkdm_sleep(dsp_clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700271
272 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
273 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700274 clkdm_sleep(gfx_clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700275
Paul Walmsley51d070a2011-01-27 02:52:55 -0700276 /* Enable hardware-supervised idle for all clkdms */
Paul Walmsley92206fd2012-02-02 02:38:50 -0700277 clkdm_for_each(omap_pm_clkdms_setup, NULL);
Paul Walmsley369d5612010-01-26 20:13:01 -0700278 clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700279
Paul Walmsley14164082012-02-02 02:30:50 -0700280#ifdef CONFIG_SUSPEND
281 omap_pm_suspend = omap2_enter_full_retention;
282#endif
283
Kevin Hilman8bd22942009-05-28 10:56:16 -0700284 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
285 * stabilisation */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700286 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
287 OMAP2_PRCM_CLKSSETUP_OFFSET);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700288
289 /* Configure automatic voltage transition */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700290 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
291 OMAP2_PRCM_VOLTSETUP_OFFSET);
292 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
293 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
294 OMAP24XX_MEMRETCTRL_MASK |
295 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
296 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
297 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700298
299 /* Enable wake-up events */
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700300 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
301 WKUP_MOD, PM_WKEN);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700302}
303
Kevin Hilman7cc515f2009-06-10 09:02:25 -0700304static int __init omap2_pm_init(void)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700305{
306 u32 l;
307
308 if (!cpu_is_omap24xx())
309 return -ENODEV;
310
311 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700312 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
Kevin Hilman8bd22942009-05-28 10:56:16 -0700313 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
314
Paul Walmsley369d5612010-01-26 20:13:01 -0700315 /* Look up important powerdomains */
Kevin Hilman8bd22942009-05-28 10:56:16 -0700316
317 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
318 if (!mpu_pwrdm)
319 pr_err("PM: mpu_pwrdm not found\n");
320
321 core_pwrdm = pwrdm_lookup("core_pwrdm");
322 if (!core_pwrdm)
323 pr_err("PM: core_pwrdm not found\n");
324
Paul Walmsley369d5612010-01-26 20:13:01 -0700325 /* Look up important clockdomains */
326
327 mpu_clkdm = clkdm_lookup("mpu_clkdm");
328 if (!mpu_clkdm)
329 pr_err("PM: mpu_clkdm not found\n");
330
331 wkup_clkdm = clkdm_lookup("wkup_clkdm");
332 if (!wkup_clkdm)
333 pr_err("PM: wkup_clkdm not found\n");
334
Kevin Hilman8bd22942009-05-28 10:56:16 -0700335 dsp_clkdm = clkdm_lookup("dsp_clkdm");
336 if (!dsp_clkdm)
Paul Walmsley369d5612010-01-26 20:13:01 -0700337 pr_err("PM: dsp_clkdm not found\n");
Kevin Hilman8bd22942009-05-28 10:56:16 -0700338
339 gfx_clkdm = clkdm_lookup("gfx_clkdm");
340 if (!gfx_clkdm)
341 pr_err("PM: gfx_clkdm not found\n");
342
343
344 osc_ck = clk_get(NULL, "osc_ck");
345 if (IS_ERR(osc_ck)) {
346 printk(KERN_ERR "could not get osc_ck\n");
347 return -ENODEV;
348 }
349
350 if (cpu_is_omap242x()) {
351 emul_ck = clk_get(NULL, "emul_ck");
352 if (IS_ERR(emul_ck)) {
353 printk(KERN_ERR "could not get emul_ck\n");
354 clk_put(osc_ck);
355 return -ENODEV;
356 }
357 }
358
359 prcm_setup_regs();
360
361 /* Hack to prevent MPU retention when STI console is enabled. */
362 {
363 const struct omap_sti_console_config *sti;
364
365 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
366 struct omap_sti_console_config);
367 if (sti != NULL && sti->enable)
368 sti_console_enabled = 1;
369 }
370
371 /*
372 * We copy the assembler sleep/wakeup routines to SRAM.
373 * These routines need to be in SRAM as that's the only
374 * memory the MPU can see when it wakes up.
375 */
376 if (cpu_is_omap24xx()) {
377 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
378 omap24xx_idle_loop_suspend_sz);
379
380 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
381 omap24xx_cpu_suspend_sz);
382 }
383
Nicolas Pitre0bcd24b2012-01-04 16:27:48 -0500384 arm_pm_idle = omap2_pm_idle;
Kevin Hilman8bd22942009-05-28 10:56:16 -0700385
386 return 0;
387}
388
389late_initcall(omap2_pm_init);