blob: 5aa5435e3ff186fbc5254c8463d8f97a90ba9445 [file] [log] [blame]
Paul Walmsley69d88a02008-03-18 10:02:50 +02001#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
3
4/*
5 * OMAP2/3 PRCM base and module definitions
6 *
Tero Kristo0a84a912011-12-16 14:36:58 -07007 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
Rajendra Nayak77772d52009-12-08 18:24:49 -07008 * Copyright (C) 2007-2009 Nokia Corporation
Paul Walmsley69d88a02008-03-18 10:02:50 +02009 *
10 * Written by Paul Walmsley
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
Paul Walmsley69d88a02008-03-18 10:02:50 +020017/* Module offsets from both CM_BASE & PRM_BASE */
18
19/*
20 * Offsets that are the same on 24xx and 34xx
21 *
22 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
23 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
24 */
25#define OCP_MOD 0x000
26#define MPU_MOD 0x100
27#define CORE_MOD 0x200
28#define GFX_MOD 0x300
29#define WKUP_MOD 0x400
30#define PLL_MOD 0x500
31
32
33/* Chip-specific module offsets */
Tony Lindgrenc2d43e32008-07-03 12:24:38 +030034#define OMAP24XX_GR_MOD OCP_MOD
Paul Walmsley69d88a02008-03-18 10:02:50 +020035#define OMAP24XX_DSP_MOD 0x800
36
37#define OMAP2430_MDM_MOD 0xc00
38
39/* IVA2 module is < base on 3430 */
40#define OMAP3430_IVA2_MOD -0x800
41#define OMAP3430ES2_SGX_MOD GFX_MOD
42#define OMAP3430_CCR_MOD PLL_MOD
43#define OMAP3430_DSS_MOD 0x600
44#define OMAP3430_CAM_MOD 0x700
45#define OMAP3430_PER_MOD 0x800
46#define OMAP3430_EMU_MOD 0x900
47#define OMAP3430_GR_MOD 0xa00
48#define OMAP3430_NEON_MOD 0xb00
49#define OMAP3430ES2_USBHOST_MOD 0xc00
50
Paul Walmsley69d88a02008-03-18 10:02:50 +020051/* 24XX register bits shared between CM & PRM registers */
52
53/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
54#define OMAP2420_EN_MMC_SHIFT 26
Paul Walmsley2fd0f752010-05-18 18:40:23 -060055#define OMAP2420_EN_MMC_MASK (1 << 26)
Paul Walmsley69d88a02008-03-18 10:02:50 +020056#define OMAP24XX_EN_UART2_SHIFT 22
Paul Walmsley2fd0f752010-05-18 18:40:23 -060057#define OMAP24XX_EN_UART2_MASK (1 << 22)
Paul Walmsley69d88a02008-03-18 10:02:50 +020058#define OMAP24XX_EN_UART1_SHIFT 21
Paul Walmsley2fd0f752010-05-18 18:40:23 -060059#define OMAP24XX_EN_UART1_MASK (1 << 21)
Paul Walmsley69d88a02008-03-18 10:02:50 +020060#define OMAP24XX_EN_MCSPI2_SHIFT 18
Paul Walmsley2fd0f752010-05-18 18:40:23 -060061#define OMAP24XX_EN_MCSPI2_MASK (1 << 18)
Paul Walmsley69d88a02008-03-18 10:02:50 +020062#define OMAP24XX_EN_MCSPI1_SHIFT 17
Paul Walmsley2fd0f752010-05-18 18:40:23 -060063#define OMAP24XX_EN_MCSPI1_MASK (1 << 17)
Paul Walmsley69d88a02008-03-18 10:02:50 +020064#define OMAP24XX_EN_MCBSP2_SHIFT 16
Paul Walmsley2fd0f752010-05-18 18:40:23 -060065#define OMAP24XX_EN_MCBSP2_MASK (1 << 16)
Paul Walmsley69d88a02008-03-18 10:02:50 +020066#define OMAP24XX_EN_MCBSP1_SHIFT 15
Paul Walmsley2fd0f752010-05-18 18:40:23 -060067#define OMAP24XX_EN_MCBSP1_MASK (1 << 15)
Paul Walmsley69d88a02008-03-18 10:02:50 +020068#define OMAP24XX_EN_GPT12_SHIFT 14
Paul Walmsley2fd0f752010-05-18 18:40:23 -060069#define OMAP24XX_EN_GPT12_MASK (1 << 14)
Paul Walmsley69d88a02008-03-18 10:02:50 +020070#define OMAP24XX_EN_GPT11_SHIFT 13
Paul Walmsley2fd0f752010-05-18 18:40:23 -060071#define OMAP24XX_EN_GPT11_MASK (1 << 13)
Paul Walmsley69d88a02008-03-18 10:02:50 +020072#define OMAP24XX_EN_GPT10_SHIFT 12
Paul Walmsley2fd0f752010-05-18 18:40:23 -060073#define OMAP24XX_EN_GPT10_MASK (1 << 12)
Paul Walmsley69d88a02008-03-18 10:02:50 +020074#define OMAP24XX_EN_GPT9_SHIFT 11
Paul Walmsley2fd0f752010-05-18 18:40:23 -060075#define OMAP24XX_EN_GPT9_MASK (1 << 11)
Paul Walmsley69d88a02008-03-18 10:02:50 +020076#define OMAP24XX_EN_GPT8_SHIFT 10
Paul Walmsley2fd0f752010-05-18 18:40:23 -060077#define OMAP24XX_EN_GPT8_MASK (1 << 10)
Paul Walmsley69d88a02008-03-18 10:02:50 +020078#define OMAP24XX_EN_GPT7_SHIFT 9
Paul Walmsley2fd0f752010-05-18 18:40:23 -060079#define OMAP24XX_EN_GPT7_MASK (1 << 9)
Paul Walmsley69d88a02008-03-18 10:02:50 +020080#define OMAP24XX_EN_GPT6_SHIFT 8
Paul Walmsley2fd0f752010-05-18 18:40:23 -060081#define OMAP24XX_EN_GPT6_MASK (1 << 8)
Paul Walmsley69d88a02008-03-18 10:02:50 +020082#define OMAP24XX_EN_GPT5_SHIFT 7
Paul Walmsley2fd0f752010-05-18 18:40:23 -060083#define OMAP24XX_EN_GPT5_MASK (1 << 7)
Paul Walmsley69d88a02008-03-18 10:02:50 +020084#define OMAP24XX_EN_GPT4_SHIFT 6
Paul Walmsley2fd0f752010-05-18 18:40:23 -060085#define OMAP24XX_EN_GPT4_MASK (1 << 6)
Paul Walmsley69d88a02008-03-18 10:02:50 +020086#define OMAP24XX_EN_GPT3_SHIFT 5
Paul Walmsley2fd0f752010-05-18 18:40:23 -060087#define OMAP24XX_EN_GPT3_MASK (1 << 5)
Paul Walmsley69d88a02008-03-18 10:02:50 +020088#define OMAP24XX_EN_GPT2_SHIFT 4
Paul Walmsley2fd0f752010-05-18 18:40:23 -060089#define OMAP24XX_EN_GPT2_MASK (1 << 4)
Paul Walmsley69d88a02008-03-18 10:02:50 +020090#define OMAP2420_EN_VLYNQ_SHIFT 3
Paul Walmsley2fd0f752010-05-18 18:40:23 -060091#define OMAP2420_EN_VLYNQ_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +020092
93/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
94#define OMAP2430_EN_GPIO5_SHIFT 10
Paul Walmsley2fd0f752010-05-18 18:40:23 -060095#define OMAP2430_EN_GPIO5_MASK (1 << 10)
Paul Walmsley69d88a02008-03-18 10:02:50 +020096#define OMAP2430_EN_MCSPI3_SHIFT 9
Paul Walmsley2fd0f752010-05-18 18:40:23 -060097#define OMAP2430_EN_MCSPI3_MASK (1 << 9)
Paul Walmsley69d88a02008-03-18 10:02:50 +020098#define OMAP2430_EN_MMCHS2_SHIFT 8
Paul Walmsley2fd0f752010-05-18 18:40:23 -060099#define OMAP2430_EN_MMCHS2_MASK (1 << 8)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200100#define OMAP2430_EN_MMCHS1_SHIFT 7
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600101#define OMAP2430_EN_MMCHS1_MASK (1 << 7)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200102#define OMAP24XX_EN_UART3_SHIFT 2
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600103#define OMAP24XX_EN_UART3_MASK (1 << 2)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200104#define OMAP24XX_EN_USB_SHIFT 0
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600105#define OMAP24XX_EN_USB_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200106
107/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
108#define OMAP2430_EN_MDM_INTC_SHIFT 11
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600109#define OMAP2430_EN_MDM_INTC_MASK (1 << 11)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200110#define OMAP2430_EN_USBHS_SHIFT 6
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600111#define OMAP2430_EN_USBHS_MASK (1 << 6)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200112
113/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700114#define OMAP2420_ST_MMC_SHIFT 26
115#define OMAP2420_ST_MMC_MASK (1 << 26)
116#define OMAP24XX_ST_UART2_SHIFT 22
117#define OMAP24XX_ST_UART2_MASK (1 << 22)
118#define OMAP24XX_ST_UART1_SHIFT 21
119#define OMAP24XX_ST_UART1_MASK (1 << 21)
120#define OMAP24XX_ST_MCSPI2_SHIFT 18
121#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
122#define OMAP24XX_ST_MCSPI1_SHIFT 17
123#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
Charulatha V3cb72fa2011-02-24 12:51:46 -0800124#define OMAP24XX_ST_MCBSP2_SHIFT 16
125#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
126#define OMAP24XX_ST_MCBSP1_SHIFT 15
127#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700128#define OMAP24XX_ST_GPT12_SHIFT 14
129#define OMAP24XX_ST_GPT12_MASK (1 << 14)
130#define OMAP24XX_ST_GPT11_SHIFT 13
131#define OMAP24XX_ST_GPT11_MASK (1 << 13)
132#define OMAP24XX_ST_GPT10_SHIFT 12
133#define OMAP24XX_ST_GPT10_MASK (1 << 12)
134#define OMAP24XX_ST_GPT9_SHIFT 11
135#define OMAP24XX_ST_GPT9_MASK (1 << 11)
136#define OMAP24XX_ST_GPT8_SHIFT 10
137#define OMAP24XX_ST_GPT8_MASK (1 << 10)
138#define OMAP24XX_ST_GPT7_SHIFT 9
139#define OMAP24XX_ST_GPT7_MASK (1 << 9)
140#define OMAP24XX_ST_GPT6_SHIFT 8
141#define OMAP24XX_ST_GPT6_MASK (1 << 8)
142#define OMAP24XX_ST_GPT5_SHIFT 7
143#define OMAP24XX_ST_GPT5_MASK (1 << 7)
144#define OMAP24XX_ST_GPT4_SHIFT 6
145#define OMAP24XX_ST_GPT4_MASK (1 << 6)
146#define OMAP24XX_ST_GPT3_SHIFT 5
147#define OMAP24XX_ST_GPT3_MASK (1 << 5)
148#define OMAP24XX_ST_GPT2_SHIFT 4
149#define OMAP24XX_ST_GPT2_MASK (1 << 4)
150#define OMAP2420_ST_VLYNQ_SHIFT 3
151#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200152
153/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700154#define OMAP2430_ST_MDM_INTC_SHIFT 11
155#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
156#define OMAP2430_ST_GPIO5_SHIFT 10
157#define OMAP2430_ST_GPIO5_MASK (1 << 10)
158#define OMAP2430_ST_MCSPI3_SHIFT 9
159#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
160#define OMAP2430_ST_MMCHS2_SHIFT 8
161#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
162#define OMAP2430_ST_MMCHS1_SHIFT 7
163#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
164#define OMAP2430_ST_USBHS_SHIFT 6
165#define OMAP2430_ST_USBHS_MASK (1 << 6)
166#define OMAP24XX_ST_UART3_SHIFT 2
167#define OMAP24XX_ST_UART3_MASK (1 << 2)
168#define OMAP24XX_ST_USB_SHIFT 0
169#define OMAP24XX_ST_USB_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200170
171/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
172#define OMAP24XX_EN_GPIOS_SHIFT 2
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600173#define OMAP24XX_EN_GPIOS_MASK (1 << 2)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200174#define OMAP24XX_EN_GPT1_SHIFT 0
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600175#define OMAP24XX_EN_GPT1_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200176
177/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
Paul Walmsleyc2015dc2010-12-06 20:52:40 +0000178#define OMAP24XX_ST_GPIOS_SHIFT 2
179#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
180#define OMAP24XX_ST_GPT1_SHIFT 0
181#define OMAP24XX_ST_GPT1_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200182
183/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
Paul Walmsleyc2015dc2010-12-06 20:52:40 +0000184#define OMAP2430_ST_MDM_SHIFT 0
185#define OMAP2430_ST_MDM_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200186
187
188/* 3430 register bits shared between CM & PRM registers */
189
190/* CM_REVISION, PRM_REVISION shared bits */
191#define OMAP3430_REV_SHIFT 0
192#define OMAP3430_REV_MASK (0xff << 0)
193
194/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600195#define OMAP3430_AUTOIDLE_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200196
197/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
Paul Walmsleyb1636052011-03-01 13:12:56 -0800198#define OMAP3430_EN_MMC3_MASK (1 << 30)
199#define OMAP3430_EN_MMC3_SHIFT 30
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600200#define OMAP3430_EN_MMC2_MASK (1 << 25)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200201#define OMAP3430_EN_MMC2_SHIFT 25
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600202#define OMAP3430_EN_MMC1_MASK (1 << 24)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200203#define OMAP3430_EN_MMC1_SHIFT 24
Kyle Manna4bf90f62011-10-18 13:47:41 -0500204#define OMAP3430_EN_UART4_MASK (1 << 23)
205#define OMAP3430_EN_UART4_SHIFT 23
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600206#define OMAP3430_EN_MCSPI4_MASK (1 << 21)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200207#define OMAP3430_EN_MCSPI4_SHIFT 21
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600208#define OMAP3430_EN_MCSPI3_MASK (1 << 20)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200209#define OMAP3430_EN_MCSPI3_SHIFT 20
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600210#define OMAP3430_EN_MCSPI2_MASK (1 << 19)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200211#define OMAP3430_EN_MCSPI2_SHIFT 19
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600212#define OMAP3430_EN_MCSPI1_MASK (1 << 18)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200213#define OMAP3430_EN_MCSPI1_SHIFT 18
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600214#define OMAP3430_EN_I2C3_MASK (1 << 17)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200215#define OMAP3430_EN_I2C3_SHIFT 17
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600216#define OMAP3430_EN_I2C2_MASK (1 << 16)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200217#define OMAP3430_EN_I2C2_SHIFT 16
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600218#define OMAP3430_EN_I2C1_MASK (1 << 15)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200219#define OMAP3430_EN_I2C1_SHIFT 15
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600220#define OMAP3430_EN_UART2_MASK (1 << 14)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200221#define OMAP3430_EN_UART2_SHIFT 14
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600222#define OMAP3430_EN_UART1_MASK (1 << 13)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200223#define OMAP3430_EN_UART1_SHIFT 13
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600224#define OMAP3430_EN_GPT11_MASK (1 << 12)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200225#define OMAP3430_EN_GPT11_SHIFT 12
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600226#define OMAP3430_EN_GPT10_MASK (1 << 11)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200227#define OMAP3430_EN_GPT10_SHIFT 11
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600228#define OMAP3430_EN_MCBSP5_MASK (1 << 10)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200229#define OMAP3430_EN_MCBSP5_SHIFT 10
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600230#define OMAP3430_EN_MCBSP1_MASK (1 << 9)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200231#define OMAP3430_EN_MCBSP1_SHIFT 9
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600232#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200233#define OMAP3430_EN_FSHOSTUSB_SHIFT 5
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600234#define OMAP3430_EN_D2D_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200235#define OMAP3430_EN_D2D_SHIFT 3
236
237/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600238#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4)
239#define OMAP3430_EN_HSOTGUSB_SHIFT 4
Paul Walmsley69d88a02008-03-18 10:02:50 +0200240
241/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
Paul Walmsleyb1636052011-03-01 13:12:56 -0800242#define OMAP3430_ST_MMC3_SHIFT 30
243#define OMAP3430_ST_MMC3_MASK (1 << 30)
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700244#define OMAP3430_ST_MMC2_SHIFT 25
245#define OMAP3430_ST_MMC2_MASK (1 << 25)
246#define OMAP3430_ST_MMC1_SHIFT 24
247#define OMAP3430_ST_MMC1_MASK (1 << 24)
248#define OMAP3430_ST_MCSPI4_SHIFT 21
249#define OMAP3430_ST_MCSPI4_MASK (1 << 21)
250#define OMAP3430_ST_MCSPI3_SHIFT 20
251#define OMAP3430_ST_MCSPI3_MASK (1 << 20)
252#define OMAP3430_ST_MCSPI2_SHIFT 19
253#define OMAP3430_ST_MCSPI2_MASK (1 << 19)
254#define OMAP3430_ST_MCSPI1_SHIFT 18
255#define OMAP3430_ST_MCSPI1_MASK (1 << 18)
256#define OMAP3430_ST_I2C3_SHIFT 17
257#define OMAP3430_ST_I2C3_MASK (1 << 17)
258#define OMAP3430_ST_I2C2_SHIFT 16
259#define OMAP3430_ST_I2C2_MASK (1 << 16)
260#define OMAP3430_ST_I2C1_SHIFT 15
261#define OMAP3430_ST_I2C1_MASK (1 << 15)
262#define OMAP3430_ST_UART2_SHIFT 14
263#define OMAP3430_ST_UART2_MASK (1 << 14)
264#define OMAP3430_ST_UART1_SHIFT 13
265#define OMAP3430_ST_UART1_MASK (1 << 13)
266#define OMAP3430_ST_GPT11_SHIFT 12
267#define OMAP3430_ST_GPT11_MASK (1 << 12)
268#define OMAP3430_ST_GPT10_SHIFT 11
269#define OMAP3430_ST_GPT10_MASK (1 << 11)
270#define OMAP3430_ST_MCBSP5_SHIFT 10
271#define OMAP3430_ST_MCBSP5_MASK (1 << 10)
272#define OMAP3430_ST_MCBSP1_SHIFT 9
273#define OMAP3430_ST_MCBSP1_MASK (1 << 9)
274#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
275#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
276#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
277#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
278#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
279#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
280#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
281#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
282#define OMAP3430_ST_D2D_SHIFT 3
283#define OMAP3430_ST_D2D_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200284
285/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600286#define OMAP3430_EN_GPIO1_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200287#define OMAP3430_EN_GPIO1_SHIFT 3
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600288#define OMAP3430_EN_GPT12_MASK (1 << 1)
Kevin Hilman8bd22942009-05-28 10:56:16 -0700289#define OMAP3430_EN_GPT12_SHIFT 1
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600290#define OMAP3430_EN_GPT1_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200291#define OMAP3430_EN_GPT1_SHIFT 0
292
293/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600294#define OMAP3430_EN_SR2_MASK (1 << 7)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200295#define OMAP3430_EN_SR2_SHIFT 7
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600296#define OMAP3430_EN_SR1_MASK (1 << 6)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200297#define OMAP3430_EN_SR1_SHIFT 6
298
299/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600300#define OMAP3430_EN_GPT12_MASK (1 << 1)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200301#define OMAP3430_EN_GPT12_SHIFT 1
302
303/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700304#define OMAP3430_ST_SR2_SHIFT 7
305#define OMAP3430_ST_SR2_MASK (1 << 7)
306#define OMAP3430_ST_SR1_SHIFT 6
307#define OMAP3430_ST_SR1_MASK (1 << 6)
308#define OMAP3430_ST_GPIO1_SHIFT 3
309#define OMAP3430_ST_GPIO1_MASK (1 << 3)
310#define OMAP3430_ST_GPT12_SHIFT 1
311#define OMAP3430_ST_GPT12_MASK (1 << 1)
312#define OMAP3430_ST_GPT1_SHIFT 0
313#define OMAP3430_ST_GPT1_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200314
315/*
316 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
317 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
318 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
319 */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600320#define OMAP3430_EN_MPU_MASK (1 << 1)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200321#define OMAP3430_EN_MPU_SHIFT 1
322
323/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
Kevin Hilman046465b2010-09-27 20:19:30 +0530324
325#define OMAP3630_EN_UART4_MASK (1 << 18)
326#define OMAP3630_EN_UART4_SHIFT 18
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600327#define OMAP3430_EN_GPIO6_MASK (1 << 17)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200328#define OMAP3430_EN_GPIO6_SHIFT 17
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600329#define OMAP3430_EN_GPIO5_MASK (1 << 16)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200330#define OMAP3430_EN_GPIO5_SHIFT 16
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600331#define OMAP3430_EN_GPIO4_MASK (1 << 15)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200332#define OMAP3430_EN_GPIO4_SHIFT 15
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600333#define OMAP3430_EN_GPIO3_MASK (1 << 14)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200334#define OMAP3430_EN_GPIO3_SHIFT 14
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600335#define OMAP3430_EN_GPIO2_MASK (1 << 13)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200336#define OMAP3430_EN_GPIO2_SHIFT 13
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600337#define OMAP3430_EN_UART3_MASK (1 << 11)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200338#define OMAP3430_EN_UART3_SHIFT 11
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600339#define OMAP3430_EN_GPT9_MASK (1 << 10)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200340#define OMAP3430_EN_GPT9_SHIFT 10
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600341#define OMAP3430_EN_GPT8_MASK (1 << 9)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200342#define OMAP3430_EN_GPT8_SHIFT 9
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600343#define OMAP3430_EN_GPT7_MASK (1 << 8)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200344#define OMAP3430_EN_GPT7_SHIFT 8
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600345#define OMAP3430_EN_GPT6_MASK (1 << 7)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200346#define OMAP3430_EN_GPT6_SHIFT 7
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600347#define OMAP3430_EN_GPT5_MASK (1 << 6)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200348#define OMAP3430_EN_GPT5_SHIFT 6
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600349#define OMAP3430_EN_GPT4_MASK (1 << 5)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200350#define OMAP3430_EN_GPT4_SHIFT 5
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600351#define OMAP3430_EN_GPT3_MASK (1 << 4)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200352#define OMAP3430_EN_GPT3_SHIFT 4
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600353#define OMAP3430_EN_GPT2_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200354#define OMAP3430_EN_GPT2_SHIFT 3
355
356/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
357/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
358 * be ST_* bits instead? */
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600359#define OMAP3430_EN_MCBSP4_MASK (1 << 2)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200360#define OMAP3430_EN_MCBSP4_SHIFT 2
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600361#define OMAP3430_EN_MCBSP3_MASK (1 << 1)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200362#define OMAP3430_EN_MCBSP3_SHIFT 1
Paul Walmsley2fd0f752010-05-18 18:40:23 -0600363#define OMAP3430_EN_MCBSP2_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200364#define OMAP3430_EN_MCBSP2_SHIFT 0
365
366/* CM_IDLEST_PER, PM_WKST_PER shared bits */
Govindraj.Re5863682010-09-27 20:20:25 +0530367#define OMAP3630_ST_UART4_SHIFT 18
368#define OMAP3630_ST_UART4_MASK (1 << 18)
Paul Walmsleyda0747d2009-01-28 12:18:22 -0700369#define OMAP3430_ST_GPIO6_SHIFT 17
370#define OMAP3430_ST_GPIO6_MASK (1 << 17)
371#define OMAP3430_ST_GPIO5_SHIFT 16
372#define OMAP3430_ST_GPIO5_MASK (1 << 16)
373#define OMAP3430_ST_GPIO4_SHIFT 15
374#define OMAP3430_ST_GPIO4_MASK (1 << 15)
375#define OMAP3430_ST_GPIO3_SHIFT 14
376#define OMAP3430_ST_GPIO3_MASK (1 << 14)
377#define OMAP3430_ST_GPIO2_SHIFT 13
378#define OMAP3430_ST_GPIO2_MASK (1 << 13)
379#define OMAP3430_ST_UART3_SHIFT 11
380#define OMAP3430_ST_UART3_MASK (1 << 11)
381#define OMAP3430_ST_GPT9_SHIFT 10
382#define OMAP3430_ST_GPT9_MASK (1 << 10)
383#define OMAP3430_ST_GPT8_SHIFT 9
384#define OMAP3430_ST_GPT8_MASK (1 << 9)
385#define OMAP3430_ST_GPT7_SHIFT 8
386#define OMAP3430_ST_GPT7_MASK (1 << 8)
387#define OMAP3430_ST_GPT6_SHIFT 7
388#define OMAP3430_ST_GPT6_MASK (1 << 7)
389#define OMAP3430_ST_GPT5_SHIFT 6
390#define OMAP3430_ST_GPT5_MASK (1 << 6)
391#define OMAP3430_ST_GPT4_SHIFT 5
392#define OMAP3430_ST_GPT4_MASK (1 << 5)
393#define OMAP3430_ST_GPT3_SHIFT 4
394#define OMAP3430_ST_GPT3_MASK (1 << 4)
395#define OMAP3430_ST_GPT2_SHIFT 3
396#define OMAP3430_ST_GPT2_MASK (1 << 3)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200397
398/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
Paul Walmsleyecb24aa2008-08-19 11:08:43 +0300399#define OMAP3430_EN_CORE_SHIFT 0
400#define OMAP3430_EN_CORE_MASK (1 << 0)
Paul Walmsley69d88a02008-03-18 10:02:50 +0200401
Paul Walmsleyd198b512010-12-21 15:30:54 -0700402
403/*
404 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
405 * submodule to exit hardreset
406 */
407#define MAX_MODULE_HARDRESET_WAIT 10000
408
Paul Walmsley59fb6592010-12-21 15:30:55 -0700409# ifndef __ASSEMBLER__
410extern void __iomem *prm_base;
411extern void __iomem *cm_base;
412extern void __iomem *cm2_base;
Tero Kristo0a84a912011-12-16 14:36:58 -0700413
414/**
415 * struct omap_prcm_irq - describes a PRCM interrupt bit
416 * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
417 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
418 * @priority: should this interrupt be handled before @priority=false IRQs?
419 *
420 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
421 * On systems with multiple PRM MPU IRQ registers, the bitfields read from
422 * the registers are concatenated, so @offset could be > 31 on these systems -
423 * see omap_prm_irq_handler() for more details. I/O ring interrupts should
424 * have @priority set to true.
425 */
426struct omap_prcm_irq {
427 const char *name;
428 unsigned int offset;
429 bool priority;
430};
431
432/**
433 * struct omap_prcm_irq_setup - PRCM interrupt controller details
434 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
435 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
436 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
437 * @nr_irqs: number of entries in the @irqs array
438 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
439 * @irq: MPU IRQ asserted when a PRCM interrupt arrives
440 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
441 * @ocp_barrier: fn ptr to force buffered PRM writes to complete
Tero Kristo91285b62011-12-16 14:36:58 -0700442 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
443 * @restore_irqen: fn ptr to save and clear IRQENABLE regs
444 * @saved_mask: IRQENABLE regs are saved here during suspend
Tero Kristo0a84a912011-12-16 14:36:58 -0700445 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
446 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
Tero Kristo91285b62011-12-16 14:36:58 -0700447 * @suspended: set to true after Linux suspend code has called our ->prepare()
448 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
Tero Kristo0a84a912011-12-16 14:36:58 -0700449 *
Tero Kristo91285b62011-12-16 14:36:58 -0700450 * @saved_mask, @priority_mask, @base_irq, @suspended, and
451 * @suspend_save_flag are populated dynamically, and are not to be
Tero Kristo0a84a912011-12-16 14:36:58 -0700452 * specified in static initializers.
453 */
454struct omap_prcm_irq_setup {
455 u16 ack;
456 u16 mask;
457 u8 nr_regs;
458 u8 nr_irqs;
459 const struct omap_prcm_irq *irqs;
460 int irq;
461 void (*read_pending_irqs)(unsigned long *events);
462 void (*ocp_barrier)(void);
Tero Kristo91285b62011-12-16 14:36:58 -0700463 void (*save_and_clear_irqen)(u32 *saved_mask);
464 void (*restore_irqen)(u32 *saved_mask);
465 u32 *saved_mask;
Tero Kristo0a84a912011-12-16 14:36:58 -0700466 u32 *priority_mask;
467 int base_irq;
Tero Kristo91285b62011-12-16 14:36:58 -0700468 bool suspended;
469 bool suspend_save_flag;
Tero Kristo0a84a912011-12-16 14:36:58 -0700470};
471
472/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
473#define OMAP_PRCM_IRQ(_name, _offset, _priority) { \
474 .name = _name, \
475 .offset = _offset, \
476 .priority = _priority \
477 }
478
479extern void omap_prcm_irq_cleanup(void);
480extern int omap_prcm_register_chain_handler(
481 struct omap_prcm_irq_setup *irq_setup);
482extern int omap_prcm_event_to_irq(const char *event);
Tero Kristo91285b62011-12-16 14:36:58 -0700483extern void omap_prcm_irq_prepare(void);
484extern void omap_prcm_irq_complete(void);
Tero Kristo0a84a912011-12-16 14:36:58 -0700485
Paul Walmsley59fb6592010-12-21 15:30:55 -0700486# endif
487
Paul Walmsley69d88a02008-03-18 10:02:50 +0200488#endif
489