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gerrit-public.fairphone.software / kernel / msm / edf1b8fd93eb283fa9101c33765164133391ded9 / . / arch / powerpc / boot / dts / p5020ds.dts
blob: 419e20832fa6c068dbed554b56b1def29493c575 [file] [log] [blame]
Kumar Galaedf1b8f2011-05-09 15:24:57 -0500[diff] [blame^]1/*
2 * P5020DS Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 model = "fsl,P5020DS";
39 compatible = "fsl,P5020DS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: PowerPC,e5500@0 {
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 next-level-cache = <&cpc>;
86 };
87 };
88 cpu1: PowerPC,e5500@1 {
89 device_type = "cpu";
90 reg = <1>;
91 next-level-cache = <&L2_1>;
92 L2_1: l2-cache {
93 next-level-cache = <&cpc>;
94 };
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 };
101
102 soc: soc@ffe000000 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 device_type = "soc";
106 compatible = "simple-bus";
107 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
108 reg = <0xf 0xfe000000 0 0x00001000>;
109
110 soc-sram-error {
111 compatible = "fsl,soc-sram-error";
112 interrupts = <16 2 1 29>;
113 };
114
115 corenet-law@0 {
116 compatible = "fsl,corenet-law";
117 reg = <0x0 0x1000>;
118 fsl,num-laws = <32>;
119 };
120
121 memory-controller@8000 {
122 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
123 reg = <0x8000 0x1000>;
124 interrupts = <16 2 1 23>;
125 };
126
127 memory-controller@9000 {
128 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
129 reg = <0x9000 0x1000>;
130 interrupts = <16 2 1 22>;
131 };
132
133 cpc: l3-cache-controller@10000 {
134 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
135 reg = <0x10000 0x1000
136 0x11000 0x1000>;
137 interrupts = <16 2 1 27
138 16 2 1 26>;
139 };
140
141 corenet-cf@18000 {
142 compatible = "fsl,corenet-cf";
143 reg = <0x18000 0x1000>;
144 interrupts = <16 2 1 31>;
145 fsl,ccf-num-csdids = <32>;
146 fsl,ccf-num-snoopids = <32>;
147 };
148
149 iommu@20000 {
150 compatible = "fsl,pamu-v1.0", "fsl,pamu";
151 reg = <0x20000 0x4000>;
152 interrupts = <
153 24 2 0 0
154 16 2 1 30>;
155 };
156
157 mpic: pic@40000 {
158 clock-frequency = <0>;
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <4>;
162 reg = <0x40000 0x40000>;
163 compatible = "fsl,mpic", "chrp,open-pic";
164 device_type = "open-pic";
165 };
166
167 msi0: msi@41600 {
168 compatible = "fsl,mpic-msi";
169 reg = <0x41600 0x200>;
170 msi-available-ranges = <0 0x100>;
171 interrupts = <
172 0xe0 0 0 0
173 0xe1 0 0 0
174 0xe2 0 0 0
175 0xe3 0 0 0
176 0xe4 0 0 0
177 0xe5 0 0 0
178 0xe6 0 0 0
179 0xe7 0 0 0>;
180 };
181
182 msi1: msi@41800 {
183 compatible = "fsl,mpic-msi";
184 reg = <0x41800 0x200>;
185 msi-available-ranges = <0 0x100>;
186 interrupts = <
187 0xe8 0 0 0
188 0xe9 0 0 0
189 0xea 0 0 0
190 0xeb 0 0 0
191 0xec 0 0 0
192 0xed 0 0 0
193 0xee 0 0 0
194 0xef 0 0 0>;
195 };
196
197 msi2: msi@41a00 {
198 compatible = "fsl,mpic-msi";
199 reg = <0x41a00 0x200>;
200 msi-available-ranges = <0 0x100>;
201 interrupts = <
202 0xf0 0 0 0
203 0xf1 0 0 0
204 0xf2 0 0 0
205 0xf3 0 0 0
206 0xf4 0 0 0
207 0xf5 0 0 0
208 0xf6 0 0 0
209 0xf7 0 0 0>;
210 };
211
212 guts: global-utilities@e0000 {
213 compatible = "fsl,qoriq-device-config-1.0";
214 reg = <0xe0000 0xe00>;
215 fsl,has-rstcr;
216 #sleep-cells = <1>;
217 fsl,liodn-bits = <12>;
218 };
219
220 pins: global-utilities@e0e00 {
221 compatible = "fsl,qoriq-pin-control-1.0";
222 reg = <0xe0e00 0x200>;
223 #sleep-cells = <2>;
224 };
225
226 clockgen: global-utilities@e1000 {
227 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
228 reg = <0xe1000 0x1000>;
229 clock-frequency = <0>;
230 };
231
232 rcpm: global-utilities@e2000 {
233 compatible = "fsl,qoriq-rcpm-1.0";
234 reg = <0xe2000 0x1000>;
235 #sleep-cells = <1>;
236 };
237
238 sfp: sfp@e8000 {
239 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
240 reg = <0xe8000 0x1000>;
241 };
242
243 serdes: serdes@ea000 {
244 compatible = "fsl,p5020-serdes";
245 reg = <0xea000 0x1000>;
246 };
247
248 dma0: dma@100300 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
252 reg = <0x100300 0x4>;
253 ranges = <0x0 0x100100 0x200>;
254 cell-index = <0>;
255 dma-channel@0 {
256 compatible = "fsl,p5020-dma-channel",
257 "fsl,eloplus-dma-channel";
258 reg = <0x0 0x80>;
259 cell-index = <0>;
260 interrupts = <28 2 0 0>;
261 };
262 dma-channel@80 {
263 compatible = "fsl,p5020-dma-channel",
264 "fsl,eloplus-dma-channel";
265 reg = <0x80 0x80>;
266 cell-index = <1>;
267 interrupts = <29 2 0 0>;
268 };
269 dma-channel@100 {
270 compatible = "fsl,p5020-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x100 0x80>;
273 cell-index = <2>;
274 interrupts = <30 2 0 0>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,p5020-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupts = <31 2 0 0>;
282 };
283 };
284
285 dma1: dma@101300 {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
289 reg = <0x101300 0x4>;
290 ranges = <0x0 0x101100 0x200>;
291 cell-index = <1>;
292 dma-channel@0 {
293 compatible = "fsl,p5020-dma-channel",
294 "fsl,eloplus-dma-channel";
295 reg = <0x0 0x80>;
296 cell-index = <0>;
297 interrupts = <32 2 0 0>;
298 };
299 dma-channel@80 {
300 compatible = "fsl,p5020-dma-channel",
301 "fsl,eloplus-dma-channel";
302 reg = <0x80 0x80>;
303 cell-index = <1>;
304 interrupts = <33 2 0 0>;
305 };
306 dma-channel@100 {
307 compatible = "fsl,p5020-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x100 0x80>;
310 cell-index = <2>;
311 interrupts = <34 2 0 0>;
312 };
313 dma-channel@180 {
314 compatible = "fsl,p5020-dma-channel",
315 "fsl,eloplus-dma-channel";
316 reg = <0x180 0x80>;
317 cell-index = <3>;
318 interrupts = <35 2 0 0>;
319 };
320 };
321
322 spi@110000 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
326 reg = <0x110000 0x1000>;
327 interrupts = <53 0x2 0 0>;
328 fsl,espi-num-chipselects = <4>;
329
330 flash@0 {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 compatible = "spansion,s25sl12801";
334 reg = <0>;
335 spi-max-frequency = <40000000>; /* input clock */
336 partition@u-boot {
337 label = "u-boot";
338 reg = <0x00000000 0x00100000>;
339 read-only;
340 };
341 partition@kernel {
342 label = "kernel";
343 reg = <0x00100000 0x00500000>;
344 read-only;
345 };
346 partition@dtb {
347 label = "dtb";
348 reg = <0x00600000 0x00100000>;
349 read-only;
350 };
351 partition@fs {
352 label = "file system";
353 reg = <0x00700000 0x00900000>;
354 };
355 };
356 };
357
358 sdhc: sdhc@114000 {
359 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
360 reg = <0x114000 0x1000>;
361 interrupts = <48 2 0 0>;
362 sdhci,auto-cmd12;
363 clock-frequency = <0>;
364 };
365
366 i2c@118000 {
367 #address-cells = <1>;
368 #size-cells = <0>;
369 cell-index = <0>;
370 compatible = "fsl-i2c";
371 reg = <0x118000 0x100>;
372 interrupts = <38 2 0 0>;
373 dfsrr;
374 };
375
376 i2c@118100 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 cell-index = <1>;
380 compatible = "fsl-i2c";
381 reg = <0x118100 0x100>;
382 interrupts = <38 2 0 0>;
383 dfsrr;
384 eeprom@51 {
385 compatible = "at24,24c256";
386 reg = <0x51>;
387 };
388 eeprom@52 {
389 compatible = "at24,24c256";
390 reg = <0x52>;
391 };
392 };
393
394 i2c@119000 {
395 #address-cells = <1>;
396 #size-cells = <0>;
397 cell-index = <2>;
398 compatible = "fsl-i2c";
399 reg = <0x119000 0x100>;
400 interrupts = <39 2 0 0>;
401 dfsrr;
402 };
403
404 i2c@119100 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 cell-index = <3>;
408 compatible = "fsl-i2c";
409 reg = <0x119100 0x100>;
410 interrupts = <39 2 0 0>;
411 dfsrr;
412 rtc@68 {
413 compatible = "dallas,ds3232";
414 reg = <0x68>;
415 interrupts = <0x1 0x1 0 0>;
416 };
417 };
418
419 serial0: serial@11c500 {
420 cell-index = <0>;
421 device_type = "serial";
422 compatible = "ns16550";
423 reg = <0x11c500 0x100>;
424 clock-frequency = <0>;
425 interrupts = <36 2 0 0>;
426 };
427
428 serial1: serial@11c600 {
429 cell-index = <1>;
430 device_type = "serial";
431 compatible = "ns16550";
432 reg = <0x11c600 0x100>;
433 clock-frequency = <0>;
434 interrupts = <36 2 0 0>;
435 };
436
437 serial2: serial@11d500 {
438 cell-index = <2>;
439 device_type = "serial";
440 compatible = "ns16550";
441 reg = <0x11d500 0x100>;
442 clock-frequency = <0>;
443 interrupts = <37 2 0 0>;
444 };
445
446 serial3: serial@11d600 {
447 cell-index = <3>;
448 device_type = "serial";
449 compatible = "ns16550";
450 reg = <0x11d600 0x100>;
451 clock-frequency = <0>;
452 interrupts = <37 2 0 0>;
453 };
454
455 gpio0: gpio@130000 {
456 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
457 reg = <0x130000 0x1000>;
458 interrupts = <55 2 0 0>;
459 #gpio-cells = <2>;
460 gpio-controller;
461 };
462
463 usb0: usb@210000 {
464 compatible = "fsl,p5020-usb2-mph",
465 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
466 reg = <0x210000 0x1000>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 interrupts = <44 0x2 0 0>;
470 phy_type = "utmi";
471 port0;
472 };
473
474 usb1: usb@211000 {
475 compatible = "fsl,p5020-usb2-dr",
476 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
477 reg = <0x211000 0x1000>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 interrupts = <45 0x2 0 0>;
481 dr_mode = "host";
482 phy_type = "utmi";
483 };
484
485 sata@220000 {
486 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
487 reg = <0x220000 0x1000>;
488 interrupts = <68 0x2 0 0>;
489 };
490
491 sata@221000 {
492 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
493 reg = <0x221000 0x1000>;
494 interrupts = <69 0x2 0 0>;
495 };
496
497 crypto: crypto@300000 {
498 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
499 #address-cells = <1>;
500 #size-cells = <1>;
501 reg = <0x300000 0x10000>;
502 ranges = <0 0x300000 0x10000>;
503 interrupts = <92 2 0 0>;
504
505 sec_jr0: jr@1000 {
506 compatible = "fsl,sec-v4.2-job-ring",
507 "fsl,sec-v4.0-job-ring";
508 reg = <0x1000 0x1000>;
509 interrupts = <88 2 0 0>;
510 };
511
512 sec_jr1: jr@2000 {
513 compatible = "fsl,sec-v4.2-job-ring",
514 "fsl,sec-v4.0-job-ring";
515 reg = <0x2000 0x1000>;
516 interrupts = <89 2 0 0>;
517 };
518
519 sec_jr2: jr@3000 {
520 compatible = "fsl,sec-v4.2-job-ring",
521 "fsl,sec-v4.0-job-ring";
522 reg = <0x3000 0x1000>;
523 interrupts = <90 2 0 0>;
524 };
525
526 sec_jr3: jr@4000 {
527 compatible = "fsl,sec-v4.2-job-ring",
528 "fsl,sec-v4.0-job-ring";
529 reg = <0x4000 0x1000>;
530 interrupts = <91 2 0 0>;
531 };
532
533 rtic@6000 {
534 compatible = "fsl,sec-v4.2-rtic",
535 "fsl,sec-v4.0-rtic";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 reg = <0x6000 0x100>;
539 ranges = <0x0 0x6100 0xe00>;
540
541 rtic_a: rtic-a@0 {
542 compatible = "fsl,sec-v4.2-rtic-memory",
543 "fsl,sec-v4.0-rtic-memory";
544 reg = <0x00 0x20 0x100 0x80>;
545 };
546
547 rtic_b: rtic-b@20 {
548 compatible = "fsl,sec-v4.2-rtic-memory",
549 "fsl,sec-v4.0-rtic-memory";
550 reg = <0x20 0x20 0x200 0x80>;
551 };
552
553 rtic_c: rtic-c@40 {
554 compatible = "fsl,sec-v4.2-rtic-memory",
555 "fsl,sec-v4.0-rtic-memory";
556 reg = <0x40 0x20 0x300 0x80>;
557 };
558
559 rtic_d: rtic-d@60 {
560 compatible = "fsl,sec-v4.2-rtic-memory",
561 "fsl,sec-v4.0-rtic-memory";
562 reg = <0x60 0x20 0x500 0x80>;
563 };
564 };
565 };
566
567 sec_mon: sec_mon@314000 {
568 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
569 reg = <0x314000 0x1000>;
570 interrupts = <93 2 0 0>;
571 };
572 };
573
574 localbus@ffe124000 {
575 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
576 reg = <0xf 0xfe124000 0 0x1000>;
577 interrupts = <25 2 0 0>;
578 #address-cells = <2>;
579 #size-cells = <1>;
580
581 ranges = <0 0 0xf 0xe8000000 0x08000000
582 3 0 0xf 0xffdf0000 0x00008000>;
583
584 flash@0,0 {
585 compatible = "cfi-flash";
586 reg = <0 0 0x08000000>;
587 bank-width = <2>;
588 device-width = <2>;
589 };
590
591 board-control@3,0 {
592 compatible = "fsl,p5020ds-pixis";
593 reg = <3 0 0x20>;
594 };
595 };
596
597 pci0: pcie@ffe200000 {
598 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
599 device_type = "pci";
600 #size-cells = <2>;
601 #address-cells = <3>;
602 reg = <0xf 0xfe200000 0 0x1000>;
603 bus-range = <0x0 0xff>;
604 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
605 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
606 clock-frequency = <0x1fca055>;
607 fsl,msi = <&msi0>;
608 interrupts = <16 2 1 15>;
609
610 pcie@0 {
611 reg = <0 0 0 0 0>;
612 #interrupt-cells = <1>;
613 #size-cells = <2>;
614 #address-cells = <3>;
615 device_type = "pci";
616 interrupts = <16 2 1 15>;
617 interrupt-map-mask = <0xf800 0 0 7>;
618 interrupt-map = <
619 /* IDSEL 0x0 */
620 0000 0 0 1 &mpic 40 1 0 0
621 0000 0 0 2 &mpic 1 1 0 0
622 0000 0 0 3 &mpic 2 1 0 0
623 0000 0 0 4 &mpic 3 1 0 0
624 >;
625 ranges = <0x02000000 0 0xe0000000
626 0x02000000 0 0xe0000000
627 0 0x20000000
628
629 0x01000000 0 0x00000000
630 0x01000000 0 0x00000000
631 0 0x00010000>;
632 };
633 };
634
635 pci1: pcie@ffe201000 {
636 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
637 device_type = "pci";
638 #size-cells = <2>;
639 #address-cells = <3>;
640 reg = <0xf 0xfe201000 0 0x1000>;
641 bus-range = <0 0xff>;
642 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
643 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
644 clock-frequency = <0x1fca055>;
645 fsl,msi = <&msi1>;
646 interrupts = <16 2 1 14>;
647 pcie@0 {
648 reg = <0 0 0 0 0>;
649 #interrupt-cells = <1>;
650 #size-cells = <2>;
651 #address-cells = <3>;
652 device_type = "pci";
653 interrupts = <16 2 1 14>;
654 interrupt-map-mask = <0xf800 0 0 7>;
655 interrupt-map = <
656 /* IDSEL 0x0 */
657 0000 0 0 1 &mpic 41 1 0 0
658 0000 0 0 2 &mpic 5 1 0 0
659 0000 0 0 3 &mpic 6 1 0 0
660 0000 0 0 4 &mpic 7 1 0 0
661 >;
662 ranges = <0x02000000 0 0xe0000000
663 0x02000000 0 0xe0000000
664 0 0x20000000
665
666 0x01000000 0 0x00000000
667 0x01000000 0 0x00000000
668 0 0x00010000>;
669 };
670 };
671
672 pci2: pcie@ffe202000 {
673 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
674 device_type = "pci";
675 #size-cells = <2>;
676 #address-cells = <3>;
677 reg = <0xf 0xfe202000 0 0x1000>;
678 bus-range = <0x0 0xff>;
679 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
680 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
681 clock-frequency = <0x1fca055>;
682 fsl,msi = <&msi2>;
683 interrupts = <16 2 1 13>;
684 pcie@0 {
685 reg = <0 0 0 0 0>;
686 #interrupt-cells = <1>;
687 #size-cells = <2>;
688 #address-cells = <3>;
689 device_type = "pci";
690 interrupts = <16 2 1 13>;
691 interrupt-map-mask = <0xf800 0 0 7>;
692 interrupt-map = <
693 /* IDSEL 0x0 */
694 0000 0 0 1 &mpic 42 1 0 0
695 0000 0 0 2 &mpic 9 1 0 0
696 0000 0 0 3 &mpic 10 1 0 0
697 0000 0 0 4 &mpic 11 1 0 0
698 >;
699 ranges = <0x02000000 0 0xe0000000
700 0x02000000 0 0xe0000000
701 0 0x20000000
702
703 0x01000000 0 0x00000000
704 0x01000000 0 0x00000000
705 0 0x00010000>;
706 };
707 };
708
709 pci3: pcie@ffe203000 {
710 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
711 device_type = "pci";
712 #size-cells = <2>;
713 #address-cells = <3>;
714 reg = <0xf 0xfe203000 0 0x1000>;
715 bus-range = <0x0 0xff>;
716 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
717 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
718 clock-frequency = <0x1fca055>;
719 fsl,msi = <&msi2>;
720 interrupts = <16 2 1 12>;
721 pcie@0 {
722 reg = <0 0 0 0 0>;
723 #interrupt-cells = <1>;
724 #size-cells = <2>;
725 #address-cells = <3>;
726 device_type = "pci";
727 interrupts = <16 2 1 12>;
728 interrupt-map-mask = <0xf800 0 0 7>;
729 interrupt-map = <
730 /* IDSEL 0x0 */
731 0000 0 0 1 &mpic 43 1 0 0
732 0000 0 0 2 &mpic 0 1 0 0
733 0000 0 0 3 &mpic 4 1 0 0
734 0000 0 0 4 &mpic 8 1 0 0
735 >;
736 ranges = <0x02000000 0 0xe0000000
737 0x02000000 0 0xe0000000
738 0 0x20000000
739
740 0x01000000 0 0x00000000
741 0x01000000 0 0x00000000
742 0 0x00010000>;
743 };
744 };
745};