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gerrit-public.fairphone.software / kernel / msm / ee940eb44f76503dc818b8a8ed21869b84990547 / . / arch / arm / mach-msm / include / mach / rpm-regulator-8660.h
blob: 85dcd897a26ec63cfdb7b552a07962dcdb7a6e2a [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]14#ifndef __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8660_H
15#define __ARCH_ARM_MACH_MSM_INCLUDE_MACH_RPM_REGULATOR_8660_H
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]16
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]17#define RPM_VREG_PIN_CTRL_PM8058_A0 0x01
18#define RPM_VREG_PIN_CTRL_PM8058_A1 0x02
19#define RPM_VREG_PIN_CTRL_PM8058_D0 0x04
20#define RPM_VREG_PIN_CTRL_PM8058_D1 0x08
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]21
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]22#define RPM_VREG_PIN_CTRL_PM8901_A0 0x01
23#define RPM_VREG_PIN_CTRL_PM8901_A1 0x02
24#define RPM_VREG_PIN_CTRL_PM8901_D0 0x04
25#define RPM_VREG_PIN_CTRL_PM8901_D1 0x08
26
27
28/**
29 * enum rpm_vreg_pin_fn_8660 - RPM regulator pin function choices
30 * %RPM_VREG_PIN_FN_8660_ENABLE: pin control switches between disable and
31 * enable
32 * %RPM_VREG_PIN_FN_8660_MODE: pin control switches between LPM and HPM
33 * %RPM_VREG_PIN_FN_8660_SLEEP_B: regulator is forced into LPM when
34 * sleep_b signal is asserted
35 * %RPM_VREG_PIN_FN_8660_NONE: do not use pin control for the regulator
36 * and do not allow another master to
37 * request pin control
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]38 *
39 * The pin function specified in platform data corresponds to the active state
40 * pin function value. Pin function will be NONE until a consumer requests
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]41 * pin control to be enabled.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]42 */
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]43enum rpm_vreg_pin_fn_8660 {
44 RPM_VREG_PIN_FN_8660_ENABLE = 0,
45 RPM_VREG_PIN_FN_8660_MODE,
46 RPM_VREG_PIN_FN_8660_SLEEP_B,
47 RPM_VREG_PIN_FN_8660_NONE,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]48};
49
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]50/**
51 * enum rpm_vreg_force_mode_8660 - RPM regulator force mode choices
52 * %RPM_VREG_FORCE_MODE_8660_PIN_CTRL: allow pin control usage
53 * %RPM_VREG_FORCE_MODE_8660_NONE: do not force any mode
54 * %RPM_VREG_FORCE_MODE_8660_LPM: force into low power mode
55 * %RPM_VREG_FORCE_MODE_8660_HPM: force into high power mode
56 *
57 * Force mode is used to override aggregation with other masters and to set
58 * special operating modes.
59 */
60enum rpm_vreg_force_mode_8660 {
61 RPM_VREG_FORCE_MODE_8660_PIN_CTRL = 0,
62 RPM_VREG_FORCE_MODE_8660_NONE = 0,
63 RPM_VREG_FORCE_MODE_8660_LPM,
64 RPM_VREG_FORCE_MODE_8660_HPM,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]65};
66
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]67enum rpm_vreg_id_8660 {
68 RPM_VREG_ID_PM8058_L0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]69 RPM_VREG_ID_PM8058_L1,
70 RPM_VREG_ID_PM8058_L2,
71 RPM_VREG_ID_PM8058_L3,
72 RPM_VREG_ID_PM8058_L4,
73 RPM_VREG_ID_PM8058_L5,
74 RPM_VREG_ID_PM8058_L6,
75 RPM_VREG_ID_PM8058_L7,
76 RPM_VREG_ID_PM8058_L8,
77 RPM_VREG_ID_PM8058_L9,
78 RPM_VREG_ID_PM8058_L10,
79 RPM_VREG_ID_PM8058_L11,
80 RPM_VREG_ID_PM8058_L12,
81 RPM_VREG_ID_PM8058_L13,
82 RPM_VREG_ID_PM8058_L14,
83 RPM_VREG_ID_PM8058_L15,
84 RPM_VREG_ID_PM8058_L16,
85 RPM_VREG_ID_PM8058_L17,
86 RPM_VREG_ID_PM8058_L18,
87 RPM_VREG_ID_PM8058_L19,
88 RPM_VREG_ID_PM8058_L20,
89 RPM_VREG_ID_PM8058_L21,
90 RPM_VREG_ID_PM8058_L22,
91 RPM_VREG_ID_PM8058_L23,
92 RPM_VREG_ID_PM8058_L24,
93 RPM_VREG_ID_PM8058_L25,
94 RPM_VREG_ID_PM8058_S0,
95 RPM_VREG_ID_PM8058_S1,
96 RPM_VREG_ID_PM8058_S2,
97 RPM_VREG_ID_PM8058_S3,
98 RPM_VREG_ID_PM8058_S4,
99 RPM_VREG_ID_PM8058_LVS0,
100 RPM_VREG_ID_PM8058_LVS1,
101 RPM_VREG_ID_PM8058_NCP,
102 RPM_VREG_ID_PM8901_L0,
103 RPM_VREG_ID_PM8901_L1,
104 RPM_VREG_ID_PM8901_L2,
105 RPM_VREG_ID_PM8901_L3,
106 RPM_VREG_ID_PM8901_L4,
107 RPM_VREG_ID_PM8901_L5,
108 RPM_VREG_ID_PM8901_L6,
109 RPM_VREG_ID_PM8901_S0,
110 RPM_VREG_ID_PM8901_S1,
111 RPM_VREG_ID_PM8901_S2,
112 RPM_VREG_ID_PM8901_S3,
113 RPM_VREG_ID_PM8901_S4,
114 RPM_VREG_ID_PM8901_LVS0,
115 RPM_VREG_ID_PM8901_LVS1,
116 RPM_VREG_ID_PM8901_LVS2,
117 RPM_VREG_ID_PM8901_LVS3,
118 RPM_VREG_ID_PM8901_MVS0,
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]119 RPM_VREG_ID_8660_MAX_REAL = RPM_VREG_ID_PM8901_MVS0,
120
121 /* The following are IDs for regulator devices to enable pin control. */
122 RPM_VREG_ID_PM8058_L0_PC,
123 RPM_VREG_ID_PM8058_L1_PC,
124 RPM_VREG_ID_PM8058_L2_PC,
125 RPM_VREG_ID_PM8058_L3_PC,
126 RPM_VREG_ID_PM8058_L4_PC,
127 RPM_VREG_ID_PM8058_L5_PC,
128 RPM_VREG_ID_PM8058_L6_PC,
129 RPM_VREG_ID_PM8058_L7_PC,
130 RPM_VREG_ID_PM8058_L8_PC,
131 RPM_VREG_ID_PM8058_L9_PC,
132 RPM_VREG_ID_PM8058_L10_PC,
133 RPM_VREG_ID_PM8058_L11_PC,
134 RPM_VREG_ID_PM8058_L12_PC,
135 RPM_VREG_ID_PM8058_L13_PC,
136 RPM_VREG_ID_PM8058_L14_PC,
137 RPM_VREG_ID_PM8058_L15_PC,
138 RPM_VREG_ID_PM8058_L16_PC,
139 RPM_VREG_ID_PM8058_L17_PC,
140 RPM_VREG_ID_PM8058_L18_PC,
141 RPM_VREG_ID_PM8058_L19_PC,
142 RPM_VREG_ID_PM8058_L20_PC,
143 RPM_VREG_ID_PM8058_L21_PC,
144 RPM_VREG_ID_PM8058_L22_PC,
145 RPM_VREG_ID_PM8058_L23_PC,
146 RPM_VREG_ID_PM8058_L24_PC,
147 RPM_VREG_ID_PM8058_L25_PC,
148 RPM_VREG_ID_PM8058_S0_PC,
149 RPM_VREG_ID_PM8058_S1_PC,
150 RPM_VREG_ID_PM8058_S2_PC,
151 RPM_VREG_ID_PM8058_S3_PC,
152 RPM_VREG_ID_PM8058_S4_PC,
153 RPM_VREG_ID_PM8058_LVS0_PC,
154 RPM_VREG_ID_PM8058_LVS1_PC,
155
156 RPM_VREG_ID_PM8901_L0_PC,
157 RPM_VREG_ID_PM8901_L1_PC,
158 RPM_VREG_ID_PM8901_L2_PC,
159 RPM_VREG_ID_PM8901_L3_PC,
160 RPM_VREG_ID_PM8901_L4_PC,
161 RPM_VREG_ID_PM8901_L5_PC,
162 RPM_VREG_ID_PM8901_L6_PC,
163 RPM_VREG_ID_PM8901_S0_PC,
164 RPM_VREG_ID_PM8901_S1_PC,
165 RPM_VREG_ID_PM8901_S2_PC,
166 RPM_VREG_ID_PM8901_S3_PC,
167 RPM_VREG_ID_PM8901_S4_PC,
168 RPM_VREG_ID_PM8901_LVS0_PC,
169 RPM_VREG_ID_PM8901_LVS1_PC,
170 RPM_VREG_ID_PM8901_LVS2_PC,
171 RPM_VREG_ID_PM8901_LVS3_PC,
172 RPM_VREG_ID_PM8901_MVS0_PC,
173 RPM_VREG_ID_8660_MAX = RPM_VREG_ID_PM8901_MVS0_PC,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]174};
175
176/* Minimum high power mode loads in uA. */
David Collins6f032ba2011-08-31 14:08:15 -0700[diff] [blame]177#define RPM_VREG_8660_LDO_50_HPM_MIN_LOAD 5000
178#define RPM_VREG_8660_LDO_150_HPM_MIN_LOAD 10000
179#define RPM_VREG_8660_LDO_300_HPM_MIN_LOAD 10000
180#define RPM_VREG_8660_SMPS_HPM_MIN_LOAD 50000
181#define RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD 100000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]182
183#endif