Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1 | /* |
| 2 | * sata_mv.c - Marvell SATA support |
| 3 | * |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 4 | * Copyright 2005: EMC Corporation, all rights reserved. |
Jeff Garzik | e2b1be5 | 2005-11-18 14:04:23 -0500 | [diff] [blame] | 5 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 6 | * |
| 7 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/pci.h> |
| 27 | #include <linux/init.h> |
| 28 | #include <linux/blkdev.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/interrupt.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 31 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 32 | #include <linux/device.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 33 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 34 | #include <scsi/scsi_cmnd.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 35 | #include <linux/libata.h> |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 36 | |
| 37 | #define DRV_NAME "sata_mv" |
Jeff Garzik | cb48cab | 2007-02-26 06:04:24 -0500 | [diff] [blame] | 38 | #define DRV_VERSION "0.8" |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 39 | |
| 40 | enum { |
| 41 | /* BAR's are enumerated in terms of pci_resource_start() terms */ |
| 42 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ |
| 43 | MV_IO_BAR = 2, /* offset 0x18: IO space */ |
| 44 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ |
| 45 | |
| 46 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ |
| 47 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ |
| 48 | |
| 49 | MV_PCI_REG_BASE = 0, |
| 50 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 51 | MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), |
| 52 | MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), |
| 53 | MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), |
| 54 | MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), |
| 55 | MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), |
| 56 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 57 | MV_SATAHC0_REG_BASE = 0x20000, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 58 | MV_FLASH_CTL = 0x1046c, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 59 | MV_GPIO_PORT_CTL = 0x104f0, |
| 60 | MV_RESET_CFG = 0x180d8, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 61 | |
| 62 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 63 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, |
| 64 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ |
| 65 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, |
| 66 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 67 | MV_USE_Q_DEPTH = ATA_DEF_QUEUE, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 68 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 69 | MV_MAX_Q_DEPTH = 32, |
| 70 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, |
| 71 | |
| 72 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB |
| 73 | * CRPB needs alignment on a 256B boundary. Size == 256B |
| 74 | * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB |
| 75 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
| 76 | */ |
| 77 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), |
| 78 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), |
| 79 | MV_MAX_SG_CT = 176, |
| 80 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
| 81 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), |
| 82 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 83 | MV_PORTS_PER_HC = 4, |
| 84 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ |
| 85 | MV_PORT_HC_SHIFT = 2, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 86 | /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 87 | MV_PORT_MASK = 3, |
| 88 | |
| 89 | /* Host Flags */ |
| 90 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ |
| 91 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 92 | MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Jeff Garzik | 5063019 | 2005-12-13 02:29:45 -0500 | [diff] [blame] | 93 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | |
Albert Lee | 1f3461a | 2006-05-23 18:12:30 +0800 | [diff] [blame] | 94 | ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING), |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 95 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 96 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 97 | CRQB_FLAG_READ = (1 << 0), |
| 98 | CRQB_TAG_SHIFT = 1, |
| 99 | CRQB_CMD_ADDR_SHIFT = 8, |
| 100 | CRQB_CMD_CS = (0x2 << 11), |
| 101 | CRQB_CMD_LAST = (1 << 15), |
| 102 | |
| 103 | CRPB_FLAG_STATUS_SHIFT = 8, |
| 104 | |
| 105 | EPRD_FLAG_END_OF_TBL = (1 << 31), |
| 106 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 107 | /* PCI interface registers */ |
| 108 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 109 | PCI_COMMAND_OFS = 0xc00, |
| 110 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 111 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
| 112 | STOP_PCI_MASTER = (1 << 2), |
| 113 | PCI_MASTER_EMPTY = (1 << 3), |
| 114 | GLOB_SFT_RST = (1 << 4), |
| 115 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 116 | MV_PCI_MODE = 0xd00, |
| 117 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
| 118 | MV_PCI_DISC_TIMER = 0xd04, |
| 119 | MV_PCI_MSI_TRIGGER = 0xc38, |
| 120 | MV_PCI_SERR_MASK = 0xc28, |
| 121 | MV_PCI_XBAR_TMOUT = 0x1d04, |
| 122 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
| 123 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, |
| 124 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, |
| 125 | MV_PCI_ERR_COMMAND = 0x1d50, |
| 126 | |
| 127 | PCI_IRQ_CAUSE_OFS = 0x1d58, |
| 128 | PCI_IRQ_MASK_OFS = 0x1d5c, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 129 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
| 130 | |
| 131 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, |
| 132 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, |
| 133 | PORT0_ERR = (1 << 0), /* shift by port # */ |
| 134 | PORT0_DONE = (1 << 1), /* shift by port # */ |
| 135 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
| 136 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ |
| 137 | PCI_ERR = (1 << 18), |
| 138 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ |
| 139 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 140 | PORTS_0_3_COAL_DONE = (1 << 8), |
| 141 | PORTS_4_7_COAL_DONE = (1 << 17), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 142 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ |
| 143 | GPIO_INT = (1 << 22), |
| 144 | SELF_INT = (1 << 23), |
| 145 | TWSI_INT = (1 << 24), |
| 146 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 147 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 148 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 149 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
| 150 | HC_MAIN_RSVD), |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 151 | HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
| 152 | HC_MAIN_RSVD_5), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 153 | |
| 154 | /* SATAHC registers */ |
| 155 | HC_CFG_OFS = 0, |
| 156 | |
| 157 | HC_IRQ_CAUSE_OFS = 0x14, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 158 | CRPB_DMA_DONE = (1 << 0), /* shift by port # */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 159 | HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ |
| 160 | DEV_IRQ = (1 << 8), /* shift by port # */ |
| 161 | |
| 162 | /* Shadow block registers */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 163 | SHD_BLK_OFS = 0x100, |
| 164 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 165 | |
| 166 | /* SATA registers */ |
| 167 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ |
| 168 | SATA_ACTIVE_OFS = 0x350, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 169 | PHY_MODE3 = 0x310, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 170 | PHY_MODE4 = 0x314, |
| 171 | PHY_MODE2 = 0x330, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 172 | MV5_PHY_MODE = 0x74, |
| 173 | MV5_LT_MODE = 0x30, |
| 174 | MV5_PHY_CTL = 0x0C, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 175 | SATA_INTERFACE_CTL = 0x050, |
| 176 | |
| 177 | MV_M2_PREAMP_MASK = 0x7e0, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 178 | |
| 179 | /* Port registers */ |
| 180 | EDMA_CFG_OFS = 0, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 181 | EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */ |
| 182 | EDMA_CFG_NCQ = (1 << 5), |
| 183 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ |
| 184 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ |
| 185 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 186 | |
| 187 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, |
| 188 | EDMA_ERR_IRQ_MASK_OFS = 0xc, |
| 189 | EDMA_ERR_D_PAR = (1 << 0), |
| 190 | EDMA_ERR_PRD_PAR = (1 << 1), |
| 191 | EDMA_ERR_DEV = (1 << 2), |
| 192 | EDMA_ERR_DEV_DCON = (1 << 3), |
| 193 | EDMA_ERR_DEV_CON = (1 << 4), |
| 194 | EDMA_ERR_SERR = (1 << 5), |
| 195 | EDMA_ERR_SELF_DIS = (1 << 7), |
| 196 | EDMA_ERR_BIST_ASYNC = (1 << 8), |
| 197 | EDMA_ERR_CRBQ_PAR = (1 << 9), |
| 198 | EDMA_ERR_CRPB_PAR = (1 << 10), |
| 199 | EDMA_ERR_INTRL_PAR = (1 << 11), |
| 200 | EDMA_ERR_IORDY = (1 << 12), |
| 201 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), |
| 202 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), |
| 203 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), |
| 204 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), |
| 205 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), |
| 206 | EDMA_ERR_TRANS_PROTO = (1 << 31), |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 207 | EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 208 | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | |
| 209 | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 210 | EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 211 | EDMA_ERR_LNK_DATA_RX | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 212 | EDMA_ERR_LNK_DATA_TX | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 213 | EDMA_ERR_TRANS_PROTO), |
| 214 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 215 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
| 216 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 217 | |
| 218 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, |
| 219 | EDMA_REQ_Q_PTR_SHIFT = 5, |
| 220 | |
| 221 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, |
| 222 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, |
| 223 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 224 | EDMA_RSP_Q_PTR_SHIFT = 3, |
| 225 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 226 | EDMA_CMD_OFS = 0x28, |
| 227 | EDMA_EN = (1 << 0), |
| 228 | EDMA_DS = (1 << 1), |
| 229 | ATA_RST = (1 << 2), |
| 230 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 231 | EDMA_IORDY_TMOUT = 0x34, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 232 | EDMA_ARB_CFG = 0x38, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 233 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 234 | /* Host private flags (hp_flags) */ |
| 235 | MV_HP_FLAG_MSI = (1 << 0), |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 236 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
| 237 | MV_HP_ERRATA_50XXB2 = (1 << 2), |
| 238 | MV_HP_ERRATA_60X1B2 = (1 << 3), |
| 239 | MV_HP_ERRATA_60X1C0 = (1 << 4), |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 240 | MV_HP_ERRATA_XX42A0 = (1 << 5), |
| 241 | MV_HP_50XX = (1 << 6), |
| 242 | MV_HP_GEN_IIE = (1 << 7), |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 243 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 244 | /* Port private flags (pp_flags) */ |
| 245 | MV_PP_FLAG_EDMA_EN = (1 << 0), |
| 246 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), |
| 247 | }; |
| 248 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 249 | #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 250 | #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 251 | #define IS_GEN_I(hpriv) IS_50XX(hpriv) |
| 252 | #define IS_GEN_II(hpriv) IS_60XX(hpriv) |
| 253 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 254 | |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 255 | enum { |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 256 | MV_DMA_BOUNDARY = 0xffffffffU, |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 257 | |
| 258 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
| 259 | |
| 260 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
| 261 | }; |
| 262 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 263 | enum chip_type { |
| 264 | chip_504x, |
| 265 | chip_508x, |
| 266 | chip_5080, |
| 267 | chip_604x, |
| 268 | chip_608x, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 269 | chip_6042, |
| 270 | chip_7042, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 271 | }; |
| 272 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 273 | /* Command ReQuest Block: 32B */ |
| 274 | struct mv_crqb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 275 | __le32 sg_addr; |
| 276 | __le32 sg_addr_hi; |
| 277 | __le16 ctrl_flags; |
| 278 | __le16 ata_cmd[11]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 279 | }; |
| 280 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 281 | struct mv_crqb_iie { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 282 | __le32 addr; |
| 283 | __le32 addr_hi; |
| 284 | __le32 flags; |
| 285 | __le32 len; |
| 286 | __le32 ata_cmd[4]; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 287 | }; |
| 288 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 289 | /* Command ResPonse Block: 8B */ |
| 290 | struct mv_crpb { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 291 | __le16 id; |
| 292 | __le16 flags; |
| 293 | __le32 tmstmp; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
| 297 | struct mv_sg { |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 298 | __le32 addr; |
| 299 | __le32 flags_size; |
| 300 | __le32 addr_hi; |
| 301 | __le32 reserved; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 302 | }; |
| 303 | |
| 304 | struct mv_port_priv { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 305 | struct mv_crqb *crqb; |
| 306 | dma_addr_t crqb_dma; |
| 307 | struct mv_crpb *crpb; |
| 308 | dma_addr_t crpb_dma; |
| 309 | struct mv_sg *sg_tbl; |
| 310 | dma_addr_t sg_tbl_dma; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 311 | u32 pp_flags; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 312 | }; |
| 313 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 314 | struct mv_port_signal { |
| 315 | u32 amps; |
| 316 | u32 pre; |
| 317 | }; |
| 318 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 319 | struct mv_host_priv; |
| 320 | struct mv_hw_ops { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 321 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 322 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 323 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 324 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, |
| 325 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 326 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 327 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 328 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 329 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 330 | }; |
| 331 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 332 | struct mv_host_priv { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 333 | u32 hp_flags; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 334 | struct mv_port_signal signal[8]; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 335 | const struct mv_hw_ops *ops; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | static void mv_irq_clear(struct ata_port *ap); |
| 339 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); |
| 340 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 341 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); |
| 342 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 343 | static void mv_phy_reset(struct ata_port *ap); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 344 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 345 | static int mv_port_start(struct ata_port *ap); |
| 346 | static void mv_port_stop(struct ata_port *ap); |
| 347 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 348 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 349 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 350 | static irqreturn_t mv_interrupt(int irq, void *dev_instance); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 351 | static void mv_eng_timeout(struct ata_port *ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 352 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
| 353 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 354 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 355 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 356 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 357 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 358 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 359 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 360 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 361 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 362 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 363 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 364 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 365 | unsigned int port); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 366 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 367 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
| 368 | void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 369 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 370 | unsigned int n_hc); |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 371 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
| 372 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 373 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 374 | unsigned int port_no); |
| 375 | static void mv_stop_and_reset(struct ata_port *ap); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 376 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 377 | static struct scsi_host_template mv_sht = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 378 | .module = THIS_MODULE, |
| 379 | .name = DRV_NAME, |
| 380 | .ioctl = ata_scsi_ioctl, |
| 381 | .queuecommand = ata_scsi_queuecmd, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 382 | .can_queue = MV_USE_Q_DEPTH, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 383 | .this_id = ATA_SHT_THIS_ID, |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 384 | .sg_tablesize = MV_MAX_SG_CT, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 385 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 386 | .emulated = ATA_SHT_EMULATED, |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 387 | .use_clustering = 1, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 388 | .proc_name = DRV_NAME, |
| 389 | .dma_boundary = MV_DMA_BOUNDARY, |
| 390 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 391 | .slave_destroy = ata_scsi_slave_destroy, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 392 | .bios_param = ata_std_bios_param, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 393 | }; |
| 394 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 395 | static const struct ata_port_operations mv5_ops = { |
| 396 | .port_disable = ata_port_disable, |
| 397 | |
| 398 | .tf_load = ata_tf_load, |
| 399 | .tf_read = ata_tf_read, |
| 400 | .check_status = ata_check_status, |
| 401 | .exec_command = ata_exec_command, |
| 402 | .dev_select = ata_std_dev_select, |
| 403 | |
| 404 | .phy_reset = mv_phy_reset, |
Jeff Garzik | cffacd8 | 2007-03-09 09:46:47 -0500 | [diff] [blame] | 405 | .cable_detect = ata_cable_sata, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 406 | |
| 407 | .qc_prep = mv_qc_prep, |
| 408 | .qc_issue = mv_qc_issue, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 409 | .data_xfer = ata_data_xfer, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 410 | |
| 411 | .eng_timeout = mv_eng_timeout, |
| 412 | |
| 413 | .irq_handler = mv_interrupt, |
| 414 | .irq_clear = mv_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 415 | .irq_on = ata_irq_on, |
| 416 | .irq_ack = ata_irq_ack, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 417 | |
| 418 | .scr_read = mv5_scr_read, |
| 419 | .scr_write = mv5_scr_write, |
| 420 | |
| 421 | .port_start = mv_port_start, |
| 422 | .port_stop = mv_port_stop, |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 423 | }; |
| 424 | |
| 425 | static const struct ata_port_operations mv6_ops = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 426 | .port_disable = ata_port_disable, |
| 427 | |
| 428 | .tf_load = ata_tf_load, |
| 429 | .tf_read = ata_tf_read, |
| 430 | .check_status = ata_check_status, |
| 431 | .exec_command = ata_exec_command, |
| 432 | .dev_select = ata_std_dev_select, |
| 433 | |
| 434 | .phy_reset = mv_phy_reset, |
Jeff Garzik | cffacd8 | 2007-03-09 09:46:47 -0500 | [diff] [blame] | 435 | .cable_detect = ata_cable_sata, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 436 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 437 | .qc_prep = mv_qc_prep, |
| 438 | .qc_issue = mv_qc_issue, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 439 | .data_xfer = ata_data_xfer, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 440 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 441 | .eng_timeout = mv_eng_timeout, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 442 | |
| 443 | .irq_handler = mv_interrupt, |
| 444 | .irq_clear = mv_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 445 | .irq_on = ata_irq_on, |
| 446 | .irq_ack = ata_irq_ack, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 447 | |
| 448 | .scr_read = mv_scr_read, |
| 449 | .scr_write = mv_scr_write, |
| 450 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 451 | .port_start = mv_port_start, |
| 452 | .port_stop = mv_port_stop, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 453 | }; |
| 454 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 455 | static const struct ata_port_operations mv_iie_ops = { |
| 456 | .port_disable = ata_port_disable, |
| 457 | |
| 458 | .tf_load = ata_tf_load, |
| 459 | .tf_read = ata_tf_read, |
| 460 | .check_status = ata_check_status, |
| 461 | .exec_command = ata_exec_command, |
| 462 | .dev_select = ata_std_dev_select, |
| 463 | |
| 464 | .phy_reset = mv_phy_reset, |
Jeff Garzik | cffacd8 | 2007-03-09 09:46:47 -0500 | [diff] [blame] | 465 | .cable_detect = ata_cable_sata, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 466 | |
| 467 | .qc_prep = mv_qc_prep_iie, |
| 468 | .qc_issue = mv_qc_issue, |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 469 | .data_xfer = ata_data_xfer, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 470 | |
| 471 | .eng_timeout = mv_eng_timeout, |
| 472 | |
| 473 | .irq_handler = mv_interrupt, |
| 474 | .irq_clear = mv_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 475 | .irq_on = ata_irq_on, |
| 476 | .irq_ack = ata_irq_ack, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 477 | |
| 478 | .scr_read = mv_scr_read, |
| 479 | .scr_write = mv_scr_write, |
| 480 | |
| 481 | .port_start = mv_port_start, |
| 482 | .port_stop = mv_port_stop, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 483 | }; |
| 484 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 485 | static const struct ata_port_info mv_port_info[] = { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 486 | { /* chip_504x */ |
| 487 | .sht = &mv_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 488 | .flags = MV_COMMON_FLAGS, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 489 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 490 | .udma_mask = 0x7f, /* udma0-6 */ |
| 491 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 492 | }, |
| 493 | { /* chip_508x */ |
| 494 | .sht = &mv_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 495 | .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 496 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 497 | .udma_mask = 0x7f, /* udma0-6 */ |
| 498 | .port_ops = &mv5_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 499 | }, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 500 | { /* chip_5080 */ |
| 501 | .sht = &mv_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 502 | .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 503 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 504 | .udma_mask = 0x7f, /* udma0-6 */ |
| 505 | .port_ops = &mv5_ops, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 506 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 507 | { /* chip_604x */ |
| 508 | .sht = &mv_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 509 | .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 510 | .pio_mask = 0x1f, /* pio0-4 */ |
| 511 | .udma_mask = 0x7f, /* udma0-6 */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 512 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 513 | }, |
| 514 | { /* chip_608x */ |
| 515 | .sht = &mv_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 516 | .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 517 | MV_FLAG_DUAL_HC), |
| 518 | .pio_mask = 0x1f, /* pio0-4 */ |
| 519 | .udma_mask = 0x7f, /* udma0-6 */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 520 | .port_ops = &mv6_ops, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 521 | }, |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 522 | { /* chip_6042 */ |
| 523 | .sht = &mv_sht, |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 524 | .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 525 | .pio_mask = 0x1f, /* pio0-4 */ |
| 526 | .udma_mask = 0x7f, /* udma0-6 */ |
| 527 | .port_ops = &mv_iie_ops, |
| 528 | }, |
| 529 | { /* chip_7042 */ |
| 530 | .sht = &mv_sht, |
Olof Johansson | e93f09d | 2007-01-18 18:39:59 -0600 | [diff] [blame] | 531 | .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 532 | .pio_mask = 0x1f, /* pio0-4 */ |
| 533 | .udma_mask = 0x7f, /* udma0-6 */ |
| 534 | .port_ops = &mv_iie_ops, |
| 535 | }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 536 | }; |
| 537 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 538 | static const struct pci_device_id mv_pci_tbl[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 539 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
| 540 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, |
| 541 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, |
| 542 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 543 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 544 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, |
| 545 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, |
| 546 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, |
| 547 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, |
| 548 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, |
Jeff Garzik | 2917953 | 2005-11-11 08:08:03 -0500 | [diff] [blame] | 549 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 550 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, |
| 551 | |
Olof Johansson | e93f09d | 2007-01-18 18:39:59 -0600 | [diff] [blame] | 552 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, |
| 553 | |
Morrison, Tom | 6a3d586 | 2007-03-06 02:38:10 -0800 | [diff] [blame] | 554 | /* add Marvell 7042 support */ |
| 555 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
| 556 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 557 | { } /* terminate list */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 558 | }; |
| 559 | |
| 560 | static struct pci_driver mv_pci_driver = { |
| 561 | .name = DRV_NAME, |
| 562 | .id_table = mv_pci_tbl, |
| 563 | .probe = mv_init_one, |
| 564 | .remove = ata_pci_remove_one, |
| 565 | }; |
| 566 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 567 | static const struct mv_hw_ops mv5xxx_ops = { |
| 568 | .phy_errata = mv5_phy_errata, |
| 569 | .enable_leds = mv5_enable_leds, |
| 570 | .read_preamp = mv5_read_preamp, |
| 571 | .reset_hc = mv5_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 572 | .reset_flash = mv5_reset_flash, |
| 573 | .reset_bus = mv5_reset_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 574 | }; |
| 575 | |
| 576 | static const struct mv_hw_ops mv6xxx_ops = { |
| 577 | .phy_errata = mv6_phy_errata, |
| 578 | .enable_leds = mv6_enable_leds, |
| 579 | .read_preamp = mv6_read_preamp, |
| 580 | .reset_hc = mv6_reset_hc, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 581 | .reset_flash = mv6_reset_flash, |
| 582 | .reset_bus = mv_reset_pci_bus, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 583 | }; |
| 584 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 585 | /* |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 586 | * module options |
| 587 | */ |
| 588 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ |
| 589 | |
| 590 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 591 | /* move to PCI layer or libata core? */ |
| 592 | static int pci_go_64(struct pci_dev *pdev) |
| 593 | { |
| 594 | int rc; |
| 595 | |
| 596 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 597 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 598 | if (rc) { |
| 599 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 600 | if (rc) { |
| 601 | dev_printk(KERN_ERR, &pdev->dev, |
| 602 | "64-bit DMA enable failed\n"); |
| 603 | return rc; |
| 604 | } |
| 605 | } |
| 606 | } else { |
| 607 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 608 | if (rc) { |
| 609 | dev_printk(KERN_ERR, &pdev->dev, |
| 610 | "32-bit DMA enable failed\n"); |
| 611 | return rc; |
| 612 | } |
| 613 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 614 | if (rc) { |
| 615 | dev_printk(KERN_ERR, &pdev->dev, |
| 616 | "32-bit consistent DMA enable failed\n"); |
| 617 | return rc; |
| 618 | } |
| 619 | } |
| 620 | |
| 621 | return rc; |
| 622 | } |
| 623 | |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 624 | /* |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 625 | * Functions |
| 626 | */ |
| 627 | |
| 628 | static inline void writelfl(unsigned long data, void __iomem *addr) |
| 629 | { |
| 630 | writel(data, addr); |
| 631 | (void) readl(addr); /* flush to avoid PCI posted write */ |
| 632 | } |
| 633 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 634 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
| 635 | { |
| 636 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); |
| 637 | } |
| 638 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 639 | static inline unsigned int mv_hc_from_port(unsigned int port) |
| 640 | { |
| 641 | return port >> MV_PORT_HC_SHIFT; |
| 642 | } |
| 643 | |
| 644 | static inline unsigned int mv_hardport_from_port(unsigned int port) |
| 645 | { |
| 646 | return port & MV_PORT_MASK; |
| 647 | } |
| 648 | |
| 649 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
| 650 | unsigned int port) |
| 651 | { |
| 652 | return mv_hc_base(base, mv_hc_from_port(port)); |
| 653 | } |
| 654 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 655 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
| 656 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 657 | return mv_hc_base_from_port(base, port) + |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 658 | MV_SATAHC_ARBTR_REG_SZ + |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 659 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 660 | } |
| 661 | |
| 662 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
| 663 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 664 | return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 665 | } |
| 666 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 667 | static inline int mv_get_hc_count(unsigned long port_flags) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 668 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 669 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 670 | } |
| 671 | |
| 672 | static void mv_irq_clear(struct ata_port *ap) |
| 673 | { |
| 674 | } |
| 675 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 676 | /** |
| 677 | * mv_start_dma - Enable eDMA engine |
| 678 | * @base: port base address |
| 679 | * @pp: port private data |
| 680 | * |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 681 | * Verify the local cache of the eDMA state is accurate with a |
| 682 | * WARN_ON. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 683 | * |
| 684 | * LOCKING: |
| 685 | * Inherited from caller. |
| 686 | */ |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 687 | static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 688 | { |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 689 | if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) { |
| 690 | writelfl(EDMA_EN, base + EDMA_CMD_OFS); |
| 691 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
| 692 | } |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 693 | WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS))); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 694 | } |
| 695 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 696 | /** |
| 697 | * mv_stop_dma - Disable eDMA engine |
| 698 | * @ap: ATA channel to manipulate |
| 699 | * |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 700 | * Verify the local cache of the eDMA state is accurate with a |
| 701 | * WARN_ON. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 702 | * |
| 703 | * LOCKING: |
| 704 | * Inherited from caller. |
| 705 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 706 | static void mv_stop_dma(struct ata_port *ap) |
| 707 | { |
| 708 | void __iomem *port_mmio = mv_ap_base(ap); |
| 709 | struct mv_port_priv *pp = ap->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 710 | u32 reg; |
| 711 | int i; |
| 712 | |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 713 | if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) { |
| 714 | /* Disable EDMA if active. The disable bit auto clears. |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 715 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 716 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
| 717 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 718 | } else { |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 719 | WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 720 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 721 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 722 | /* now properly wait for the eDMA to stop */ |
| 723 | for (i = 1000; i > 0; i--) { |
| 724 | reg = readl(port_mmio + EDMA_CMD_OFS); |
| 725 | if (!(EDMA_EN & reg)) { |
| 726 | break; |
| 727 | } |
| 728 | udelay(100); |
| 729 | } |
| 730 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 731 | if (EDMA_EN & reg) { |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 732 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 733 | /* FIXME: Consider doing a reset here to recover */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 734 | } |
| 735 | } |
| 736 | |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 737 | #ifdef ATA_DEBUG |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 738 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
| 739 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 740 | int b, w; |
| 741 | for (b = 0; b < bytes; ) { |
| 742 | DPRINTK("%p: ", start + b); |
| 743 | for (w = 0; b < bytes && w < 4; w++) { |
| 744 | printk("%08x ",readl(start + b)); |
| 745 | b += sizeof(u32); |
| 746 | } |
| 747 | printk("\n"); |
| 748 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 749 | } |
Jeff Garzik | 8a70f8d | 2005-10-05 17:19:47 -0400 | [diff] [blame] | 750 | #endif |
| 751 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 752 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
| 753 | { |
| 754 | #ifdef ATA_DEBUG |
| 755 | int b, w; |
| 756 | u32 dw; |
| 757 | for (b = 0; b < bytes; ) { |
| 758 | DPRINTK("%02x: ", b); |
| 759 | for (w = 0; b < bytes && w < 4; w++) { |
| 760 | (void) pci_read_config_dword(pdev,b,&dw); |
| 761 | printk("%08x ",dw); |
| 762 | b += sizeof(u32); |
| 763 | } |
| 764 | printk("\n"); |
| 765 | } |
| 766 | #endif |
| 767 | } |
| 768 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, |
| 769 | struct pci_dev *pdev) |
| 770 | { |
| 771 | #ifdef ATA_DEBUG |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 772 | void __iomem *hc_base = mv_hc_base(mmio_base, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 773 | port >> MV_PORT_HC_SHIFT); |
| 774 | void __iomem *port_base; |
| 775 | int start_port, num_ports, p, start_hc, num_hcs, hc; |
| 776 | |
| 777 | if (0 > port) { |
| 778 | start_hc = start_port = 0; |
| 779 | num_ports = 8; /* shld be benign for 4 port devs */ |
| 780 | num_hcs = 2; |
| 781 | } else { |
| 782 | start_hc = port >> MV_PORT_HC_SHIFT; |
| 783 | start_port = port; |
| 784 | num_ports = num_hcs = 1; |
| 785 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 786 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 787 | num_ports > 1 ? num_ports - 1 : start_port); |
| 788 | |
| 789 | if (NULL != pdev) { |
| 790 | DPRINTK("PCI config space regs:\n"); |
| 791 | mv_dump_pci_cfg(pdev, 0x68); |
| 792 | } |
| 793 | DPRINTK("PCI regs:\n"); |
| 794 | mv_dump_mem(mmio_base+0xc00, 0x3c); |
| 795 | mv_dump_mem(mmio_base+0xd00, 0x34); |
| 796 | mv_dump_mem(mmio_base+0xf00, 0x4); |
| 797 | mv_dump_mem(mmio_base+0x1d00, 0x6c); |
| 798 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { |
Dan Aloni | d220c37 | 2006-04-10 23:20:22 -0700 | [diff] [blame] | 799 | hc_base = mv_hc_base(mmio_base, hc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 800 | DPRINTK("HC regs (HC %i):\n", hc); |
| 801 | mv_dump_mem(hc_base, 0x1c); |
| 802 | } |
| 803 | for (p = start_port; p < start_port + num_ports; p++) { |
| 804 | port_base = mv_port_base(mmio_base, p); |
| 805 | DPRINTK("EDMA regs (port %i):\n",p); |
| 806 | mv_dump_mem(port_base, 0x54); |
| 807 | DPRINTK("SATA regs (port %i):\n",p); |
| 808 | mv_dump_mem(port_base+0x300, 0x60); |
| 809 | } |
| 810 | #endif |
| 811 | } |
| 812 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 813 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) |
| 814 | { |
| 815 | unsigned int ofs; |
| 816 | |
| 817 | switch (sc_reg_in) { |
| 818 | case SCR_STATUS: |
| 819 | case SCR_CONTROL: |
| 820 | case SCR_ERROR: |
| 821 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); |
| 822 | break; |
| 823 | case SCR_ACTIVE: |
| 824 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ |
| 825 | break; |
| 826 | default: |
| 827 | ofs = 0xffffffffU; |
| 828 | break; |
| 829 | } |
| 830 | return ofs; |
| 831 | } |
| 832 | |
| 833 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) |
| 834 | { |
| 835 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 836 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 837 | if (0xffffffffU != ofs) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 838 | return readl(mv_ap_base(ap) + ofs); |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 839 | else |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 840 | return (u32) ofs; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 841 | } |
| 842 | |
| 843 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
| 844 | { |
| 845 | unsigned int ofs = mv_scr_offset(sc_reg_in); |
| 846 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 847 | if (0xffffffffU != ofs) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 848 | writelfl(val, mv_ap_base(ap) + ofs); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 849 | } |
| 850 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 851 | static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio) |
| 852 | { |
| 853 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); |
| 854 | |
| 855 | /* set up non-NCQ EDMA configuration */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 856 | cfg &= ~(1 << 9); /* disable equeue */ |
| 857 | |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 858 | if (IS_GEN_I(hpriv)) { |
| 859 | cfg &= ~0x1f; /* clear queue depth */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 860 | cfg |= (1 << 8); /* enab config burst size mask */ |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 861 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 862 | |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 863 | else if (IS_GEN_II(hpriv)) { |
| 864 | cfg &= ~0x1f; /* clear queue depth */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 865 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 866 | cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */ |
| 867 | } |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 868 | |
| 869 | else if (IS_GEN_IIE(hpriv)) { |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 870 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
| 871 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 872 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ |
| 873 | cfg |= (1 << 18); /* enab early completion */ |
Jeff Garzik | e728eab | 2007-02-25 02:53:41 -0500 | [diff] [blame] | 874 | cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ |
| 875 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ |
| 876 | cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 877 | } |
| 878 | |
| 879 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); |
| 880 | } |
| 881 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 882 | /** |
| 883 | * mv_port_start - Port specific init/start routine. |
| 884 | * @ap: ATA channel to manipulate |
| 885 | * |
| 886 | * Allocate and point to DMA memory, init port private memory, |
| 887 | * zero indices. |
| 888 | * |
| 889 | * LOCKING: |
| 890 | * Inherited from caller. |
| 891 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 892 | static int mv_port_start(struct ata_port *ap) |
| 893 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 894 | struct device *dev = ap->host->dev; |
| 895 | struct mv_host_priv *hpriv = ap->host->private_data; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 896 | struct mv_port_priv *pp; |
| 897 | void __iomem *port_mmio = mv_ap_base(ap); |
| 898 | void *mem; |
| 899 | dma_addr_t mem_dma; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 900 | int rc; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 901 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 902 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 903 | if (!pp) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 904 | return -ENOMEM; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 905 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 906 | mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, |
| 907 | GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 908 | if (!mem) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 909 | return -ENOMEM; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 910 | memset(mem, 0, MV_PORT_PRIV_DMA_SZ); |
| 911 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 912 | rc = ata_pad_alloc(ap, dev); |
| 913 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 914 | return rc; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 915 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 916 | /* First item in chunk of DMA memory: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 917 | * 32-slot command request table (CRQB), 32 bytes each in size |
| 918 | */ |
| 919 | pp->crqb = mem; |
| 920 | pp->crqb_dma = mem_dma; |
| 921 | mem += MV_CRQB_Q_SZ; |
| 922 | mem_dma += MV_CRQB_Q_SZ; |
| 923 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 924 | /* Second item: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 925 | * 32-slot command response table (CRPB), 8 bytes each in size |
| 926 | */ |
| 927 | pp->crpb = mem; |
| 928 | pp->crpb_dma = mem_dma; |
| 929 | mem += MV_CRPB_Q_SZ; |
| 930 | mem_dma += MV_CRPB_Q_SZ; |
| 931 | |
| 932 | /* Third item: |
| 933 | * Table of scatter-gather descriptors (ePRD), 16 bytes each |
| 934 | */ |
| 935 | pp->sg_tbl = mem; |
| 936 | pp->sg_tbl_dma = mem_dma; |
| 937 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 938 | mv_edma_cfg(hpriv, port_mmio); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 939 | |
| 940 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 941 | writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 942 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 943 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 944 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
| 945 | writelfl(pp->crqb_dma & 0xffffffff, |
| 946 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
| 947 | else |
| 948 | writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 949 | |
| 950 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 951 | |
| 952 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
| 953 | writelfl(pp->crpb_dma & 0xffffffff, |
| 954 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
| 955 | else |
| 956 | writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
| 957 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 958 | writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 959 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
| 960 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 961 | /* Don't turn on EDMA here...do it before DMA commands only. Else |
| 962 | * we'll be unable to send non-data, PIO, etc due to restricted access |
| 963 | * to shadow regs. |
| 964 | */ |
| 965 | ap->private_data = pp; |
| 966 | return 0; |
| 967 | } |
| 968 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 969 | /** |
| 970 | * mv_port_stop - Port specific cleanup/stop routine. |
| 971 | * @ap: ATA channel to manipulate |
| 972 | * |
| 973 | * Stop DMA, cleanup port memory. |
| 974 | * |
| 975 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 976 | * This routine uses the host lock to protect the DMA stop. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 977 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 978 | static void mv_port_stop(struct ata_port *ap) |
| 979 | { |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 980 | unsigned long flags; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 981 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 982 | spin_lock_irqsave(&ap->host->lock, flags); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 983 | mv_stop_dma(ap); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 984 | spin_unlock_irqrestore(&ap->host->lock, flags); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 985 | } |
| 986 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 987 | /** |
| 988 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries |
| 989 | * @qc: queued command whose SG list to source from |
| 990 | * |
| 991 | * Populate the SG list and mark the last entry. |
| 992 | * |
| 993 | * LOCKING: |
| 994 | * Inherited from caller. |
| 995 | */ |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 996 | static unsigned int mv_fill_sg(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 997 | { |
| 998 | struct mv_port_priv *pp = qc->ap->private_data; |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 999 | unsigned int n_sg = 0; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1000 | struct scatterlist *sg; |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1001 | struct mv_sg *mv_sg; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1002 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1003 | mv_sg = pp->sg_tbl; |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1004 | ata_for_each_sg(sg, qc) { |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1005 | dma_addr_t addr = sg_dma_address(sg); |
| 1006 | u32 sg_len = sg_dma_len(sg); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1007 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1008 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1009 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1010 | mv_sg->flags_size = cpu_to_le32(sg_len & 0xffff); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1011 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1012 | if (ata_sg_is_last(sg, qc)) |
| 1013 | mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 1014 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1015 | mv_sg++; |
| 1016 | n_sg++; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1017 | } |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 1018 | |
| 1019 | return n_sg; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1020 | } |
| 1021 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1022 | static inline unsigned mv_inc_q_index(unsigned index) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1023 | { |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1024 | return (index + 1) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1025 | } |
| 1026 | |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 1027 | static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1028 | { |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1029 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1030 | (last ? CRQB_CMD_LAST : 0); |
Mark Lord | 559eeda | 2006-05-19 16:40:15 -0400 | [diff] [blame] | 1031 | *cmdw = cpu_to_le16(tmp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1032 | } |
| 1033 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1034 | /** |
| 1035 | * mv_qc_prep - Host specific command preparation. |
| 1036 | * @qc: queued command to prepare |
| 1037 | * |
| 1038 | * This routine simply redirects to the general purpose routine |
| 1039 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1040 | * (command request block), does some sanity checking, and calls |
| 1041 | * the SG load routine. |
| 1042 | * |
| 1043 | * LOCKING: |
| 1044 | * Inherited from caller. |
| 1045 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1046 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
| 1047 | { |
| 1048 | struct ata_port *ap = qc->ap; |
| 1049 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | e146987 | 2006-05-22 19:02:03 -0400 | [diff] [blame] | 1050 | __le16 *cw; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1051 | struct ata_taskfile *tf; |
| 1052 | u16 flags = 0; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1053 | unsigned in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1054 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1055 | if (ATA_PROT_DMA != qc->tf.protocol) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1056 | return; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1057 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1058 | /* Fill in command request block |
| 1059 | */ |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1060 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1061 | flags |= CRQB_FLAG_READ; |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1062 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1063 | flags |= qc->tag << CRQB_TAG_SHIFT; |
| 1064 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1065 | /* get current queue index from hardware */ |
| 1066 | in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS) |
| 1067 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1068 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1069 | pp->crqb[in_index].sg_addr = |
| 1070 | cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
| 1071 | pp->crqb[in_index].sg_addr_hi = |
| 1072 | cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
| 1073 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
| 1074 | |
| 1075 | cw = &pp->crqb[in_index].ata_cmd[0]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1076 | tf = &qc->tf; |
| 1077 | |
| 1078 | /* Sadly, the CRQB cannot accomodate all registers--there are |
| 1079 | * only 11 bytes...so we must pick and choose required |
| 1080 | * registers based on the command. So, we drop feature and |
| 1081 | * hob_feature for [RW] DMA commands, but they are needed for |
| 1082 | * NCQ. NCQ will drop hob_nsect. |
| 1083 | */ |
| 1084 | switch (tf->command) { |
| 1085 | case ATA_CMD_READ: |
| 1086 | case ATA_CMD_READ_EXT: |
| 1087 | case ATA_CMD_WRITE: |
| 1088 | case ATA_CMD_WRITE_EXT: |
Jens Axboe | c15d85c | 2006-02-15 15:59:25 +0100 | [diff] [blame] | 1089 | case ATA_CMD_WRITE_FUA_EXT: |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1090 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
| 1091 | break; |
| 1092 | #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ |
| 1093 | case ATA_CMD_FPDMA_READ: |
| 1094 | case ATA_CMD_FPDMA_WRITE: |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1095 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1096 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
| 1097 | break; |
| 1098 | #endif /* FIXME: remove this line when NCQ added */ |
| 1099 | default: |
| 1100 | /* The only other commands EDMA supports in non-queued and |
| 1101 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none |
| 1102 | * of which are defined/used by Linux. If we get here, this |
| 1103 | * driver needs work. |
| 1104 | * |
| 1105 | * FIXME: modify libata to give qc_prep a return value and |
| 1106 | * return error here. |
| 1107 | */ |
| 1108 | BUG_ON(tf->command); |
| 1109 | break; |
| 1110 | } |
| 1111 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); |
| 1112 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); |
| 1113 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); |
| 1114 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); |
| 1115 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); |
| 1116 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); |
| 1117 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); |
| 1118 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); |
| 1119 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ |
| 1120 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1121 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1122 | return; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1123 | mv_fill_sg(qc); |
| 1124 | } |
| 1125 | |
| 1126 | /** |
| 1127 | * mv_qc_prep_iie - Host specific command preparation. |
| 1128 | * @qc: queued command to prepare |
| 1129 | * |
| 1130 | * This routine simply redirects to the general purpose routine |
| 1131 | * if command is not DMA. Else, it handles prep of the CRQB |
| 1132 | * (command request block), does some sanity checking, and calls |
| 1133 | * the SG load routine. |
| 1134 | * |
| 1135 | * LOCKING: |
| 1136 | * Inherited from caller. |
| 1137 | */ |
| 1138 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) |
| 1139 | { |
| 1140 | struct ata_port *ap = qc->ap; |
| 1141 | struct mv_port_priv *pp = ap->private_data; |
| 1142 | struct mv_crqb_iie *crqb; |
| 1143 | struct ata_taskfile *tf; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1144 | unsigned in_index; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1145 | u32 flags = 0; |
| 1146 | |
| 1147 | if (ATA_PROT_DMA != qc->tf.protocol) |
| 1148 | return; |
| 1149 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1150 | /* Fill in Gen IIE command request block |
| 1151 | */ |
| 1152 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
| 1153 | flags |= CRQB_FLAG_READ; |
| 1154 | |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1155 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1156 | flags |= qc->tag << CRQB_TAG_SHIFT; |
| 1157 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1158 | /* get current queue index from hardware */ |
| 1159 | in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS) |
| 1160 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
| 1161 | |
| 1162 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1163 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
| 1164 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
| 1165 | crqb->flags = cpu_to_le32(flags); |
| 1166 | |
| 1167 | tf = &qc->tf; |
| 1168 | crqb->ata_cmd[0] = cpu_to_le32( |
| 1169 | (tf->command << 16) | |
| 1170 | (tf->feature << 24) |
| 1171 | ); |
| 1172 | crqb->ata_cmd[1] = cpu_to_le32( |
| 1173 | (tf->lbal << 0) | |
| 1174 | (tf->lbam << 8) | |
| 1175 | (tf->lbah << 16) | |
| 1176 | (tf->device << 24) |
| 1177 | ); |
| 1178 | crqb->ata_cmd[2] = cpu_to_le32( |
| 1179 | (tf->hob_lbal << 0) | |
| 1180 | (tf->hob_lbam << 8) | |
| 1181 | (tf->hob_lbah << 16) | |
| 1182 | (tf->hob_feature << 24) |
| 1183 | ); |
| 1184 | crqb->ata_cmd[3] = cpu_to_le32( |
| 1185 | (tf->nsect << 0) | |
| 1186 | (tf->hob_nsect << 8) |
| 1187 | ); |
| 1188 | |
| 1189 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
| 1190 | return; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1191 | mv_fill_sg(qc); |
| 1192 | } |
| 1193 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1194 | /** |
| 1195 | * mv_qc_issue - Initiate a command to the host |
| 1196 | * @qc: queued command to start |
| 1197 | * |
| 1198 | * This routine simply redirects to the general purpose routine |
| 1199 | * if command is not DMA. Else, it sanity checks our local |
| 1200 | * caches of the request producer/consumer indices then enables |
| 1201 | * DMA and bumps the request producer index. |
| 1202 | * |
| 1203 | * LOCKING: |
| 1204 | * Inherited from caller. |
| 1205 | */ |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1206 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1207 | { |
| 1208 | void __iomem *port_mmio = mv_ap_base(qc->ap); |
| 1209 | struct mv_port_priv *pp = qc->ap->private_data; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1210 | unsigned in_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1211 | u32 in_ptr; |
| 1212 | |
| 1213 | if (ATA_PROT_DMA != qc->tf.protocol) { |
| 1214 | /* We're about to send a non-EDMA capable command to the |
| 1215 | * port. Turn off EDMA so there won't be problems accessing |
| 1216 | * shadow block, etc registers. |
| 1217 | */ |
| 1218 | mv_stop_dma(qc->ap); |
| 1219 | return ata_qc_issue_prot(qc); |
| 1220 | } |
| 1221 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1222 | in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 1223 | in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1224 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1225 | /* until we do queuing, the queue should be empty at this point */ |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1226 | WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) |
| 1227 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1228 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1229 | in_index = mv_inc_q_index(in_index); /* now incr producer index */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1230 | |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1231 | mv_start_dma(port_mmio, pp); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1232 | |
| 1233 | /* and write the request in pointer to kick the EDMA to life */ |
| 1234 | in_ptr &= EDMA_REQ_Q_BASE_LO_MASK; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1235 | in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1236 | writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
| 1237 | |
| 1238 | return 0; |
| 1239 | } |
| 1240 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1241 | /** |
| 1242 | * mv_get_crpb_status - get status from most recently completed cmd |
| 1243 | * @ap: ATA channel to manipulate |
| 1244 | * |
| 1245 | * This routine is for use when the port is in DMA mode, when it |
| 1246 | * will be using the CRPB (command response block) method of |
Tejun Heo | beec7db | 2006-02-11 19:11:13 +0900 | [diff] [blame] | 1247 | * returning command completion information. We check indices |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1248 | * are good, grab status, and bump the response consumer index to |
| 1249 | * prove that we're up to date. |
| 1250 | * |
| 1251 | * LOCKING: |
| 1252 | * Inherited from caller. |
| 1253 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1254 | static u8 mv_get_crpb_status(struct ata_port *ap) |
| 1255 | { |
| 1256 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1257 | struct mv_port_priv *pp = ap->private_data; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1258 | unsigned out_index; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1259 | u32 out_ptr; |
Mark Lord | 806a6e7 | 2006-03-21 21:11:53 -0500 | [diff] [blame] | 1260 | u8 ata_status; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1261 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1262 | out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
| 1263 | out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1264 | |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1265 | ata_status = le16_to_cpu(pp->crpb[out_index].flags) |
| 1266 | >> CRPB_FLAG_STATUS_SHIFT; |
Mark Lord | 806a6e7 | 2006-03-21 21:11:53 -0500 | [diff] [blame] | 1267 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1268 | /* increment our consumer index... */ |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1269 | out_index = mv_inc_q_index(out_index); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1270 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1271 | /* and, until we do NCQ, there should only be 1 CRPB waiting */ |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1272 | WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) |
| 1273 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1274 | |
| 1275 | /* write out our inc'd consumer index so EDMA knows we're caught up */ |
| 1276 | out_ptr &= EDMA_RSP_Q_BASE_LO_MASK; |
Mark Lord | a643243 | 2006-05-19 16:36:36 -0400 | [diff] [blame] | 1277 | out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1278 | writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
| 1279 | |
| 1280 | /* Return ATA status register for completed CRPB */ |
Mark Lord | 806a6e7 | 2006-03-21 21:11:53 -0500 | [diff] [blame] | 1281 | return ata_status; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1282 | } |
| 1283 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1284 | /** |
| 1285 | * mv_err_intr - Handle error interrupts on the port |
| 1286 | * @ap: ATA channel to manipulate |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1287 | * @reset_allowed: bool: 0 == don't trigger from reset here |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1288 | * |
| 1289 | * In most cases, just clear the interrupt and move on. However, |
| 1290 | * some cases require an eDMA reset, which is done right before |
| 1291 | * the COMRESET in mv_phy_reset(). The SERR case requires a |
| 1292 | * clear of pending errors in the SATA SERROR register. Finally, |
| 1293 | * if the port disabled DMA, update our cached copy to match. |
| 1294 | * |
| 1295 | * LOCKING: |
| 1296 | * Inherited from caller. |
| 1297 | */ |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1298 | static void mv_err_intr(struct ata_port *ap, int reset_allowed) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1299 | { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1300 | void __iomem *port_mmio = mv_ap_base(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1301 | u32 edma_err_cause, serr = 0; |
| 1302 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1303 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 1304 | |
| 1305 | if (EDMA_ERR_SERR & edma_err_cause) { |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1306 | sata_scr_read(ap, SCR_ERROR, &serr); |
| 1307 | sata_scr_write_flush(ap, SCR_ERROR, serr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1308 | } |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1309 | if (EDMA_ERR_SELF_DIS & edma_err_cause) { |
| 1310 | struct mv_port_priv *pp = ap->private_data; |
| 1311 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
| 1312 | } |
| 1313 | DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x " |
Tejun Heo | 44877b4 | 2007-02-21 01:06:51 +0900 | [diff] [blame] | 1314 | "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1315 | |
| 1316 | /* Clear EDMA now that SERR cleanup done */ |
| 1317 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 1318 | |
| 1319 | /* check for fatal here and recover if needed */ |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1320 | if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause)) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1321 | mv_stop_and_reset(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1322 | } |
| 1323 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1324 | /** |
| 1325 | * mv_host_intr - Handle all interrupts on the given host controller |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1326 | * @host: host specific structure |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1327 | * @relevant: port error bits relevant to this host controller |
| 1328 | * @hc: which host controller we're to look at |
| 1329 | * |
| 1330 | * Read then write clear the HC interrupt status then walk each |
| 1331 | * port connected to the HC and see if it needs servicing. Port |
| 1332 | * success ints are reported in the HC interrupt status reg, the |
| 1333 | * port error ints are reported in the higher level main |
| 1334 | * interrupt status register and thus are passed in via the |
| 1335 | * 'relevant' argument. |
| 1336 | * |
| 1337 | * LOCKING: |
| 1338 | * Inherited from caller. |
| 1339 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1340 | static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1341 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1342 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1343 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1344 | struct ata_queued_cmd *qc; |
| 1345 | u32 hc_irq_cause; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1346 | int shift, port, port0, hard_port, handled; |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 1347 | unsigned int err_mask; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1348 | |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1349 | if (hc == 0) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1350 | port0 = 0; |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1351 | else |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1352 | port0 = MV_PORTS_PER_HC; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1353 | |
| 1354 | /* we'll need the HC success int register in most cases */ |
| 1355 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1356 | if (hc_irq_cause) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1357 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1358 | |
| 1359 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", |
| 1360 | hc,relevant,hc_irq_cause); |
| 1361 | |
| 1362 | for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { |
Jeff Garzik | cd85f6e | 2006-03-20 19:49:54 -0500 | [diff] [blame] | 1363 | u8 ata_status = 0; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1364 | struct ata_port *ap = host->ports[port]; |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1365 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | 55d8ca4 | 2006-03-29 19:43:31 -0500 | [diff] [blame] | 1366 | |
Mark Lord | e857f14 | 2006-05-19 16:33:03 -0400 | [diff] [blame] | 1367 | hard_port = mv_hardport_from_port(port); /* range 0..3 */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1368 | handled = 0; /* ensure ata_status is set if handled++ */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1369 | |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1370 | /* Note that DEV_IRQ might happen spuriously during EDMA, |
Mark Lord | e857f14 | 2006-05-19 16:33:03 -0400 | [diff] [blame] | 1371 | * and should be ignored in such cases. |
| 1372 | * The cause of this is still under investigation. |
Jeff Garzik | 8190bdb | 2006-05-24 01:53:39 -0400 | [diff] [blame] | 1373 | */ |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1374 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { |
| 1375 | /* EDMA: check for response queue interrupt */ |
| 1376 | if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) { |
| 1377 | ata_status = mv_get_crpb_status(ap); |
| 1378 | handled = 1; |
| 1379 | } |
| 1380 | } else { |
| 1381 | /* PIO: check for device (drive) interrupt */ |
| 1382 | if ((DEV_IRQ << hard_port) & hc_irq_cause) { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1383 | ata_status = readb(ap->ioaddr.status_addr); |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1384 | handled = 1; |
Mark Lord | e857f14 | 2006-05-19 16:33:03 -0400 | [diff] [blame] | 1385 | /* ignore spurious intr if drive still BUSY */ |
| 1386 | if (ata_status & ATA_BUSY) { |
| 1387 | ata_status = 0; |
| 1388 | handled = 0; |
| 1389 | } |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1390 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1391 | } |
| 1392 | |
Jeff Garzik | 029f546 | 2006-04-02 10:30:40 -0400 | [diff] [blame] | 1393 | if (ap && (ap->flags & ATA_FLAG_DISABLED)) |
Jeff Garzik | a2c91a8 | 2005-11-17 05:44:44 -0500 | [diff] [blame] | 1394 | continue; |
| 1395 | |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 1396 | err_mask = ac_err_mask(ata_status); |
| 1397 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1398 | shift = port << 1; /* (port * 2) */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1399 | if (port >= MV_PORTS_PER_HC) { |
| 1400 | shift++; /* skip bit 8 in the HC Main IRQ reg */ |
| 1401 | } |
| 1402 | if ((PORT0_ERR << shift) & relevant) { |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 1403 | mv_err_intr(ap, 1); |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 1404 | err_mask |= AC_ERR_OTHER; |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1405 | handled = 1; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1406 | } |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1407 | |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1408 | if (handled) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1409 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Mark Lord | 63af2a5 | 2006-03-29 09:50:31 -0500 | [diff] [blame] | 1410 | if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1411 | VPRINTK("port %u IRQ found for qc, " |
| 1412 | "ata_status 0x%x\n", port,ata_status); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1413 | /* mark qc status appropriately */ |
Jeff Garzik | 701db69 | 2005-12-06 04:52:48 -0500 | [diff] [blame] | 1414 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) { |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 1415 | qc->err_mask |= err_mask; |
| 1416 | ata_qc_complete(qc); |
| 1417 | } |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1418 | } |
| 1419 | } |
| 1420 | } |
| 1421 | VPRINTK("EXIT\n"); |
| 1422 | } |
| 1423 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1424 | /** |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1425 | * mv_interrupt - |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1426 | * @irq: unused |
| 1427 | * @dev_instance: private data; in this case the host structure |
| 1428 | * @regs: unused |
| 1429 | * |
| 1430 | * Read the read only register to determine if any host |
| 1431 | * controllers have pending interrupts. If so, call lower level |
| 1432 | * routine to handle. Also check for PCI errors which are only |
| 1433 | * reported here. |
| 1434 | * |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 1435 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1436 | * This routine holds the host lock while processing pending |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 1437 | * interrupts. |
| 1438 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1439 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1440 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1441 | struct ata_host *host = dev_instance; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1442 | unsigned int hc, handled = 0, n_hcs; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1443 | void __iomem *mmio = host->iomap[MV_PRIMARY_BAR]; |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 1444 | struct mv_host_priv *hpriv; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1445 | u32 irq_stat; |
| 1446 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1447 | irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1448 | |
| 1449 | /* check the cases where we either have nothing pending or have read |
| 1450 | * a bogus register value which can indicate HW removal or PCI fault |
| 1451 | */ |
Jeff Garzik | 3517726 | 2007-02-24 21:26:42 -0500 | [diff] [blame] | 1452 | if (!irq_stat || (0xffffffffU == irq_stat)) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1453 | return IRQ_NONE; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1454 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1455 | n_hcs = mv_get_hc_count(host->ports[0]->flags); |
| 1456 | spin_lock(&host->lock); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1457 | |
| 1458 | for (hc = 0; hc < n_hcs; hc++) { |
| 1459 | u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); |
| 1460 | if (relevant) { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1461 | mv_host_intr(host, relevant, hc); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1462 | handled++; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1463 | } |
| 1464 | } |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 1465 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1466 | hpriv = host->private_data; |
Mark Lord | 615ab95 | 2006-05-19 16:24:56 -0400 | [diff] [blame] | 1467 | if (IS_60XX(hpriv)) { |
| 1468 | /* deal with the interrupt coalescing bits */ |
| 1469 | if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) { |
| 1470 | writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO); |
| 1471 | writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI); |
| 1472 | writelfl(0, mmio + MV_IRQ_COAL_CAUSE); |
| 1473 | } |
| 1474 | } |
| 1475 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1476 | if (PCI_ERR & irq_stat) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1477 | printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n", |
| 1478 | readl(mmio + PCI_IRQ_CAUSE_OFS)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1479 | |
Brett Russ | afb0edd | 2005-10-05 17:08:42 -0400 | [diff] [blame] | 1480 | DPRINTK("All regs @ PCI error\n"); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1481 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1482 | |
| 1483 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
| 1484 | handled++; |
| 1485 | } |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1486 | spin_unlock(&host->lock); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1487 | |
| 1488 | return IRQ_RETVAL(handled); |
| 1489 | } |
| 1490 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1491 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
| 1492 | { |
| 1493 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); |
| 1494 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; |
| 1495 | |
| 1496 | return hc_mmio + ofs; |
| 1497 | } |
| 1498 | |
| 1499 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
| 1500 | { |
| 1501 | unsigned int ofs; |
| 1502 | |
| 1503 | switch (sc_reg_in) { |
| 1504 | case SCR_STATUS: |
| 1505 | case SCR_ERROR: |
| 1506 | case SCR_CONTROL: |
| 1507 | ofs = sc_reg_in * sizeof(u32); |
| 1508 | break; |
| 1509 | default: |
| 1510 | ofs = 0xffffffffU; |
| 1511 | break; |
| 1512 | } |
| 1513 | return ofs; |
| 1514 | } |
| 1515 | |
| 1516 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) |
| 1517 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1518 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
| 1519 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1520 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1521 | |
| 1522 | if (ofs != 0xffffffffU) |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1523 | return readl(addr + ofs); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1524 | else |
| 1525 | return (u32) ofs; |
| 1526 | } |
| 1527 | |
| 1528 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) |
| 1529 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1530 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
| 1531 | void __iomem *addr = mv5_phy_base(mmio, ap->port_no); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1532 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
| 1533 | |
| 1534 | if (ofs != 0xffffffffU) |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1535 | writelfl(val, addr + ofs); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1536 | } |
| 1537 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1538 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) |
| 1539 | { |
| 1540 | u8 rev_id; |
| 1541 | int early_5080; |
| 1542 | |
| 1543 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); |
| 1544 | |
| 1545 | early_5080 = (pdev->device == 0x5080) && (rev_id == 0); |
| 1546 | |
| 1547 | if (!early_5080) { |
| 1548 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1549 | tmp |= (1 << 0); |
| 1550 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1551 | } |
| 1552 | |
| 1553 | mv_reset_pci_bus(pdev, mmio); |
| 1554 | } |
| 1555 | |
| 1556 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 1557 | { |
| 1558 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); |
| 1559 | } |
| 1560 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1561 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1562 | void __iomem *mmio) |
| 1563 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1564 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
| 1565 | u32 tmp; |
| 1566 | |
| 1567 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1568 | |
| 1569 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ |
| 1570 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1571 | } |
| 1572 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1573 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1574 | { |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 1575 | u32 tmp; |
| 1576 | |
| 1577 | writel(0, mmio + MV_GPIO_PORT_CTL); |
| 1578 | |
| 1579 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ |
| 1580 | |
| 1581 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); |
| 1582 | tmp |= ~(1 << 0); |
| 1583 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1584 | } |
| 1585 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1586 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1587 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1588 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1589 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
| 1590 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); |
| 1591 | u32 tmp; |
| 1592 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); |
| 1593 | |
| 1594 | if (fix_apm_sq) { |
| 1595 | tmp = readl(phy_mmio + MV5_LT_MODE); |
| 1596 | tmp |= (1 << 19); |
| 1597 | writel(tmp, phy_mmio + MV5_LT_MODE); |
| 1598 | |
| 1599 | tmp = readl(phy_mmio + MV5_PHY_CTL); |
| 1600 | tmp &= ~0x3; |
| 1601 | tmp |= 0x1; |
| 1602 | writel(tmp, phy_mmio + MV5_PHY_CTL); |
| 1603 | } |
| 1604 | |
| 1605 | tmp = readl(phy_mmio + MV5_PHY_MODE); |
| 1606 | tmp &= ~mask; |
| 1607 | tmp |= hpriv->signal[port].pre; |
| 1608 | tmp |= hpriv->signal[port].amps; |
| 1609 | writel(tmp, phy_mmio + MV5_PHY_MODE); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1610 | } |
| 1611 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1612 | |
| 1613 | #undef ZERO |
| 1614 | #define ZERO(reg) writel(0, port_mmio + (reg)) |
| 1615 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1616 | unsigned int port) |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1617 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1618 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 1619 | |
| 1620 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
| 1621 | |
| 1622 | mv_channel_reset(hpriv, mmio, port); |
| 1623 | |
| 1624 | ZERO(0x028); /* command */ |
| 1625 | writel(0x11f, port_mmio + EDMA_CFG_OFS); |
| 1626 | ZERO(0x004); /* timer */ |
| 1627 | ZERO(0x008); /* irq err cause */ |
| 1628 | ZERO(0x00c); /* irq err mask */ |
| 1629 | ZERO(0x010); /* rq bah */ |
| 1630 | ZERO(0x014); /* rq inp */ |
| 1631 | ZERO(0x018); /* rq outp */ |
| 1632 | ZERO(0x01c); /* respq bah */ |
| 1633 | ZERO(0x024); /* respq outp */ |
| 1634 | ZERO(0x020); /* respq inp */ |
| 1635 | ZERO(0x02c); /* test control */ |
| 1636 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
| 1637 | } |
| 1638 | #undef ZERO |
| 1639 | |
| 1640 | #define ZERO(reg) writel(0, hc_mmio + (reg)) |
| 1641 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1642 | unsigned int hc) |
| 1643 | { |
| 1644 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 1645 | u32 tmp; |
| 1646 | |
| 1647 | ZERO(0x00c); |
| 1648 | ZERO(0x010); |
| 1649 | ZERO(0x014); |
| 1650 | ZERO(0x018); |
| 1651 | |
| 1652 | tmp = readl(hc_mmio + 0x20); |
| 1653 | tmp &= 0x1c1c1c1c; |
| 1654 | tmp |= 0x03030303; |
| 1655 | writel(tmp, hc_mmio + 0x20); |
| 1656 | } |
| 1657 | #undef ZERO |
| 1658 | |
| 1659 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1660 | unsigned int n_hc) |
| 1661 | { |
| 1662 | unsigned int hc, port; |
| 1663 | |
| 1664 | for (hc = 0; hc < n_hc; hc++) { |
| 1665 | for (port = 0; port < MV_PORTS_PER_HC; port++) |
| 1666 | mv5_reset_hc_port(hpriv, mmio, |
| 1667 | (hc * MV_PORTS_PER_HC) + port); |
| 1668 | |
| 1669 | mv5_reset_one_hc(hpriv, mmio, hc); |
| 1670 | } |
| 1671 | |
| 1672 | return 0; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1673 | } |
| 1674 | |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 1675 | #undef ZERO |
| 1676 | #define ZERO(reg) writel(0, mmio + (reg)) |
| 1677 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) |
| 1678 | { |
| 1679 | u32 tmp; |
| 1680 | |
| 1681 | tmp = readl(mmio + MV_PCI_MODE); |
| 1682 | tmp &= 0xff00ffff; |
| 1683 | writel(tmp, mmio + MV_PCI_MODE); |
| 1684 | |
| 1685 | ZERO(MV_PCI_DISC_TIMER); |
| 1686 | ZERO(MV_PCI_MSI_TRIGGER); |
| 1687 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
| 1688 | ZERO(HC_MAIN_IRQ_MASK_OFS); |
| 1689 | ZERO(MV_PCI_SERR_MASK); |
| 1690 | ZERO(PCI_IRQ_CAUSE_OFS); |
| 1691 | ZERO(PCI_IRQ_MASK_OFS); |
| 1692 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
| 1693 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); |
| 1694 | ZERO(MV_PCI_ERR_ATTRIBUTE); |
| 1695 | ZERO(MV_PCI_ERR_COMMAND); |
| 1696 | } |
| 1697 | #undef ZERO |
| 1698 | |
| 1699 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) |
| 1700 | { |
| 1701 | u32 tmp; |
| 1702 | |
| 1703 | mv5_reset_flash(hpriv, mmio); |
| 1704 | |
| 1705 | tmp = readl(mmio + MV_GPIO_PORT_CTL); |
| 1706 | tmp &= 0x3; |
| 1707 | tmp |= (1 << 5) | (1 << 6); |
| 1708 | writel(tmp, mmio + MV_GPIO_PORT_CTL); |
| 1709 | } |
| 1710 | |
| 1711 | /** |
| 1712 | * mv6_reset_hc - Perform the 6xxx global soft reset |
| 1713 | * @mmio: base address of the HBA |
| 1714 | * |
| 1715 | * This routine only applies to 6xxx parts. |
| 1716 | * |
| 1717 | * LOCKING: |
| 1718 | * Inherited from caller. |
| 1719 | */ |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1720 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1721 | unsigned int n_hc) |
Jeff Garzik | 101ffae | 2005-11-12 22:17:49 -0500 | [diff] [blame] | 1722 | { |
| 1723 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; |
| 1724 | int i, rc = 0; |
| 1725 | u32 t; |
| 1726 | |
| 1727 | /* Following procedure defined in PCI "main command and status |
| 1728 | * register" table. |
| 1729 | */ |
| 1730 | t = readl(reg); |
| 1731 | writel(t | STOP_PCI_MASTER, reg); |
| 1732 | |
| 1733 | for (i = 0; i < 1000; i++) { |
| 1734 | udelay(1); |
| 1735 | t = readl(reg); |
| 1736 | if (PCI_MASTER_EMPTY & t) { |
| 1737 | break; |
| 1738 | } |
| 1739 | } |
| 1740 | if (!(PCI_MASTER_EMPTY & t)) { |
| 1741 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); |
| 1742 | rc = 1; |
| 1743 | goto done; |
| 1744 | } |
| 1745 | |
| 1746 | /* set reset */ |
| 1747 | i = 5; |
| 1748 | do { |
| 1749 | writel(t | GLOB_SFT_RST, reg); |
| 1750 | t = readl(reg); |
| 1751 | udelay(1); |
| 1752 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); |
| 1753 | |
| 1754 | if (!(GLOB_SFT_RST & t)) { |
| 1755 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); |
| 1756 | rc = 1; |
| 1757 | goto done; |
| 1758 | } |
| 1759 | |
| 1760 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ |
| 1761 | i = 5; |
| 1762 | do { |
| 1763 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); |
| 1764 | t = readl(reg); |
| 1765 | udelay(1); |
| 1766 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); |
| 1767 | |
| 1768 | if (GLOB_SFT_RST & t) { |
| 1769 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); |
| 1770 | rc = 1; |
| 1771 | } |
| 1772 | done: |
| 1773 | return rc; |
| 1774 | } |
| 1775 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1776 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1777 | void __iomem *mmio) |
| 1778 | { |
| 1779 | void __iomem *port_mmio; |
| 1780 | u32 tmp; |
| 1781 | |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1782 | tmp = readl(mmio + MV_RESET_CFG); |
| 1783 | if ((tmp & (1 << 0)) == 0) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1784 | hpriv->signal[idx].amps = 0x7 << 8; |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1785 | hpriv->signal[idx].pre = 0x1 << 5; |
| 1786 | return; |
| 1787 | } |
| 1788 | |
| 1789 | port_mmio = mv_port_base(mmio, idx); |
| 1790 | tmp = readl(port_mmio + PHY_MODE2); |
| 1791 | |
| 1792 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ |
| 1793 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ |
| 1794 | } |
| 1795 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1796 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1797 | { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1798 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); |
Jeff Garzik | ba3fe8f | 2005-11-12 19:08:48 -0500 | [diff] [blame] | 1799 | } |
| 1800 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1801 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1802 | unsigned int port) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1803 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1804 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 1805 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1806 | u32 hp_flags = hpriv->hp_flags; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1807 | int fix_phy_mode2 = |
| 1808 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1809 | int fix_phy_mode4 = |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1810 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
| 1811 | u32 m2, tmp; |
| 1812 | |
| 1813 | if (fix_phy_mode2) { |
| 1814 | m2 = readl(port_mmio + PHY_MODE2); |
| 1815 | m2 &= ~(1 << 16); |
| 1816 | m2 |= (1 << 31); |
| 1817 | writel(m2, port_mmio + PHY_MODE2); |
| 1818 | |
| 1819 | udelay(200); |
| 1820 | |
| 1821 | m2 = readl(port_mmio + PHY_MODE2); |
| 1822 | m2 &= ~((1 << 16) | (1 << 31)); |
| 1823 | writel(m2, port_mmio + PHY_MODE2); |
| 1824 | |
| 1825 | udelay(200); |
| 1826 | } |
| 1827 | |
| 1828 | /* who knows what this magic does */ |
| 1829 | tmp = readl(port_mmio + PHY_MODE3); |
| 1830 | tmp &= ~0x7F800000; |
| 1831 | tmp |= 0x2A800000; |
| 1832 | writel(tmp, port_mmio + PHY_MODE3); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1833 | |
| 1834 | if (fix_phy_mode4) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1835 | u32 m4; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1836 | |
| 1837 | m4 = readl(port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1838 | |
| 1839 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
| 1840 | tmp = readl(port_mmio + 0x310); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1841 | |
| 1842 | m4 = (m4 & ~(1 << 1)) | (1 << 0); |
| 1843 | |
| 1844 | writel(m4, port_mmio + PHY_MODE4); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1845 | |
| 1846 | if (hp_flags & MV_HP_ERRATA_60X1B2) |
| 1847 | writel(tmp, port_mmio + 0x310); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1848 | } |
| 1849 | |
| 1850 | /* Revert values of pre-emphasis and signal amps to the saved ones */ |
| 1851 | m2 = readl(port_mmio + PHY_MODE2); |
| 1852 | |
| 1853 | m2 &= ~MV_M2_PREAMP_MASK; |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 1854 | m2 |= hpriv->signal[port].amps; |
| 1855 | m2 |= hpriv->signal[port].pre; |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 1856 | m2 &= ~(1 << 16); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1857 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 1858 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
| 1859 | if (IS_GEN_IIE(hpriv)) { |
| 1860 | m2 &= ~0xC30FF01F; |
| 1861 | m2 |= 0x0000900F; |
| 1862 | } |
| 1863 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1864 | writel(m2, port_mmio + PHY_MODE2); |
| 1865 | } |
| 1866 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1867 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
| 1868 | unsigned int port_no) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1869 | { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1870 | void __iomem *port_mmio = mv_port_base(mmio, port_no); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1871 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1872 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1873 | |
| 1874 | if (IS_60XX(hpriv)) { |
| 1875 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); |
Mark Lord | eb46d68 | 2006-05-19 16:29:21 -0400 | [diff] [blame] | 1876 | ifctl |= (1 << 7); /* enable gen2i speed */ |
| 1877 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1878 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); |
| 1879 | } |
| 1880 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1881 | udelay(25); /* allow reset propagation */ |
| 1882 | |
| 1883 | /* Spec never mentions clearing the bit. Marvell's driver does |
| 1884 | * clear the bit, however. |
| 1885 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1886 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1887 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1888 | hpriv->ops->phy_errata(hpriv, mmio, port_no); |
| 1889 | |
| 1890 | if (IS_50XX(hpriv)) |
| 1891 | mdelay(1); |
| 1892 | } |
| 1893 | |
| 1894 | static void mv_stop_and_reset(struct ata_port *ap) |
| 1895 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1896 | struct mv_host_priv *hpriv = ap->host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1897 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1898 | |
| 1899 | mv_stop_dma(ap); |
| 1900 | |
| 1901 | mv_channel_reset(hpriv, mmio, ap->port_no); |
| 1902 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1903 | __mv_phy_reset(ap, 0); |
| 1904 | } |
| 1905 | |
| 1906 | static inline void __msleep(unsigned int msec, int can_sleep) |
| 1907 | { |
| 1908 | if (can_sleep) |
| 1909 | msleep(msec); |
| 1910 | else |
| 1911 | mdelay(msec); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1912 | } |
| 1913 | |
| 1914 | /** |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1915 | * __mv_phy_reset - Perform eDMA reset followed by COMRESET |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1916 | * @ap: ATA channel to manipulate |
| 1917 | * |
| 1918 | * Part of this is taken from __sata_phy_reset and modified to |
| 1919 | * not sleep since this routine gets called from interrupt level. |
| 1920 | * |
| 1921 | * LOCKING: |
| 1922 | * Inherited from caller. This is coded to safe to call at |
| 1923 | * interrupt level, i.e. it does not sleep. |
| 1924 | */ |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1925 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep) |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1926 | { |
| 1927 | struct mv_port_priv *pp = ap->private_data; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1928 | struct mv_host_priv *hpriv = ap->host->private_data; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1929 | void __iomem *port_mmio = mv_ap_base(ap); |
| 1930 | struct ata_taskfile tf; |
| 1931 | struct ata_device *dev = &ap->device[0]; |
| 1932 | unsigned long timeout; |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1933 | int retry = 5; |
| 1934 | u32 sstatus; |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 1935 | |
| 1936 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 1937 | |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 1938 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1939 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
| 1940 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1941 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1942 | /* Issue COMRESET via SControl */ |
| 1943 | comreset_retry: |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1944 | sata_scr_write_flush(ap, SCR_CONTROL, 0x301); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1945 | __msleep(1, can_sleep); |
| 1946 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1947 | sata_scr_write_flush(ap, SCR_CONTROL, 0x300); |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1948 | __msleep(20, can_sleep); |
| 1949 | |
| 1950 | timeout = jiffies + msecs_to_jiffies(200); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1951 | do { |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1952 | sata_scr_read(ap, SCR_STATUS, &sstatus); |
Andres Salomon | 62f1d0e | 2006-09-11 08:51:05 -0400 | [diff] [blame] | 1953 | if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1954 | break; |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1955 | |
| 1956 | __msleep(1, can_sleep); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1957 | } while (time_before(jiffies, timeout)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1958 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1959 | /* work around errata */ |
| 1960 | if (IS_60XX(hpriv) && |
| 1961 | (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && |
| 1962 | (retry-- > 0)) |
| 1963 | goto comreset_retry; |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 1964 | |
| 1965 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1966 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
| 1967 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); |
| 1968 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1969 | if (ata_port_online(ap)) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1970 | ata_port_probe(ap); |
| 1971 | } else { |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1972 | sata_scr_read(ap, SCR_STATUS, &sstatus); |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 1973 | ata_port_printk(ap, KERN_INFO, |
| 1974 | "no device found (phy stat %08x)\n", sstatus); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 1975 | ata_port_disable(ap); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1976 | return; |
| 1977 | } |
| 1978 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 1979 | /* even after SStatus reflects that device is ready, |
| 1980 | * it seems to take a while for link to be fully |
| 1981 | * established (and thus Status no longer 0x80/0x7F), |
| 1982 | * so we poll a bit for that, here. |
| 1983 | */ |
| 1984 | retry = 20; |
| 1985 | while (1) { |
| 1986 | u8 drv_stat = ata_check_status(ap); |
| 1987 | if ((drv_stat != 0x80) && (drv_stat != 0x7f)) |
| 1988 | break; |
| 1989 | __msleep(500, can_sleep); |
| 1990 | if (retry-- <= 0) |
| 1991 | break; |
| 1992 | } |
| 1993 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1994 | tf.lbah = readb(ap->ioaddr.lbah_addr); |
| 1995 | tf.lbam = readb(ap->ioaddr.lbam_addr); |
| 1996 | tf.lbal = readb(ap->ioaddr.lbal_addr); |
| 1997 | tf.nsect = readb(ap->ioaddr.nsect_addr); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 1998 | |
| 1999 | dev->class = ata_dev_classify(&tf); |
Tejun Heo | e1211e3 | 2006-04-01 01:38:18 +0900 | [diff] [blame] | 2000 | if (!ata_dev_enabled(dev)) { |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2001 | VPRINTK("Port disabled post-sig: No device present.\n"); |
| 2002 | ata_port_disable(ap); |
| 2003 | } |
Jeff Garzik | 095fec8 | 2005-11-12 09:50:49 -0500 | [diff] [blame] | 2004 | |
| 2005 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2006 | |
| 2007 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
| 2008 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2009 | VPRINTK("EXIT\n"); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2010 | } |
| 2011 | |
Jeff Garzik | 2237467 | 2005-11-17 10:59:48 -0500 | [diff] [blame] | 2012 | static void mv_phy_reset(struct ata_port *ap) |
| 2013 | { |
| 2014 | __mv_phy_reset(ap, 1); |
| 2015 | } |
| 2016 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2017 | /** |
| 2018 | * mv_eng_timeout - Routine called by libata when SCSI times out I/O |
| 2019 | * @ap: ATA channel to manipulate |
| 2020 | * |
| 2021 | * Intent is to clear all pending error conditions, reset the |
| 2022 | * chip/bus, fail the command, and move on. |
| 2023 | * |
| 2024 | * LOCKING: |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2025 | * This routine holds the host lock while failing the command. |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2026 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2027 | static void mv_eng_timeout(struct ata_port *ap) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2028 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2029 | void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR]; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2030 | struct ata_queued_cmd *qc; |
Mark Lord | 2f9719b | 2006-06-07 12:53:29 -0400 | [diff] [blame] | 2031 | unsigned long flags; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2032 | |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 2033 | ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n"); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2034 | DPRINTK("All regs @ start of eng_timeout\n"); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2035 | mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev)); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2036 | |
| 2037 | qc = ata_qc_from_tag(ap, ap->active_tag); |
| 2038 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2039 | mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2040 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2041 | spin_lock_irqsave(&ap->host->lock, flags); |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 2042 | mv_err_intr(ap, 0); |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2043 | mv_stop_and_reset(ap); |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2044 | spin_unlock_irqrestore(&ap->host->lock, flags); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2045 | |
Mark Lord | 9b358e3 | 2006-05-19 16:21:03 -0400 | [diff] [blame] | 2046 | WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE)); |
| 2047 | if (qc->flags & ATA_QCFLAG_ACTIVE) { |
| 2048 | qc->err_mask |= AC_ERR_TIMEOUT; |
| 2049 | ata_eh_qc_complete(qc); |
| 2050 | } |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2051 | } |
| 2052 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2053 | /** |
| 2054 | * mv_port_init - Perform some early initialization on a single port. |
| 2055 | * @port: libata data structure storing shadow register addresses |
| 2056 | * @port_mmio: base address of the port |
| 2057 | * |
| 2058 | * Initialize shadow register mmio addresses, clear outstanding |
| 2059 | * interrupts on the port, and unmask interrupts for the future |
| 2060 | * start of the port. |
| 2061 | * |
| 2062 | * LOCKING: |
| 2063 | * Inherited from caller. |
| 2064 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2065 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
| 2066 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2067 | void __iomem *shd_base = port_mmio + SHD_BLK_OFS; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2068 | unsigned serr_ofs; |
| 2069 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2070 | /* PIO related setup |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2071 | */ |
| 2072 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2073 | port->error_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2074 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
| 2075 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); |
| 2076 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); |
| 2077 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); |
| 2078 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); |
| 2079 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2080 | port->status_addr = |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2081 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
| 2082 | /* special case: control/altstatus doesn't have ATA_REG_ address */ |
| 2083 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; |
| 2084 | |
| 2085 | /* unused: */ |
Randy Dunlap | 8d9db2d | 2007-02-16 01:40:06 -0800 | [diff] [blame] | 2086 | port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2087 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2088 | /* Clear any currently outstanding port interrupt conditions */ |
| 2089 | serr_ofs = mv_scr_offset(SCR_ERROR); |
| 2090 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); |
| 2091 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
| 2092 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2093 | /* unmask all EDMA error interrupts */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2094 | writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2095 | |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2096 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2097 | readl(port_mmio + EDMA_CFG_OFS), |
| 2098 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), |
| 2099 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2100 | } |
| 2101 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2102 | static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv, |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 2103 | unsigned int board_idx) |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2104 | { |
| 2105 | u8 rev_id; |
| 2106 | u32 hp_flags = hpriv->hp_flags; |
| 2107 | |
| 2108 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); |
| 2109 | |
| 2110 | switch(board_idx) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2111 | case chip_5080: |
| 2112 | hpriv->ops = &mv5xxx_ops; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2113 | hp_flags |= MV_HP_50XX; |
| 2114 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2115 | switch (rev_id) { |
| 2116 | case 0x1: |
| 2117 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2118 | break; |
| 2119 | case 0x3: |
| 2120 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2121 | break; |
| 2122 | default: |
| 2123 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2124 | "Applying 50XXB2 workarounds to unknown rev\n"); |
| 2125 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2126 | break; |
| 2127 | } |
| 2128 | break; |
| 2129 | |
| 2130 | case chip_504x: |
| 2131 | case chip_508x: |
| 2132 | hpriv->ops = &mv5xxx_ops; |
| 2133 | hp_flags |= MV_HP_50XX; |
| 2134 | |
| 2135 | switch (rev_id) { |
| 2136 | case 0x0: |
| 2137 | hp_flags |= MV_HP_ERRATA_50XXB0; |
| 2138 | break; |
| 2139 | case 0x3: |
| 2140 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2141 | break; |
| 2142 | default: |
| 2143 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2144 | "Applying B2 workarounds to unknown rev\n"); |
| 2145 | hp_flags |= MV_HP_ERRATA_50XXB2; |
| 2146 | break; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2147 | } |
| 2148 | break; |
| 2149 | |
| 2150 | case chip_604x: |
| 2151 | case chip_608x: |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2152 | hpriv->ops = &mv6xxx_ops; |
| 2153 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2154 | switch (rev_id) { |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2155 | case 0x7: |
| 2156 | hp_flags |= MV_HP_ERRATA_60X1B2; |
| 2157 | break; |
| 2158 | case 0x9: |
| 2159 | hp_flags |= MV_HP_ERRATA_60X1C0; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2160 | break; |
| 2161 | default: |
| 2162 | dev_printk(KERN_WARNING, &pdev->dev, |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2163 | "Applying B2 workarounds to unknown rev\n"); |
| 2164 | hp_flags |= MV_HP_ERRATA_60X1B2; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2165 | break; |
| 2166 | } |
| 2167 | break; |
| 2168 | |
Jeff Garzik | e4e7b89 | 2006-01-31 12:18:41 -0500 | [diff] [blame] | 2169 | case chip_7042: |
| 2170 | case chip_6042: |
| 2171 | hpriv->ops = &mv6xxx_ops; |
| 2172 | |
| 2173 | hp_flags |= MV_HP_GEN_IIE; |
| 2174 | |
| 2175 | switch (rev_id) { |
| 2176 | case 0x0: |
| 2177 | hp_flags |= MV_HP_ERRATA_XX42A0; |
| 2178 | break; |
| 2179 | case 0x1: |
| 2180 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2181 | break; |
| 2182 | default: |
| 2183 | dev_printk(KERN_WARNING, &pdev->dev, |
| 2184 | "Applying 60X1C0 workarounds to unknown rev\n"); |
| 2185 | hp_flags |= MV_HP_ERRATA_60X1C0; |
| 2186 | break; |
| 2187 | } |
| 2188 | break; |
| 2189 | |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2190 | default: |
| 2191 | printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); |
| 2192 | return 1; |
| 2193 | } |
| 2194 | |
| 2195 | hpriv->hp_flags = hp_flags; |
| 2196 | |
| 2197 | return 0; |
| 2198 | } |
| 2199 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2200 | /** |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2201 | * mv_init_host - Perform some early initialization of the host. |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2202 | * @pdev: host PCI device |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2203 | * @probe_ent: early data struct representing the host |
| 2204 | * |
| 2205 | * If possible, do an early global reset of the host. Then do |
| 2206 | * our port init and clear/unmask all/relevant host interrupts. |
| 2207 | * |
| 2208 | * LOCKING: |
| 2209 | * Inherited from caller. |
| 2210 | */ |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2211 | static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2212 | unsigned int board_idx) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2213 | { |
| 2214 | int rc = 0, n_hc, port, hc; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2215 | void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR]; |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2216 | struct mv_host_priv *hpriv = probe_ent->private_data; |
| 2217 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2218 | /* global interrupt mask */ |
| 2219 | writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); |
| 2220 | |
| 2221 | rc = mv_chip_id(pdev, hpriv, board_idx); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2222 | if (rc) |
| 2223 | goto done; |
| 2224 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2225 | n_hc = mv_get_hc_count(probe_ent->port_flags); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2226 | probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; |
| 2227 | |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2228 | for (port = 0; port < probe_ent->n_ports; port++) |
| 2229 | hpriv->ops->read_preamp(hpriv, port, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2230 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2231 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2232 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2233 | goto done; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2234 | |
Jeff Garzik | 522479f | 2005-11-12 22:14:02 -0500 | [diff] [blame] | 2235 | hpriv->ops->reset_flash(hpriv, mmio); |
| 2236 | hpriv->ops->reset_bus(pdev, mmio); |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2237 | hpriv->ops->enable_leds(hpriv, mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2238 | |
| 2239 | for (port = 0; port < probe_ent->n_ports; port++) { |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2240 | if (IS_60XX(hpriv)) { |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2241 | void __iomem *port_mmio = mv_port_base(mmio, port); |
| 2242 | |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2243 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); |
Mark Lord | eb46d68 | 2006-05-19 16:29:21 -0400 | [diff] [blame] | 2244 | ifctl |= (1 << 7); /* enable gen2i speed */ |
| 2245 | ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */ |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2246 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); |
| 2247 | } |
| 2248 | |
Jeff Garzik | c9d3913 | 2005-11-13 17:47:51 -0500 | [diff] [blame] | 2249 | hpriv->ops->phy_errata(hpriv, mmio, port); |
Jeff Garzik | 2a47ce0 | 2005-11-12 23:05:14 -0500 | [diff] [blame] | 2250 | } |
| 2251 | |
| 2252 | for (port = 0; port < probe_ent->n_ports; port++) { |
| 2253 | void __iomem *port_mmio = mv_port_base(mmio, port); |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2254 | mv_port_init(&probe_ent->port[port], port_mmio); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2255 | } |
| 2256 | |
| 2257 | for (hc = 0; hc < n_hc; hc++) { |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2258 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
| 2259 | |
| 2260 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " |
| 2261 | "(before clear)=0x%08x\n", hc, |
| 2262 | readl(hc_mmio + HC_CFG_OFS), |
| 2263 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); |
| 2264 | |
| 2265 | /* Clear any currently outstanding hc interrupt conditions */ |
| 2266 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2267 | } |
| 2268 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2269 | /* Clear any currently outstanding host interrupt conditions */ |
| 2270 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
| 2271 | |
| 2272 | /* and unmask interrupt generation for host regs */ |
| 2273 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); |
Jeff Garzik | fb621e2 | 2007-02-25 04:19:45 -0500 | [diff] [blame] | 2274 | |
| 2275 | if (IS_50XX(hpriv)) |
| 2276 | writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS); |
| 2277 | else |
| 2278 | writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2279 | |
| 2280 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2281 | "PCI int cause/mask=0x%08x/0x%08x\n", |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2282 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), |
| 2283 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), |
| 2284 | readl(mmio + PCI_IRQ_CAUSE_OFS), |
| 2285 | readl(mmio + PCI_IRQ_MASK_OFS)); |
Jeff Garzik | bca1c4e | 2005-11-12 12:48:15 -0500 | [diff] [blame] | 2286 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2287 | done: |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2288 | return rc; |
| 2289 | } |
| 2290 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2291 | /** |
| 2292 | * mv_print_info - Dump key info to kernel log for perusal. |
| 2293 | * @probe_ent: early data struct representing the host |
| 2294 | * |
| 2295 | * FIXME: complete this. |
| 2296 | * |
| 2297 | * LOCKING: |
| 2298 | * Inherited from caller. |
| 2299 | */ |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2300 | static void mv_print_info(struct ata_probe_ent *probe_ent) |
| 2301 | { |
| 2302 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
| 2303 | struct mv_host_priv *hpriv = probe_ent->private_data; |
| 2304 | u8 rev_id, scc; |
| 2305 | const char *scc_s; |
| 2306 | |
| 2307 | /* Use this to determine the HW stepping of the chip so we know |
| 2308 | * what errata to workaround |
| 2309 | */ |
| 2310 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); |
| 2311 | |
| 2312 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
| 2313 | if (scc == 0) |
| 2314 | scc_s = "SCSI"; |
| 2315 | else if (scc == 0x01) |
| 2316 | scc_s = "RAID"; |
| 2317 | else |
| 2318 | scc_s = "unknown"; |
| 2319 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2320 | dev_printk(KERN_INFO, &pdev->dev, |
| 2321 | "%u slots %u ports %s mode IRQ via %s\n", |
Jeff Garzik | 8b26024 | 2005-11-12 12:32:50 -0500 | [diff] [blame] | 2322 | (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2323 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
| 2324 | } |
| 2325 | |
Brett Russ | 05b308e | 2005-10-05 17:08:53 -0400 | [diff] [blame] | 2326 | /** |
| 2327 | * mv_init_one - handle a positive probe of a Marvell host |
| 2328 | * @pdev: PCI device found |
| 2329 | * @ent: PCI device ID entry for the matched host |
| 2330 | * |
| 2331 | * LOCKING: |
| 2332 | * Inherited from caller. |
| 2333 | */ |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2334 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 2335 | { |
| 2336 | static int printed_version = 0; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2337 | struct device *dev = &pdev->dev; |
| 2338 | struct ata_probe_ent *probe_ent; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2339 | struct mv_host_priv *hpriv; |
| 2340 | unsigned int board_idx = (unsigned int)ent->driver_data; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2341 | int rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2342 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 2343 | if (!printed_version++) |
| 2344 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2345 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2346 | rc = pcim_enable_device(pdev); |
| 2347 | if (rc) |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2348 | return rc; |
Mark Lord | eb46d68 | 2006-05-19 16:29:21 -0400 | [diff] [blame] | 2349 | pci_set_master(pdev); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2350 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2351 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
| 2352 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2353 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2354 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2355 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2356 | |
Jeff Garzik | d88184f | 2007-02-26 01:26:06 -0500 | [diff] [blame] | 2357 | rc = pci_go_64(pdev); |
| 2358 | if (rc) |
| 2359 | return rc; |
| 2360 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2361 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); |
| 2362 | if (probe_ent == NULL) |
| 2363 | return -ENOMEM; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2364 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2365 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 2366 | INIT_LIST_HEAD(&probe_ent->node); |
| 2367 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2368 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 2369 | if (!hpriv) |
| 2370 | return -ENOMEM; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2371 | |
| 2372 | probe_ent->sht = mv_port_info[board_idx].sht; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 2373 | probe_ent->port_flags = mv_port_info[board_idx].flags; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2374 | probe_ent->pio_mask = mv_port_info[board_idx].pio_mask; |
| 2375 | probe_ent->udma_mask = mv_port_info[board_idx].udma_mask; |
| 2376 | probe_ent->port_ops = mv_port_info[board_idx].port_ops; |
| 2377 | |
| 2378 | probe_ent->irq = pdev->irq; |
Thomas Gleixner | 1d6f359 | 2006-07-01 19:29:42 -0700 | [diff] [blame] | 2379 | probe_ent->irq_flags = IRQF_SHARED; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 2380 | probe_ent->iomap = pcim_iomap_table(pdev); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2381 | probe_ent->private_data = hpriv; |
| 2382 | |
| 2383 | /* initialize adapter */ |
Jeff Garzik | 47c2b67 | 2005-11-12 21:13:17 -0500 | [diff] [blame] | 2384 | rc = mv_init_host(pdev, probe_ent, board_idx); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2385 | if (rc) |
| 2386 | return rc; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2387 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2388 | /* Enable interrupts */ |
Tejun Heo | 6a59dcf | 2007-02-24 15:12:31 +0900 | [diff] [blame] | 2389 | if (msi && pci_enable_msi(pdev)) |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2390 | pci_intx(pdev, 1); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2391 | |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2392 | mv_dump_pci_cfg(pdev, 0x68); |
| 2393 | mv_print_info(probe_ent); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2394 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2395 | if (ata_device_add(probe_ent) == 0) |
| 2396 | return -ENODEV; |
Brett Russ | 3196194 | 2005-09-30 01:36:00 -0400 | [diff] [blame] | 2397 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 2398 | devm_kfree(dev, probe_ent); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2399 | return 0; |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2400 | } |
| 2401 | |
| 2402 | static int __init mv_init(void) |
| 2403 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 2404 | return pci_register_driver(&mv_pci_driver); |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2405 | } |
| 2406 | |
| 2407 | static void __exit mv_exit(void) |
| 2408 | { |
| 2409 | pci_unregister_driver(&mv_pci_driver); |
| 2410 | } |
| 2411 | |
| 2412 | MODULE_AUTHOR("Brett Russ"); |
| 2413 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); |
| 2414 | MODULE_LICENSE("GPL"); |
| 2415 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); |
| 2416 | MODULE_VERSION(DRV_VERSION); |
| 2417 | |
Jeff Garzik | ddef9bb | 2006-02-02 16:17:06 -0500 | [diff] [blame] | 2418 | module_param(msi, int, 0444); |
| 2419 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); |
| 2420 | |
Brett Russ | 20f733e | 2005-09-01 18:26:17 -0400 | [diff] [blame] | 2421 | module_init(mv_init); |
| 2422 | module_exit(mv_exit); |