Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /** |
| 2 | * @file op_model_athlon.h |
| 3 | * athlon / K7 model-specific MSR operations |
| 4 | * |
| 5 | * @remark Copyright 2002 OProfile authors |
| 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
| 11 | */ |
| 12 | |
| 13 | #include <linux/oprofile.h> |
| 14 | #include <asm/ptrace.h> |
| 15 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 16 | #include <asm/nmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | |
| 18 | #include "op_x86_model.h" |
| 19 | #include "op_counter.h" |
| 20 | |
| 21 | #define NUM_COUNTERS 4 |
| 22 | #define NUM_CONTROLS 4 |
| 23 | |
| 24 | #define CTR_READ(l,h,msrs,c) do {rdmsr(msrs->counters[(c)].addr, (l), (h));} while (0) |
| 25 | #define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1);} while (0) |
| 26 | #define CTR_OVERFLOWED(n) (!((n) & (1U<<31))) |
| 27 | |
| 28 | #define CTRL_READ(l,h,msrs,c) do {rdmsr(msrs->controls[(c)].addr, (l), (h));} while (0) |
| 29 | #define CTRL_WRITE(l,h,msrs,c) do {wrmsr(msrs->controls[(c)].addr, (l), (h));} while (0) |
| 30 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) |
| 31 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) |
| 32 | #define CTRL_CLEAR(x) (x &= (1<<21)) |
| 33 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) |
| 34 | #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16)) |
| 35 | #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17)) |
| 36 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) |
| 37 | #define CTRL_SET_EVENT(val, e) (val |= e) |
| 38 | |
| 39 | static unsigned long reset_value[NUM_COUNTERS]; |
| 40 | |
| 41 | static void athlon_fill_in_addresses(struct op_msrs * const msrs) |
| 42 | { |
| 43 | msrs->counters[0].addr = MSR_K7_PERFCTR0; |
| 44 | msrs->counters[1].addr = MSR_K7_PERFCTR1; |
| 45 | msrs->counters[2].addr = MSR_K7_PERFCTR2; |
| 46 | msrs->counters[3].addr = MSR_K7_PERFCTR3; |
| 47 | |
| 48 | msrs->controls[0].addr = MSR_K7_EVNTSEL0; |
| 49 | msrs->controls[1].addr = MSR_K7_EVNTSEL1; |
| 50 | msrs->controls[2].addr = MSR_K7_EVNTSEL2; |
| 51 | msrs->controls[3].addr = MSR_K7_EVNTSEL3; |
| 52 | } |
| 53 | |
| 54 | |
| 55 | static void athlon_setup_ctrs(struct op_msrs const * const msrs) |
| 56 | { |
| 57 | unsigned int low, high; |
| 58 | int i; |
| 59 | |
| 60 | /* clear all counters */ |
| 61 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
| 62 | CTRL_READ(low, high, msrs, i); |
| 63 | CTRL_CLEAR(low); |
| 64 | CTRL_WRITE(low, high, msrs, i); |
| 65 | } |
| 66 | |
| 67 | /* avoid a false detection of ctr overflows in NMI handler */ |
| 68 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 69 | CTR_WRITE(1, msrs, i); |
| 70 | } |
| 71 | |
| 72 | /* enable active counters */ |
| 73 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 74 | if (counter_config[i].enabled) { |
| 75 | reset_value[i] = counter_config[i].count; |
| 76 | |
| 77 | CTR_WRITE(counter_config[i].count, msrs, i); |
| 78 | |
| 79 | CTRL_READ(low, high, msrs, i); |
| 80 | CTRL_CLEAR(low); |
| 81 | CTRL_SET_ENABLE(low); |
| 82 | CTRL_SET_USR(low, counter_config[i].user); |
| 83 | CTRL_SET_KERN(low, counter_config[i].kernel); |
| 84 | CTRL_SET_UM(low, counter_config[i].unit_mask); |
| 85 | CTRL_SET_EVENT(low, counter_config[i].event); |
| 86 | CTRL_WRITE(low, high, msrs, i); |
| 87 | } else { |
| 88 | reset_value[i] = 0; |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | |
| 94 | static int athlon_check_ctrs(struct pt_regs * const regs, |
| 95 | struct op_msrs const * const msrs) |
| 96 | { |
| 97 | unsigned int low, high; |
| 98 | int i; |
| 99 | |
| 100 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
| 101 | CTR_READ(low, high, msrs, i); |
| 102 | if (CTR_OVERFLOWED(low)) { |
| 103 | oprofile_add_sample(regs, i); |
| 104 | CTR_WRITE(reset_value[i], msrs, i); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | /* See op_model_ppro.c */ |
| 109 | return 1; |
| 110 | } |
| 111 | |
| 112 | |
| 113 | static void athlon_start(struct op_msrs const * const msrs) |
| 114 | { |
| 115 | unsigned int low, high; |
| 116 | int i; |
| 117 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 118 | if (reset_value[i]) { |
| 119 | CTRL_READ(low, high, msrs, i); |
| 120 | CTRL_SET_ACTIVE(low); |
| 121 | CTRL_WRITE(low, high, msrs, i); |
| 122 | } |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | |
| 127 | static void athlon_stop(struct op_msrs const * const msrs) |
| 128 | { |
| 129 | unsigned int low,high; |
| 130 | int i; |
| 131 | |
| 132 | /* Subtle: stop on all counters to avoid race with |
| 133 | * setting our pm callback */ |
| 134 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 135 | CTRL_READ(low, high, msrs, i); |
| 136 | CTRL_SET_INACTIVE(low); |
| 137 | CTRL_WRITE(low, high, msrs, i); |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | |
| 142 | struct op_x86_model_spec const op_athlon_spec = { |
| 143 | .num_counters = NUM_COUNTERS, |
| 144 | .num_controls = NUM_CONTROLS, |
| 145 | .fill_in_addresses = &athlon_fill_in_addresses, |
| 146 | .setup_ctrs = &athlon_setup_ctrs, |
| 147 | .check_ctrs = &athlon_check_ctrs, |
| 148 | .start = &athlon_start, |
| 149 | .stop = &athlon_stop |
| 150 | }; |