| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #include <linux/config.h> |
| 2 | |
| 3 | .global __main |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | .global __rom_start |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | |
| 6 | .global _rambase |
| 7 | .global _ramstart |
| 8 | |
| 9 | .global splash_bits |
| 10 | .global _start |
| 11 | .global _stext |
| Greg Ungerer | d2f386d | 2006-06-26 16:34:09 +1000 | [diff] [blame] | 12 | .global _edata |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | |
| 14 | #define DEBUG |
| 15 | #define ROM_OFFSET 0x10C00000 |
| 16 | #define STACK_GAURD 0x10 |
| 17 | |
| 18 | .text |
| 19 | |
| 20 | _start: |
| 21 | _stext: |
| 22 | movew #0x2700, %sr /* Exceptions off! */ |
| 23 | |
| 24 | #if 0 |
| 25 | /* Init chip registers. uCsimm specific */ |
| 26 | moveb #0x00, 0xfffffb0b /* Watchdog off */ |
| 27 | moveb #0x10, 0xfffff000 /* SCR */ |
| 28 | |
| 29 | movew #0x2400, 0xfffff200 /* PLLCR */ |
| 30 | movew #0x0123, 0xfffff202 /* PLLFSR */ |
| 31 | |
| 32 | moveb #0x00, 0xfffff40b /* enable chip select */ |
| 33 | moveb #0x00, 0xfffff423 /* enable /DWE */ |
| 34 | moveb #0x08, 0xfffffd0d /* disable hardmap */ |
| 35 | moveb #0x07, 0xfffffd0e /* level 7 interrupt clear */ |
| 36 | |
| 37 | movew #0x8600, 0xfffff100 /* FLASH at 0x10c00000 */ |
| 38 | movew #0x018b, 0xfffff110 /* 2Meg, enable, 0ws */ |
| 39 | |
| 40 | movew #0x8f00, 0xfffffc00 /* DRAM configuration */ |
| 41 | movew #0x9667, 0xfffffc02 /* DRAM control */ |
| 42 | movew #0x0000, 0xfffff106 /* DRAM at 0x00000000 */ |
| 43 | movew #0x068f, 0xfffff116 /* 8Meg, enable, 0ws */ |
| 44 | |
| 45 | moveb #0x40, 0xfffff300 /* IVR */ |
| 46 | movel #0x007FFFFF, %d0 /* IMR */ |
| 47 | movel %d0, 0xfffff304 |
| 48 | |
| 49 | moveb 0xfffff42b, %d0 |
| 50 | andb #0xe0, %d0 |
| 51 | moveb %d0, 0xfffff42b |
| 52 | |
| 53 | moveb #0x08, 0xfffff907 /* Ignore CTS */ |
| 54 | movew #0x010b, 0xfffff902 /* BAUD to 9600 */ |
| 55 | movew #0xe100, 0xfffff900 /* enable */ |
| 56 | #endif |
| 57 | |
| 58 | movew #16384, %d0 /* PLL settle wait loop */ |
| 59 | L0: |
| 60 | subw #1, %d0 |
| 61 | bne L0 |
| 62 | #ifdef DEBUG |
| 63 | moveq #70, %d7 /* 'F' */ |
| 64 | moveb %d7,0xfffff907 /* No absolute addresses */ |
| 65 | pclp1: |
| 66 | movew 0xfffff906, %d7 |
| 67 | andw #0x2000, %d7 |
| 68 | beq pclp1 |
| 69 | #endif /* DEBUG */ |
| 70 | |
| 71 | #ifdef CONFIG_RELOCATE |
| 72 | /* Copy me to RAM */ |
| 73 | moveal #__rom_start, %a0 |
| Greg Ungerer | d2f386d | 2006-06-26 16:34:09 +1000 | [diff] [blame] | 74 | moveal #_stext, %a1 |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | moveal #_edata, %a2 |
| 76 | |
| 77 | /* Copy %a0 to %a1 until %a1 == %a2 */ |
| 78 | LD1: |
| 79 | movel %a0@+, %d0 |
| 80 | movel %d0, %a1@+ |
| 81 | cmpal %a1, %a2 |
| 82 | bhi LD1 |
| 83 | |
| 84 | #ifdef DEBUG |
| 85 | moveq #74, %d7 /* 'J' */ |
| 86 | moveb %d7,0xfffff907 /* No absolute addresses */ |
| 87 | pclp2: |
| 88 | movew 0xfffff906, %d7 |
| 89 | andw #0x2000, %d7 |
| 90 | beq pclp2 |
| 91 | #endif /* DEBUG */ |
| 92 | /* jump into the RAM copy */ |
| 93 | jmp ram_jump |
| 94 | ram_jump: |
| 95 | |
| 96 | #endif /* CONFIG_RELOCATE */ |
| 97 | |
| 98 | #ifdef DEBUG |
| 99 | moveq #82, %d7 /* 'R' */ |
| 100 | moveb %d7,0xfffff907 /* No absolute addresses */ |
| 101 | pclp3: |
| 102 | movew 0xfffff906, %d7 |
| 103 | andw #0x2000, %d7 |
| 104 | beq pclp3 |
| 105 | #endif /* DEBUG */ |
| 106 | moveal #0x007ffff0, %ssp |
| 107 | moveal #_sbss, %a0 |
| 108 | moveal #_ebss, %a1 |
| 109 | |
| 110 | /* Copy 0 to %a0 until %a0 >= %a1 */ |
| 111 | L1: |
| 112 | movel #0, %a0@+ |
| 113 | cmpal %a0, %a1 |
| 114 | bhi L1 |
| 115 | |
| 116 | #ifdef DEBUG |
| 117 | moveq #67, %d7 /* 'C' */ |
| 118 | jsr putc |
| 119 | #endif /* DEBUG */ |
| 120 | |
| 121 | pea 0 |
| 122 | pea env |
| 123 | pea %sp@(4) |
| 124 | pea 0 |
| 125 | |
| 126 | #ifdef DEBUG |
| 127 | moveq #70, %d7 /* 'F' */ |
| 128 | jsr putc |
| 129 | #endif /* DEBUG */ |
| 130 | |
| 131 | lp: |
| 132 | jsr start_kernel |
| 133 | jmp lp |
| 134 | _exit: |
| 135 | |
| 136 | jmp _exit |
| 137 | |
| 138 | __main: |
| 139 | /* nothing */ |
| 140 | rts |
| 141 | |
| 142 | #ifdef DEBUG |
| 143 | putc: |
| 144 | moveb %d7,0xfffff907 |
| 145 | pclp: |
| 146 | movew 0xfffff906, %d7 |
| 147 | andw #0x2000, %d7 |
| 148 | beq pclp |
| 149 | rts |
| 150 | #endif /* DEBUG */ |
| 151 | |
| 152 | .data |
| 153 | |
| 154 | /* |
| 155 | * Set up the usable of RAM stuff. Size of RAM is determined then |
| 156 | * an initial stack set up at the end. |
| 157 | */ |
| 158 | .align 4 |
| 159 | _ramvec: |
| 160 | .long 0 |
| 161 | _rambase: |
| 162 | .long 0 |
| 163 | _ramstart: |
| 164 | .long 0 |
| 165 | _ramend: |
| 166 | .long 0 |
| 167 | |
| 168 | env: |
| 169 | .long 0 |