Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 2 | * arch/arm/mach-omap2/serial.c |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * OMAP2 serial support. |
| 5 | * |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
| 8 | * |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 9 | * Major rework for PM support by Kevin Hilman |
| 10 | * |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
| 12 | * |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 13 | * Copyright (C) 2009 Texas Instruments |
| 14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com |
| 15 | * |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 16 | * This file is subject to the terms and conditions of the GNU General Public |
| 17 | * License. See the file "COPYING" in the main directory of this archive |
| 18 | * for more details. |
| 19 | */ |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/init.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 22 | #include <linux/serial_reg.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 23 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 24 | #include <linux/io.h> |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 25 | #include <linux/delay.h> |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/serial_8250.h> |
Kevin Hilman | 3244fcd | 2010-09-27 20:19:53 +0530 | [diff] [blame] | 29 | #include <linux/pm_runtime.h> |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 30 | #include <linux/console.h> |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 31 | |
| 32 | #ifdef CONFIG_SERIAL_OMAP |
| 33 | #include <plat/omap-serial.h> |
| 34 | #endif |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 35 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 36 | #include <plat/common.h> |
| 37 | #include <plat/board.h> |
| 38 | #include <plat/clock.h> |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 39 | #include <plat/dma.h> |
| 40 | #include <plat/omap_hwmod.h> |
| 41 | #include <plat/omap_device.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 42 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 43 | #include "prm2xxx_3xxx.h" |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 44 | #include "pm.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 45 | #include "cm2xxx_3xxx.h" |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 46 | #include "prm-regbits-34xx.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 47 | #include "control.h" |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 48 | #include "mux.h" |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 49 | |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 50 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 51 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
| 52 | |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 53 | #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 54 | #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 55 | |
Tony Lindgren | 301fe8e | 2010-02-01 12:34:31 -0800 | [diff] [blame] | 56 | /* |
| 57 | * NOTE: By default the serial timeout is disabled as it causes lost characters |
| 58 | * over the serial ports. This means that the UART clocks will stay on until |
| 59 | * disabled via sysfs. This also causes that any deeper omap sleep states are |
| 60 | * blocked. |
| 61 | */ |
| 62 | #define DEFAULT_TIMEOUT 0 |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 63 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 64 | #define MAX_UART_HWMOD_NAME_LEN 16 |
| 65 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 66 | struct omap_uart_state { |
| 67 | int num; |
| 68 | int can_sleep; |
| 69 | struct timer_list timer; |
| 70 | u32 timeout; |
| 71 | |
| 72 | void __iomem *wk_st; |
| 73 | void __iomem *wk_en; |
| 74 | u32 wk_mask; |
| 75 | u32 padconf; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 76 | u32 dma_enabled; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 77 | |
| 78 | struct clk *ick; |
| 79 | struct clk *fck; |
| 80 | int clocked; |
| 81 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 82 | int irq; |
| 83 | int regshift; |
| 84 | int irqflags; |
| 85 | void __iomem *membase; |
| 86 | resource_size_t mapbase; |
| 87 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 88 | struct list_head node; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 89 | struct omap_hwmod *oh; |
| 90 | struct platform_device *pdev; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 91 | |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 92 | u32 errata; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 93 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
| 94 | int context_valid; |
| 95 | |
| 96 | /* Registers to be saved/restored for OFF-mode */ |
| 97 | u16 dll; |
| 98 | u16 dlh; |
| 99 | u16 ier; |
| 100 | u16 sysc; |
| 101 | u16 scr; |
| 102 | u16 wer; |
Govindraj R | 5ade4ff | 2010-08-02 13:18:11 +0300 | [diff] [blame] | 103 | u16 mcr; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 104 | #endif |
| 105 | }; |
| 106 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 107 | static LIST_HEAD(uart_list); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 108 | static u8 num_uarts; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 109 | |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 110 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 111 | int offset) |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 112 | { |
| 113 | offset <<= up->regshift; |
| 114 | return (unsigned int)__raw_readb(up->membase + offset); |
| 115 | } |
| 116 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 117 | static inline unsigned int serial_read_reg(struct omap_uart_state *uart, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 118 | int offset) |
| 119 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 120 | offset <<= uart->regshift; |
| 121 | return (unsigned int)__raw_readb(uart->membase + offset); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 122 | } |
| 123 | |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 124 | static inline void __serial_write_reg(struct uart_port *up, int offset, |
| 125 | int value) |
| 126 | { |
| 127 | offset <<= up->regshift; |
| 128 | __raw_writeb(value, up->membase + offset); |
| 129 | } |
| 130 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 131 | static inline void serial_write_reg(struct omap_uart_state *uart, int offset, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 132 | int value) |
| 133 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 134 | offset <<= uart->regshift; |
| 135 | __raw_writeb(value, uart->membase + offset); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | /* |
| 139 | * Internal UARTs need to be initialized for the 8250 autoconfig to work |
| 140 | * properly. Note that the TX watermark initialization may not be needed |
| 141 | * once the 8250.c watermark handling code is merged. |
| 142 | */ |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 143 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 144 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 145 | { |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 146 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 147 | serial_write_reg(uart, UART_OMAP_SCR, 0x08); |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 148 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 149 | } |
| 150 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 151 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
| 152 | |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 153 | /* |
| 154 | * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) |
| 155 | * The access to uart register after MDR1 Access |
| 156 | * causes UART to corrupt data. |
| 157 | * |
| 158 | * Need a delay = |
| 159 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) |
| 160 | * give 10 times as much |
| 161 | */ |
| 162 | static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, |
| 163 | u8 fcr_val) |
| 164 | { |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 165 | u8 timeout = 255; |
| 166 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 167 | serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 168 | udelay(2); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 169 | serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 170 | UART_FCR_CLEAR_RCVR); |
| 171 | /* |
| 172 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and |
| 173 | * TX_FIFO_E bit is 1. |
| 174 | */ |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 175 | while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 176 | (UART_LSR_THRE | UART_LSR_DR))) { |
| 177 | timeout--; |
| 178 | if (!timeout) { |
| 179 | /* Should *never* happen. we warn and carry on */ |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 180 | dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", |
| 181 | serial_read_reg(uart, UART_LSR)); |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 182 | break; |
| 183 | } |
| 184 | udelay(1); |
| 185 | } |
| 186 | } |
| 187 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 188 | static void omap_uart_save_context(struct omap_uart_state *uart) |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 189 | { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 190 | u16 lcr = 0; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 191 | |
| 192 | if (!enable_off_mode) |
| 193 | return; |
| 194 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 195 | lcr = serial_read_reg(uart, UART_LCR); |
Andrei Emeltchenko | 662b083a | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 196 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 197 | uart->dll = serial_read_reg(uart, UART_DLL); |
| 198 | uart->dlh = serial_read_reg(uart, UART_DLM); |
| 199 | serial_write_reg(uart, UART_LCR, lcr); |
| 200 | uart->ier = serial_read_reg(uart, UART_IER); |
| 201 | uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); |
| 202 | uart->scr = serial_read_reg(uart, UART_OMAP_SCR); |
| 203 | uart->wer = serial_read_reg(uart, UART_OMAP_WER); |
Andrei Emeltchenko | 662b083a | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 204 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 205 | uart->mcr = serial_read_reg(uart, UART_MCR); |
| 206 | serial_write_reg(uart, UART_LCR, lcr); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 207 | |
| 208 | uart->context_valid = 1; |
| 209 | } |
| 210 | |
| 211 | static void omap_uart_restore_context(struct omap_uart_state *uart) |
| 212 | { |
| 213 | u16 efr = 0; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 214 | |
| 215 | if (!enable_off_mode) |
| 216 | return; |
| 217 | |
| 218 | if (!uart->context_valid) |
| 219 | return; |
| 220 | |
| 221 | uart->context_valid = 0; |
| 222 | |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 223 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 224 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 225 | else |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 226 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
| 227 | |
Andrei Emeltchenko | 662b083a | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 228 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 229 | efr = serial_read_reg(uart, UART_EFR); |
| 230 | serial_write_reg(uart, UART_EFR, UART_EFR_ECB); |
| 231 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ |
| 232 | serial_write_reg(uart, UART_IER, 0x0); |
Andrei Emeltchenko | 662b083a | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 233 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 234 | serial_write_reg(uart, UART_DLL, uart->dll); |
| 235 | serial_write_reg(uart, UART_DLM, uart->dlh); |
| 236 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ |
| 237 | serial_write_reg(uart, UART_IER, uart->ier); |
Andrei Emeltchenko | 662b083a | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 238 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 239 | serial_write_reg(uart, UART_MCR, uart->mcr); |
Andrei Emeltchenko | 662b083a | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 240 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 241 | serial_write_reg(uart, UART_EFR, efr); |
| 242 | serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); |
| 243 | serial_write_reg(uart, UART_OMAP_SCR, uart->scr); |
| 244 | serial_write_reg(uart, UART_OMAP_WER, uart->wer); |
| 245 | serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 246 | |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 247 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 248 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 249 | else |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 250 | /* UART 16x mode */ |
Andrei Emeltchenko | 498cb95 | 2010-11-30 14:11:49 -0800 | [diff] [blame] | 251 | serial_write_reg(uart, UART_OMAP_MDR1, |
| 252 | UART_OMAP_MDR1_16X_MODE); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 253 | } |
| 254 | #else |
| 255 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} |
| 256 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} |
| 257 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ |
| 258 | |
| 259 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) |
| 260 | { |
| 261 | if (uart->clocked) |
| 262 | return; |
| 263 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 264 | omap_device_enable(uart->pdev); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 265 | uart->clocked = 1; |
| 266 | omap_uart_restore_context(uart); |
| 267 | } |
| 268 | |
| 269 | #ifdef CONFIG_PM |
| 270 | |
| 271 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) |
| 272 | { |
| 273 | if (!uart->clocked) |
| 274 | return; |
| 275 | |
| 276 | omap_uart_save_context(uart); |
| 277 | uart->clocked = 0; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 278 | omap_device_idle(uart->pdev); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 279 | } |
| 280 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 281 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
| 282 | { |
| 283 | /* Set wake-enable bit */ |
| 284 | if (uart->wk_en && uart->wk_mask) { |
| 285 | u32 v = __raw_readl(uart->wk_en); |
| 286 | v |= uart->wk_mask; |
| 287 | __raw_writel(v, uart->wk_en); |
| 288 | } |
| 289 | |
| 290 | /* Ensure IOPAD wake-enables are set */ |
| 291 | if (cpu_is_omap34xx() && uart->padconf) { |
| 292 | u16 v = omap_ctrl_readw(uart->padconf); |
| 293 | v |= OMAP3_PADCONF_WAKEUPENABLE0; |
| 294 | omap_ctrl_writew(v, uart->padconf); |
| 295 | } |
| 296 | } |
| 297 | |
| 298 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) |
| 299 | { |
| 300 | /* Clear wake-enable bit */ |
| 301 | if (uart->wk_en && uart->wk_mask) { |
| 302 | u32 v = __raw_readl(uart->wk_en); |
| 303 | v &= ~uart->wk_mask; |
| 304 | __raw_writel(v, uart->wk_en); |
| 305 | } |
| 306 | |
| 307 | /* Ensure IOPAD wake-enables are cleared */ |
| 308 | if (cpu_is_omap34xx() && uart->padconf) { |
| 309 | u16 v = omap_ctrl_readw(uart->padconf); |
| 310 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; |
| 311 | omap_ctrl_writew(v, uart->padconf); |
| 312 | } |
| 313 | } |
| 314 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 315 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 316 | int enable) |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 317 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 318 | u8 idlemode; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 319 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 320 | if (enable) { |
| 321 | /** |
| 322 | * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests |
| 323 | * in Smartidle Mode When Configured for DMA Operations. |
| 324 | */ |
| 325 | if (uart->dma_enabled) |
| 326 | idlemode = HWMOD_IDLEMODE_FORCE; |
| 327 | else |
| 328 | idlemode = HWMOD_IDLEMODE_SMART; |
| 329 | } else { |
| 330 | idlemode = HWMOD_IDLEMODE_NO; |
| 331 | } |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 332 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 333 | omap_hwmod_set_slave_idlemode(uart->oh, idlemode); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static void omap_uart_block_sleep(struct omap_uart_state *uart) |
| 337 | { |
| 338 | omap_uart_enable_clocks(uart); |
| 339 | |
| 340 | omap_uart_smart_idle_enable(uart, 0); |
| 341 | uart->can_sleep = 0; |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 342 | if (uart->timeout) |
| 343 | mod_timer(&uart->timer, jiffies + uart->timeout); |
| 344 | else |
| 345 | del_timer(&uart->timer); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) |
| 349 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 350 | if (device_may_wakeup(&uart->pdev->dev)) |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 351 | omap_uart_enable_wakeup(uart); |
| 352 | else |
| 353 | omap_uart_disable_wakeup(uart); |
| 354 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 355 | if (!uart->clocked) |
| 356 | return; |
| 357 | |
| 358 | omap_uart_smart_idle_enable(uart, 1); |
| 359 | uart->can_sleep = 1; |
| 360 | del_timer(&uart->timer); |
| 361 | } |
| 362 | |
| 363 | static void omap_uart_idle_timer(unsigned long data) |
| 364 | { |
| 365 | struct omap_uart_state *uart = (struct omap_uart_state *)data; |
| 366 | |
| 367 | omap_uart_allow_sleep(uart); |
| 368 | } |
| 369 | |
| 370 | void omap_uart_prepare_idle(int num) |
| 371 | { |
| 372 | struct omap_uart_state *uart; |
| 373 | |
| 374 | list_for_each_entry(uart, &uart_list, node) { |
| 375 | if (num == uart->num && uart->can_sleep) { |
| 376 | omap_uart_disable_clocks(uart); |
| 377 | return; |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 378 | } |
| 379 | } |
| 380 | } |
| 381 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 382 | void omap_uart_resume_idle(int num) |
| 383 | { |
| 384 | struct omap_uart_state *uart; |
| 385 | |
| 386 | list_for_each_entry(uart, &uart_list, node) { |
Kevin Hilman | f910043 | 2010-11-24 11:09:03 -0800 | [diff] [blame] | 387 | if (num == uart->num && uart->can_sleep) { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 388 | omap_uart_enable_clocks(uart); |
| 389 | |
| 390 | /* Check for IO pad wakeup */ |
| 391 | if (cpu_is_omap34xx() && uart->padconf) { |
| 392 | u16 p = omap_ctrl_readw(uart->padconf); |
| 393 | |
| 394 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) |
| 395 | omap_uart_block_sleep(uart); |
| 396 | } |
| 397 | |
| 398 | /* Check for normal UART wakeup */ |
| 399 | if (__raw_readl(uart->wk_st) & uart->wk_mask) |
| 400 | omap_uart_block_sleep(uart); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 401 | return; |
| 402 | } |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | void omap_uart_prepare_suspend(void) |
| 407 | { |
| 408 | struct omap_uart_state *uart; |
| 409 | |
| 410 | list_for_each_entry(uart, &uart_list, node) { |
| 411 | omap_uart_allow_sleep(uart); |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | int omap_uart_can_sleep(void) |
| 416 | { |
| 417 | struct omap_uart_state *uart; |
| 418 | int can_sleep = 1; |
| 419 | |
| 420 | list_for_each_entry(uart, &uart_list, node) { |
| 421 | if (!uart->clocked) |
| 422 | continue; |
| 423 | |
| 424 | if (!uart->can_sleep) { |
| 425 | can_sleep = 0; |
| 426 | continue; |
| 427 | } |
| 428 | |
| 429 | /* This UART can now safely sleep. */ |
| 430 | omap_uart_allow_sleep(uart); |
| 431 | } |
| 432 | |
| 433 | return can_sleep; |
| 434 | } |
| 435 | |
| 436 | /** |
| 437 | * omap_uart_interrupt() |
| 438 | * |
| 439 | * This handler is used only to detect that *any* UART interrupt has |
| 440 | * occurred. It does _nothing_ to handle the interrupt. Rather, |
| 441 | * any UART interrupt will trigger the inactivity timer so the |
| 442 | * UART will not idle or sleep for its timeout period. |
| 443 | * |
| 444 | **/ |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 445 | /* static int first_interrupt; */ |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 446 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) |
| 447 | { |
| 448 | struct omap_uart_state *uart = dev_id; |
| 449 | |
| 450 | omap_uart_block_sleep(uart); |
| 451 | |
| 452 | return IRQ_NONE; |
| 453 | } |
| 454 | |
| 455 | static void omap_uart_idle_init(struct omap_uart_state *uart) |
| 456 | { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 457 | int ret; |
| 458 | |
| 459 | uart->can_sleep = 0; |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 460 | uart->timeout = DEFAULT_TIMEOUT; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 461 | setup_timer(&uart->timer, omap_uart_idle_timer, |
| 462 | (unsigned long) uart); |
Tony Lindgren | 301fe8e | 2010-02-01 12:34:31 -0800 | [diff] [blame] | 463 | if (uart->timeout) |
| 464 | mod_timer(&uart->timer, jiffies + uart->timeout); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 465 | omap_uart_smart_idle_enable(uart, 0); |
| 466 | |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 467 | if (cpu_is_omap34xx() && !cpu_is_ti816x()) { |
Govindraj.R | 52663ae | 2010-09-27 20:20:41 +0530 | [diff] [blame] | 468 | u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 469 | u32 wk_mask = 0; |
| 470 | u32 padconf = 0; |
| 471 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 472 | /* XXX These PRM accesses do not belong here */ |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 473 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); |
| 474 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); |
| 475 | switch (uart->num) { |
| 476 | case 0: |
| 477 | wk_mask = OMAP3430_ST_UART1_MASK; |
| 478 | padconf = 0x182; |
| 479 | break; |
| 480 | case 1: |
| 481 | wk_mask = OMAP3430_ST_UART2_MASK; |
| 482 | padconf = 0x17a; |
| 483 | break; |
| 484 | case 2: |
| 485 | wk_mask = OMAP3430_ST_UART3_MASK; |
| 486 | padconf = 0x19e; |
| 487 | break; |
Govindraj.R | 52663ae | 2010-09-27 20:20:41 +0530 | [diff] [blame] | 488 | case 3: |
| 489 | wk_mask = OMAP3630_ST_UART4_MASK; |
| 490 | padconf = 0x0d2; |
| 491 | break; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 492 | } |
| 493 | uart->wk_mask = wk_mask; |
| 494 | uart->padconf = padconf; |
| 495 | } else if (cpu_is_omap24xx()) { |
| 496 | u32 wk_mask = 0; |
Kevin Hilman | cb74f02 | 2010-10-20 23:19:03 +0000 | [diff] [blame] | 497 | u32 wk_en = PM_WKEN1, wk_st = PM_WKST1; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 498 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 499 | switch (uart->num) { |
| 500 | case 0: |
| 501 | wk_mask = OMAP24XX_ST_UART1_MASK; |
| 502 | break; |
| 503 | case 1: |
| 504 | wk_mask = OMAP24XX_ST_UART2_MASK; |
| 505 | break; |
| 506 | case 2: |
Kevin Hilman | cb74f02 | 2010-10-20 23:19:03 +0000 | [diff] [blame] | 507 | wk_en = OMAP24XX_PM_WKEN2; |
| 508 | wk_st = OMAP24XX_PM_WKST2; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 509 | wk_mask = OMAP24XX_ST_UART3_MASK; |
| 510 | break; |
| 511 | } |
| 512 | uart->wk_mask = wk_mask; |
Kevin Hilman | cb74f02 | 2010-10-20 23:19:03 +0000 | [diff] [blame] | 513 | if (cpu_is_omap2430()) { |
| 514 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); |
| 515 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); |
| 516 | } else if (cpu_is_omap2420()) { |
| 517 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); |
| 518 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); |
| 519 | } |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 520 | } else { |
Nishanth Menon | c54bae1 | 2010-08-02 13:18:11 +0300 | [diff] [blame] | 521 | uart->wk_en = NULL; |
| 522 | uart->wk_st = NULL; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 523 | uart->wk_mask = 0; |
| 524 | uart->padconf = 0; |
| 525 | } |
| 526 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 527 | uart->irqflags |= IRQF_SHARED; |
| 528 | ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, |
| 529 | IRQF_SHARED, "serial idle", (void *)uart); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 530 | WARN_ON(ret); |
| 531 | } |
| 532 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 533 | void omap_uart_enable_irqs(int enable) |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 534 | { |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 535 | int ret; |
| 536 | struct omap_uart_state *uart; |
| 537 | |
| 538 | list_for_each_entry(uart, &uart_list, node) { |
Kevin Hilman | 3244fcd | 2010-09-27 20:19:53 +0530 | [diff] [blame] | 539 | if (enable) { |
| 540 | pm_runtime_put_sync(&uart->pdev->dev); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 541 | ret = request_threaded_irq(uart->irq, NULL, |
| 542 | omap_uart_interrupt, |
| 543 | IRQF_SHARED, |
| 544 | "serial idle", |
| 545 | (void *)uart); |
Kevin Hilman | 3244fcd | 2010-09-27 20:19:53 +0530 | [diff] [blame] | 546 | } else { |
| 547 | pm_runtime_get_noresume(&uart->pdev->dev); |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 548 | free_irq(uart->irq, (void *)uart); |
Kevin Hilman | 3244fcd | 2010-09-27 20:19:53 +0530 | [diff] [blame] | 549 | } |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 550 | } |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 551 | } |
| 552 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 553 | static ssize_t sleep_timeout_show(struct device *dev, |
| 554 | struct device_attribute *attr, |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 555 | char *buf) |
| 556 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 557 | struct platform_device *pdev = to_platform_device(dev); |
| 558 | struct omap_device *odev = to_omap_device(pdev); |
| 559 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 560 | |
| 561 | return sprintf(buf, "%u\n", uart->timeout / HZ); |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 562 | } |
| 563 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 564 | static ssize_t sleep_timeout_store(struct device *dev, |
| 565 | struct device_attribute *attr, |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 566 | const char *buf, size_t n) |
| 567 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 568 | struct platform_device *pdev = to_platform_device(dev); |
| 569 | struct omap_device *odev = to_omap_device(pdev); |
| 570 | struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 571 | unsigned int value; |
| 572 | |
| 573 | if (sscanf(buf, "%u", &value) != 1) { |
Sergio Aguirre | 10c805e | 2010-03-09 13:22:14 -0600 | [diff] [blame] | 574 | dev_err(dev, "sleep_timeout_store: Invalid value\n"); |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 575 | return -EINVAL; |
| 576 | } |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 577 | |
| 578 | uart->timeout = value * HZ; |
| 579 | if (uart->timeout) |
| 580 | mod_timer(&uart->timer, jiffies + uart->timeout); |
| 581 | else |
| 582 | /* A zero value means disable timeout feature */ |
| 583 | omap_uart_block_sleep(uart); |
| 584 | |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 585 | return n; |
| 586 | } |
| 587 | |
Nishanth Menon | bfe6977 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 588 | static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, |
| 589 | sleep_timeout_store); |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 590 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 591 | #else |
| 592 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} |
Santosh Shilimkar | a1b04cc | 2010-10-11 11:05:18 +0000 | [diff] [blame] | 593 | static void omap_uart_block_sleep(struct omap_uart_state *uart) |
| 594 | { |
| 595 | /* Needed to enable UART clocks when built without CONFIG_PM */ |
| 596 | omap_uart_enable_clocks(uart); |
| 597 | } |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 598 | #define DEV_CREATE_FILE(dev, attr) |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 599 | #endif /* CONFIG_PM */ |
| 600 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 601 | #ifndef CONFIG_SERIAL_OMAP |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 602 | /* |
| 603 | * Override the default 8250 read handler: mem_serial_in() |
| 604 | * Empty RX fifo read causes an abort on omap3630 and omap4 |
| 605 | * This function makes sure that an empty rx fifo is not read on these silicons |
| 606 | * (OMAP1/2/3430 are not affected) |
| 607 | */ |
| 608 | static unsigned int serial_in_override(struct uart_port *up, int offset) |
| 609 | { |
| 610 | if (UART_RX == offset) { |
| 611 | unsigned int lsr; |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 612 | lsr = __serial_read_reg(up, UART_LSR); |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 613 | if (!(lsr & UART_LSR_DR)) |
| 614 | return -EPERM; |
| 615 | } |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 616 | |
| 617 | return __serial_read_reg(up, offset); |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 618 | } |
| 619 | |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 620 | static void serial_out_override(struct uart_port *up, int offset, int value) |
| 621 | { |
| 622 | unsigned int status, tmout = 10000; |
| 623 | |
| 624 | status = __serial_read_reg(up, UART_LSR); |
| 625 | while (!(status & UART_LSR_THRE)) { |
| 626 | /* Wait up to 10ms for the character(s) to be sent. */ |
| 627 | if (--tmout == 0) |
| 628 | break; |
| 629 | udelay(1); |
| 630 | status = __serial_read_reg(up, UART_LSR); |
| 631 | } |
| 632 | __serial_write_reg(up, offset, value); |
| 633 | } |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 634 | #endif |
| 635 | |
Tony Lindgren | 3e16f92 | 2011-02-14 15:40:20 -0800 | [diff] [blame] | 636 | static int __init omap_serial_early_init(void) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 637 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 638 | int i = 0; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 639 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 640 | do { |
| 641 | char oh_name[MAX_UART_HWMOD_NAME_LEN]; |
| 642 | struct omap_hwmod *oh; |
| 643 | struct omap_uart_state *uart; |
Thomas Weber | 21b9034 | 2010-02-25 09:40:19 +0000 | [diff] [blame] | 644 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 645 | snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, |
| 646 | "uart%d", i + 1); |
| 647 | oh = omap_hwmod_lookup(oh_name); |
| 648 | if (!oh) |
| 649 | break; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 650 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 651 | uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); |
| 652 | if (WARN_ON(!uart)) |
Tony Lindgren | 3e16f92 | 2011-02-14 15:40:20 -0800 | [diff] [blame] | 653 | return -ENODEV; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 654 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 655 | uart->oh = oh; |
| 656 | uart->num = i++; |
| 657 | list_add_tail(&uart->node, &uart_list); |
| 658 | num_uarts++; |
| 659 | |
Tony Lindgren | 84f90c9 | 2009-10-16 09:53:00 -0700 | [diff] [blame] | 660 | /* |
Paul Walmsley | 550c809 | 2011-02-28 11:58:14 -0700 | [diff] [blame] | 661 | * NOTE: omap_hwmod_setup*() has not yet been called, |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 662 | * so no hwmod functions will work yet. |
Tony Lindgren | 84f90c9 | 2009-10-16 09:53:00 -0700 | [diff] [blame] | 663 | */ |
Tony Lindgren | 84f90c9 | 2009-10-16 09:53:00 -0700 | [diff] [blame] | 664 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 665 | /* |
| 666 | * During UART early init, device need to be probed |
| 667 | * to determine SoC specific init before omap_device |
| 668 | * is ready. Therefore, don't allow idle here |
| 669 | */ |
| 670 | uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; |
| 671 | } while (1); |
Tony Lindgren | 3e16f92 | 2011-02-14 15:40:20 -0800 | [diff] [blame] | 672 | |
| 673 | return 0; |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 674 | } |
Tony Lindgren | 3e16f92 | 2011-02-14 15:40:20 -0800 | [diff] [blame] | 675 | core_initcall(omap_serial_early_init); |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 676 | |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 677 | /** |
| 678 | * omap_serial_init_port() - initialize single serial port |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 679 | * @bdata: port specific board data pointer |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 680 | * |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 681 | * This function initialies serial driver for given port only. |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 682 | * Platforms can call this function instead of omap_serial_init() |
| 683 | * if they don't plan to use all available UARTs as serial ports. |
| 684 | * |
| 685 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), |
| 686 | * use only one of the two. |
| 687 | */ |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 688 | void __init omap_serial_init_port(struct omap_board_data *bdata) |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 689 | { |
| 690 | struct omap_uart_state *uart; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 691 | struct omap_hwmod *oh; |
Kevin Hilman | 3528c58 | 2011-07-21 13:48:45 -0700 | [diff] [blame] | 692 | struct platform_device *pdev; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 693 | void *pdata = NULL; |
| 694 | u32 pdata_size = 0; |
| 695 | char *name; |
| 696 | #ifndef CONFIG_SERIAL_OMAP |
| 697 | struct plat_serial8250_port ports[2] = { |
| 698 | {}, |
| 699 | {.flags = 0}, |
| 700 | }; |
| 701 | struct plat_serial8250_port *p = &ports[0]; |
| 702 | #else |
| 703 | struct omap_uart_port_info omap_up; |
| 704 | #endif |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 705 | |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 706 | if (WARN_ON(!bdata)) |
Sergio Aguirre | e88d556 | 2010-02-27 14:13:43 -0600 | [diff] [blame] | 707 | return; |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 708 | if (WARN_ON(bdata->id < 0)) |
| 709 | return; |
| 710 | if (WARN_ON(bdata->id >= num_uarts)) |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 711 | return; |
| 712 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 713 | list_for_each_entry(uart, &uart_list, node) |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 714 | if (bdata->id == uart->num) |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 715 | break; |
| 716 | |
| 717 | oh = uart->oh; |
| 718 | uart->dma_enabled = 0; |
| 719 | #ifndef CONFIG_SERIAL_OMAP |
| 720 | name = "serial8250"; |
| 721 | |
| 722 | /* |
| 723 | * !! 8250 driver does not use standard IORESOURCE* It |
| 724 | * has it's own custom pdata that can be taken from |
| 725 | * the hwmod resource data. But, this needs to be |
| 726 | * done after the build. |
| 727 | * |
| 728 | * ?? does it have to be done before the register ?? |
| 729 | * YES, because platform_device_data_add() copies |
| 730 | * pdata, it does not use a pointer. |
| 731 | */ |
| 732 | p->flags = UPF_BOOT_AUTOCONF; |
| 733 | p->iotype = UPIO_MEM; |
| 734 | p->regshift = 2; |
| 735 | p->uartclk = OMAP24XX_BASE_BAUD * 16; |
| 736 | p->irq = oh->mpu_irqs[0].irq; |
| 737 | p->mapbase = oh->slaves[0]->addr->pa_start; |
| 738 | p->membase = omap_hwmod_get_mpu_rt_va(oh); |
| 739 | p->irqflags = IRQF_SHARED; |
| 740 | p->private_data = uart; |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 741 | |
vikram pandita | 30e53bc | 2010-02-15 10:03:33 -0800 | [diff] [blame] | 742 | /* |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 743 | * omap44xx, ti816x: Never read empty UART fifo |
vikram pandita | 30e53bc | 2010-02-15 10:03:33 -0800 | [diff] [blame] | 744 | * omap3xxx: Never read empty UART fifo on UARTs |
| 745 | * with IP rev >=0x52 |
| 746 | */ |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 747 | uart->regshift = p->regshift; |
| 748 | uart->membase = p->membase; |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 749 | if (cpu_is_omap44xx() || cpu_is_ti816x()) |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 750 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 751 | else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 752 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) |
| 753 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
| 754 | |
| 755 | if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 756 | p->serial_in = serial_in_override; |
| 757 | p->serial_out = serial_out_override; |
| 758 | } |
| 759 | |
| 760 | pdata = &ports[0]; |
| 761 | pdata_size = 2 * sizeof(struct plat_serial8250_port); |
| 762 | #else |
| 763 | |
| 764 | name = DRIVER_NAME; |
| 765 | |
| 766 | omap_up.dma_enabled = uart->dma_enabled; |
| 767 | omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; |
| 768 | omap_up.mapbase = oh->slaves[0]->addr->pa_start; |
| 769 | omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); |
| 770 | omap_up.irqflags = IRQF_SHARED; |
| 771 | omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; |
| 772 | |
| 773 | pdata = &omap_up; |
| 774 | pdata_size = sizeof(struct omap_uart_port_info); |
| 775 | #endif |
| 776 | |
| 777 | if (WARN_ON(!oh)) |
| 778 | return; |
| 779 | |
Kevin Hilman | 3528c58 | 2011-07-21 13:48:45 -0700 | [diff] [blame] | 780 | pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, |
Benoit Cousson | f718e2c | 2011-08-10 15:30:09 +0200 | [diff] [blame^] | 781 | NULL, 0, false); |
Kevin Hilman | 3528c58 | 2011-07-21 13:48:45 -0700 | [diff] [blame] | 782 | WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 783 | name, oh->name); |
| 784 | |
Kevin Hilman | 9f8b694 | 2011-08-01 09:33:13 -0700 | [diff] [blame] | 785 | omap_device_disable_idle_on_suspend(pdev); |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 786 | oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); |
| 787 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 788 | uart->irq = oh->mpu_irqs[0].irq; |
| 789 | uart->regshift = 2; |
| 790 | uart->mapbase = oh->slaves[0]->addr->pa_start; |
| 791 | uart->membase = omap_hwmod_get_mpu_rt_va(oh); |
Kevin Hilman | 3528c58 | 2011-07-21 13:48:45 -0700 | [diff] [blame] | 792 | uart->pdev = pdev; |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 793 | |
| 794 | oh->dev_attr = uart; |
| 795 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 796 | console_lock(); /* in case the earlycon is on the UART */ |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 797 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 798 | /* |
| 799 | * Because of early UART probing, UART did not get idled |
| 800 | * on init. Now that omap_device is ready, ensure full idle |
| 801 | * before doing omap_device_enable(). |
| 802 | */ |
| 803 | omap_hwmod_idle(uart->oh); |
| 804 | |
| 805 | omap_device_enable(uart->pdev); |
| 806 | omap_uart_idle_init(uart); |
| 807 | omap_uart_reset(uart); |
| 808 | omap_hwmod_enable_wakeup(uart->oh); |
| 809 | omap_device_idle(uart->pdev); |
| 810 | |
| 811 | /* |
| 812 | * Need to block sleep long enough for interrupt driven |
| 813 | * driver to start. Console driver is in polling mode |
| 814 | * so device needs to be kept enabled while polling driver |
| 815 | * is in use. |
| 816 | */ |
| 817 | if (uart->timeout) |
| 818 | uart->timeout = (30 * HZ); |
| 819 | omap_uart_block_sleep(uart); |
| 820 | uart->timeout = DEFAULT_TIMEOUT; |
| 821 | |
Torben Hohn | ac751ef | 2011-01-25 15:07:35 -0800 | [diff] [blame] | 822 | console_unlock(); |
Paul Walmsley | 0d8e2d0 | 2010-11-24 16:49:05 -0700 | [diff] [blame] | 823 | |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 824 | if ((cpu_is_omap34xx() && uart->padconf) || |
| 825 | (uart->wk_en && uart->wk_mask)) { |
Kevin Hilman | 3528c58 | 2011-07-21 13:48:45 -0700 | [diff] [blame] | 826 | device_init_wakeup(&pdev->dev, true); |
| 827 | DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout); |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 828 | } |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 829 | |
| 830 | /* Enable the MDR1 errata for OMAP3 */ |
Hemant Pedanekar | 0100171 | 2011-02-16 08:31:39 -0800 | [diff] [blame] | 831 | if (cpu_is_omap34xx() && !cpu_is_ti816x()) |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 832 | uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 833 | } |
| 834 | |
| 835 | /** |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 836 | * omap_serial_init() - initialize all supported serial ports |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 837 | * |
| 838 | * Initializes all available UARTs as serial ports. Platforms |
| 839 | * can call this function when they want to have default behaviour |
| 840 | * for serial ports (e.g initialize them all as serial ports). |
| 841 | */ |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 842 | void __init omap_serial_init(void) |
| 843 | { |
Kevin Hilman | 6f251e9 | 2010-09-27 20:19:38 +0530 | [diff] [blame] | 844 | struct omap_uart_state *uart; |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 845 | struct omap_board_data bdata; |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 846 | |
Tony Lindgren | 40e4439 | 2010-12-22 18:42:35 -0800 | [diff] [blame] | 847 | list_for_each_entry(uart, &uart_list, node) { |
| 848 | bdata.id = uart->num; |
| 849 | bdata.flags = 0; |
| 850 | bdata.pads = NULL; |
| 851 | bdata.pads_cnt = 0; |
| 852 | omap_serial_init_port(&bdata); |
| 853 | |
| 854 | } |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 855 | } |