Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/clk.h> |
| 21 | #include <linux/iopoll.h> |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 22 | #include <linux/regulator/consumer.h> |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 23 | |
| 24 | #include <mach/rpm-regulator-smd.h> |
| 25 | #include <mach/socinfo.h> |
| 26 | #include <mach/rpm-smd.h> |
| 27 | |
| 28 | #include "clock-local2.h" |
| 29 | #include "clock-pll.h" |
| 30 | #include "clock-rpm.h" |
| 31 | #include "clock-voter.h" |
| 32 | #include "clock.h" |
| 33 | |
| 34 | enum { |
| 35 | GCC_BASE, |
| 36 | MMSS_BASE, |
| 37 | LPASS_BASE, |
| 38 | APCS_BASE, |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 39 | APCS_PLL_BASE, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 40 | N_BASES, |
| 41 | }; |
| 42 | |
| 43 | static void __iomem *virt_bases[N_BASES]; |
| 44 | |
| 45 | #define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x)) |
| 46 | #define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x)) |
| 47 | #define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x)) |
| 48 | #define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x)) |
| 49 | |
| 50 | #define GPLL0_MODE 0x0000 |
| 51 | #define GPLL0_L_VAL 0x0004 |
| 52 | #define GPLL0_M_VAL 0x0008 |
| 53 | #define GPLL0_N_VAL 0x000C |
| 54 | #define GPLL0_USER_CTL 0x0010 |
| 55 | #define GPLL0_STATUS 0x001C |
| 56 | #define GPLL2_MODE 0x0080 |
| 57 | #define GPLL2_L_VAL 0x0084 |
| 58 | #define GPLL2_M_VAL 0x0088 |
| 59 | #define GPLL2_N_VAL 0x008C |
| 60 | #define GPLL2_USER_CTL 0x0090 |
| 61 | #define GPLL2_STATUS 0x009C |
| 62 | #define CONFIG_NOC_BCR 0x0140 |
| 63 | #define MMSS_BCR 0x0240 |
| 64 | #define MMSS_NOC_CFG_AHB_CBCR 0x024C |
| 65 | #define MSS_CFG_AHB_CBCR 0x0280 |
| 66 | #define MSS_Q6_BIMC_AXI_CBCR 0x0284 |
| 67 | #define USB_HS_BCR 0x0480 |
| 68 | #define USB_HS_SYSTEM_CBCR 0x0484 |
| 69 | #define USB_HS_AHB_CBCR 0x0488 |
| 70 | #define USB_HS_SYSTEM_CMD_RCGR 0x0490 |
| 71 | #define USB2A_PHY_BCR 0x04A8 |
| 72 | #define USB2A_PHY_SLEEP_CBCR 0x04AC |
| 73 | #define SDCC1_BCR 0x04C0 |
| 74 | #define SDCC1_APPS_CMD_RCGR 0x04D0 |
| 75 | #define SDCC1_APPS_CBCR 0x04C4 |
| 76 | #define SDCC1_AHB_CBCR 0x04C8 |
| 77 | #define SDCC2_BCR 0x0500 |
| 78 | #define SDCC2_APPS_CMD_RCGR 0x0510 |
| 79 | #define SDCC2_APPS_CBCR 0x0504 |
| 80 | #define SDCC2_AHB_CBCR 0x0508 |
| 81 | #define BLSP1_BCR 0x05C0 |
| 82 | #define BLSP1_AHB_CBCR 0x05C4 |
| 83 | #define BLSP1_QUP1_BCR 0x0640 |
| 84 | #define BLSP1_QUP1_SPI_APPS_CBCR 0x0644 |
| 85 | #define BLSP1_QUP1_I2C_APPS_CBCR 0x0648 |
| 86 | #define BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x064C |
| 87 | #define BLSP1_UART1_BCR 0x0680 |
| 88 | #define BLSP1_UART1_APPS_CBCR 0x0684 |
| 89 | #define BLSP1_UART1_SIM_CBCR 0x0688 |
| 90 | #define BLSP1_UART1_APPS_CMD_RCGR 0x068C |
| 91 | #define BLSP1_QUP2_BCR 0x06C0 |
| 92 | #define BLSP1_QUP2_SPI_APPS_CBCR 0x06C4 |
| 93 | #define BLSP1_QUP2_I2C_APPS_CBCR 0x06C8 |
| 94 | #define BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x06CC |
| 95 | #define BLSP1_UART2_BCR 0x0700 |
| 96 | #define BLSP1_UART2_APPS_CBCR 0x0704 |
| 97 | #define BLSP1_UART2_SIM_CBCR 0x0708 |
| 98 | #define BLSP1_UART2_APPS_CMD_RCGR 0x070C |
| 99 | #define BLSP1_QUP3_BCR 0x0740 |
| 100 | #define BLSP1_QUP3_SPI_APPS_CBCR 0x0744 |
| 101 | #define BLSP1_QUP3_I2C_APPS_CBCR 0x0748 |
| 102 | #define BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x074C |
| 103 | #define BLSP1_UART3_BCR 0x0780 |
| 104 | #define BLSP1_UART3_APPS_CBCR 0x0784 |
| 105 | #define BLSP1_UART3_SIM_CBCR 0x0788 |
| 106 | #define BLSP1_UART3_APPS_CMD_RCGR 0x078C |
| 107 | #define BLSP1_QUP4_BCR 0x07C0 |
| 108 | #define BLSP1_QUP4_SPI_APPS_CBCR 0x07C4 |
| 109 | #define BLSP1_QUP4_I2C_APPS_CBCR 0x07C8 |
| 110 | #define BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x07CC |
| 111 | #define BLSP1_UART4_BCR 0x0800 |
| 112 | #define BLSP1_UART4_APPS_CBCR 0x0804 |
| 113 | #define BLSP1_UART4_SIM_CBCR 0x0808 |
| 114 | #define BLSP1_UART4_APPS_CMD_RCGR 0x080C |
| 115 | #define BLSP1_QUP5_BCR 0x0840 |
| 116 | #define BLSP1_QUP5_SPI_APPS_CBCR 0x0844 |
| 117 | #define BLSP1_QUP5_I2C_APPS_CBCR 0x0848 |
| 118 | #define BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x084C |
| 119 | #define BLSP1_UART5_BCR 0x0880 |
| 120 | #define BLSP1_UART5_APPS_CBCR 0x0884 |
| 121 | #define BLSP1_UART5_SIM_CBCR 0x0888 |
| 122 | #define BLSP1_UART5_APPS_CMD_RCGR 0x088C |
| 123 | #define BLSP1_QUP6_BCR 0x08C0 |
| 124 | #define BLSP1_QUP6_SPI_APPS_CBCR 0x08C4 |
| 125 | #define BLSP1_QUP6_I2C_APPS_CBCR 0x08C8 |
| 126 | #define BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x08CC |
| 127 | #define BLSP1_UART6_BCR 0x0900 |
| 128 | #define BLSP1_UART6_APPS_CBCR 0x0904 |
| 129 | #define BLSP1_UART6_SIM_CBCR 0x0908 |
| 130 | #define BLSP1_UART6_APPS_CMD_RCGR 0x090C |
| 131 | #define PDM_BCR 0x0CC0 |
| 132 | #define PDM_AHB_CBCR 0x0CC4 |
| 133 | #define PDM2_CBCR 0x0CCC |
| 134 | #define PDM2_CMD_RCGR 0x0CD0 |
| 135 | #define PRNG_BCR 0x0D00 |
| 136 | #define PRNG_AHB_CBCR 0x0D04 |
| 137 | #define BOOT_ROM_BCR 0x0E00 |
| 138 | #define BOOT_ROM_AHB_CBCR 0x0E04 |
| 139 | #define CE1_BCR 0x1040 |
| 140 | #define CE1_CMD_RCGR 0x1050 |
| 141 | #define CE1_CBCR 0x1044 |
| 142 | #define CE1_AXI_CBCR 0x1048 |
| 143 | #define CE1_AHB_CBCR 0x104C |
| 144 | #define COPSS_SMMU_AHB_CBCR 0x015C |
| 145 | #define LPSS_SMMU_AHB_CBCR 0x0158 |
| 146 | #define LPASS_Q6_AXI_CBCR 0x11C0 |
| 147 | #define APCS_GPLL_ENA_VOTE 0x1480 |
| 148 | #define APCS_CLOCK_BRANCH_ENA_VOTE 0x1484 |
| 149 | #define APCS_CLOCK_SLEEP_ENA_VOTE 0x1488 |
| 150 | #define GP1_CBCR 0x1900 |
| 151 | #define GP1_CMD_RCGR 0x1904 |
| 152 | #define GP2_CBCR 0x1940 |
| 153 | #define GP2_CMD_RCGR 0x1944 |
| 154 | #define GP3_CBCR 0x1980 |
| 155 | #define GP3_CMD_RCGR 0x1984 |
| 156 | #define XO_CBCR 0x0034 |
| 157 | |
| 158 | #define MMPLL0_PLL_MODE 0x0000 |
| 159 | #define MMPLL0_PLL_L_VAL 0x0004 |
| 160 | #define MMPLL0_PLL_M_VAL 0x0008 |
| 161 | #define MMPLL0_PLL_N_VAL 0x000C |
| 162 | #define MMPLL0_PLL_USER_CTL 0x0010 |
| 163 | #define MMPLL0_PLL_STATUS 0x001C |
| 164 | #define MMSS_PLL_VOTE_APCS_REG 0x0100 |
| 165 | #define MMPLL1_PLL_MODE 0x4100 |
| 166 | #define MMPLL1_PLL_L_VAL 0x4104 |
| 167 | #define MMPLL1_PLL_M_VAL 0x4108 |
| 168 | #define MMPLL1_PLL_N_VAL 0x410C |
| 169 | #define MMPLL1_PLL_USER_CTL 0x4110 |
| 170 | #define MMPLL1_PLL_STATUS 0x411C |
| 171 | #define DSI_PCLK_CMD_RCGR 0x2000 |
| 172 | #define DSI_CMD_RCGR 0x2020 |
| 173 | #define MDP_VSYNC_CMD_RCGR 0x2080 |
| 174 | #define DSI_BYTE_CMD_RCGR 0x2120 |
| 175 | #define DSI_ESC_CMD_RCGR 0x2160 |
| 176 | #define DSI_BCR 0x2200 |
| 177 | #define DSI_BYTE_BCR 0x2204 |
| 178 | #define DSI_ESC_BCR 0x2208 |
| 179 | #define DSI_AHB_BCR 0x220C |
| 180 | #define DSI_PCLK_BCR 0x2214 |
| 181 | #define MDP_LCDC_BCR 0x2218 |
| 182 | #define MDP_DSI_BCR 0x221C |
| 183 | #define MDP_VSYNC_BCR 0x2220 |
| 184 | #define MDP_AXI_BCR 0x2224 |
| 185 | #define MDP_AHB_BCR 0x2228 |
| 186 | #define MDP_AXI_CBCR 0x2314 |
| 187 | #define MDP_VSYNC_CBCR 0x231C |
| 188 | #define MDP_AHB_CBCR 0x2318 |
| 189 | #define DSI_PCLK_CBCR 0x233C |
| 190 | #define GMEM_GFX3D_CBCR 0x4038 |
| 191 | #define MDP_LCDC_CBCR 0x2340 |
| 192 | #define MDP_DSI_CBCR 0x2320 |
| 193 | #define DSI_CBCR 0x2324 |
| 194 | #define DSI_BYTE_CBCR 0x2328 |
| 195 | #define DSI_ESC_CBCR 0x232C |
| 196 | #define DSI_AHB_CBCR 0x2330 |
| 197 | #define CSI0PHYTIMER_CMD_RCGR 0x3000 |
| 198 | #define CSI0PHYTIMER_BCR 0x3020 |
| 199 | #define CSI0PHYTIMER_CBCR 0x3024 |
| 200 | #define CSI1PHYTIMER_CMD_RCGR 0x3030 |
| 201 | #define CSI1PHYTIMER_BCR 0x3050 |
| 202 | #define CSI1PHYTIMER_CBCR 0x3054 |
| 203 | #define CSI0_CMD_RCGR 0x3090 |
| 204 | #define CSI0_BCR 0x30B0 |
| 205 | #define CSI0_CBCR 0x30B4 |
| 206 | #define CSI_AHB_BCR 0x30B8 |
| 207 | #define CSI_AHB_CBCR 0x30BC |
| 208 | #define CSI0PHY_BCR 0x30C0 |
| 209 | #define CSI0PHY_CBCR 0x30C4 |
| 210 | #define CSI0RDI_BCR 0x30D0 |
| 211 | #define CSI0RDI_CBCR 0x30D4 |
| 212 | #define CSI0PIX_BCR 0x30E0 |
| 213 | #define CSI0PIX_CBCR 0x30E4 |
| 214 | #define CSI1_CMD_RCGR 0x3100 |
| 215 | #define CSI1_BCR 0x3120 |
| 216 | #define CSI1_CBCR 0x3124 |
| 217 | #define CSI1PHY_BCR 0x3130 |
| 218 | #define CSI1PHY_CBCR 0x3134 |
| 219 | #define CSI1RDI_BCR 0x3140 |
| 220 | #define CSI1RDI_CBCR 0x3144 |
| 221 | #define CSI1PIX_BCR 0x3150 |
| 222 | #define CSI1PIX_CBCR 0x3154 |
| 223 | #define MCLK0_CMD_RCGR 0x3360 |
| 224 | #define MCLK0_BCR 0x3380 |
| 225 | #define MCLK0_CBCR 0x3384 |
| 226 | #define MCLK1_CMD_RCGR 0x3390 |
| 227 | #define MCLK1_BCR 0x33B0 |
| 228 | #define MCLK1_CBCR 0x33B4 |
| 229 | #define VFE_CMD_RCGR 0x3600 |
| 230 | #define VFE_BCR 0x36A0 |
| 231 | #define VFE_AHB_BCR 0x36AC |
| 232 | #define VFE_AXI_BCR 0x36B0 |
| 233 | #define VFE_CBCR 0x36A8 |
| 234 | #define VFE_AHB_CBCR 0x36B8 |
| 235 | #define VFE_AXI_CBCR 0x36BC |
| 236 | #define CSI_VFE_BCR 0x3700 |
| 237 | #define CSI_VFE_CBCR 0x3704 |
| 238 | #define GFX3D_CMD_RCGR 0x4000 |
| 239 | #define OXILI_GFX3D_CBCR 0x4028 |
| 240 | #define OXILI_GFX3D_BCR 0x4030 |
| 241 | #define OXILI_AHB_BCR 0x4044 |
| 242 | #define OXILI_AHB_CBCR 0x403C |
| 243 | #define AHB_CMD_RCGR 0x5000 |
| 244 | #define MMSSNOCAHB_BCR 0x5020 |
| 245 | #define MMSSNOCAHB_BTO_BCR 0x5030 |
| 246 | #define MMSS_MISC_AHB_BCR 0x5034 |
| 247 | #define MMSS_MMSSNOC_AHB_CBCR 0x5024 |
| 248 | #define MMSS_MMSSNOC_BTO_AHB_CBCR 0x5028 |
| 249 | #define MMSS_MISC_AHB_CBCR 0x502C |
| 250 | #define AXI_CMD_RCGR 0x5040 |
| 251 | #define MMSSNOCAXI_BCR 0x5060 |
| 252 | #define MMSS_S0_AXI_BCR 0x5068 |
| 253 | #define MMSS_S0_AXI_CBCR 0x5064 |
| 254 | #define MMSS_MMSSNOC_AXI_CBCR 0x506C |
| 255 | #define BIMC_GFX_BCR 0x5090 |
| 256 | #define BIMC_GFX_CBCR 0x5094 |
| 257 | |
| 258 | #define AUDIO_CORE_GDSCR 0x7000 |
| 259 | #define SPDM_BCR 0x1000 |
| 260 | #define LPAAUDIO_PLL_MODE 0x0000 |
| 261 | #define LPAAUDIO_PLL_L_VAL 0x0004 |
| 262 | #define LPAAUDIO_PLL_M_VAL 0x0008 |
| 263 | #define LPAAUDIO_PLL_N_VAL 0x000C |
| 264 | #define LPAAUDIO_PLL_USER_CTL 0x0010 |
| 265 | #define LPAAUDIO_PLL_STATUS 0x001C |
| 266 | #define LPAQ6_PLL_MODE 0x1000 |
| 267 | #define LPAQ6_PLL_USER_CTL 0x1010 |
| 268 | #define LPAQ6_PLL_STATUS 0x101C |
| 269 | #define LPA_PLL_VOTE_APPS 0x2000 |
| 270 | #define AUDIO_CORE_BCR_SLP_CBCR 0x4004 |
| 271 | #define Q6SS_BCR_SLP_CBCR 0x6004 |
| 272 | #define AUDIO_CORE_GDSC_XO_CBCR 0x7004 |
| 273 | #define AUDIO_CORE_LPAIF_DMA_CBCR 0x9000 |
| 274 | #define AUDIO_CORE_LPAIF_CSR_CBCR 0x9004 |
| 275 | #define LPAIF_SPKR_CMD_RCGR 0xA000 |
| 276 | #define AUDIO_CORE_LPAIF_CODEC_SPKR_OSR_CBCR 0xA014 |
| 277 | #define AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR 0xA018 |
| 278 | #define AUDIO_CORE_LPAIF_CODEC_SPKR_EBIT_CBCR 0xA01C |
| 279 | #define LPAIF_PRI_CMD_RCGR 0xB000 |
| 280 | #define AUDIO_CORE_LPAIF_PRI_OSR_CBCR 0xB014 |
| 281 | #define AUDIO_CORE_LPAIF_PRI_IBIT_CBCR 0xB018 |
| 282 | #define AUDIO_CORE_LPAIF_PRI_EBIT_CBCR 0xB01C |
| 283 | #define LPAIF_SEC_CMD_RCGR 0xC000 |
| 284 | #define AUDIO_CORE_LPAIF_SEC_OSR_CBCR 0xC014 |
| 285 | #define AUDIO_CORE_LPAIF_SEC_IBIT_CBCR 0xC018 |
| 286 | #define AUDIO_CORE_LPAIF_SEC_EBIT_CBCR 0xC01C |
| 287 | #define LPAIF_TER_CMD_RCGR 0xD000 |
| 288 | #define AUDIO_CORE_LPAIF_TER_OSR_CBCR 0xD014 |
| 289 | #define AUDIO_CORE_LPAIF_TER_IBIT_CBCR 0xD018 |
| 290 | #define AUDIO_CORE_LPAIF_TER_EBIT_CBCR 0xD01C |
| 291 | #define LPAIF_QUAD_CMD_RCGR 0xE000 |
| 292 | #define AUDIO_CORE_LPAIF_QUAD_OSR_CBCR 0xE014 |
| 293 | #define AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR 0xE018 |
| 294 | #define AUDIO_CORE_LPAIF_QUAD_EBIT_CBCR 0xE01C |
| 295 | #define LPAIF_PCM0_CMD_RCGR 0xF000 |
| 296 | #define AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR 0xF014 |
| 297 | #define AUDIO_CORE_LPAIF_PCM0_EBIT_CBCR 0xF018 |
| 298 | #define LPAIF_PCM1_CMD_RCGR 0x10000 |
| 299 | #define AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR 0x10014 |
| 300 | #define AUDIO_CORE_LPAIF_PCM1_EBIT_CBCR 0x10018 |
| 301 | #define SLIMBUS_CMD_RCGR 0x12000 |
| 302 | #define AUDIO_CORE_SLIMBUS_CORE_CBCR 0x12014 |
| 303 | #define LPAIF_PCMOE_CMD_RCGR 0x13000 |
| 304 | #define AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR 0x13014 |
| 305 | #define Q6CORE_CMD_RCGR 0x14000 |
| 306 | #define SLEEP_CMD_RCGR 0x15000 |
| 307 | #define SPDM_CMD_RCGR 0x16000 |
| 308 | #define AUDIO_WRAPPER_SPDM_CBCR 0x16014 |
| 309 | #define XO_CMD_RCGR 0x17000 |
| 310 | #define AHBFABRIC_CMD_RCGR 0x18000 |
| 311 | #define AUDIO_CORE_LPM_CBCR 0x19000 |
| 312 | #define AUDIO_CORE_AVSYNC_CSR_CBCR 0x1A000 |
| 313 | #define AUDIO_CORE_AVSYNC_XO_CBCR 0x1A004 |
| 314 | #define AUDIO_CORE_AVSYNC_BT_XO_CBCR 0x1A008 |
| 315 | #define AUDIO_CORE_AVSYNC_FM_XO_CBCR 0x1A00C |
| 316 | #define AUDIO_CORE_IXFABRIC_CBCR 0x1B000 |
| 317 | #define AUDIO_WRAPPER_EFABRIC_CBCR 0x1B004 |
| 318 | #define AUDIO_CORE_TCM_SLAVE_CBCR 0x1C000 |
| 319 | #define AUDIO_CORE_CSR_CBCR 0x1D000 |
| 320 | #define AUDIO_CORE_DML_CBCR 0x1E000 |
| 321 | #define AUDIO_CORE_SYSNOC_CBCR 0x1F000 |
| 322 | #define AUDIO_WRAPPER_SYSNOC_SWAY_CBCR 0x1F004 |
| 323 | #define AUDIO_CORE_TIMEOUT_CBCR 0x20000 |
| 324 | #define AUDIO_WRAPPER_TIMEOUT_CBCR 0x20004 |
| 325 | #define AUDIO_CORE_SECURITY_CBCR 0x21000 |
| 326 | #define AUDIO_WRAPPER_SECURITY_CBCR 0x21004 |
| 327 | #define Q6SS_AHB_LFABIF_CBCR 0x22000 |
| 328 | #define Q6SS_AHBM_CBCR 0x22004 |
| 329 | #define AUDIO_WRAPPER_LCC_CSR_CBCR 0x23000 |
| 330 | #define AUDIO_WRAPPER_BR_CBCR 0x24000 |
| 331 | #define AUDIO_WRAPPER_SMEM_CBCR 0x25000 |
| 332 | #define Q6SS_XO_CBCR 0x26000 |
| 333 | #define Q6SS_SLP_CBCR 0x26004 |
| 334 | #define LPASS_Q6SS_BCR 0x6000 |
| 335 | #define AUDIO_WRAPPER_STM_XO_CBCR 0x27000 |
| 336 | #define AUDIO_CORE_IXFABRIC_SPDMTM_CSR_CBCR 0x28000 |
| 337 | #define AUDIO_WRAPPER_EFABRIC_SPDMTM_CSR_CBCR 0x28004 |
| 338 | |
| 339 | /* Mux source select values */ |
| 340 | #define gcc_xo_source_val 0 |
| 341 | #define gpll0_source_val 1 |
| 342 | #define gnd_source_val 5 |
| 343 | #define mmpll0_mm_source_val 1 |
| 344 | #define mmpll1_mm_source_val 2 |
| 345 | #define gpll0_mm_source_val 5 |
| 346 | #define gcc_xo_mm_source_val 0 |
| 347 | #define mm_gnd_source_val 6 |
| 348 | #define cxo_lpass_source_val 0 |
| 349 | #define lpapll0_lpass_source_val 1 |
| 350 | #define gpll0_lpass_source_val 5 |
| 351 | #define dsipll_mm_source_val 1 |
| 352 | |
| 353 | #define F(f, s, div, m, n) \ |
| 354 | { \ |
| 355 | .freq_hz = (f), \ |
| 356 | .src_clk = &s##_clk_src.c, \ |
| 357 | .m_val = (m), \ |
| 358 | .n_val = ~((n)-(m)) * !!(n), \ |
| 359 | .d_val = ~(n),\ |
| 360 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 361 | | BVAL(10, 8, s##_source_val), \ |
| 362 | } |
| 363 | |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 364 | #define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \ |
| 365 | { \ |
| 366 | .freq_hz = (f), \ |
| 367 | .l_val = (l), \ |
| 368 | .m_val = (m), \ |
| 369 | .n_val = (n), \ |
| 370 | .pre_div_val = BVAL(12, 12, (pre_div)), \ |
| 371 | .post_div_val = BVAL(9, 8, (post_div)), \ |
| 372 | .vco_val = BVAL(29, 28, (vco)), \ |
| 373 | } |
| 374 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 375 | #define F_MM(f, s, div, m, n) \ |
| 376 | { \ |
| 377 | .freq_hz = (f), \ |
| 378 | .src_clk = &s##_clk_src.c, \ |
| 379 | .m_val = (m), \ |
| 380 | .n_val = ~((n)-(m)) * !!(n), \ |
| 381 | .d_val = ~(n),\ |
| 382 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 383 | | BVAL(10, 8, s##_mm_source_val), \ |
| 384 | } |
| 385 | |
| 386 | #define F_HDMI(f, s, div, m, n) \ |
| 387 | { \ |
| 388 | .freq_hz = (f), \ |
| 389 | .src_clk = &s##_clk_src, \ |
| 390 | .m_val = (m), \ |
| 391 | .n_val = ~((n)-(m)) * !!(n), \ |
| 392 | .d_val = ~(n),\ |
| 393 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 394 | | BVAL(10, 8, s##_mm_source_val), \ |
| 395 | } |
| 396 | |
| 397 | #define F_MDSS(f, s, div, m, n) \ |
| 398 | { \ |
| 399 | .freq_hz = (f), \ |
| 400 | .m_val = (m), \ |
| 401 | .n_val = ~((n)-(m)) * !!(n), \ |
| 402 | .d_val = ~(n),\ |
| 403 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 404 | | BVAL(10, 8, s##_mm_source_val), \ |
| 405 | } |
| 406 | |
| 407 | #define F_LPASS(f, s, div, m, n) \ |
| 408 | { \ |
| 409 | .freq_hz = (f), \ |
| 410 | .src_clk = &s##_clk_src.c, \ |
| 411 | .m_val = (m), \ |
| 412 | .n_val = ~((n)-(m)) * !!(n), \ |
| 413 | .d_val = ~(n),\ |
| 414 | .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \ |
| 415 | | BVAL(10, 8, s##_lpass_source_val), \ |
| 416 | } |
| 417 | |
| 418 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
| 419 | .vdd_class = &vdd_dig, \ |
| 420 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 421 | [VDD_DIG_##l1] = (f1), \ |
| 422 | }, \ |
| 423 | .num_fmax = VDD_DIG_NUM |
| 424 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
| 425 | .vdd_class = &vdd_dig, \ |
| 426 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 427 | [VDD_DIG_##l1] = (f1), \ |
| 428 | [VDD_DIG_##l2] = (f2), \ |
| 429 | }, \ |
| 430 | .num_fmax = VDD_DIG_NUM |
| 431 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
| 432 | .vdd_class = &vdd_dig, \ |
| 433 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 434 | [VDD_DIG_##l1] = (f1), \ |
| 435 | [VDD_DIG_##l2] = (f2), \ |
| 436 | [VDD_DIG_##l3] = (f3), \ |
| 437 | }, \ |
| 438 | .num_fmax = VDD_DIG_NUM |
| 439 | |
| 440 | enum vdd_dig_levels { |
| 441 | VDD_DIG_NONE, |
| 442 | VDD_DIG_LOW, |
| 443 | VDD_DIG_NOMINAL, |
| 444 | VDD_DIG_HIGH, |
| 445 | VDD_DIG_NUM |
| 446 | }; |
| 447 | |
| 448 | static const int vdd_corner[] = { |
| 449 | [VDD_DIG_NONE] = RPM_REGULATOR_CORNER_NONE, |
| 450 | [VDD_DIG_LOW] = RPM_REGULATOR_CORNER_SVS_SOC, |
| 451 | [VDD_DIG_NOMINAL] = RPM_REGULATOR_CORNER_NORMAL, |
| 452 | [VDD_DIG_HIGH] = RPM_REGULATOR_CORNER_SUPER_TURBO, |
| 453 | }; |
| 454 | |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 455 | static struct regulator *vdd_dig_reg; |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 456 | |
| 457 | static int set_vdd_dig(struct clk_vdd_class *vdd_class, int level) |
| 458 | { |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 459 | return regulator_set_voltage(vdd_dig_reg, vdd_corner[level], |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 460 | RPM_REGULATOR_CORNER_SUPER_TURBO); |
| 461 | } |
| 462 | |
| 463 | static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig, VDD_DIG_NUM); |
| 464 | |
| 465 | #define RPM_MISC_CLK_TYPE 0x306b6c63 |
| 466 | #define RPM_BUS_CLK_TYPE 0x316b6c63 |
| 467 | #define RPM_MEM_CLK_TYPE 0x326b6c63 |
| 468 | |
| 469 | #define RPM_SMD_KEY_ENABLE 0x62616E45 |
| 470 | |
| 471 | #define CXO_ID 0x0 |
| 472 | #define QDSS_ID 0x1 |
| 473 | #define RPM_SCALING_ENABLE_ID 0x2 |
| 474 | |
| 475 | #define PNOC_ID 0x0 |
| 476 | #define SNOC_ID 0x1 |
| 477 | #define CNOC_ID 0x2 |
| 478 | #define MMSSNOC_AHB_ID 0x3 |
| 479 | |
| 480 | #define BIMC_ID 0x0 |
| 481 | #define OXILI_ID 0x1 |
| 482 | #define OCMEM_ID 0x2 |
| 483 | |
| 484 | #define D0_ID 1 |
| 485 | #define D1_ID 2 |
| 486 | #define A0_ID 3 |
| 487 | #define A1_ID 4 |
| 488 | #define A2_ID 5 |
| 489 | #define DIFF_CLK_ID 7 |
| 490 | #define DIV_CLK_ID 11 |
| 491 | |
| 492 | DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL); |
| 493 | DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL); |
| 494 | DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL); |
| 495 | DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE, |
| 496 | MMSSNOC_AHB_ID, NULL); |
| 497 | |
| 498 | DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL); |
| 499 | |
| 500 | DEFINE_CLK_RPM_SMD_BRANCH(gcc_xo_clk_src, gcc_xo_a_clk_src, |
| 501 | RPM_MISC_CLK_TYPE, CXO_ID, 19200000); |
| 502 | DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID); |
| 503 | |
| 504 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID); |
| 505 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID); |
| 506 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID); |
| 507 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID); |
| 508 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID); |
| 509 | DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk, div_a_clk, DIV_CLK_ID); |
| 510 | DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID); |
| 511 | |
| 512 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID); |
| 513 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID); |
| 514 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID); |
| 515 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID); |
| 516 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID); |
| 517 | |
| 518 | static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX); |
| 519 | static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX); |
| 520 | static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX); |
| 521 | static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX); |
| 522 | static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX); |
| 523 | static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX); |
| 524 | |
| 525 | static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX); |
| 526 | static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX); |
| 527 | static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX); |
| 528 | |
| 529 | static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX); |
| 530 | static DEFINE_CLK_VOTER(pnoc_iommu_clk, &pnoc_clk.c, LONG_MAX); |
| 531 | static DEFINE_CLK_VOTER(pnoc_qseecom_clk, &pnoc_clk.c, LONG_MAX); |
| 532 | |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 533 | static DEFINE_CLK_MEASURE(apc0_m_clk); |
| 534 | static DEFINE_CLK_MEASURE(apc1_m_clk); |
| 535 | static DEFINE_CLK_MEASURE(apc2_m_clk); |
| 536 | static DEFINE_CLK_MEASURE(apc3_m_clk); |
| 537 | static DEFINE_CLK_MEASURE(l2_m_clk); |
| 538 | |
| 539 | #define APCS_SH_PLL_MODE 0x000 |
| 540 | #define APCS_SH_PLL_L_VAL 0x004 |
| 541 | #define APCS_SH_PLL_M_VAL 0x008 |
| 542 | #define APCS_SH_PLL_N_VAL 0x00C |
| 543 | #define APCS_SH_PLL_USER_CTL 0x010 |
| 544 | #define APCS_SH_PLL_CONFIG_CTL 0x014 |
| 545 | #define APCS_SH_PLL_STATUS 0x01C |
| 546 | |
| 547 | enum vdd_sr2_pll_levels { |
| 548 | VDD_SR2_PLL_OFF, |
| 549 | VDD_SR2_PLL_ON, |
| 550 | VDD_SR2_PLL_NUM |
| 551 | }; |
| 552 | |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 553 | static struct regulator *vdd_sr2_reg; |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 554 | |
| 555 | static int set_vdd_sr2_pll(struct clk_vdd_class *vdd_class, int level) |
| 556 | { |
| 557 | if (level == VDD_SR2_PLL_ON) { |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 558 | return regulator_set_voltage(vdd_sr2_reg, 1800000, |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 559 | 1800000); |
| 560 | } else { |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 561 | return regulator_set_voltage(vdd_sr2_reg, 0, 1800000); |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 562 | } |
| 563 | } |
| 564 | |
| 565 | static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll, |
| 566 | VDD_SR2_PLL_NUM); |
| 567 | |
| 568 | static struct pll_freq_tbl apcs_pll_freq[] = { |
| 569 | F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 570 | F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 571 | F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 572 | F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 573 | PLL_F_END |
| 574 | }; |
| 575 | |
| 576 | static struct pll_clk a7sspll = { |
| 577 | .mode_reg = (void __iomem *)APCS_SH_PLL_MODE, |
| 578 | .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL, |
| 579 | .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL, |
| 580 | .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL, |
| 581 | .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL, |
| 582 | .status_reg = (void __iomem *)APCS_SH_PLL_STATUS, |
| 583 | .freq_tbl = apcs_pll_freq, |
| 584 | .masks = { |
| 585 | .vco_mask = BM(29, 28), |
| 586 | .pre_div_mask = BIT(12), |
| 587 | .post_div_mask = BM(9, 8), |
| 588 | .mn_en_mask = BIT(24), |
| 589 | .main_output_mask = BIT(0), |
| 590 | }, |
| 591 | .base = &virt_bases[APCS_PLL_BASE], |
| 592 | .c = { |
| 593 | .dbg_name = "a7sspll", |
| 594 | .ops = &clk_ops_sr2_pll, |
| 595 | .vdd_class = &vdd_sr2_pll, |
| 596 | .fmax = (unsigned long [VDD_SR2_PLL_NUM]) { |
| 597 | [VDD_SR2_PLL_ON] = ULONG_MAX, |
| 598 | }, |
| 599 | .num_fmax = VDD_SR2_PLL_NUM, |
| 600 | CLK_INIT(a7sspll.c), |
| 601 | /* |
| 602 | * Need to skip handoff of the acpu pll to avoid |
| 603 | * turning off the pll when the cpu is using it |
| 604 | */ |
| 605 | .flags = CLKFLAG_SKIP_HANDOFF, |
| 606 | }, |
| 607 | }; |
| 608 | |
| 609 | static unsigned int soft_vote_gpll0; |
| 610 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 611 | static struct pll_vote_clk gpll0_clk_src = { |
| 612 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE, |
| 613 | .en_mask = BIT(0), |
| 614 | .status_reg = (void __iomem *)GPLL0_STATUS, |
| 615 | .status_mask = BIT(17), |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 616 | .soft_vote = &soft_vote_gpll0, |
| 617 | .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 618 | .base = &virt_bases[GCC_BASE], |
| 619 | .c = { |
| 620 | .parent = &gcc_xo_clk_src.c, |
| 621 | .rate = 600000000, |
| 622 | .dbg_name = "gpll0_clk_src", |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 623 | .ops = &clk_ops_pll_acpu_vote, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 624 | CLK_INIT(gpll0_clk_src.c), |
| 625 | }, |
| 626 | }; |
| 627 | |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 628 | static struct pll_vote_clk gpll0_ao_clk_src = { |
| 629 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE, |
| 630 | .en_mask = BIT(0), |
| 631 | .status_reg = (void __iomem *)GPLL0_STATUS, |
| 632 | .status_mask = BIT(17), |
| 633 | .soft_vote = &soft_vote_gpll0, |
| 634 | .soft_vote_mask = PLL_SOFT_VOTE_ACPU, |
| 635 | .base = &virt_bases[GCC_BASE], |
| 636 | .c = { |
| 637 | .rate = 600000000, |
| 638 | .dbg_name = "gpll0_ao_clk_src", |
| 639 | .ops = &clk_ops_pll_acpu_vote, |
| 640 | CLK_INIT(gpll0_ao_clk_src.c), |
| 641 | }, |
| 642 | }; |
| 643 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 644 | static struct pll_vote_clk mmpll0_clk_src = { |
| 645 | .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS_REG, |
| 646 | .en_mask = BIT(0), |
| 647 | .status_reg = (void __iomem *)MMPLL0_PLL_STATUS, |
| 648 | .status_mask = BIT(17), |
| 649 | .base = &virt_bases[MMSS_BASE], |
| 650 | .c = { |
| 651 | .parent = &gcc_xo_clk_src.c, |
| 652 | .dbg_name = "mmpll0_clk_src", |
| 653 | .rate = 800000000, |
| 654 | .ops = &clk_ops_pll_vote, |
| 655 | CLK_INIT(mmpll0_clk_src.c), |
| 656 | }, |
| 657 | }; |
| 658 | |
| 659 | static struct pll_config_regs mmpll0_regs __initdata = { |
| 660 | .l_reg = (void __iomem *)MMPLL0_PLL_L_VAL, |
| 661 | .m_reg = (void __iomem *)MMPLL0_PLL_M_VAL, |
| 662 | .n_reg = (void __iomem *)MMPLL0_PLL_N_VAL, |
| 663 | .config_reg = (void __iomem *)MMPLL0_PLL_USER_CTL, |
| 664 | .mode_reg = (void __iomem *)MMPLL0_PLL_MODE, |
| 665 | .base = &virt_bases[MMSS_BASE], |
| 666 | }; |
| 667 | |
| 668 | static struct pll_clk mmpll1_clk_src = { |
| 669 | .mode_reg = (void __iomem *)MMPLL1_PLL_MODE, |
| 670 | .status_reg = (void __iomem *)MMPLL1_PLL_STATUS, |
| 671 | .base = &virt_bases[MMSS_BASE], |
| 672 | .c = { |
| 673 | .parent = &gcc_xo_clk_src.c, |
| 674 | .dbg_name = "mmpll1_clk_src", |
| 675 | .rate = 1200000000, |
| 676 | .ops = &clk_ops_local_pll, |
| 677 | CLK_INIT(mmpll1_clk_src.c), |
| 678 | }, |
| 679 | }; |
| 680 | |
| 681 | static struct pll_config_regs mmpll1_regs __initdata = { |
| 682 | .l_reg = (void __iomem *)MMPLL1_PLL_L_VAL, |
| 683 | .m_reg = (void __iomem *)MMPLL1_PLL_M_VAL, |
| 684 | .n_reg = (void __iomem *)MMPLL1_PLL_N_VAL, |
| 685 | .config_reg = (void __iomem *)MMPLL1_PLL_USER_CTL, |
| 686 | .mode_reg = (void __iomem *)MMPLL1_PLL_MODE, |
| 687 | .base = &virt_bases[MMSS_BASE], |
| 688 | }; |
| 689 | |
| 690 | static struct pll_vote_clk lpapll0_clk_src = { |
| 691 | .en_reg = (void __iomem *)LPA_PLL_VOTE_APPS, |
| 692 | .en_mask = BIT(0), |
| 693 | .status_reg = (void __iomem *)LPAAUDIO_PLL_STATUS, |
| 694 | .status_mask = BIT(17), |
| 695 | .base = &virt_bases[LPASS_BASE], |
| 696 | .c = { |
| 697 | .parent = &gcc_xo_clk_src.c, |
| 698 | .rate = 491520000, |
| 699 | .dbg_name = "lpapll0_clk_src", |
| 700 | .ops = &clk_ops_pll_vote, |
| 701 | CLK_INIT(lpapll0_clk_src.c), |
| 702 | }, |
| 703 | }; |
| 704 | |
| 705 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { |
| 706 | F( 960000, gcc_xo, 10, 1, 2), |
| 707 | F( 4800000, gcc_xo, 4, 0, 0), |
| 708 | F( 9600000, gcc_xo, 2, 0, 0), |
| 709 | F(15000000, gpll0, 10, 1, 4), |
| 710 | F(19200000, gcc_xo, 1, 0, 0), |
| 711 | F(25000000, gpll0, 12, 1, 2), |
| 712 | F(50000000, gpll0, 12, 0, 0), |
| 713 | F_END, |
| 714 | }; |
| 715 | |
| 716 | static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { |
| 717 | .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR, |
| 718 | .set_rate = set_rate_mnd, |
| 719 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 720 | .current_freq = &rcg_dummy_freq, |
| 721 | .base = &virt_bases[GCC_BASE], |
| 722 | .c = { |
| 723 | .dbg_name = "blsp1_qup1_spi_apps_clk_src", |
| 724 | .ops = &clk_ops_rcg_mnd, |
| 725 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 726 | CLK_INIT(blsp1_qup1_spi_apps_clk_src.c), |
| 727 | }, |
| 728 | }; |
| 729 | |
| 730 | static struct rcg_clk blsp1_qup2_spi_apps_clk_src = { |
| 731 | .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR, |
| 732 | .set_rate = set_rate_mnd, |
| 733 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 734 | .current_freq = &rcg_dummy_freq, |
| 735 | .base = &virt_bases[GCC_BASE], |
| 736 | .c = { |
| 737 | .dbg_name = "blsp1_qup2_spi_apps_clk_src", |
| 738 | .ops = &clk_ops_rcg_mnd, |
| 739 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 740 | CLK_INIT(blsp1_qup2_spi_apps_clk_src.c), |
| 741 | }, |
| 742 | }; |
| 743 | |
| 744 | static struct rcg_clk blsp1_qup3_spi_apps_clk_src = { |
| 745 | .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR, |
| 746 | .set_rate = set_rate_mnd, |
| 747 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 748 | .current_freq = &rcg_dummy_freq, |
| 749 | .base = &virt_bases[GCC_BASE], |
| 750 | .c = { |
| 751 | .dbg_name = "blsp1_qup3_spi_apps_clk_src", |
| 752 | .ops = &clk_ops_rcg_mnd, |
| 753 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 754 | CLK_INIT(blsp1_qup3_spi_apps_clk_src.c), |
| 755 | }, |
| 756 | }; |
| 757 | |
| 758 | static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { |
| 759 | .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR, |
| 760 | .set_rate = set_rate_mnd, |
| 761 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 762 | .current_freq = &rcg_dummy_freq, |
| 763 | .base = &virt_bases[GCC_BASE], |
| 764 | .c = { |
| 765 | .dbg_name = "blsp1_qup4_spi_apps_clk_src", |
| 766 | .ops = &clk_ops_rcg_mnd, |
| 767 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 768 | CLK_INIT(blsp1_qup4_spi_apps_clk_src.c), |
| 769 | }, |
| 770 | }; |
| 771 | |
| 772 | static struct rcg_clk blsp1_qup5_spi_apps_clk_src = { |
| 773 | .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR, |
| 774 | .set_rate = set_rate_mnd, |
| 775 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 776 | .current_freq = &rcg_dummy_freq, |
| 777 | .base = &virt_bases[GCC_BASE], |
| 778 | .c = { |
| 779 | .dbg_name = "blsp1_qup5_spi_apps_clk_src", |
| 780 | .ops = &clk_ops_rcg_mnd, |
| 781 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 782 | CLK_INIT(blsp1_qup5_spi_apps_clk_src.c), |
| 783 | }, |
| 784 | }; |
| 785 | |
| 786 | static struct rcg_clk blsp1_qup6_spi_apps_clk_src = { |
| 787 | .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR, |
| 788 | .set_rate = set_rate_mnd, |
| 789 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 790 | .current_freq = &rcg_dummy_freq, |
| 791 | .base = &virt_bases[GCC_BASE], |
| 792 | .c = { |
| 793 | .dbg_name = "blsp1_qup6_spi_apps_clk_src", |
| 794 | .ops = &clk_ops_rcg_mnd, |
| 795 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 796 | CLK_INIT(blsp1_qup6_spi_apps_clk_src.c), |
| 797 | }, |
| 798 | }; |
| 799 | |
| 800 | static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { |
| 801 | F( 3686400, gpll0, 1, 96, 15625), |
| 802 | F( 7372800, gpll0, 1, 192, 15625), |
| 803 | F(14745600, gpll0, 1, 384, 15625), |
| 804 | F(16000000, gpll0, 5, 2, 15), |
| 805 | F(19200000, gcc_xo, 1, 0, 0), |
| 806 | F(24000000, gpll0, 5, 1, 5), |
| 807 | F(32000000, gpll0, 1, 4, 75), |
| 808 | F(40000000, gpll0, 15, 0, 0), |
| 809 | F(46400000, gpll0, 1, 29, 375), |
| 810 | F(48000000, gpll0, 12.5, 0, 0), |
| 811 | F(51200000, gpll0, 1, 32, 375), |
| 812 | F(56000000, gpll0, 1, 7, 75), |
| 813 | F(58982400, gpll0, 1, 1536, 15625), |
| 814 | F(60000000, gpll0, 10, 0, 0), |
| 815 | F_END, |
| 816 | }; |
| 817 | |
| 818 | static struct rcg_clk blsp1_uart1_apps_clk_src = { |
| 819 | .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR, |
| 820 | .set_rate = set_rate_mnd, |
| 821 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 822 | .current_freq = &rcg_dummy_freq, |
| 823 | .base = &virt_bases[GCC_BASE], |
| 824 | .c = { |
| 825 | .dbg_name = "blsp1_uart1_apps_clk_src", |
| 826 | .ops = &clk_ops_rcg_mnd, |
| 827 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 828 | CLK_INIT(blsp1_uart1_apps_clk_src.c), |
| 829 | }, |
| 830 | }; |
| 831 | |
| 832 | static struct rcg_clk blsp1_uart2_apps_clk_src = { |
| 833 | .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR, |
| 834 | .set_rate = set_rate_mnd, |
| 835 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 836 | .current_freq = &rcg_dummy_freq, |
| 837 | .base = &virt_bases[GCC_BASE], |
| 838 | .c = { |
| 839 | .dbg_name = "blsp1_uart2_apps_clk_src", |
| 840 | .ops = &clk_ops_rcg_mnd, |
| 841 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 842 | CLK_INIT(blsp1_uart2_apps_clk_src.c), |
| 843 | }, |
| 844 | }; |
| 845 | |
| 846 | static struct rcg_clk blsp1_uart3_apps_clk_src = { |
| 847 | .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR, |
| 848 | .set_rate = set_rate_mnd, |
| 849 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 850 | .current_freq = &rcg_dummy_freq, |
| 851 | .base = &virt_bases[GCC_BASE], |
| 852 | .c = { |
| 853 | .dbg_name = "blsp1_uart3_apps_clk_src", |
| 854 | .ops = &clk_ops_rcg_mnd, |
| 855 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 856 | CLK_INIT(blsp1_uart3_apps_clk_src.c), |
| 857 | }, |
| 858 | }; |
| 859 | |
| 860 | static struct rcg_clk blsp1_uart4_apps_clk_src = { |
| 861 | .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR, |
| 862 | .set_rate = set_rate_mnd, |
| 863 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 864 | .current_freq = &rcg_dummy_freq, |
| 865 | .base = &virt_bases[GCC_BASE], |
| 866 | .c = { |
| 867 | .dbg_name = "blsp1_uart4_apps_clk_src", |
| 868 | .ops = &clk_ops_rcg_mnd, |
| 869 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 870 | CLK_INIT(blsp1_uart4_apps_clk_src.c), |
| 871 | }, |
| 872 | }; |
| 873 | |
| 874 | static struct rcg_clk blsp1_uart5_apps_clk_src = { |
| 875 | .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR, |
| 876 | .set_rate = set_rate_mnd, |
| 877 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 878 | .current_freq = &rcg_dummy_freq, |
| 879 | .base = &virt_bases[GCC_BASE], |
| 880 | .c = { |
| 881 | .dbg_name = "blsp1_uart5_apps_clk_src", |
| 882 | .ops = &clk_ops_rcg_mnd, |
| 883 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 884 | CLK_INIT(blsp1_uart5_apps_clk_src.c), |
| 885 | }, |
| 886 | }; |
| 887 | |
| 888 | static struct rcg_clk blsp1_uart6_apps_clk_src = { |
| 889 | .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR, |
| 890 | .set_rate = set_rate_mnd, |
| 891 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 892 | .current_freq = &rcg_dummy_freq, |
| 893 | .base = &virt_bases[GCC_BASE], |
| 894 | .c = { |
| 895 | .dbg_name = "blsp1_uart6_apps_clk_src", |
| 896 | .ops = &clk_ops_rcg_mnd, |
| 897 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 898 | CLK_INIT(blsp1_uart6_apps_clk_src.c), |
| 899 | }, |
| 900 | }; |
| 901 | |
| 902 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 903 | F(50000000, gpll0, 12, 0, 0), |
| 904 | F(100000000, gpll0, 6, 0, 0), |
| 905 | F_END, |
| 906 | }; |
| 907 | |
| 908 | static struct rcg_clk ce1_clk_src = { |
| 909 | .cmd_rcgr_reg = CE1_CMD_RCGR, |
| 910 | .set_rate = set_rate_hid, |
| 911 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 912 | .current_freq = &rcg_dummy_freq, |
| 913 | .base = &virt_bases[GCC_BASE], |
| 914 | .c = { |
| 915 | .dbg_name = "ce1_clk_src", |
| 916 | .ops = &clk_ops_rcg, |
| 917 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 918 | CLK_INIT(ce1_clk_src.c), |
| 919 | }, |
| 920 | }; |
| 921 | |
| 922 | static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = { |
| 923 | F(19200000, gcc_xo, 1, 0, 0), |
| 924 | F_END, |
| 925 | }; |
| 926 | |
| 927 | static struct rcg_clk gp1_clk_src = { |
| 928 | .cmd_rcgr_reg = GP1_CMD_RCGR, |
| 929 | .set_rate = set_rate_mnd, |
| 930 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
| 931 | .current_freq = &rcg_dummy_freq, |
| 932 | .base = &virt_bases[GCC_BASE], |
| 933 | .c = { |
| 934 | .dbg_name = "gp1_clk_src", |
| 935 | .ops = &clk_ops_rcg_mnd, |
| 936 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 937 | CLK_INIT(gp1_clk_src.c), |
| 938 | }, |
| 939 | }; |
| 940 | |
| 941 | static struct rcg_clk gp2_clk_src = { |
| 942 | .cmd_rcgr_reg = GP2_CMD_RCGR, |
| 943 | .set_rate = set_rate_mnd, |
| 944 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
| 945 | .current_freq = &rcg_dummy_freq, |
| 946 | .base = &virt_bases[GCC_BASE], |
| 947 | .c = { |
| 948 | .dbg_name = "gp2_clk_src", |
| 949 | .ops = &clk_ops_rcg_mnd, |
| 950 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 951 | CLK_INIT(gp2_clk_src.c), |
| 952 | }, |
| 953 | }; |
| 954 | |
| 955 | static struct rcg_clk gp3_clk_src = { |
| 956 | .cmd_rcgr_reg = GP3_CMD_RCGR, |
| 957 | .set_rate = set_rate_mnd, |
| 958 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
| 959 | .current_freq = &rcg_dummy_freq, |
| 960 | .base = &virt_bases[GCC_BASE], |
| 961 | .c = { |
| 962 | .dbg_name = "gp3_clk_src", |
| 963 | .ops = &clk_ops_rcg_mnd, |
| 964 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 965 | CLK_INIT(gp3_clk_src.c), |
| 966 | }, |
| 967 | }; |
| 968 | |
| 969 | static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = { |
| 970 | F(60000000, gpll0, 10, 0, 0), |
| 971 | F_END, |
| 972 | }; |
| 973 | |
| 974 | static struct rcg_clk pdm2_clk_src = { |
| 975 | .cmd_rcgr_reg = PDM2_CMD_RCGR, |
| 976 | .set_rate = set_rate_hid, |
| 977 | .freq_tbl = ftbl_gcc_pdm2_clk, |
| 978 | .current_freq = &rcg_dummy_freq, |
| 979 | .base = &virt_bases[GCC_BASE], |
| 980 | .c = { |
| 981 | .dbg_name = "pdm2_clk_src", |
| 982 | .ops = &clk_ops_rcg, |
| 983 | VDD_DIG_FMAX_MAP1(LOW, 120000000), |
| 984 | CLK_INIT(pdm2_clk_src.c), |
| 985 | }, |
| 986 | }; |
| 987 | |
| 988 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = { |
| 989 | F( 144000, gcc_xo, 16, 3, 25), |
| 990 | F( 400000, gcc_xo, 12, 1, 4), |
| 991 | F( 20000000, gpll0, 15, 1, 2), |
| 992 | F( 25000000, gpll0, 12, 1, 2), |
| 993 | F( 50000000, gpll0, 12, 0, 0), |
| 994 | F(100000000, gpll0, 6, 0, 0), |
| 995 | F(200000000, gpll0, 3, 0, 0), |
| 996 | F_END, |
| 997 | }; |
| 998 | |
| 999 | static struct rcg_clk sdcc1_apps_clk_src = { |
| 1000 | .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR, |
| 1001 | .set_rate = set_rate_mnd, |
| 1002 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 1003 | .current_freq = &rcg_dummy_freq, |
| 1004 | .base = &virt_bases[GCC_BASE], |
| 1005 | .c = { |
| 1006 | .dbg_name = "sdcc1_apps_clk_src", |
| 1007 | .ops = &clk_ops_rcg_mnd, |
| 1008 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1009 | CLK_INIT(sdcc1_apps_clk_src.c), |
| 1010 | }, |
| 1011 | }; |
| 1012 | |
| 1013 | static struct rcg_clk sdcc2_apps_clk_src = { |
| 1014 | .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR, |
| 1015 | .set_rate = set_rate_mnd, |
| 1016 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 1017 | .current_freq = &rcg_dummy_freq, |
| 1018 | .base = &virt_bases[GCC_BASE], |
| 1019 | .c = { |
| 1020 | .dbg_name = "sdcc2_apps_clk_src", |
| 1021 | .ops = &clk_ops_rcg_mnd, |
| 1022 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1023 | CLK_INIT(sdcc2_apps_clk_src.c), |
| 1024 | }, |
| 1025 | }; |
| 1026 | |
| 1027 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
| 1028 | F(75000000, gpll0, 8, 0, 0), |
| 1029 | F_END, |
| 1030 | }; |
| 1031 | |
| 1032 | static struct rcg_clk usb_hs_system_clk_src = { |
| 1033 | .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR, |
| 1034 | .set_rate = set_rate_hid, |
| 1035 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 1036 | .current_freq = &rcg_dummy_freq, |
| 1037 | .base = &virt_bases[GCC_BASE], |
| 1038 | .c = { |
| 1039 | .dbg_name = "usb_hs_system_clk_src", |
| 1040 | .ops = &clk_ops_rcg, |
| 1041 | VDD_DIG_FMAX_MAP2(LOW, 60000000, NOMINAL, 100000000), |
| 1042 | CLK_INIT(usb_hs_system_clk_src.c), |
| 1043 | }, |
| 1044 | }; |
| 1045 | |
| 1046 | static struct local_vote_clk gcc_blsp1_ahb_clk = { |
| 1047 | .cbcr_reg = BLSP1_AHB_CBCR, |
| 1048 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1049 | .en_mask = BIT(17), |
| 1050 | .base = &virt_bases[GCC_BASE], |
| 1051 | .c = { |
| 1052 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 1053 | .ops = &clk_ops_vote, |
| 1054 | CLK_INIT(gcc_blsp1_ahb_clk.c), |
| 1055 | }, |
| 1056 | }; |
| 1057 | |
| 1058 | static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { |
| 1059 | .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR, |
| 1060 | .has_sibling = 1, |
| 1061 | .base = &virt_bases[GCC_BASE], |
| 1062 | .c = { |
| 1063 | .parent = &gcc_xo_clk_src.c, |
| 1064 | .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 1065 | .ops = &clk_ops_branch, |
| 1066 | CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c), |
| 1067 | }, |
| 1068 | }; |
| 1069 | |
| 1070 | static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = { |
| 1071 | .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR, |
| 1072 | .has_sibling = 0, |
| 1073 | .base = &virt_bases[GCC_BASE], |
| 1074 | .c = { |
| 1075 | .parent = &blsp1_qup1_spi_apps_clk_src.c, |
| 1076 | .dbg_name = "gcc_blsp1_qup1_spi_apps_clk", |
| 1077 | .ops = &clk_ops_branch, |
| 1078 | CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c), |
| 1079 | }, |
| 1080 | }; |
| 1081 | |
| 1082 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
| 1083 | .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR, |
| 1084 | .has_sibling = 1, |
| 1085 | .base = &virt_bases[GCC_BASE], |
| 1086 | .c = { |
| 1087 | .parent = &gcc_xo_clk_src.c, |
| 1088 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 1089 | .ops = &clk_ops_branch, |
| 1090 | CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c), |
| 1091 | }, |
| 1092 | }; |
| 1093 | |
| 1094 | static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = { |
| 1095 | .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR, |
| 1096 | .has_sibling = 0, |
| 1097 | .base = &virt_bases[GCC_BASE], |
| 1098 | .c = { |
| 1099 | .parent = &blsp1_qup2_spi_apps_clk_src.c, |
| 1100 | .dbg_name = "gcc_blsp1_qup2_spi_apps_clk", |
| 1101 | .ops = &clk_ops_branch, |
| 1102 | CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c), |
| 1103 | }, |
| 1104 | }; |
| 1105 | |
| 1106 | static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = { |
| 1107 | .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR, |
| 1108 | .has_sibling = 1, |
| 1109 | .base = &virt_bases[GCC_BASE], |
| 1110 | .c = { |
| 1111 | .parent = &gcc_xo_clk_src.c, |
| 1112 | .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 1113 | .ops = &clk_ops_branch, |
| 1114 | CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c), |
| 1115 | }, |
| 1116 | }; |
| 1117 | |
| 1118 | static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = { |
| 1119 | .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR, |
| 1120 | .has_sibling = 0, |
| 1121 | .base = &virt_bases[GCC_BASE], |
| 1122 | .c = { |
| 1123 | .parent = &blsp1_qup3_spi_apps_clk_src.c, |
| 1124 | .dbg_name = "gcc_blsp1_qup3_spi_apps_clk", |
| 1125 | .ops = &clk_ops_branch, |
| 1126 | CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c), |
| 1127 | }, |
| 1128 | }; |
| 1129 | |
| 1130 | static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = { |
| 1131 | .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR, |
| 1132 | .has_sibling = 1, |
| 1133 | .base = &virt_bases[GCC_BASE], |
| 1134 | .c = { |
| 1135 | .parent = &gcc_xo_clk_src.c, |
| 1136 | .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 1137 | .ops = &clk_ops_branch, |
| 1138 | CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c), |
| 1139 | }, |
| 1140 | }; |
| 1141 | |
| 1142 | static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { |
| 1143 | .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR, |
| 1144 | .has_sibling = 0, |
| 1145 | .base = &virt_bases[GCC_BASE], |
| 1146 | .c = { |
| 1147 | .parent = &blsp1_qup4_spi_apps_clk_src.c, |
| 1148 | .dbg_name = "gcc_blsp1_qup4_spi_apps_clk", |
| 1149 | .ops = &clk_ops_branch, |
| 1150 | CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c), |
| 1151 | }, |
| 1152 | }; |
| 1153 | |
| 1154 | static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = { |
| 1155 | .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR, |
| 1156 | .has_sibling = 1, |
| 1157 | .base = &virt_bases[GCC_BASE], |
| 1158 | .c = { |
| 1159 | .parent = &gcc_xo_clk_src.c, |
| 1160 | .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk", |
| 1161 | .ops = &clk_ops_branch, |
| 1162 | CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c), |
| 1163 | }, |
| 1164 | }; |
| 1165 | |
| 1166 | static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = { |
| 1167 | .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR, |
| 1168 | .has_sibling = 0, |
| 1169 | .base = &virt_bases[GCC_BASE], |
| 1170 | .c = { |
| 1171 | .parent = &blsp1_qup5_spi_apps_clk_src.c, |
| 1172 | .dbg_name = "gcc_blsp1_qup5_spi_apps_clk", |
| 1173 | .ops = &clk_ops_branch, |
| 1174 | CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c), |
| 1175 | }, |
| 1176 | }; |
| 1177 | |
| 1178 | static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { |
| 1179 | .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR, |
| 1180 | .has_sibling = 1, |
| 1181 | .base = &virt_bases[GCC_BASE], |
| 1182 | .c = { |
| 1183 | .parent = &gcc_xo_clk_src.c, |
| 1184 | .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", |
| 1185 | .ops = &clk_ops_branch, |
| 1186 | CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), |
| 1187 | }, |
| 1188 | }; |
| 1189 | |
| 1190 | static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = { |
| 1191 | .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR, |
| 1192 | .has_sibling = 0, |
| 1193 | .base = &virt_bases[GCC_BASE], |
| 1194 | .c = { |
| 1195 | .parent = &blsp1_qup6_spi_apps_clk_src.c, |
| 1196 | .dbg_name = "gcc_blsp1_qup6_spi_apps_clk", |
| 1197 | .ops = &clk_ops_branch, |
| 1198 | CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c), |
| 1199 | }, |
| 1200 | }; |
| 1201 | |
| 1202 | static struct branch_clk gcc_blsp1_uart1_apps_clk = { |
| 1203 | .cbcr_reg = BLSP1_UART1_APPS_CBCR, |
| 1204 | .has_sibling = 0, |
| 1205 | .base = &virt_bases[GCC_BASE], |
| 1206 | .c = { |
| 1207 | .parent = &blsp1_uart1_apps_clk_src.c, |
| 1208 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 1209 | .ops = &clk_ops_branch, |
| 1210 | CLK_INIT(gcc_blsp1_uart1_apps_clk.c), |
| 1211 | }, |
| 1212 | }; |
| 1213 | |
| 1214 | static struct branch_clk gcc_blsp1_uart2_apps_clk = { |
| 1215 | .cbcr_reg = BLSP1_UART2_APPS_CBCR, |
| 1216 | .has_sibling = 0, |
| 1217 | .base = &virt_bases[GCC_BASE], |
| 1218 | .c = { |
| 1219 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 1220 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 1221 | .ops = &clk_ops_branch, |
| 1222 | CLK_INIT(gcc_blsp1_uart2_apps_clk.c), |
| 1223 | }, |
| 1224 | }; |
| 1225 | |
| 1226 | static struct branch_clk gcc_blsp1_uart3_apps_clk = { |
| 1227 | .cbcr_reg = BLSP1_UART3_APPS_CBCR, |
| 1228 | .has_sibling = 0, |
| 1229 | .base = &virt_bases[GCC_BASE], |
| 1230 | .c = { |
| 1231 | .parent = &blsp1_uart3_apps_clk_src.c, |
| 1232 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 1233 | .ops = &clk_ops_branch, |
| 1234 | CLK_INIT(gcc_blsp1_uart3_apps_clk.c), |
| 1235 | }, |
| 1236 | }; |
| 1237 | |
| 1238 | static struct branch_clk gcc_blsp1_uart4_apps_clk = { |
| 1239 | .cbcr_reg = BLSP1_UART4_APPS_CBCR, |
| 1240 | .has_sibling = 0, |
| 1241 | .base = &virt_bases[GCC_BASE], |
| 1242 | .c = { |
| 1243 | .parent = &blsp1_uart4_apps_clk_src.c, |
| 1244 | .dbg_name = "gcc_blsp1_uart4_apps_clk", |
| 1245 | .ops = &clk_ops_branch, |
| 1246 | CLK_INIT(gcc_blsp1_uart4_apps_clk.c), |
| 1247 | }, |
| 1248 | }; |
| 1249 | |
| 1250 | static struct branch_clk gcc_blsp1_uart5_apps_clk = { |
| 1251 | .cbcr_reg = BLSP1_UART5_APPS_CBCR, |
| 1252 | .has_sibling = 0, |
| 1253 | .base = &virt_bases[GCC_BASE], |
| 1254 | .c = { |
| 1255 | .parent = &blsp1_uart5_apps_clk_src.c, |
| 1256 | .dbg_name = "gcc_blsp1_uart5_apps_clk", |
| 1257 | .ops = &clk_ops_branch, |
| 1258 | CLK_INIT(gcc_blsp1_uart5_apps_clk.c), |
| 1259 | }, |
| 1260 | }; |
| 1261 | |
| 1262 | static struct branch_clk gcc_blsp1_uart6_apps_clk = { |
| 1263 | .cbcr_reg = BLSP1_UART6_APPS_CBCR, |
| 1264 | .has_sibling = 0, |
| 1265 | .base = &virt_bases[GCC_BASE], |
| 1266 | .c = { |
| 1267 | .parent = &blsp1_uart6_apps_clk_src.c, |
| 1268 | .dbg_name = "gcc_blsp1_uart6_apps_clk", |
| 1269 | .ops = &clk_ops_branch, |
| 1270 | CLK_INIT(gcc_blsp1_uart6_apps_clk.c), |
| 1271 | }, |
| 1272 | }; |
| 1273 | |
| 1274 | static struct local_vote_clk gcc_boot_rom_ahb_clk = { |
| 1275 | .cbcr_reg = BOOT_ROM_AHB_CBCR, |
| 1276 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1277 | .en_mask = BIT(10), |
| 1278 | .base = &virt_bases[GCC_BASE], |
| 1279 | .c = { |
| 1280 | .dbg_name = "gcc_boot_rom_ahb_clk", |
| 1281 | .ops = &clk_ops_vote, |
| 1282 | CLK_INIT(gcc_boot_rom_ahb_clk.c), |
| 1283 | }, |
| 1284 | }; |
| 1285 | |
| 1286 | static struct local_vote_clk gcc_ce1_ahb_clk = { |
| 1287 | .cbcr_reg = CE1_AHB_CBCR, |
| 1288 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1289 | .en_mask = BIT(3), |
| 1290 | .base = &virt_bases[GCC_BASE], |
| 1291 | .c = { |
| 1292 | .dbg_name = "gcc_ce1_ahb_clk", |
| 1293 | .ops = &clk_ops_vote, |
| 1294 | CLK_INIT(gcc_ce1_ahb_clk.c), |
| 1295 | }, |
| 1296 | }; |
| 1297 | |
| 1298 | static struct local_vote_clk gcc_ce1_axi_clk = { |
| 1299 | .cbcr_reg = CE1_AXI_CBCR, |
| 1300 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1301 | .en_mask = BIT(4), |
| 1302 | .base = &virt_bases[GCC_BASE], |
| 1303 | .c = { |
| 1304 | .dbg_name = "gcc_ce1_axi_clk", |
| 1305 | .ops = &clk_ops_vote, |
| 1306 | CLK_INIT(gcc_ce1_axi_clk.c), |
| 1307 | }, |
| 1308 | }; |
| 1309 | |
| 1310 | static struct local_vote_clk gcc_ce1_clk = { |
| 1311 | .cbcr_reg = CE1_CBCR, |
| 1312 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1313 | .en_mask = BIT(5), |
| 1314 | .base = &virt_bases[GCC_BASE], |
| 1315 | .c = { |
| 1316 | .dbg_name = "gcc_ce1_clk", |
| 1317 | .ops = &clk_ops_vote, |
| 1318 | CLK_INIT(gcc_ce1_clk.c), |
| 1319 | }, |
| 1320 | }; |
| 1321 | |
| 1322 | static struct branch_clk gcc_copss_smmu_ahb_clk = { |
| 1323 | .cbcr_reg = COPSS_SMMU_AHB_CBCR, |
| 1324 | .has_sibling = 1, |
| 1325 | .base = &virt_bases[GCC_BASE], |
| 1326 | .c = { |
| 1327 | .dbg_name = "gcc_copss_smmu_ahb_clk", |
| 1328 | .ops = &clk_ops_branch, |
| 1329 | CLK_INIT(gcc_copss_smmu_ahb_clk.c), |
| 1330 | }, |
| 1331 | }; |
| 1332 | |
| 1333 | static struct branch_clk gcc_lpss_smmu_ahb_clk = { |
| 1334 | .cbcr_reg = LPSS_SMMU_AHB_CBCR, |
| 1335 | .has_sibling = 1, |
| 1336 | .base = &virt_bases[GCC_BASE], |
| 1337 | .c = { |
| 1338 | .dbg_name = "gcc_lpss_smmu_ahb_clk", |
| 1339 | .ops = &clk_ops_branch, |
| 1340 | CLK_INIT(gcc_lpss_smmu_ahb_clk.c), |
| 1341 | }, |
| 1342 | }; |
| 1343 | |
| 1344 | static struct branch_clk gcc_gp1_clk = { |
| 1345 | .cbcr_reg = GP1_CBCR, |
| 1346 | .has_sibling = 0, |
| 1347 | .base = &virt_bases[GCC_BASE], |
| 1348 | .c = { |
| 1349 | .parent = &gp1_clk_src.c, |
| 1350 | .dbg_name = "gcc_gp1_clk", |
| 1351 | .ops = &clk_ops_branch, |
| 1352 | CLK_INIT(gcc_gp1_clk.c), |
| 1353 | }, |
| 1354 | }; |
| 1355 | |
| 1356 | static struct branch_clk gcc_gp2_clk = { |
| 1357 | .cbcr_reg = GP2_CBCR, |
| 1358 | .has_sibling = 0, |
| 1359 | .base = &virt_bases[GCC_BASE], |
| 1360 | .c = { |
| 1361 | .parent = &gp2_clk_src.c, |
| 1362 | .dbg_name = "gcc_gp2_clk", |
| 1363 | .ops = &clk_ops_branch, |
| 1364 | CLK_INIT(gcc_gp2_clk.c), |
| 1365 | }, |
| 1366 | }; |
| 1367 | |
| 1368 | static struct branch_clk gcc_gp3_clk = { |
| 1369 | .cbcr_reg = GP3_CBCR, |
| 1370 | .has_sibling = 0, |
| 1371 | .base = &virt_bases[GCC_BASE], |
| 1372 | .c = { |
| 1373 | .parent = &gp3_clk_src.c, |
| 1374 | .dbg_name = "gcc_gp3_clk", |
| 1375 | .ops = &clk_ops_branch, |
| 1376 | CLK_INIT(gcc_gp3_clk.c), |
| 1377 | }, |
| 1378 | }; |
| 1379 | |
| 1380 | static struct branch_clk gcc_lpass_q6_axi_clk = { |
| 1381 | .cbcr_reg = LPASS_Q6_AXI_CBCR, |
| 1382 | .has_sibling = 1, |
| 1383 | .base = &virt_bases[GCC_BASE], |
Vikram Mulukutla | 2dfa8b1 | 2013-01-15 18:17:10 -0800 | [diff] [blame] | 1384 | /* FIXME: Remove this once simulation is fixed. */ |
| 1385 | .halt_check = DELAY, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 1386 | .c = { |
| 1387 | .dbg_name = "gcc_lpass_q6_axi_clk", |
| 1388 | .ops = &clk_ops_branch, |
| 1389 | CLK_INIT(gcc_lpass_q6_axi_clk.c), |
| 1390 | }, |
| 1391 | }; |
| 1392 | |
| 1393 | static struct branch_clk gcc_mmss_noc_cfg_ahb_clk = { |
| 1394 | .cbcr_reg = MMSS_NOC_CFG_AHB_CBCR, |
| 1395 | .has_sibling = 1, |
| 1396 | .base = &virt_bases[GCC_BASE], |
| 1397 | .c = { |
| 1398 | .dbg_name = "gcc_mmss_noc_cfg_ahb_clk", |
| 1399 | .ops = &clk_ops_branch, |
| 1400 | CLK_INIT(gcc_mmss_noc_cfg_ahb_clk.c), |
| 1401 | }, |
| 1402 | }; |
| 1403 | |
| 1404 | static struct branch_clk gcc_mss_cfg_ahb_clk = { |
| 1405 | .cbcr_reg = MSS_CFG_AHB_CBCR, |
| 1406 | .has_sibling = 1, |
| 1407 | .base = &virt_bases[GCC_BASE], |
| 1408 | .c = { |
| 1409 | .dbg_name = "gcc_mss_cfg_ahb_clk", |
| 1410 | .ops = &clk_ops_branch, |
| 1411 | CLK_INIT(gcc_mss_cfg_ahb_clk.c), |
| 1412 | }, |
| 1413 | }; |
| 1414 | |
| 1415 | static struct branch_clk gcc_mss_q6_bimc_axi_clk = { |
| 1416 | .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR, |
| 1417 | .has_sibling = 1, |
| 1418 | .base = &virt_bases[GCC_BASE], |
| 1419 | .c = { |
| 1420 | .dbg_name = "gcc_mss_q6_bimc_axi_clk", |
| 1421 | .ops = &clk_ops_branch, |
| 1422 | CLK_INIT(gcc_mss_q6_bimc_axi_clk.c), |
| 1423 | }, |
| 1424 | }; |
| 1425 | |
| 1426 | static struct branch_clk gcc_pdm2_clk = { |
| 1427 | .cbcr_reg = PDM2_CBCR, |
| 1428 | .has_sibling = 0, |
| 1429 | .base = &virt_bases[GCC_BASE], |
| 1430 | .c = { |
| 1431 | .parent = &pdm2_clk_src.c, |
| 1432 | .dbg_name = "gcc_pdm2_clk", |
| 1433 | .ops = &clk_ops_branch, |
| 1434 | CLK_INIT(gcc_pdm2_clk.c), |
| 1435 | }, |
| 1436 | }; |
| 1437 | |
| 1438 | static struct branch_clk gcc_pdm_ahb_clk = { |
| 1439 | .cbcr_reg = PDM_AHB_CBCR, |
| 1440 | .has_sibling = 1, |
| 1441 | .base = &virt_bases[GCC_BASE], |
| 1442 | .c = { |
| 1443 | .dbg_name = "gcc_pdm_ahb_clk", |
| 1444 | .ops = &clk_ops_branch, |
| 1445 | CLK_INIT(gcc_pdm_ahb_clk.c), |
| 1446 | }, |
| 1447 | }; |
| 1448 | |
| 1449 | static struct local_vote_clk gcc_prng_ahb_clk = { |
| 1450 | .cbcr_reg = PRNG_AHB_CBCR, |
| 1451 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1452 | .en_mask = BIT(13), |
| 1453 | .base = &virt_bases[GCC_BASE], |
| 1454 | .c = { |
| 1455 | .dbg_name = "gcc_prng_ahb_clk", |
| 1456 | .ops = &clk_ops_vote, |
| 1457 | CLK_INIT(gcc_prng_ahb_clk.c), |
| 1458 | }, |
| 1459 | }; |
| 1460 | |
| 1461 | static struct branch_clk gcc_sdcc1_ahb_clk = { |
| 1462 | .cbcr_reg = SDCC1_AHB_CBCR, |
| 1463 | .has_sibling = 1, |
| 1464 | .base = &virt_bases[GCC_BASE], |
| 1465 | .c = { |
| 1466 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 1467 | .ops = &clk_ops_branch, |
| 1468 | CLK_INIT(gcc_sdcc1_ahb_clk.c), |
| 1469 | }, |
| 1470 | }; |
| 1471 | |
| 1472 | static struct branch_clk gcc_sdcc1_apps_clk = { |
| 1473 | .cbcr_reg = SDCC1_APPS_CBCR, |
| 1474 | .has_sibling = 0, |
| 1475 | .base = &virt_bases[GCC_BASE], |
| 1476 | .c = { |
| 1477 | .parent = &sdcc1_apps_clk_src.c, |
| 1478 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 1479 | .ops = &clk_ops_branch, |
| 1480 | CLK_INIT(gcc_sdcc1_apps_clk.c), |
| 1481 | }, |
| 1482 | }; |
| 1483 | |
| 1484 | static struct branch_clk gcc_sdcc2_ahb_clk = { |
| 1485 | .cbcr_reg = SDCC2_AHB_CBCR, |
| 1486 | .has_sibling = 1, |
| 1487 | .base = &virt_bases[GCC_BASE], |
| 1488 | .c = { |
| 1489 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 1490 | .ops = &clk_ops_branch, |
| 1491 | CLK_INIT(gcc_sdcc2_ahb_clk.c), |
| 1492 | }, |
| 1493 | }; |
| 1494 | |
| 1495 | static struct branch_clk gcc_sdcc2_apps_clk = { |
| 1496 | .cbcr_reg = SDCC2_APPS_CBCR, |
| 1497 | .has_sibling = 0, |
| 1498 | .base = &virt_bases[GCC_BASE], |
| 1499 | .c = { |
| 1500 | .parent = &sdcc2_apps_clk_src.c, |
| 1501 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 1502 | .ops = &clk_ops_branch, |
| 1503 | CLK_INIT(gcc_sdcc2_apps_clk.c), |
| 1504 | }, |
| 1505 | }; |
| 1506 | |
| 1507 | static struct branch_clk gcc_usb2a_phy_sleep_clk = { |
| 1508 | .cbcr_reg = USB2A_PHY_SLEEP_CBCR, |
| 1509 | .has_sibling = 1, |
| 1510 | .base = &virt_bases[GCC_BASE], |
| 1511 | .c = { |
| 1512 | .dbg_name = "gcc_usb2a_phy_sleep_clk", |
| 1513 | .ops = &clk_ops_branch, |
| 1514 | CLK_INIT(gcc_usb2a_phy_sleep_clk.c), |
| 1515 | }, |
| 1516 | }; |
| 1517 | |
| 1518 | static struct branch_clk gcc_usb_hs_ahb_clk = { |
| 1519 | .cbcr_reg = USB_HS_AHB_CBCR, |
| 1520 | .has_sibling = 1, |
| 1521 | .base = &virt_bases[GCC_BASE], |
| 1522 | .c = { |
| 1523 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 1524 | .ops = &clk_ops_branch, |
| 1525 | CLK_INIT(gcc_usb_hs_ahb_clk.c), |
| 1526 | }, |
| 1527 | }; |
| 1528 | |
| 1529 | static struct branch_clk gcc_usb_hs_system_clk = { |
| 1530 | .cbcr_reg = USB_HS_SYSTEM_CBCR, |
| 1531 | .has_sibling = 0, |
| 1532 | .bcr_reg = USB_HS_BCR, |
| 1533 | .base = &virt_bases[GCC_BASE], |
| 1534 | .c = { |
| 1535 | .parent = &usb_hs_system_clk_src.c, |
| 1536 | .dbg_name = "gcc_usb_hs_system_clk", |
| 1537 | .ops = &clk_ops_branch, |
| 1538 | CLK_INIT(gcc_usb_hs_system_clk.c), |
| 1539 | }, |
| 1540 | }; |
| 1541 | |
| 1542 | static struct clk_freq_tbl ftbl_csi0_1_clk[] = { |
| 1543 | F_MM(100000000, gpll0, 6, 0, 0), |
| 1544 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 1545 | F_END, |
| 1546 | }; |
| 1547 | |
| 1548 | static struct rcg_clk csi0_clk_src = { |
| 1549 | .cmd_rcgr_reg = CSI0_CMD_RCGR, |
| 1550 | .set_rate = set_rate_hid, |
| 1551 | .freq_tbl = ftbl_csi0_1_clk, |
| 1552 | .current_freq = &rcg_dummy_freq, |
| 1553 | .base = &virt_bases[MMSS_BASE], |
| 1554 | .c = { |
| 1555 | .dbg_name = "csi0_clk_src", |
| 1556 | .ops = &clk_ops_rcg, |
| 1557 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1558 | CLK_INIT(csi0_clk_src.c), |
| 1559 | }, |
| 1560 | }; |
| 1561 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 1562 | static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = { |
| 1563 | F_MM( 19200000, gcc_xo, 1, 0, 0), |
| 1564 | F_MM( 37500000, gpll0, 16, 0, 0), |
| 1565 | F_MM( 50000000, gpll0, 12, 0, 0), |
| 1566 | F_MM( 75000000, gpll0, 8, 0, 0), |
| 1567 | F_MM(100000000, gpll0, 6, 0, 0), |
| 1568 | F_MM(150000000, gpll0, 4, 0, 0), |
| 1569 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 1570 | F_END, |
| 1571 | }; |
| 1572 | |
| 1573 | static struct rcg_clk axi_clk_src = { |
| 1574 | .cmd_rcgr_reg = AXI_CMD_RCGR, |
| 1575 | .set_rate = set_rate_hid, |
| 1576 | .freq_tbl = ftbl_mmss_mmssnoc_axi_clk, |
| 1577 | .current_freq = &rcg_dummy_freq, |
| 1578 | .base = &virt_bases[MMSS_BASE], |
| 1579 | .c = { |
| 1580 | .dbg_name = "axi_clk_src", |
| 1581 | .ops = &clk_ops_rcg, |
| 1582 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1583 | CLK_INIT(axi_clk_src.c), |
| 1584 | }, |
| 1585 | }; |
| 1586 | |
Vikram Mulukutla | e1e5c48 | 2013-01-28 14:43:20 -0800 | [diff] [blame] | 1587 | static DEFINE_CLK_VOTER(mdp_axi_clk_src, &axi_clk_src.c, 200000000); |
| 1588 | static DEFINE_CLK_VOTER(mmssnoc_axi_clk_src, &axi_clk_src.c, 200000000); |
| 1589 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 1590 | static struct clk_freq_tbl ftbl_dsi_pclk_clk[] = { |
| 1591 | F_MDSS( 50000000, dsipll, 10, 0, 0), |
| 1592 | F_MDSS(103330000, dsipll, 9, 0, 0), |
| 1593 | F_END, |
| 1594 | }; |
| 1595 | |
| 1596 | static struct rcg_clk dsi_pclk_clk_src = { |
| 1597 | .cmd_rcgr_reg = DSI_PCLK_CMD_RCGR, |
| 1598 | .set_rate = set_rate_mnd, |
| 1599 | .freq_tbl = ftbl_dsi_pclk_clk, |
| 1600 | .current_freq = &rcg_dummy_freq, |
| 1601 | .base = &virt_bases[MMSS_BASE], |
| 1602 | .c = { |
| 1603 | .dbg_name = "dsi_pclk_clk_src", |
| 1604 | .ops = &clk_ops_rcg_mnd, |
| 1605 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 103330000), |
| 1606 | CLK_INIT(dsi_pclk_clk_src.c), |
| 1607 | }, |
| 1608 | }; |
| 1609 | |
| 1610 | static struct clk_freq_tbl ftbl_oxili_gfx3d_clk[] = { |
| 1611 | F_MM( 19200000, gcc_xo, 1, 0, 0), |
| 1612 | F_MM( 37500000, gpll0, 16, 0, 0), |
| 1613 | F_MM( 50000000, gpll0, 12, 0, 0), |
| 1614 | F_MM( 75000000, gpll0, 8, 0, 0), |
| 1615 | F_MM(100000000, gpll0, 6, 0, 0), |
| 1616 | F_MM(150000000, gpll0, 4, 0, 0), |
| 1617 | F_MM(200000000, gpll0, 3, 0, 0), |
| 1618 | F_MM(300000000, gpll0, 2, 0, 0), |
| 1619 | F_MM(400000000, mmpll1, 3, 0, 0), |
| 1620 | F_END, |
| 1621 | }; |
| 1622 | |
| 1623 | static struct rcg_clk gfx3d_clk_src = { |
| 1624 | .cmd_rcgr_reg = GFX3D_CMD_RCGR, |
| 1625 | .set_rate = set_rate_hid, |
| 1626 | .freq_tbl = ftbl_oxili_gfx3d_clk, |
| 1627 | .current_freq = &rcg_dummy_freq, |
| 1628 | .base = &virt_bases[MMSS_BASE], |
| 1629 | .c = { |
| 1630 | .dbg_name = "gfx3d_clk_src", |
| 1631 | .ops = &clk_ops_rcg, |
| 1632 | VDD_DIG_FMAX_MAP3(LOW, 150000000, NOMINAL, 300000000, HIGH, |
| 1633 | 400000000), |
| 1634 | CLK_INIT(gfx3d_clk_src.c), |
| 1635 | }, |
| 1636 | }; |
| 1637 | |
| 1638 | static struct clk_freq_tbl ftbl_vfe_clk[] = { |
| 1639 | F_MM( 37500000, gpll0, 16, 0, 0), |
| 1640 | F_MM( 50000000, gpll0, 12, 0, 0), |
| 1641 | F_MM( 60000000, gpll0, 10, 0, 0), |
| 1642 | F_MM( 80000000, gpll0, 7.5, 0, 0), |
| 1643 | F_MM(100000000, gpll0, 6, 0, 0), |
| 1644 | F_MM(109090000, gpll0, 5.5, 0, 0), |
| 1645 | F_MM(133330000, gpll0, 4.5, 0, 0), |
| 1646 | F_MM(200000000, gpll0, 3, 0, 0), |
| 1647 | F_MM(228570000, mmpll0, 3.5, 0, 0), |
| 1648 | F_MM(266670000, mmpll0, 3, 0, 0), |
| 1649 | F_MM(320000000, mmpll0, 2.5, 0, 0), |
| 1650 | F_END, |
| 1651 | }; |
| 1652 | |
| 1653 | static struct rcg_clk vfe_clk_src = { |
| 1654 | .cmd_rcgr_reg = VFE_CMD_RCGR, |
| 1655 | .set_rate = set_rate_hid, |
| 1656 | .freq_tbl = ftbl_vfe_clk, |
| 1657 | .current_freq = &rcg_dummy_freq, |
| 1658 | .base = &virt_bases[MMSS_BASE], |
| 1659 | .c = { |
| 1660 | .dbg_name = "vfe_clk_src", |
| 1661 | .ops = &clk_ops_rcg, |
| 1662 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH, |
| 1663 | 320000000), |
| 1664 | CLK_INIT(vfe_clk_src.c), |
| 1665 | }, |
| 1666 | }; |
| 1667 | |
| 1668 | static struct rcg_clk csi1_clk_src = { |
| 1669 | .cmd_rcgr_reg = CSI1_CMD_RCGR, |
| 1670 | .set_rate = set_rate_hid, |
| 1671 | .freq_tbl = ftbl_csi0_1_clk, |
| 1672 | .current_freq = &rcg_dummy_freq, |
| 1673 | .base = &virt_bases[MMSS_BASE], |
| 1674 | .c = { |
| 1675 | .dbg_name = "csi1_clk_src", |
| 1676 | .ops = &clk_ops_rcg, |
| 1677 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1678 | CLK_INIT(csi1_clk_src.c), |
| 1679 | }, |
| 1680 | }; |
| 1681 | |
| 1682 | static struct clk_freq_tbl ftbl_csi0_1phytimer_clk[] = { |
| 1683 | F_MM(100000000, gpll0, 6, 0, 0), |
| 1684 | F_MM(200000000, mmpll0, 4, 0, 0), |
| 1685 | F_END, |
| 1686 | }; |
| 1687 | |
| 1688 | static struct rcg_clk csi0phytimer_clk_src = { |
| 1689 | .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR, |
| 1690 | .set_rate = set_rate_hid, |
| 1691 | .freq_tbl = ftbl_csi0_1phytimer_clk, |
| 1692 | .current_freq = &rcg_dummy_freq, |
| 1693 | .base = &virt_bases[MMSS_BASE], |
| 1694 | .c = { |
| 1695 | .dbg_name = "csi0phytimer_clk_src", |
| 1696 | .ops = &clk_ops_rcg, |
| 1697 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1698 | CLK_INIT(csi0phytimer_clk_src.c), |
| 1699 | }, |
| 1700 | }; |
| 1701 | |
| 1702 | static struct rcg_clk csi1phytimer_clk_src = { |
| 1703 | .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR, |
| 1704 | .set_rate = set_rate_hid, |
| 1705 | .freq_tbl = ftbl_csi0_1phytimer_clk, |
| 1706 | .current_freq = &rcg_dummy_freq, |
| 1707 | .base = &virt_bases[MMSS_BASE], |
| 1708 | .c = { |
| 1709 | .dbg_name = "csi1phytimer_clk_src", |
| 1710 | .ops = &clk_ops_rcg, |
| 1711 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1712 | CLK_INIT(csi1phytimer_clk_src.c), |
| 1713 | }, |
| 1714 | }; |
| 1715 | |
| 1716 | static struct clk_freq_tbl ftbl_dsi_clk[] = { |
| 1717 | F_MDSS(155000000, dsipll, 6, 0, 0), |
| 1718 | F_MDSS(310000000, dsipll, 3, 0, 0), |
| 1719 | F_END, |
| 1720 | }; |
| 1721 | |
| 1722 | static struct rcg_clk dsi_clk_src = { |
| 1723 | .cmd_rcgr_reg = DSI_CMD_RCGR, |
| 1724 | .set_rate = set_rate_mnd, |
| 1725 | .freq_tbl = ftbl_dsi_clk, |
| 1726 | .current_freq = &rcg_dummy_freq, |
| 1727 | .base = &virt_bases[MMSS_BASE], |
| 1728 | .c = { |
| 1729 | .dbg_name = "dsi_clk_src", |
| 1730 | .ops = &clk_ops_rcg_mnd, |
| 1731 | VDD_DIG_FMAX_MAP2(LOW, 155000000, NOMINAL, 310000000), |
| 1732 | CLK_INIT(dsi_clk_src.c), |
| 1733 | }, |
| 1734 | }; |
| 1735 | |
| 1736 | static struct clk_freq_tbl ftbl_dsi_byte_clk[] = { |
| 1737 | F_MDSS( 62500000, dsipll, 12, 0, 0), |
| 1738 | F_MDSS(125000000, dsipll, 6, 0, 0), |
| 1739 | F_END, |
| 1740 | }; |
| 1741 | |
| 1742 | static struct rcg_clk dsi_byte_clk_src = { |
| 1743 | .cmd_rcgr_reg = DSI_BYTE_CMD_RCGR, |
| 1744 | .set_rate = set_rate_hid, |
| 1745 | .freq_tbl = ftbl_dsi_byte_clk, |
| 1746 | .current_freq = &rcg_dummy_freq, |
| 1747 | .base = &virt_bases[MMSS_BASE], |
| 1748 | .c = { |
| 1749 | .dbg_name = "dsi_byte_clk_src", |
| 1750 | .ops = &clk_ops_rcg, |
| 1751 | VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000), |
| 1752 | CLK_INIT(dsi_byte_clk_src.c), |
| 1753 | }, |
| 1754 | }; |
| 1755 | |
| 1756 | static struct clk_freq_tbl ftbl_dsi_esc_clk[] = { |
| 1757 | F_MM(19200000, gcc_xo, 1, 0, 0), |
| 1758 | F_END, |
| 1759 | }; |
| 1760 | |
| 1761 | static struct rcg_clk dsi_esc_clk_src = { |
| 1762 | .cmd_rcgr_reg = DSI_ESC_CMD_RCGR, |
| 1763 | .set_rate = set_rate_hid, |
| 1764 | .freq_tbl = ftbl_dsi_esc_clk, |
| 1765 | .current_freq = &rcg_dummy_freq, |
| 1766 | .base = &virt_bases[MMSS_BASE], |
| 1767 | .c = { |
| 1768 | .dbg_name = "dsi_esc_clk_src", |
| 1769 | .ops = &clk_ops_rcg, |
| 1770 | VDD_DIG_FMAX_MAP1(LOW, 19200000), |
| 1771 | CLK_INIT(dsi_esc_clk_src.c), |
| 1772 | }, |
| 1773 | }; |
| 1774 | |
| 1775 | static struct clk_freq_tbl ftbl_mclk0_1_clk[] = { |
| 1776 | F_MM(66670000, gpll0, 9, 0, 0), |
| 1777 | F_END, |
| 1778 | }; |
| 1779 | |
| 1780 | static struct rcg_clk mclk0_clk_src = { |
| 1781 | .cmd_rcgr_reg = MCLK0_CMD_RCGR, |
| 1782 | .set_rate = set_rate_mnd, |
| 1783 | .freq_tbl = ftbl_mclk0_1_clk, |
| 1784 | .current_freq = &rcg_dummy_freq, |
| 1785 | .base = &virt_bases[MMSS_BASE], |
| 1786 | .c = { |
| 1787 | .dbg_name = "mclk0_clk_src", |
| 1788 | .ops = &clk_ops_rcg_mnd, |
| 1789 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 1790 | CLK_INIT(mclk0_clk_src.c), |
| 1791 | }, |
| 1792 | }; |
| 1793 | |
| 1794 | static struct rcg_clk mclk1_clk_src = { |
| 1795 | .cmd_rcgr_reg = MCLK1_CMD_RCGR, |
| 1796 | .set_rate = set_rate_mnd, |
| 1797 | .freq_tbl = ftbl_mclk0_1_clk, |
| 1798 | .current_freq = &rcg_dummy_freq, |
| 1799 | .base = &virt_bases[MMSS_BASE], |
| 1800 | .c = { |
| 1801 | .dbg_name = "mclk1_clk_src", |
| 1802 | .ops = &clk_ops_rcg_mnd, |
| 1803 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 1804 | CLK_INIT(mclk1_clk_src.c), |
| 1805 | }, |
| 1806 | }; |
| 1807 | |
| 1808 | static struct clk_freq_tbl ftbl_mdp_vsync_clk[] = { |
| 1809 | F_MM(19200000, gcc_xo, 1, 0, 0), |
| 1810 | F_END, |
| 1811 | }; |
| 1812 | |
| 1813 | static struct rcg_clk mdp_vsync_clk_src = { |
| 1814 | .cmd_rcgr_reg = MDP_VSYNC_CMD_RCGR, |
| 1815 | .set_rate = set_rate_hid, |
| 1816 | .freq_tbl = ftbl_mdp_vsync_clk, |
| 1817 | .current_freq = &rcg_dummy_freq, |
| 1818 | .base = &virt_bases[MMSS_BASE], |
| 1819 | .c = { |
| 1820 | .dbg_name = "mdp_vsync_clk_src", |
| 1821 | .ops = &clk_ops_rcg, |
| 1822 | VDD_DIG_FMAX_MAP1(LOW, 19200000), |
| 1823 | CLK_INIT(mdp_vsync_clk_src.c), |
| 1824 | }, |
| 1825 | }; |
| 1826 | |
| 1827 | static struct branch_clk bimc_gfx_clk = { |
| 1828 | .cbcr_reg = BIMC_GFX_CBCR, |
| 1829 | .has_sibling = 1, |
| 1830 | .base = &virt_bases[MMSS_BASE], |
Vikram Mulukutla | 2dfa8b1 | 2013-01-15 18:17:10 -0800 | [diff] [blame] | 1831 | /* FIXME: Remove this once simulation is fixed. */ |
| 1832 | .halt_check = DELAY, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 1833 | .c = { |
| 1834 | .dbg_name = "bimc_gfx_clk", |
| 1835 | .ops = &clk_ops_branch, |
| 1836 | CLK_INIT(bimc_gfx_clk.c), |
| 1837 | }, |
| 1838 | }; |
| 1839 | |
| 1840 | static struct branch_clk csi0_clk = { |
| 1841 | .cbcr_reg = CSI0_CBCR, |
| 1842 | .has_sibling = 1, |
| 1843 | .base = &virt_bases[MMSS_BASE], |
| 1844 | .c = { |
| 1845 | .parent = &csi0_clk_src.c, |
| 1846 | .dbg_name = "csi0_clk", |
| 1847 | .ops = &clk_ops_branch, |
| 1848 | CLK_INIT(csi0_clk.c), |
| 1849 | }, |
| 1850 | }; |
| 1851 | |
| 1852 | static struct branch_clk csi0phy_clk = { |
| 1853 | .cbcr_reg = CSI0PHY_CBCR, |
| 1854 | .has_sibling = 1, |
| 1855 | .base = &virt_bases[MMSS_BASE], |
| 1856 | .c = { |
| 1857 | .parent = &csi0_clk_src.c, |
| 1858 | .dbg_name = "csi0phy_clk", |
| 1859 | .ops = &clk_ops_branch, |
| 1860 | CLK_INIT(csi0phy_clk.c), |
| 1861 | }, |
| 1862 | }; |
| 1863 | |
| 1864 | static struct branch_clk csi0phytimer_clk = { |
| 1865 | .cbcr_reg = CSI0PHYTIMER_CBCR, |
| 1866 | .has_sibling = 0, |
| 1867 | .base = &virt_bases[MMSS_BASE], |
| 1868 | .c = { |
| 1869 | .parent = &csi0phytimer_clk_src.c, |
| 1870 | .dbg_name = "csi0phytimer_clk", |
| 1871 | .ops = &clk_ops_branch, |
| 1872 | CLK_INIT(csi0phytimer_clk.c), |
| 1873 | }, |
| 1874 | }; |
| 1875 | |
| 1876 | static struct branch_clk csi0pix_clk = { |
| 1877 | .cbcr_reg = CSI0PIX_CBCR, |
| 1878 | .has_sibling = 1, |
| 1879 | .base = &virt_bases[MMSS_BASE], |
| 1880 | .c = { |
| 1881 | .parent = &csi0_clk_src.c, |
| 1882 | .dbg_name = "csi0pix_clk", |
| 1883 | .ops = &clk_ops_branch, |
| 1884 | CLK_INIT(csi0pix_clk.c), |
| 1885 | }, |
| 1886 | }; |
| 1887 | |
| 1888 | static struct branch_clk csi0rdi_clk = { |
| 1889 | .cbcr_reg = CSI0RDI_CBCR, |
| 1890 | .has_sibling = 1, |
| 1891 | .base = &virt_bases[MMSS_BASE], |
| 1892 | .c = { |
| 1893 | .parent = &csi0_clk_src.c, |
| 1894 | .dbg_name = "csi0rdi_clk", |
| 1895 | .ops = &clk_ops_branch, |
| 1896 | CLK_INIT(csi0rdi_clk.c), |
| 1897 | }, |
| 1898 | }; |
| 1899 | |
| 1900 | static struct branch_clk csi1_clk = { |
| 1901 | .cbcr_reg = CSI1_CBCR, |
| 1902 | .has_sibling = 1, |
| 1903 | .base = &virt_bases[MMSS_BASE], |
| 1904 | .c = { |
| 1905 | .parent = &csi1_clk_src.c, |
| 1906 | .dbg_name = "csi1_clk", |
| 1907 | .ops = &clk_ops_branch, |
| 1908 | CLK_INIT(csi1_clk.c), |
| 1909 | }, |
| 1910 | }; |
| 1911 | |
| 1912 | static struct branch_clk csi1phy_clk = { |
| 1913 | .cbcr_reg = CSI1PHY_CBCR, |
| 1914 | .has_sibling = 1, |
| 1915 | .base = &virt_bases[MMSS_BASE], |
| 1916 | .c = { |
| 1917 | .parent = &csi1_clk_src.c, |
| 1918 | .dbg_name = "csi1phy_clk", |
| 1919 | .ops = &clk_ops_branch, |
| 1920 | CLK_INIT(csi1phy_clk.c), |
| 1921 | }, |
| 1922 | }; |
| 1923 | |
| 1924 | static struct branch_clk csi1phytimer_clk = { |
| 1925 | .cbcr_reg = CSI1PHYTIMER_CBCR, |
| 1926 | .has_sibling = 0, |
| 1927 | .base = &virt_bases[MMSS_BASE], |
| 1928 | .c = { |
| 1929 | .parent = &csi1phytimer_clk_src.c, |
| 1930 | .dbg_name = "csi1phytimer_clk", |
| 1931 | .ops = &clk_ops_branch, |
| 1932 | CLK_INIT(csi1phytimer_clk.c), |
| 1933 | }, |
| 1934 | }; |
| 1935 | |
| 1936 | static struct branch_clk csi1pix_clk = { |
| 1937 | .cbcr_reg = CSI1PIX_CBCR, |
| 1938 | .has_sibling = 1, |
| 1939 | .base = &virt_bases[MMSS_BASE], |
| 1940 | .c = { |
Vikram Mulukutla | a1d5c14 | 2013-01-16 10:30:12 -0800 | [diff] [blame] | 1941 | .parent = &csi1_clk_src.c, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 1942 | .dbg_name = "csi1pix_clk", |
| 1943 | .ops = &clk_ops_branch, |
| 1944 | CLK_INIT(csi1pix_clk.c), |
| 1945 | }, |
| 1946 | }; |
| 1947 | |
| 1948 | static struct branch_clk csi1rdi_clk = { |
| 1949 | .cbcr_reg = CSI1RDI_CBCR, |
| 1950 | .has_sibling = 1, |
| 1951 | .base = &virt_bases[MMSS_BASE], |
| 1952 | .c = { |
Vikram Mulukutla | a1d5c14 | 2013-01-16 10:30:12 -0800 | [diff] [blame] | 1953 | .parent = &csi1_clk_src.c, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 1954 | .dbg_name = "csi1rdi_clk", |
| 1955 | .ops = &clk_ops_branch, |
| 1956 | CLK_INIT(csi1rdi_clk.c), |
| 1957 | }, |
| 1958 | }; |
| 1959 | |
| 1960 | static struct branch_clk csi_ahb_clk = { |
| 1961 | .cbcr_reg = CSI_AHB_CBCR, |
| 1962 | .has_sibling = 1, |
| 1963 | .base = &virt_bases[MMSS_BASE], |
| 1964 | .c = { |
| 1965 | .dbg_name = "csi_ahb_clk", |
| 1966 | .ops = &clk_ops_branch, |
| 1967 | CLK_INIT(csi_ahb_clk.c), |
| 1968 | }, |
| 1969 | }; |
| 1970 | |
| 1971 | static struct branch_clk csi_vfe_clk = { |
| 1972 | .cbcr_reg = CSI_VFE_CBCR, |
| 1973 | .has_sibling = 1, |
| 1974 | .base = &virt_bases[MMSS_BASE], |
| 1975 | .c = { |
| 1976 | .parent = &vfe_clk_src.c, |
| 1977 | .dbg_name = "csi_vfe_clk", |
| 1978 | .ops = &clk_ops_branch, |
| 1979 | CLK_INIT(csi_vfe_clk.c), |
| 1980 | }, |
| 1981 | }; |
| 1982 | |
| 1983 | static struct branch_clk dsi_clk = { |
| 1984 | .cbcr_reg = DSI_CBCR, |
| 1985 | .has_sibling = 0, |
| 1986 | .base = &virt_bases[MMSS_BASE], |
| 1987 | .c = { |
| 1988 | .parent = &dsi_clk_src.c, |
| 1989 | .dbg_name = "dsi_clk", |
| 1990 | .ops = &clk_ops_branch, |
| 1991 | CLK_INIT(dsi_clk.c), |
| 1992 | }, |
| 1993 | }; |
| 1994 | |
| 1995 | static struct branch_clk dsi_ahb_clk = { |
| 1996 | .cbcr_reg = DSI_AHB_CBCR, |
| 1997 | .has_sibling = 1, |
| 1998 | .base = &virt_bases[MMSS_BASE], |
| 1999 | .c = { |
| 2000 | .dbg_name = "dsi_ahb_clk", |
| 2001 | .ops = &clk_ops_branch, |
| 2002 | CLK_INIT(dsi_ahb_clk.c), |
| 2003 | }, |
| 2004 | }; |
| 2005 | |
| 2006 | static struct branch_clk dsi_byte_clk = { |
| 2007 | .cbcr_reg = DSI_BYTE_CBCR, |
| 2008 | .has_sibling = 0, |
| 2009 | .base = &virt_bases[MMSS_BASE], |
| 2010 | .c = { |
| 2011 | .parent = &dsi_byte_clk_src.c, |
| 2012 | .dbg_name = "dsi_byte_clk", |
| 2013 | .ops = &clk_ops_branch, |
| 2014 | CLK_INIT(dsi_byte_clk.c), |
| 2015 | }, |
| 2016 | }; |
| 2017 | |
| 2018 | static struct branch_clk dsi_esc_clk = { |
| 2019 | .cbcr_reg = DSI_ESC_CBCR, |
| 2020 | .has_sibling = 0, |
| 2021 | .base = &virt_bases[MMSS_BASE], |
| 2022 | .c = { |
| 2023 | .parent = &dsi_esc_clk_src.c, |
| 2024 | .dbg_name = "dsi_esc_clk", |
| 2025 | .ops = &clk_ops_branch, |
| 2026 | CLK_INIT(dsi_esc_clk.c), |
| 2027 | }, |
| 2028 | }; |
| 2029 | |
| 2030 | static struct branch_clk dsi_pclk_clk = { |
| 2031 | .cbcr_reg = DSI_PCLK_CBCR, |
| 2032 | .has_sibling = 1, |
| 2033 | .base = &virt_bases[MMSS_BASE], |
| 2034 | .c = { |
| 2035 | .parent = &dsi_pclk_clk_src.c, |
| 2036 | .dbg_name = "dsi_pclk_clk", |
| 2037 | .ops = &clk_ops_branch, |
| 2038 | CLK_INIT(dsi_pclk_clk.c), |
| 2039 | }, |
| 2040 | }; |
| 2041 | |
| 2042 | static struct branch_clk gmem_gfx3d_clk = { |
| 2043 | .cbcr_reg = GMEM_GFX3D_CBCR, |
| 2044 | .has_sibling = 1, |
| 2045 | .base = &virt_bases[MMSS_BASE], |
| 2046 | .c = { |
| 2047 | .parent = &gfx3d_clk_src.c, |
| 2048 | .dbg_name = "gmem_gfx3d_clk", |
| 2049 | .ops = &clk_ops_branch, |
| 2050 | CLK_INIT(gmem_gfx3d_clk.c), |
| 2051 | }, |
| 2052 | }; |
| 2053 | |
| 2054 | static struct branch_clk mclk0_clk = { |
| 2055 | .cbcr_reg = MCLK0_CBCR, |
| 2056 | .has_sibling = 0, |
| 2057 | .base = &virt_bases[MMSS_BASE], |
| 2058 | .c = { |
| 2059 | .parent = &mclk0_clk_src.c, |
| 2060 | .dbg_name = "mclk0_clk", |
| 2061 | .ops = &clk_ops_branch, |
| 2062 | CLK_INIT(mclk0_clk.c), |
| 2063 | }, |
| 2064 | }; |
| 2065 | |
| 2066 | static struct branch_clk mclk1_clk = { |
| 2067 | .cbcr_reg = MCLK1_CBCR, |
| 2068 | .has_sibling = 0, |
| 2069 | .base = &virt_bases[MMSS_BASE], |
| 2070 | .c = { |
| 2071 | .parent = &mclk1_clk_src.c, |
| 2072 | .dbg_name = "mclk1_clk", |
| 2073 | .ops = &clk_ops_branch, |
| 2074 | CLK_INIT(mclk1_clk.c), |
| 2075 | }, |
| 2076 | }; |
| 2077 | |
| 2078 | static struct branch_clk mdp_ahb_clk = { |
| 2079 | .cbcr_reg = MDP_AHB_CBCR, |
| 2080 | .has_sibling = 1, |
| 2081 | .base = &virt_bases[MMSS_BASE], |
| 2082 | .c = { |
| 2083 | .dbg_name = "mdp_ahb_clk", |
| 2084 | .ops = &clk_ops_branch, |
| 2085 | CLK_INIT(mdp_ahb_clk.c), |
| 2086 | }, |
| 2087 | }; |
| 2088 | |
| 2089 | static struct branch_clk mdp_axi_clk = { |
| 2090 | .cbcr_reg = MDP_AXI_CBCR, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2091 | .base = &virt_bases[MMSS_BASE], |
Vikram Mulukutla | 2dfa8b1 | 2013-01-15 18:17:10 -0800 | [diff] [blame] | 2092 | /* FIXME: Remove this once simulation is fixed. */ |
| 2093 | .halt_check = DELAY, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2094 | .c = { |
Vikram Mulukutla | e1e5c48 | 2013-01-28 14:43:20 -0800 | [diff] [blame] | 2095 | .parent = &mdp_axi_clk_src.c, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2096 | .dbg_name = "mdp_axi_clk", |
| 2097 | .ops = &clk_ops_branch, |
| 2098 | CLK_INIT(mdp_axi_clk.c), |
| 2099 | }, |
| 2100 | }; |
| 2101 | |
| 2102 | static struct branch_clk mdp_dsi_clk = { |
| 2103 | .cbcr_reg = MDP_DSI_CBCR, |
| 2104 | .has_sibling = 1, |
| 2105 | .base = &virt_bases[MMSS_BASE], |
| 2106 | .c = { |
| 2107 | .parent = &dsi_pclk_clk_src.c, |
| 2108 | .dbg_name = "mdp_dsi_clk", |
| 2109 | .ops = &clk_ops_branch, |
| 2110 | CLK_INIT(mdp_dsi_clk.c), |
| 2111 | }, |
| 2112 | }; |
| 2113 | |
| 2114 | static struct branch_clk mdp_lcdc_clk = { |
| 2115 | .cbcr_reg = MDP_LCDC_CBCR, |
| 2116 | .has_sibling = 1, |
| 2117 | .base = &virt_bases[MMSS_BASE], |
| 2118 | .c = { |
| 2119 | .parent = &dsi_pclk_clk_src.c, |
| 2120 | .dbg_name = "mdp_lcdc_clk", |
| 2121 | .ops = &clk_ops_branch, |
| 2122 | CLK_INIT(mdp_lcdc_clk.c), |
| 2123 | }, |
| 2124 | }; |
| 2125 | |
| 2126 | static struct branch_clk mdp_vsync_clk = { |
| 2127 | .cbcr_reg = MDP_VSYNC_CBCR, |
| 2128 | .has_sibling = 0, |
| 2129 | .base = &virt_bases[MMSS_BASE], |
| 2130 | .c = { |
| 2131 | .parent = &mdp_vsync_clk_src.c, |
| 2132 | .dbg_name = "mdp_vsync_clk", |
| 2133 | .ops = &clk_ops_branch, |
| 2134 | CLK_INIT(mdp_vsync_clk.c), |
| 2135 | }, |
| 2136 | }; |
| 2137 | |
| 2138 | static struct branch_clk mmss_misc_ahb_clk = { |
| 2139 | .cbcr_reg = MMSS_MISC_AHB_CBCR, |
| 2140 | .has_sibling = 1, |
| 2141 | .base = &virt_bases[MMSS_BASE], |
| 2142 | .c = { |
| 2143 | .dbg_name = "mmss_misc_ahb_clk", |
| 2144 | .ops = &clk_ops_branch, |
| 2145 | CLK_INIT(mmss_misc_ahb_clk.c), |
| 2146 | }, |
| 2147 | }; |
| 2148 | |
| 2149 | static struct branch_clk mmss_mmssnoc_axi_clk = { |
| 2150 | .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR, |
| 2151 | .has_sibling = 1, |
| 2152 | .base = &virt_bases[MMSS_BASE], |
| 2153 | .c = { |
| 2154 | .parent = &axi_clk_src.c, |
| 2155 | .dbg_name = "mmss_mmssnoc_axi_clk", |
| 2156 | .ops = &clk_ops_branch, |
| 2157 | CLK_INIT(mmss_mmssnoc_axi_clk.c), |
| 2158 | }, |
| 2159 | }; |
| 2160 | |
| 2161 | static struct branch_clk mmss_s0_axi_clk = { |
| 2162 | .cbcr_reg = MMSS_S0_AXI_CBCR, |
| 2163 | .has_sibling = 0, |
| 2164 | .base = &virt_bases[MMSS_BASE], |
| 2165 | .c = { |
Vikram Mulukutla | e1e5c48 | 2013-01-28 14:43:20 -0800 | [diff] [blame] | 2166 | .parent = &mmssnoc_axi_clk_src.c, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2167 | .dbg_name = "mmss_s0_axi_clk", |
| 2168 | .ops = &clk_ops_branch, |
| 2169 | CLK_INIT(mmss_s0_axi_clk.c), |
| 2170 | .depends = &mmss_mmssnoc_axi_clk.c, |
| 2171 | }, |
| 2172 | }; |
| 2173 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2174 | static struct branch_clk mmss_mmssnoc_bto_ahb_clk = { |
| 2175 | .cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR, |
| 2176 | .has_sibling = 1, |
| 2177 | .base = &virt_bases[MMSS_BASE], |
| 2178 | .c = { |
| 2179 | .dbg_name = "mmss_mmssnoc_bto_ahb_clk", |
| 2180 | .ops = &clk_ops_branch, |
| 2181 | CLK_INIT(mmss_mmssnoc_bto_ahb_clk.c), |
| 2182 | }, |
| 2183 | }; |
| 2184 | |
| 2185 | static struct branch_clk oxili_ahb_clk = { |
| 2186 | .cbcr_reg = OXILI_AHB_CBCR, |
| 2187 | .has_sibling = 1, |
| 2188 | .base = &virt_bases[MMSS_BASE], |
| 2189 | .c = { |
| 2190 | .dbg_name = "oxili_ahb_clk", |
| 2191 | .ops = &clk_ops_branch, |
| 2192 | CLK_INIT(oxili_ahb_clk.c), |
| 2193 | }, |
| 2194 | }; |
| 2195 | |
| 2196 | static struct branch_clk oxili_gfx3d_clk = { |
| 2197 | .cbcr_reg = OXILI_GFX3D_CBCR, |
| 2198 | .has_sibling = 0, |
| 2199 | .base = &virt_bases[MMSS_BASE], |
| 2200 | .c = { |
| 2201 | .parent = &gfx3d_clk_src.c, |
| 2202 | .dbg_name = "oxili_gfx3d_clk", |
| 2203 | .ops = &clk_ops_branch, |
| 2204 | CLK_INIT(oxili_gfx3d_clk.c), |
| 2205 | }, |
| 2206 | }; |
| 2207 | |
| 2208 | static struct branch_clk vfe_clk = { |
| 2209 | .cbcr_reg = VFE_CBCR, |
| 2210 | .has_sibling = 1, |
| 2211 | .base = &virt_bases[MMSS_BASE], |
| 2212 | .c = { |
| 2213 | .parent = &vfe_clk_src.c, |
| 2214 | .dbg_name = "vfe_clk", |
| 2215 | .ops = &clk_ops_branch, |
| 2216 | CLK_INIT(vfe_clk.c), |
| 2217 | }, |
| 2218 | }; |
| 2219 | |
| 2220 | static struct branch_clk vfe_ahb_clk = { |
| 2221 | .cbcr_reg = VFE_AHB_CBCR, |
| 2222 | .has_sibling = 1, |
| 2223 | .base = &virt_bases[MMSS_BASE], |
| 2224 | .c = { |
| 2225 | .dbg_name = "vfe_ahb_clk", |
| 2226 | .ops = &clk_ops_branch, |
| 2227 | CLK_INIT(vfe_ahb_clk.c), |
| 2228 | }, |
| 2229 | }; |
| 2230 | |
| 2231 | static struct branch_clk vfe_axi_clk = { |
| 2232 | .cbcr_reg = VFE_AXI_CBCR, |
| 2233 | .has_sibling = 1, |
| 2234 | .base = &virt_bases[MMSS_BASE], |
Vikram Mulukutla | 2dfa8b1 | 2013-01-15 18:17:10 -0800 | [diff] [blame] | 2235 | /* FIXME: Remove this once simulation is fixed. */ |
| 2236 | .halt_check = DELAY, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2237 | .c = { |
| 2238 | .parent = &axi_clk_src.c, |
| 2239 | .dbg_name = "vfe_axi_clk", |
| 2240 | .ops = &clk_ops_branch, |
| 2241 | CLK_INIT(vfe_axi_clk.c), |
| 2242 | }, |
| 2243 | }; |
| 2244 | |
| 2245 | static struct clk_freq_tbl ftbl_audio_core_lpaif_clk[] = { |
| 2246 | F_LPASS( 512000, lpapll0, 16, 1, 60), |
| 2247 | F_LPASS( 768000, lpapll0, 16, 1, 40), |
| 2248 | F_LPASS( 1024000, lpapll0, 16, 1, 30), |
| 2249 | F_LPASS( 1536000, lpapll0, 16, 1, 20), |
| 2250 | F_LPASS( 2048000, lpapll0, 16, 1, 15), |
| 2251 | F_LPASS( 3072000, lpapll0, 16, 1, 10), |
| 2252 | F_LPASS( 4096000, lpapll0, 15, 1, 8), |
| 2253 | F_LPASS( 6144000, lpapll0, 10, 1, 8), |
| 2254 | F_LPASS( 8192000, lpapll0, 15, 1, 4), |
| 2255 | F_LPASS(12288000, lpapll0, 10, 1, 4), |
| 2256 | F_END, |
| 2257 | }; |
| 2258 | |
| 2259 | static struct rcg_clk lpaif_pri_clk_src = { |
| 2260 | .cmd_rcgr_reg = LPAIF_PRI_CMD_RCGR, |
| 2261 | .set_rate = set_rate_mnd, |
| 2262 | .freq_tbl = ftbl_audio_core_lpaif_clk, |
| 2263 | .current_freq = &rcg_dummy_freq, |
| 2264 | .base = &virt_bases[LPASS_BASE], |
| 2265 | .c = { |
| 2266 | .dbg_name = "lpaif_pri_clk_src", |
| 2267 | .ops = &clk_ops_rcg_mnd, |
| 2268 | VDD_DIG_FMAX_MAP2(LOW, 12290000, NOMINAL, 24580000), |
| 2269 | CLK_INIT(lpaif_pri_clk_src.c), |
| 2270 | }, |
| 2271 | }; |
| 2272 | |
| 2273 | static struct rcg_clk lpaif_quad_clk_src = { |
| 2274 | .cmd_rcgr_reg = LPAIF_QUAD_CMD_RCGR, |
| 2275 | .set_rate = set_rate_mnd, |
| 2276 | .freq_tbl = ftbl_audio_core_lpaif_clk, |
| 2277 | .current_freq = &rcg_dummy_freq, |
| 2278 | .base = &virt_bases[LPASS_BASE], |
| 2279 | .c = { |
| 2280 | .dbg_name = "lpaif_quad_clk_src", |
| 2281 | .ops = &clk_ops_rcg_mnd, |
| 2282 | VDD_DIG_FMAX_MAP2(LOW, 12290000, NOMINAL, 24580000), |
| 2283 | CLK_INIT(lpaif_quad_clk_src.c), |
| 2284 | }, |
| 2285 | }; |
| 2286 | |
| 2287 | static struct rcg_clk lpaif_sec_clk_src = { |
| 2288 | .cmd_rcgr_reg = LPAIF_SEC_CMD_RCGR, |
| 2289 | .set_rate = set_rate_mnd, |
| 2290 | .freq_tbl = ftbl_audio_core_lpaif_clk, |
| 2291 | .current_freq = &rcg_dummy_freq, |
| 2292 | .base = &virt_bases[LPASS_BASE], |
| 2293 | .c = { |
| 2294 | .dbg_name = "lpaif_sec_clk_src", |
| 2295 | .ops = &clk_ops_rcg_mnd, |
| 2296 | VDD_DIG_FMAX_MAP2(LOW, 12290000, NOMINAL, 24580000), |
| 2297 | CLK_INIT(lpaif_sec_clk_src.c), |
| 2298 | }, |
| 2299 | }; |
| 2300 | |
| 2301 | static struct rcg_clk lpaif_spkr_clk_src = { |
| 2302 | .cmd_rcgr_reg = LPAIF_SPKR_CMD_RCGR, |
| 2303 | .set_rate = set_rate_mnd, |
| 2304 | .freq_tbl = ftbl_audio_core_lpaif_clk, |
| 2305 | .current_freq = &rcg_dummy_freq, |
| 2306 | .base = &virt_bases[LPASS_BASE], |
| 2307 | .c = { |
| 2308 | .dbg_name = "lpaif_spkr_clk_src", |
| 2309 | .ops = &clk_ops_rcg_mnd, |
| 2310 | VDD_DIG_FMAX_MAP2(LOW, 12290000, NOMINAL, 24580000), |
| 2311 | CLK_INIT(lpaif_spkr_clk_src.c), |
| 2312 | }, |
| 2313 | }; |
| 2314 | |
| 2315 | static struct rcg_clk lpaif_ter_clk_src = { |
| 2316 | .cmd_rcgr_reg = LPAIF_TER_CMD_RCGR, |
| 2317 | .set_rate = set_rate_mnd, |
| 2318 | .freq_tbl = ftbl_audio_core_lpaif_clk, |
| 2319 | .current_freq = &rcg_dummy_freq, |
| 2320 | .base = &virt_bases[LPASS_BASE], |
| 2321 | .c = { |
| 2322 | .dbg_name = "lpaif_ter_clk_src", |
| 2323 | .ops = &clk_ops_rcg_mnd, |
| 2324 | VDD_DIG_FMAX_MAP2(LOW, 12290000, NOMINAL, 24580000), |
| 2325 | CLK_INIT(lpaif_ter_clk_src.c), |
| 2326 | }, |
| 2327 | }; |
| 2328 | |
| 2329 | static struct clk_freq_tbl ftbl_audio_core_lpaif_pcm0_1_clk[] = { |
| 2330 | F_LPASS( 512000, lpapll0, 16, 1, 60), |
| 2331 | F_LPASS( 768000, lpapll0, 16, 1, 40), |
| 2332 | F_LPASS(1024000, lpapll0, 16, 1, 30), |
| 2333 | F_LPASS(1536000, lpapll0, 16, 1, 20), |
| 2334 | F_LPASS(2048000, lpapll0, 16, 1, 15), |
| 2335 | F_LPASS(3072000, lpapll0, 16, 1, 10), |
| 2336 | F_LPASS(4096000, lpapll0, 15, 1, 8), |
| 2337 | F_LPASS(6144000, lpapll0, 10, 1, 8), |
| 2338 | F_LPASS(8192000, lpapll0, 15, 1, 4), |
| 2339 | F_END, |
| 2340 | }; |
| 2341 | |
| 2342 | static struct rcg_clk lpaif_pcm0_clk_src = { |
| 2343 | .cmd_rcgr_reg = LPAIF_PCM0_CMD_RCGR, |
| 2344 | .set_rate = set_rate_mnd, |
| 2345 | .freq_tbl = ftbl_audio_core_lpaif_pcm0_1_clk, |
| 2346 | .current_freq = &rcg_dummy_freq, |
| 2347 | .base = &virt_bases[LPASS_BASE], |
| 2348 | .c = { |
| 2349 | .dbg_name = "lpaif_pcm0_clk_src", |
| 2350 | .ops = &clk_ops_rcg_mnd, |
| 2351 | VDD_DIG_FMAX_MAP2(LOW, 4100000, NOMINAL, 8192000), |
| 2352 | CLK_INIT(lpaif_pcm0_clk_src.c), |
| 2353 | }, |
| 2354 | }; |
| 2355 | |
| 2356 | static struct rcg_clk lpaif_pcm1_clk_src = { |
| 2357 | .cmd_rcgr_reg = LPAIF_PCM1_CMD_RCGR, |
| 2358 | .set_rate = set_rate_mnd, |
| 2359 | .freq_tbl = ftbl_audio_core_lpaif_pcm0_1_clk, |
| 2360 | .current_freq = &rcg_dummy_freq, |
| 2361 | .base = &virt_bases[LPASS_BASE], |
| 2362 | .c = { |
| 2363 | .dbg_name = "lpaif_pcm1_clk_src", |
| 2364 | .ops = &clk_ops_rcg_mnd, |
| 2365 | VDD_DIG_FMAX_MAP2(LOW, 4100000, NOMINAL, 8192000), |
| 2366 | CLK_INIT(lpaif_pcm1_clk_src.c), |
| 2367 | }, |
| 2368 | }; |
| 2369 | |
| 2370 | static struct rcg_clk lpaif_pcmoe_clk_src = { |
| 2371 | .cmd_rcgr_reg = LPAIF_PCMOE_CMD_RCGR, |
| 2372 | .set_rate = set_rate_mnd, |
| 2373 | .freq_tbl = ftbl_audio_core_lpaif_pcm0_1_clk, |
| 2374 | .current_freq = &rcg_dummy_freq, |
| 2375 | .base = &virt_bases[LPASS_BASE], |
| 2376 | .c = { |
| 2377 | .dbg_name = "lpaif_pcmoe_clk_src", |
| 2378 | .ops = &clk_ops_rcg_mnd, |
| 2379 | VDD_DIG_FMAX_MAP2(LOW, 6140000, NOMINAL, 12290000), |
| 2380 | CLK_INIT(lpaif_pcmoe_clk_src.c), |
| 2381 | }, |
| 2382 | }; |
| 2383 | |
| 2384 | static struct clk_freq_tbl ftbl_audio_core_slimbus_core_clock[] = { |
| 2385 | F_LPASS(24576000, lpapll0, 4, 1, 5), |
| 2386 | F_END |
| 2387 | }; |
| 2388 | |
| 2389 | static struct rcg_clk audio_core_slimbus_core_clk_src = { |
| 2390 | .cmd_rcgr_reg = SLIMBUS_CMD_RCGR, |
| 2391 | .set_rate = set_rate_mnd, |
| 2392 | .freq_tbl = ftbl_audio_core_slimbus_core_clock, |
| 2393 | .current_freq = &rcg_dummy_freq, |
| 2394 | .base = &virt_bases[LPASS_BASE], |
| 2395 | .c = { |
| 2396 | .dbg_name = "audio_core_slimbus_core_clk_src", |
| 2397 | .ops = &clk_ops_rcg_mnd, |
| 2398 | VDD_DIG_FMAX_MAP2(LOW, 12935000, NOMINAL, 25869000), |
| 2399 | CLK_INIT(audio_core_slimbus_core_clk_src.c), |
| 2400 | }, |
| 2401 | }; |
| 2402 | |
| 2403 | static struct branch_clk audio_core_slimbus_core_clk = { |
| 2404 | .cbcr_reg = AUDIO_CORE_SLIMBUS_CORE_CBCR, |
| 2405 | .base = &virt_bases[LPASS_BASE], |
| 2406 | .c = { |
| 2407 | .parent = &audio_core_slimbus_core_clk_src.c, |
| 2408 | .dbg_name = "audio_core_slimbus_core_clk", |
| 2409 | .ops = &clk_ops_branch, |
| 2410 | CLK_INIT(audio_core_slimbus_core_clk.c), |
| 2411 | }, |
| 2412 | }; |
| 2413 | |
| 2414 | static struct branch_clk audio_core_ixfabric_clk = { |
| 2415 | .cbcr_reg = AUDIO_CORE_IXFABRIC_CBCR, |
| 2416 | .has_sibling = 1, |
| 2417 | .base = &virt_bases[LPASS_BASE], |
| 2418 | .c = { |
| 2419 | .dbg_name = "audio_core_ixfabric_clk", |
| 2420 | .ops = &clk_ops_branch, |
| 2421 | CLK_INIT(audio_core_ixfabric_clk.c), |
| 2422 | }, |
| 2423 | }; |
| 2424 | |
| 2425 | static struct branch_clk audio_wrapper_br_clk = { |
| 2426 | .cbcr_reg = AUDIO_WRAPPER_BR_CBCR, |
| 2427 | .has_sibling = 1, |
| 2428 | .base = &virt_bases[LPASS_BASE], |
| 2429 | .c = { |
| 2430 | .dbg_name = "audio_wrapper_br_clk", |
| 2431 | .ops = &clk_ops_branch, |
| 2432 | CLK_INIT(audio_wrapper_br_clk.c), |
| 2433 | }, |
| 2434 | }; |
| 2435 | |
| 2436 | static struct branch_clk q6ss_ahb_lfabif_clk = { |
| 2437 | .cbcr_reg = Q6SS_AHB_LFABIF_CBCR, |
| 2438 | .has_sibling = 1, |
| 2439 | .base = &virt_bases[LPASS_BASE], |
| 2440 | .c = { |
| 2441 | .dbg_name = "q6ss_ahb_lfabif_clk", |
| 2442 | .ops = &clk_ops_branch, |
| 2443 | CLK_INIT(q6ss_ahb_lfabif_clk.c), |
| 2444 | }, |
| 2445 | }; |
| 2446 | |
| 2447 | static struct branch_clk q6ss_ahbm_clk = { |
| 2448 | .cbcr_reg = Q6SS_AHBM_CBCR, |
| 2449 | .has_sibling = 1, |
| 2450 | .base = &virt_bases[LPASS_BASE], |
| 2451 | .c = { |
| 2452 | .dbg_name = "q6ss_ahbm_clk", |
| 2453 | .ops = &clk_ops_branch, |
| 2454 | CLK_INIT(q6ss_ahbm_clk.c), |
| 2455 | }, |
| 2456 | }; |
| 2457 | |
| 2458 | static struct branch_clk q6ss_xo_clk = { |
| 2459 | .cbcr_reg = Q6SS_XO_CBCR, |
| 2460 | .has_sibling = 1, |
| 2461 | .bcr_reg = LPASS_Q6SS_BCR, |
| 2462 | .base = &virt_bases[LPASS_BASE], |
| 2463 | .c = { |
| 2464 | .parent = &gcc_xo_clk_src.c, |
| 2465 | .dbg_name = "q6ss_xo_clk", |
| 2466 | .ops = &clk_ops_branch, |
| 2467 | CLK_INIT(q6ss_xo_clk.c), |
| 2468 | }, |
| 2469 | }; |
| 2470 | |
| 2471 | static struct branch_clk audio_core_lpaif_pcm_data_oe_clk = { |
| 2472 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR, |
| 2473 | .has_sibling = 0, |
| 2474 | .base = &virt_bases[LPASS_BASE], |
| 2475 | .c = { |
| 2476 | .parent = &lpaif_pcmoe_clk_src.c, |
| 2477 | .dbg_name = "audio_core_lpaif_pcm_data_oe_clk", |
| 2478 | .ops = &clk_ops_branch, |
| 2479 | CLK_INIT(audio_core_lpaif_pcm_data_oe_clk.c), |
| 2480 | }, |
| 2481 | }; |
| 2482 | |
| 2483 | static struct branch_clk audio_core_lpaif_pri_ebit_clk = { |
| 2484 | .cbcr_reg = AUDIO_CORE_LPAIF_PRI_EBIT_CBCR, |
| 2485 | .has_sibling = 0, |
| 2486 | .base = &virt_bases[LPASS_BASE], |
| 2487 | .c = { |
| 2488 | .dbg_name = "audio_core_lpaif_pri_ebit_clk", |
| 2489 | .ops = &clk_ops_branch, |
| 2490 | CLK_INIT(audio_core_lpaif_pri_ebit_clk.c), |
| 2491 | }, |
| 2492 | }; |
| 2493 | |
| 2494 | static struct branch_clk audio_core_lpaif_pri_ibit_clk = { |
| 2495 | .cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR, |
| 2496 | .has_sibling = 0, |
| 2497 | .max_div = 511, |
| 2498 | .base = &virt_bases[LPASS_BASE], |
| 2499 | .c = { |
| 2500 | .parent = &lpaif_pri_clk_src.c, |
| 2501 | .dbg_name = "audio_core_lpaif_pri_ibit_clk", |
| 2502 | .ops = &clk_ops_branch, |
| 2503 | CLK_INIT(audio_core_lpaif_pri_ibit_clk.c), |
| 2504 | }, |
| 2505 | }; |
| 2506 | |
| 2507 | static struct branch_clk audio_core_lpaif_pri_osr_clk = { |
| 2508 | .cbcr_reg = AUDIO_CORE_LPAIF_PRI_OSR_CBCR, |
| 2509 | .has_sibling = 0, |
| 2510 | .base = &virt_bases[LPASS_BASE], |
| 2511 | .c = { |
| 2512 | .parent = &lpaif_pri_clk_src.c, |
| 2513 | .dbg_name = "audio_core_lpaif_pri_osr_clk", |
| 2514 | .ops = &clk_ops_branch, |
| 2515 | CLK_INIT(audio_core_lpaif_pri_osr_clk.c), |
| 2516 | }, |
| 2517 | }; |
| 2518 | |
| 2519 | static struct branch_clk audio_core_lpaif_pcm0_ebit_clk = { |
| 2520 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM0_EBIT_CBCR, |
| 2521 | .has_sibling = 0, |
| 2522 | .base = &virt_bases[LPASS_BASE], |
| 2523 | .c = { |
| 2524 | .dbg_name = "audio_core_lpaif_pcm0_ebit_clk", |
| 2525 | .ops = &clk_ops_branch, |
| 2526 | CLK_INIT(audio_core_lpaif_pcm0_ebit_clk.c), |
| 2527 | }, |
| 2528 | }; |
| 2529 | |
| 2530 | static struct branch_clk audio_core_lpaif_pcm0_ibit_clk = { |
| 2531 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR, |
| 2532 | .has_sibling = 0, |
| 2533 | .base = &virt_bases[LPASS_BASE], |
| 2534 | .c = { |
| 2535 | .parent = &lpaif_pcm0_clk_src.c, |
| 2536 | .dbg_name = "audio_core_lpaif_pcm0_ibit_clk", |
| 2537 | .ops = &clk_ops_branch, |
| 2538 | CLK_INIT(audio_core_lpaif_pcm0_ibit_clk.c), |
| 2539 | }, |
| 2540 | }; |
| 2541 | |
| 2542 | static struct branch_clk audio_core_lpaif_quad_ebit_clk = { |
| 2543 | .cbcr_reg = AUDIO_CORE_LPAIF_QUAD_EBIT_CBCR, |
| 2544 | .has_sibling = 0, |
| 2545 | .base = &virt_bases[LPASS_BASE], |
| 2546 | .c = { |
| 2547 | .dbg_name = "audio_core_lpaif_quad_ebit_clk", |
| 2548 | .ops = &clk_ops_branch, |
| 2549 | CLK_INIT(audio_core_lpaif_quad_ebit_clk.c), |
| 2550 | }, |
| 2551 | }; |
| 2552 | |
| 2553 | static struct branch_clk audio_core_lpaif_quad_ibit_clk = { |
| 2554 | .cbcr_reg = AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR, |
| 2555 | .has_sibling = 0, |
| 2556 | .max_div = 511, |
| 2557 | .base = &virt_bases[LPASS_BASE], |
| 2558 | .c = { |
| 2559 | .parent = &lpaif_quad_clk_src.c, |
| 2560 | .dbg_name = "audio_core_lpaif_quad_ibit_clk", |
| 2561 | .ops = &clk_ops_branch, |
| 2562 | CLK_INIT(audio_core_lpaif_quad_ibit_clk.c), |
| 2563 | }, |
| 2564 | }; |
| 2565 | |
| 2566 | static struct branch_clk audio_core_lpaif_quad_osr_clk = { |
| 2567 | .cbcr_reg = AUDIO_CORE_LPAIF_QUAD_OSR_CBCR, |
| 2568 | .has_sibling = 0, |
| 2569 | .base = &virt_bases[LPASS_BASE], |
| 2570 | .c = { |
| 2571 | .parent = &lpaif_quad_clk_src.c, |
| 2572 | .dbg_name = "audio_core_lpaif_quad_osr_clk", |
| 2573 | .ops = &clk_ops_branch, |
| 2574 | CLK_INIT(audio_core_lpaif_quad_osr_clk.c), |
| 2575 | }, |
| 2576 | }; |
| 2577 | |
| 2578 | static struct branch_clk audio_core_lpaif_sec_ebit_clk = { |
| 2579 | .cbcr_reg = AUDIO_CORE_LPAIF_SEC_EBIT_CBCR, |
| 2580 | .has_sibling = 0, |
| 2581 | .base = &virt_bases[LPASS_BASE], |
| 2582 | .c = { |
| 2583 | .dbg_name = "audio_core_lpaif_sec_ebit_clk", |
| 2584 | .ops = &clk_ops_branch, |
| 2585 | CLK_INIT(audio_core_lpaif_sec_ebit_clk.c), |
| 2586 | }, |
| 2587 | }; |
| 2588 | |
| 2589 | static struct branch_clk audio_core_lpaif_sec_ibit_clk = { |
| 2590 | .cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR, |
| 2591 | .has_sibling = 0, |
| 2592 | .max_div = 511, |
| 2593 | .base = &virt_bases[LPASS_BASE], |
| 2594 | .c = { |
| 2595 | .parent = &lpaif_sec_clk_src.c, |
| 2596 | .dbg_name = "audio_core_lpaif_sec_ibit_clk", |
| 2597 | .ops = &clk_ops_branch, |
| 2598 | CLK_INIT(audio_core_lpaif_sec_ibit_clk.c), |
| 2599 | }, |
| 2600 | }; |
| 2601 | |
| 2602 | static struct branch_clk audio_core_lpaif_sec_osr_clk = { |
| 2603 | .cbcr_reg = AUDIO_CORE_LPAIF_SEC_OSR_CBCR, |
| 2604 | .has_sibling = 0, |
| 2605 | .base = &virt_bases[LPASS_BASE], |
| 2606 | .c = { |
| 2607 | .parent = &lpaif_sec_clk_src.c, |
| 2608 | .dbg_name = "audio_core_lpaif_sec_osr_clk", |
| 2609 | .ops = &clk_ops_branch, |
| 2610 | CLK_INIT(audio_core_lpaif_sec_osr_clk.c), |
| 2611 | }, |
| 2612 | }; |
| 2613 | |
| 2614 | static struct branch_clk audio_core_lpaif_pcm1_ebit_clk = { |
| 2615 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM1_EBIT_CBCR, |
| 2616 | .has_sibling = 0, |
| 2617 | .base = &virt_bases[LPASS_BASE], |
| 2618 | .c = { |
| 2619 | .dbg_name = "audio_core_lpaif_pcm1_ebit_clk", |
| 2620 | .ops = &clk_ops_branch, |
| 2621 | CLK_INIT(audio_core_lpaif_pcm1_ebit_clk.c), |
| 2622 | }, |
| 2623 | }; |
| 2624 | |
| 2625 | static struct branch_clk audio_core_lpaif_pcm1_ibit_clk = { |
| 2626 | .cbcr_reg = AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR, |
| 2627 | .has_sibling = 0, |
| 2628 | .base = &virt_bases[LPASS_BASE], |
| 2629 | .c = { |
| 2630 | .parent = &lpaif_pcm1_clk_src.c, |
| 2631 | .dbg_name = "audio_core_lpaif_pcm1_ibit_clk", |
| 2632 | .ops = &clk_ops_branch, |
| 2633 | CLK_INIT(audio_core_lpaif_pcm1_ibit_clk.c), |
| 2634 | }, |
| 2635 | }; |
| 2636 | |
| 2637 | static struct branch_clk audio_core_lpaif_codec_spkr_ebit_clk = { |
| 2638 | .cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_EBIT_CBCR, |
| 2639 | .has_sibling = 0, |
| 2640 | .base = &virt_bases[LPASS_BASE], |
| 2641 | .c = { |
| 2642 | .dbg_name = "audio_core_lpaif_codec_spkr_ebit_clk", |
| 2643 | .ops = &clk_ops_branch, |
| 2644 | CLK_INIT(audio_core_lpaif_codec_spkr_ebit_clk.c), |
| 2645 | }, |
| 2646 | }; |
| 2647 | |
| 2648 | static struct branch_clk audio_core_lpaif_codec_spkr_ibit_clk = { |
| 2649 | .cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR, |
| 2650 | .has_sibling = 1, |
| 2651 | .max_div = 511, |
| 2652 | .base = &virt_bases[LPASS_BASE], |
| 2653 | .c = { |
| 2654 | .parent = &lpaif_spkr_clk_src.c, |
| 2655 | .dbg_name = "audio_core_lpaif_codec_spkr_ibit_clk", |
| 2656 | .ops = &clk_ops_branch, |
| 2657 | CLK_INIT(audio_core_lpaif_codec_spkr_ibit_clk.c), |
| 2658 | }, |
| 2659 | }; |
| 2660 | |
| 2661 | static struct branch_clk audio_core_lpaif_codec_spkr_osr_clk = { |
| 2662 | .cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_OSR_CBCR, |
| 2663 | .has_sibling = 1, |
| 2664 | .base = &virt_bases[LPASS_BASE], |
| 2665 | .c = { |
| 2666 | .parent = &lpaif_spkr_clk_src.c, |
| 2667 | .dbg_name = "audio_core_lpaif_codec_spkr_osr_clk", |
| 2668 | .ops = &clk_ops_branch, |
| 2669 | CLK_INIT(audio_core_lpaif_codec_spkr_osr_clk.c), |
| 2670 | }, |
| 2671 | }; |
| 2672 | |
| 2673 | static struct branch_clk audio_core_lpaif_ter_ebit_clk = { |
| 2674 | .cbcr_reg = AUDIO_CORE_LPAIF_TER_EBIT_CBCR, |
| 2675 | .has_sibling = 0, |
| 2676 | .base = &virt_bases[LPASS_BASE], |
| 2677 | .c = { |
| 2678 | .dbg_name = "audio_core_lpaif_ter_ebit_clk", |
| 2679 | .ops = &clk_ops_branch, |
| 2680 | CLK_INIT(audio_core_lpaif_ter_ebit_clk.c), |
| 2681 | }, |
| 2682 | }; |
| 2683 | |
| 2684 | static struct branch_clk audio_core_lpaif_ter_ibit_clk = { |
| 2685 | .cbcr_reg = AUDIO_CORE_LPAIF_TER_IBIT_CBCR, |
| 2686 | .has_sibling = 0, |
| 2687 | .max_div = 511, |
| 2688 | .base = &virt_bases[LPASS_BASE], |
| 2689 | .c = { |
| 2690 | .parent = &lpaif_ter_clk_src.c, |
| 2691 | .dbg_name = "audio_core_lpaif_ter_ibit_clk", |
| 2692 | .ops = &clk_ops_branch, |
| 2693 | CLK_INIT(audio_core_lpaif_ter_ibit_clk.c), |
| 2694 | }, |
| 2695 | }; |
| 2696 | |
| 2697 | static struct branch_clk audio_core_lpaif_ter_osr_clk = { |
| 2698 | .cbcr_reg = AUDIO_CORE_LPAIF_TER_OSR_CBCR, |
| 2699 | .has_sibling = 0, |
| 2700 | .base = &virt_bases[LPASS_BASE], |
| 2701 | .c = { |
| 2702 | .parent = &lpaif_ter_clk_src.c, |
| 2703 | .dbg_name = "audio_core_lpaif_ter_osr_clk", |
| 2704 | .ops = &clk_ops_branch, |
| 2705 | CLK_INIT(audio_core_lpaif_ter_osr_clk.c), |
| 2706 | }, |
| 2707 | }; |
| 2708 | |
| 2709 | #ifdef CONFIG_DEBUG_FS |
| 2710 | |
| 2711 | struct measure_mux_entry { |
| 2712 | struct clk *c; |
| 2713 | int base; |
| 2714 | u32 debug_mux; |
| 2715 | }; |
| 2716 | |
| 2717 | static struct measure_mux_entry measure_mux[] = { |
| 2718 | { &snoc_clk.c, GCC_BASE, 0x0000}, |
| 2719 | { &cnoc_clk.c, GCC_BASE, 0x0008}, |
| 2720 | { &gcc_copss_smmu_ahb_clk.c, GCC_BASE, 0x000c}, |
| 2721 | { &gcc_lpss_smmu_ahb_clk.c, GCC_BASE, 0x000d}, |
| 2722 | { &pnoc_clk.c, GCC_BASE, 0x0010}, |
| 2723 | { &gcc_mmss_noc_cfg_ahb_clk.c, GCC_BASE, 0x002a}, |
| 2724 | { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030}, |
| 2725 | { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031}, |
| 2726 | { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060}, |
| 2727 | { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061}, |
| 2728 | { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063}, |
| 2729 | { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068}, |
| 2730 | { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069}, |
| 2731 | { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070}, |
| 2732 | { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071}, |
| 2733 | { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088}, |
| 2734 | {&gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a}, |
| 2735 | {&gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b}, |
| 2736 | { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c}, |
| 2737 | {&gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e}, |
| 2738 | {&gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090}, |
| 2739 | { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091}, |
| 2740 | {&gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093}, |
| 2741 | {&gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094}, |
| 2742 | { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095}, |
| 2743 | {&gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098}, |
| 2744 | {&gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099}, |
| 2745 | { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a}, |
| 2746 | {&gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c}, |
| 2747 | {&gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d}, |
| 2748 | { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e}, |
| 2749 | {&gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1}, |
| 2750 | {&gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2}, |
| 2751 | { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3}, |
| 2752 | { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0}, |
| 2753 | { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2}, |
| 2754 | { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8}, |
| 2755 | { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8}, |
| 2756 | { &gcc_ce1_clk.c, GCC_BASE, 0x0138}, |
| 2757 | { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139}, |
| 2758 | { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a}, |
| 2759 | { &gcc_xo_clk_src.c, GCC_BASE, 0x0149}, |
| 2760 | { &bimc_clk.c, GCC_BASE, 0x0154}, |
| 2761 | { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160}, |
| 2762 | |
Vikram Mulukutla | 82cb844 | 2013-01-28 13:36:51 -0800 | [diff] [blame] | 2763 | { &mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001}, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2764 | { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003}, |
| 2765 | {&mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004}, |
| 2766 | { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005}, |
| 2767 | { &oxili_ahb_clk.c, MMSS_BASE, 0x0007}, |
| 2768 | { &oxili_gfx3d_clk.c, MMSS_BASE, 0x0008}, |
| 2769 | { &gmem_gfx3d_clk.c, MMSS_BASE, 0x0009}, |
| 2770 | { &mdp_axi_clk.c, MMSS_BASE, 0x000a}, |
| 2771 | { &mdp_vsync_clk.c, MMSS_BASE, 0x000b}, |
| 2772 | { &mdp_ahb_clk.c, MMSS_BASE, 0x000c}, |
| 2773 | { &dsi_pclk_clk.c, MMSS_BASE, 0x000d}, |
| 2774 | { &mdp_dsi_clk.c, MMSS_BASE, 0x000e}, |
| 2775 | { &mdp_lcdc_clk.c, MMSS_BASE, 0x000f}, |
| 2776 | { &dsi_clk.c, MMSS_BASE, 0x0010}, |
| 2777 | { &dsi_byte_clk.c, MMSS_BASE, 0x0011}, |
| 2778 | { &dsi_esc_clk.c, MMSS_BASE, 0x0012}, |
| 2779 | { &dsi_ahb_clk.c, MMSS_BASE, 0x0013}, |
| 2780 | { &mclk0_clk.c, MMSS_BASE, 0x0015}, |
| 2781 | { &mclk1_clk.c, MMSS_BASE, 0x0016}, |
| 2782 | { &csi0phytimer_clk.c, MMSS_BASE, 0x0017}, |
| 2783 | { &csi1phytimer_clk.c, MMSS_BASE, 0x0018}, |
| 2784 | { &vfe_clk.c, MMSS_BASE, 0x0019}, |
| 2785 | { &vfe_ahb_clk.c, MMSS_BASE, 0x001a}, |
| 2786 | { &vfe_axi_clk.c, MMSS_BASE, 0x001b}, |
| 2787 | { &csi_vfe_clk.c, MMSS_BASE, 0x001c}, |
| 2788 | { &csi0_clk.c, MMSS_BASE, 0x001d}, |
| 2789 | { &csi_ahb_clk.c, MMSS_BASE, 0x001e}, |
| 2790 | { &csi0phy_clk.c, MMSS_BASE, 0x001f}, |
| 2791 | { &csi0rdi_clk.c, MMSS_BASE, 0x0020}, |
| 2792 | { &csi0pix_clk.c, MMSS_BASE, 0x0021}, |
| 2793 | { &csi1_clk.c, MMSS_BASE, 0x0022}, |
| 2794 | { &csi1phy_clk.c, MMSS_BASE, 0x0023}, |
| 2795 | { &csi1rdi_clk.c, MMSS_BASE, 0x0024}, |
| 2796 | { &csi1pix_clk.c, MMSS_BASE, 0x0025}, |
| 2797 | { &bimc_gfx_clk.c, MMSS_BASE, 0x0032}, |
| 2798 | |
| 2799 | { &lpaif_pcmoe_clk_src.c, LPASS_BASE, 0x000f}, |
| 2800 | { &lpaif_pcm1_clk_src.c, LPASS_BASE, 0x0012}, |
| 2801 | { &lpaif_pcm0_clk_src.c, LPASS_BASE, 0x0013}, |
| 2802 | { &lpaif_quad_clk_src.c, LPASS_BASE, 0x0014}, |
| 2803 | { &lpaif_ter_clk_src.c, LPASS_BASE, 0x0015}, |
| 2804 | { &lpaif_sec_clk_src.c, LPASS_BASE, 0x0016}, |
| 2805 | { &lpaif_pri_clk_src.c, LPASS_BASE, 0x0017}, |
| 2806 | { &lpaif_spkr_clk_src.c, LPASS_BASE, 0x0018}, |
| 2807 | { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d}, |
| 2808 | { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e}, |
| 2809 | { &audio_wrapper_br_clk.c, LPASS_BASE, 0x0022}, |
| 2810 | { &q6ss_xo_clk.c, LPASS_BASE, 0x002b}, |
| 2811 | {&audio_core_lpaif_pcm_data_oe_clk.c, LPASS_BASE, 0x0030}, |
| 2812 | { &audio_core_ixfabric_clk.c, LPASS_BASE, 0x0059}, |
| 2813 | |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 2814 | {&apc0_m_clk, APCS_BASE, 0x10}, |
| 2815 | {&apc1_m_clk, APCS_BASE, 0x11}, |
| 2816 | {&apc2_m_clk, APCS_BASE, 0x12}, |
| 2817 | {&apc3_m_clk, APCS_BASE, 0x13}, |
| 2818 | {&l2_m_clk, APCS_BASE, 0x15}, |
| 2819 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 2820 | {&dummy_clk, N_BASES, 0x0000}, |
| 2821 | }; |
| 2822 | |
| 2823 | #define GCC_DEBUG_CLK_CTL 0x1880 |
| 2824 | #define MMSS_DEBUG_CLK_CTL 0x0900 |
| 2825 | #define LPASS_DEBUG_CLK_CTL 0x29000 |
| 2826 | #define GLB_CLK_DIAG 0x001C |
| 2827 | |
| 2828 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
| 2829 | { |
| 2830 | struct measure_clk *clk = to_measure_clk(c); |
| 2831 | unsigned long flags; |
| 2832 | u32 regval, clk_sel, i; |
| 2833 | |
| 2834 | if (!parent) |
| 2835 | return -EINVAL; |
| 2836 | |
| 2837 | for (i = 0; i < (ARRAY_SIZE(measure_mux) - 1); i++) |
| 2838 | if (measure_mux[i].c == parent) |
| 2839 | break; |
| 2840 | |
| 2841 | if (measure_mux[i].c == &dummy_clk) |
| 2842 | return -EINVAL; |
| 2843 | |
| 2844 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 2845 | /* |
| 2846 | * Program the test vector, measurement period (sample_ticks) |
| 2847 | * and scaling multiplier. |
| 2848 | */ |
| 2849 | clk->sample_ticks = 0x10000; |
| 2850 | clk->multiplier = 1; |
| 2851 | |
| 2852 | switch (measure_mux[i].base) { |
| 2853 | |
| 2854 | case GCC_BASE: |
| 2855 | writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL)); |
| 2856 | clk_sel = measure_mux[i].debug_mux; |
| 2857 | break; |
| 2858 | |
| 2859 | case MMSS_BASE: |
| 2860 | writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL)); |
| 2861 | clk_sel = 0x02C; |
| 2862 | regval = BVAL(11, 0, measure_mux[i].debug_mux); |
| 2863 | writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL)); |
| 2864 | |
| 2865 | /* Activate debug clock output */ |
| 2866 | regval |= BIT(16); |
| 2867 | writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL)); |
| 2868 | break; |
| 2869 | |
| 2870 | case LPASS_BASE: |
| 2871 | writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL)); |
| 2872 | clk_sel = 0x161; |
| 2873 | regval = BVAL(11, 0, measure_mux[i].debug_mux); |
| 2874 | writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL)); |
| 2875 | |
| 2876 | /* Activate debug clock output */ |
| 2877 | regval |= BIT(20); |
| 2878 | writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL)); |
| 2879 | break; |
| 2880 | |
| 2881 | case APCS_BASE: |
| 2882 | clk->multiplier = 4; |
| 2883 | clk_sel = 0x16A; |
| 2884 | regval = measure_mux[i].debug_mux; |
| 2885 | writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG)); |
| 2886 | break; |
| 2887 | |
| 2888 | default: |
| 2889 | return -EINVAL; |
| 2890 | } |
| 2891 | |
| 2892 | /* Set debug mux clock index */ |
| 2893 | regval = BVAL(8, 0, clk_sel); |
| 2894 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL)); |
| 2895 | |
| 2896 | /* Activate debug clock output */ |
| 2897 | regval |= BIT(16); |
| 2898 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL)); |
| 2899 | |
| 2900 | /* Make sure test vector is set before starting measurements. */ |
| 2901 | mb(); |
| 2902 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2903 | |
| 2904 | return 0; |
| 2905 | } |
| 2906 | |
| 2907 | #define CLOCK_FRQ_MEASURE_CTL 0x1884 |
| 2908 | #define CLOCK_FRQ_MEASURE_STATUS 0x1888 |
| 2909 | |
| 2910 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 2911 | static u32 run_measurement(unsigned ticks) |
| 2912 | { |
| 2913 | /* Stop counters and set the XO4 counter start value. */ |
| 2914 | writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL)); |
| 2915 | |
| 2916 | /* Wait for timer to become ready. */ |
| 2917 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) & |
| 2918 | BIT(25)) != 0) |
| 2919 | cpu_relax(); |
| 2920 | |
| 2921 | /* Run measurement and wait for completion. */ |
| 2922 | writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL)); |
| 2923 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) & |
| 2924 | BIT(25)) == 0) |
| 2925 | cpu_relax(); |
| 2926 | |
| 2927 | /* Return measured ticks. */ |
| 2928 | return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) & |
| 2929 | BM(24, 0); |
| 2930 | } |
| 2931 | |
| 2932 | #define GCC_XO_DIV4_CBCR 0x10C8 |
| 2933 | #define PLLTEST_PAD_CFG 0x188C |
| 2934 | |
| 2935 | /* |
| 2936 | * Perform a hardware rate measurement for a given clock. |
| 2937 | * FOR DEBUG USE ONLY: Measurements take ~15 ms! |
| 2938 | */ |
| 2939 | static unsigned long measure_clk_get_rate(struct clk *c) |
| 2940 | { |
| 2941 | unsigned long flags; |
| 2942 | u32 gcc_xo4_reg_backup; |
| 2943 | u64 raw_count_short, raw_count_full; |
| 2944 | struct measure_clk *clk = to_measure_clk(c); |
| 2945 | unsigned ret; |
| 2946 | |
| 2947 | ret = clk_prepare_enable(&gcc_xo_clk_src.c); |
| 2948 | if (ret) { |
| 2949 | pr_warning("CXO clock failed to enable. Can't measure\n"); |
| 2950 | return 0; |
| 2951 | } |
| 2952 | |
| 2953 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 2954 | |
| 2955 | /* Enable CXO/4 and RINGOSC branch. */ |
| 2956 | gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR)); |
| 2957 | writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR)); |
| 2958 | |
| 2959 | /* |
| 2960 | * The ring oscillator counter will not reset if the measured clock |
| 2961 | * is not running. To detect this, run a short measurement before |
| 2962 | * the full measurement. If the raw results of the two are the same |
| 2963 | * then the clock must be off. |
| 2964 | */ |
| 2965 | |
| 2966 | /* Run a short measurement. (~1 ms) */ |
| 2967 | raw_count_short = run_measurement(0x1000); |
| 2968 | /* Run a full measurement. (~14 ms) */ |
| 2969 | raw_count_full = run_measurement(clk->sample_ticks); |
| 2970 | |
| 2971 | writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR)); |
| 2972 | |
| 2973 | /* Return 0 if the clock is off. */ |
| 2974 | if (raw_count_full == raw_count_short) { |
| 2975 | ret = 0; |
| 2976 | } else { |
| 2977 | /* Compute rate in Hz. */ |
| 2978 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
| 2979 | do_div(raw_count_full, ((clk->sample_ticks * 10) + 35)); |
| 2980 | ret = (raw_count_full * clk->multiplier); |
| 2981 | } |
| 2982 | |
| 2983 | writel_relaxed(0x51A00, GCC_REG_BASE(PLLTEST_PAD_CFG)); |
| 2984 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 2985 | |
| 2986 | clk_disable_unprepare(&gcc_xo_clk_src.c); |
| 2987 | |
| 2988 | return ret; |
| 2989 | } |
| 2990 | #else /* !CONFIG_DEBUG_FS */ |
| 2991 | static int measure_clk_set_parent(struct clk *clk, struct clk *parent) |
| 2992 | { |
| 2993 | return -EINVAL; |
| 2994 | } |
| 2995 | |
| 2996 | static unsigned long measure_clk_get_rate(struct clk *clk) |
| 2997 | { |
| 2998 | return 0; |
| 2999 | } |
| 3000 | #endif /* CONFIG_DEBUG_FS */ |
| 3001 | |
| 3002 | static struct clk_ops clk_ops_measure = { |
| 3003 | .set_parent = measure_clk_set_parent, |
| 3004 | .get_rate = measure_clk_get_rate, |
| 3005 | }; |
| 3006 | |
| 3007 | static struct measure_clk measure_clk = { |
| 3008 | .c = { |
| 3009 | .dbg_name = "measure_clk", |
| 3010 | .ops = &clk_ops_measure, |
| 3011 | CLK_INIT(measure_clk.c), |
| 3012 | }, |
| 3013 | .multiplier = 1, |
| 3014 | }; |
| 3015 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3016 | static struct clk_lookup msm_clocks_8610[] = { |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3017 | CLK_LOOKUP("xo", gcc_xo_clk_src.c, "msm_otg"), |
| 3018 | CLK_LOOKUP("xo", gcc_xo_clk_src.c, "fe200000.qcom,lpass"), |
| 3019 | CLK_LOOKUP("xo", gcc_xo_clk_src.c, "pil-q6v5-mss"), |
| 3020 | CLK_LOOKUP("xo", gcc_xo_clk_src.c, "pil-mba"), |
| 3021 | CLK_LOOKUP("xo", gcc_xo_clk_src.c, "fb000000.qcom,wcnss-wlan"), |
Vikram Mulukutla | 381df18 | 2013-01-28 11:39:51 -0800 | [diff] [blame] | 3022 | CLK_LOOKUP("xo", gcc_xo_clk_src.c, "fb21b000.qcom,pronto"), |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3023 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
| 3024 | |
| 3025 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"), |
| 3026 | CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"), |
| 3027 | |
| 3028 | CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"), |
| 3029 | CLK_LOOKUP("bus_clk", pnoc_qseecom_clk.c, "qseecom"), |
| 3030 | |
| 3031 | CLK_LOOKUP("bus_clk", snoc_clk.c, ""), |
| 3032 | CLK_LOOKUP("bus_clk", pnoc_clk.c, ""), |
| 3033 | CLK_LOOKUP("bus_clk", cnoc_clk.c, ""), |
| 3034 | CLK_LOOKUP("mem_clk", bimc_clk.c, ""), |
| 3035 | CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""), |
| 3036 | CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""), |
| 3037 | CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""), |
| 3038 | CLK_LOOKUP("mem_clk", bimc_a_clk.c, ""), |
| 3039 | |
| 3040 | CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"), |
| 3041 | CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"), |
| 3042 | CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"), |
| 3043 | CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"), |
| 3044 | CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"), |
| 3045 | CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"), |
| 3046 | CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"), |
| 3047 | CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"), |
| 3048 | CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""), |
| 3049 | |
| 3050 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tmc-etr"), |
| 3051 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tpiu"), |
| 3052 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-replicator"), |
| 3053 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-tmc-etf"), |
| 3054 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-merg"), |
| 3055 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-in0"), |
| 3056 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-in1"), |
| 3057 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-kpss"), |
| 3058 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-funnel-mmss"), |
| 3059 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-stm"), |
| 3060 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm0"), |
| 3061 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm1"), |
| 3062 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm2"), |
| 3063 | CLK_LOOKUP("core_clk", qdss_clk.c, "coresight-etm3"), |
| 3064 | |
| 3065 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tmc-etr"), |
| 3066 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tpiu"), |
| 3067 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-replicator"), |
| 3068 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-tmc-etf"), |
| 3069 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-merg"), |
| 3070 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-in0"), |
| 3071 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-in1"), |
| 3072 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-kpss"), |
| 3073 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-funnel-mmss"), |
| 3074 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-stm"), |
| 3075 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm0"), |
| 3076 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm1"), |
| 3077 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm2"), |
| 3078 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "coresight-etm3"), |
| 3079 | |
| 3080 | CLK_LOOKUP("core_clk_src", blsp1_qup1_spi_apps_clk_src.c, ""), |
| 3081 | CLK_LOOKUP("core_clk_src", blsp1_qup2_spi_apps_clk_src.c, ""), |
| 3082 | CLK_LOOKUP("core_clk_src", blsp1_qup3_spi_apps_clk_src.c, ""), |
| 3083 | CLK_LOOKUP("core_clk_src", blsp1_qup4_spi_apps_clk_src.c, ""), |
| 3084 | CLK_LOOKUP("core_clk_src", blsp1_qup5_spi_apps_clk_src.c, ""), |
| 3085 | CLK_LOOKUP("core_clk_src", blsp1_qup6_spi_apps_clk_src.c, ""), |
| 3086 | CLK_LOOKUP("core_clk_src", blsp1_uart1_apps_clk_src.c, ""), |
| 3087 | CLK_LOOKUP("core_clk_src", blsp1_uart2_apps_clk_src.c, ""), |
| 3088 | CLK_LOOKUP("core_clk_src", blsp1_uart3_apps_clk_src.c, ""), |
| 3089 | CLK_LOOKUP("core_clk_src", blsp1_uart4_apps_clk_src.c, ""), |
| 3090 | CLK_LOOKUP("core_clk_src", blsp1_uart5_apps_clk_src.c, ""), |
| 3091 | CLK_LOOKUP("core_clk_src", blsp1_uart6_apps_clk_src.c, ""), |
| 3092 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""), |
| 3093 | CLK_LOOKUP("core_clk_src", gp1_clk_src.c, ""), |
| 3094 | CLK_LOOKUP("core_clk_src", gp2_clk_src.c, ""), |
| 3095 | CLK_LOOKUP("core_clk_src", gp3_clk_src.c, ""), |
| 3096 | CLK_LOOKUP("core_clk_src", pdm2_clk_src.c, ""), |
| 3097 | CLK_LOOKUP("core_clk_src", sdcc1_apps_clk_src.c, ""), |
| 3098 | CLK_LOOKUP("core_clk_src", sdcc2_apps_clk_src.c, ""), |
| 3099 | CLK_LOOKUP("core_clk_src", usb_hs_system_clk_src.c, ""), |
| 3100 | |
| 3101 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, ""), |
| 3102 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""), |
| 3103 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, ""), |
| 3104 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""), |
| 3105 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""), |
| 3106 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, ""), |
| 3107 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""), |
| 3108 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""), |
| 3109 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""), |
| 3110 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""), |
| 3111 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""), |
| 3112 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""), |
| 3113 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""), |
| 3114 | CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""), |
| 3115 | CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, ""), |
| 3116 | CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, ""), |
| 3117 | CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""), |
| 3118 | CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""), |
| 3119 | CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""), |
| 3120 | CLK_LOOKUP("iface_clk", gcc_boot_rom_ahb_clk.c, ""), |
| 3121 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, ""), |
| 3122 | CLK_LOOKUP("core_clk", gcc_ce1_axi_clk.c, ""), |
| 3123 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, ""), |
| 3124 | CLK_LOOKUP("iface_clk", gcc_copss_smmu_ahb_clk.c, ""), |
| 3125 | CLK_LOOKUP("iface_clk", gcc_lpss_smmu_ahb_clk.c, ""), |
| 3126 | CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""), |
| 3127 | CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""), |
| 3128 | CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""), |
| 3129 | CLK_LOOKUP("core_clk", gcc_lpass_q6_axi_clk.c, ""), |
| 3130 | CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, ""), |
| 3131 | CLK_LOOKUP("core_clk", gcc_mss_q6_bimc_axi_clk.c, ""), |
| 3132 | CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""), |
| 3133 | CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""), |
| 3134 | CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""), |
| 3135 | CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"), |
| 3136 | CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"), |
| 3137 | CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"), |
| 3138 | CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"), |
| 3139 | CLK_LOOKUP("core_clk", gcc_usb2a_phy_sleep_clk.c, ""), |
| 3140 | CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"), |
| 3141 | CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"), |
| 3142 | |
| 3143 | CLK_LOOKUP("core_clk_src", csi0_clk_src.c, ""), |
| 3144 | CLK_LOOKUP("core_clk_src", axi_clk_src.c, ""), |
Vikram Mulukutla | e1e5c48 | 2013-01-28 14:43:20 -0800 | [diff] [blame] | 3145 | CLK_LOOKUP("", mdp_axi_clk_src.c, ""), |
| 3146 | CLK_LOOKUP("", mmssnoc_axi_clk_src.c, ""), |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3147 | CLK_LOOKUP("core_clk_src", dsi_pclk_clk_src.c, ""), |
| 3148 | CLK_LOOKUP("core_clk_src", gfx3d_clk_src.c, ""), |
| 3149 | CLK_LOOKUP("core_clk_src", vfe_clk_src.c, ""), |
| 3150 | CLK_LOOKUP("core_clk_src", csi1_clk_src.c, ""), |
| 3151 | CLK_LOOKUP("core_clk_src", csi0phytimer_clk_src.c, ""), |
| 3152 | CLK_LOOKUP("core_clk_src", csi1phytimer_clk_src.c, ""), |
| 3153 | CLK_LOOKUP("core_clk_src", dsi_clk_src.c, ""), |
| 3154 | CLK_LOOKUP("core_clk_src", dsi_byte_clk_src.c, ""), |
| 3155 | CLK_LOOKUP("core_clk_src", dsi_esc_clk_src.c, ""), |
| 3156 | CLK_LOOKUP("core_clk_src", mclk0_clk_src.c, ""), |
| 3157 | CLK_LOOKUP("core_clk_src", mclk1_clk_src.c, ""), |
| 3158 | CLK_LOOKUP("core_clk_src", mdp_vsync_clk_src.c, ""), |
| 3159 | |
| 3160 | CLK_LOOKUP("core_clk", bimc_gfx_clk.c, ""), |
| 3161 | CLK_LOOKUP("core_clk", csi0_clk.c, ""), |
| 3162 | CLK_LOOKUP("core_clk", csi0phy_clk.c, ""), |
| 3163 | CLK_LOOKUP("core_clk", csi0phytimer_clk.c, ""), |
| 3164 | CLK_LOOKUP("core_clk", csi0pix_clk.c, ""), |
| 3165 | CLK_LOOKUP("core_clk", csi0rdi_clk.c, ""), |
| 3166 | CLK_LOOKUP("core_clk", csi1_clk.c, ""), |
| 3167 | CLK_LOOKUP("core_clk", csi1phy_clk.c, ""), |
| 3168 | CLK_LOOKUP("core_clk", csi1phytimer_clk.c, ""), |
| 3169 | CLK_LOOKUP("core_clk", csi1pix_clk.c, ""), |
| 3170 | CLK_LOOKUP("core_clk", csi1rdi_clk.c, ""), |
| 3171 | CLK_LOOKUP("core_clk", csi_ahb_clk.c, ""), |
| 3172 | CLK_LOOKUP("core_clk", csi_vfe_clk.c, ""), |
| 3173 | CLK_LOOKUP("core_clk", dsi_clk.c, ""), |
| 3174 | CLK_LOOKUP("core_clk", dsi_ahb_clk.c, ""), |
| 3175 | CLK_LOOKUP("core_clk", dsi_byte_clk.c, ""), |
| 3176 | CLK_LOOKUP("core_clk", dsi_esc_clk.c, ""), |
| 3177 | CLK_LOOKUP("core_clk", dsi_pclk_clk.c, ""), |
| 3178 | CLK_LOOKUP("core_clk", gmem_gfx3d_clk.c, ""), |
| 3179 | CLK_LOOKUP("core_clk", mclk0_clk.c, ""), |
| 3180 | CLK_LOOKUP("core_clk", mclk1_clk.c, ""), |
| 3181 | CLK_LOOKUP("core_clk", mdp_ahb_clk.c, ""), |
| 3182 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""), |
| 3183 | CLK_LOOKUP("core_clk", mdp_dsi_clk.c, ""), |
| 3184 | CLK_LOOKUP("core_clk", mdp_lcdc_clk.c, ""), |
| 3185 | CLK_LOOKUP("core_clk", mdp_vsync_clk.c, ""), |
| 3186 | CLK_LOOKUP("core_clk", mmss_misc_ahb_clk.c, ""), |
| 3187 | CLK_LOOKUP("core_clk", mmss_s0_axi_clk.c, ""), |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3188 | CLK_LOOKUP("core_clk", mmss_mmssnoc_bto_ahb_clk.c, ""), |
| 3189 | CLK_LOOKUP("core_clk", mmss_mmssnoc_axi_clk.c, ""), |
| 3190 | CLK_LOOKUP("core_clk", vfe_clk.c, ""), |
| 3191 | CLK_LOOKUP("core_clk", vfe_ahb_clk.c, ""), |
| 3192 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""), |
| 3193 | |
| 3194 | CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdc00000.qcom,kgsl-3d0"), |
| 3195 | CLK_LOOKUP("iface_clk", oxili_ahb_clk.c, "fdc00000.qcom,kgsl-3d0"), |
| 3196 | CLK_LOOKUP("mem_iface_clk", bimc_gfx_clk.c, "fdc00000.qcom,kgsl-3d0"), |
| 3197 | CLK_LOOKUP("mem_clk", gmem_gfx3d_clk.c, "fdc00000.qcom,kgsl-3d0"), |
| 3198 | |
| 3199 | CLK_LOOKUP("iface_clk", vfe_ahb_clk.c, "fd890000.qcom,iommu"), |
| 3200 | CLK_LOOKUP("core_clk", vfe_axi_clk.c, "fd890000.qcom,iommu"), |
| 3201 | CLK_LOOKUP("iface_clk", mdp_ahb_clk.c, "fd860000.qcom,iommu"), |
| 3202 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "fd860000.qcom,iommu"), |
| 3203 | CLK_LOOKUP("iface_clk", mdp_ahb_clk.c, "fd870000.qcom,iommu"), |
| 3204 | CLK_LOOKUP("core_clk", mdp_axi_clk.c, "fd870000.qcom,iommu"), |
| 3205 | CLK_LOOKUP("iface_clk", oxili_ahb_clk.c, "fd880000.qcom,iommu"), |
| 3206 | CLK_LOOKUP("core_clk", bimc_gfx_clk.c, "fd880000.qcom,iommu"), |
| 3207 | CLK_LOOKUP("iface_clk", gcc_lpss_smmu_ahb_clk.c, "fd000000.qcom,iommu"), |
| 3208 | CLK_LOOKUP("core_clk", gcc_lpass_q6_axi_clk.c, "fd000000.qcom,iommu"), |
| 3209 | CLK_LOOKUP("iface_clk", gcc_copss_smmu_ahb_clk.c, |
| 3210 | "fd010000.qcom,iommu"), |
| 3211 | CLK_LOOKUP("core_clk", pnoc_iommu_clk.c, "fd010000.qcom,iommu"), |
| 3212 | |
| 3213 | CLK_LOOKUP("core_clk_src", lpaif_pri_clk_src.c, ""), |
| 3214 | CLK_LOOKUP("core_clk_src", lpaif_quad_clk_src.c, ""), |
| 3215 | CLK_LOOKUP("core_clk_src", lpaif_sec_clk_src.c, ""), |
| 3216 | CLK_LOOKUP("core_clk_src", lpaif_spkr_clk_src.c, ""), |
| 3217 | CLK_LOOKUP("core_clk_src", lpaif_ter_clk_src.c, ""), |
| 3218 | CLK_LOOKUP("core_clk_src", lpaif_pcm0_clk_src.c, ""), |
| 3219 | CLK_LOOKUP("core_clk_src", lpaif_pcm1_clk_src.c, ""), |
| 3220 | CLK_LOOKUP("core_clk_src", lpaif_pcmoe_clk_src.c, ""), |
| 3221 | CLK_LOOKUP("core_clk", audio_core_ixfabric_clk.c, ""), |
| 3222 | CLK_LOOKUP("core_clk", audio_wrapper_br_clk.c, ""), |
| 3223 | CLK_LOOKUP("core_clk", q6ss_ahb_lfabif_clk.c, ""), |
| 3224 | CLK_LOOKUP("core_clk", q6ss_ahbm_clk.c, ""), |
| 3225 | CLK_LOOKUP("core_clk", q6ss_xo_clk.c, ""), |
| 3226 | CLK_LOOKUP("core_clk", audio_core_lpaif_pcm_data_oe_clk.c, ""), |
| 3227 | CLK_LOOKUP("core_clk", audio_core_lpaif_pri_ebit_clk.c, ""), |
| 3228 | CLK_LOOKUP("core_clk", audio_core_lpaif_pri_ibit_clk.c, ""), |
| 3229 | CLK_LOOKUP("core_clk", audio_core_lpaif_pri_osr_clk.c, ""), |
| 3230 | CLK_LOOKUP("core_clk", audio_core_lpaif_pcm0_ebit_clk.c, ""), |
| 3231 | CLK_LOOKUP("core_clk", audio_core_lpaif_pcm0_ibit_clk.c, ""), |
| 3232 | CLK_LOOKUP("core_clk", audio_core_lpaif_quad_ebit_clk.c, ""), |
| 3233 | CLK_LOOKUP("core_clk", audio_core_lpaif_quad_ibit_clk.c, ""), |
| 3234 | CLK_LOOKUP("core_clk", audio_core_lpaif_quad_osr_clk.c, ""), |
| 3235 | CLK_LOOKUP("core_clk", audio_core_lpaif_sec_ebit_clk.c, ""), |
| 3236 | CLK_LOOKUP("core_clk", audio_core_lpaif_sec_ibit_clk.c, ""), |
| 3237 | CLK_LOOKUP("core_clk", audio_core_lpaif_sec_osr_clk.c, ""), |
| 3238 | CLK_LOOKUP("core_clk", audio_core_lpaif_pcm1_ebit_clk.c, ""), |
| 3239 | CLK_LOOKUP("core_clk", audio_core_lpaif_pcm1_ibit_clk.c, ""), |
| 3240 | CLK_LOOKUP("core_clk", audio_core_lpaif_codec_spkr_ebit_clk.c, ""), |
| 3241 | CLK_LOOKUP("core_clk", audio_core_lpaif_codec_spkr_ibit_clk.c, ""), |
| 3242 | CLK_LOOKUP("core_clk", audio_core_lpaif_codec_spkr_osr_clk.c, ""), |
| 3243 | CLK_LOOKUP("core_clk", audio_core_lpaif_ter_ebit_clk.c, ""), |
| 3244 | CLK_LOOKUP("core_clk", audio_core_lpaif_ter_ibit_clk.c, ""), |
| 3245 | CLK_LOOKUP("core_clk", audio_core_lpaif_ter_osr_clk.c, ""), |
| 3246 | |
| 3247 | CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"), |
| 3248 | CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"), |
| 3249 | CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"), |
| 3250 | CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"), |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 3251 | |
| 3252 | CLK_LOOKUP("xo", gcc_xo_a_clk_src.c, "f9011050.qcom,acpuclk"), |
| 3253 | CLK_LOOKUP("gpll0", gpll0_ao_clk_src.c, "f9011050.qcom,acpuclk"), |
| 3254 | CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"), |
| 3255 | |
| 3256 | CLK_LOOKUP("measure_clk", apc0_m_clk, ""), |
| 3257 | CLK_LOOKUP("measure_clk", apc1_m_clk, ""), |
| 3258 | CLK_LOOKUP("measure_clk", apc2_m_clk, ""), |
| 3259 | CLK_LOOKUP("measure_clk", apc3_m_clk, ""), |
| 3260 | CLK_LOOKUP("measure_clk", l2_m_clk, ""), |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3261 | }; |
| 3262 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3263 | static struct clk_lookup msm_clocks_8610_rumi[] = { |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3264 | CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF), |
| 3265 | CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF), |
| 3266 | CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF), |
| 3267 | CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF), |
| 3268 | CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF), |
| 3269 | CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF), |
| 3270 | CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF), |
| 3271 | CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF), |
| 3272 | CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF), |
| 3273 | CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF), |
| 3274 | CLK_DUMMY("dfab_clk", DFAB_CLK, "msm_sps", OFF), |
| 3275 | CLK_DUMMY("iface_clk", NULL, "fd890000.qcom,iommu", OFF), |
| 3276 | CLK_DUMMY("core_clk", NULL, "fd890000.qcom,iommu", OFF), |
| 3277 | CLK_DUMMY("iface_clk", NULL, "fd860000.qcom,iommu", OFF), |
| 3278 | CLK_DUMMY("core_clk", NULL, "fd860000.qcom,iommu", OFF), |
| 3279 | CLK_DUMMY("iface_clk", NULL, "fd870000.qcom,iommu", OFF), |
| 3280 | CLK_DUMMY("core_clk", NULL, "fd870000.qcom,iommu", OFF), |
| 3281 | CLK_DUMMY("iface_clk", NULL, "fd880000.qcom,iommu", OFF), |
| 3282 | CLK_DUMMY("core_clk", NULL, "fd880000.qcom,iommu", OFF), |
| 3283 | CLK_DUMMY("iface_clk", NULL, "fd000000.qcom,iommu", OFF), |
| 3284 | CLK_DUMMY("core_clk", NULL, "fd000000.qcom,iommu", OFF), |
| 3285 | CLK_DUMMY("iface_clk", NULL, "fd010000.qcom,iommu", OFF), |
| 3286 | CLK_DUMMY("core_clk", NULL, "fd010000.qcom,iommu", OFF), |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 3287 | CLK_DUMMY("xo", NULL, "f9011050.qcom,acpuclk", OFF), |
| 3288 | CLK_DUMMY("gpll0", NULL, "f9011050.qcom,acpuclk", OFF), |
| 3289 | CLK_DUMMY("a7sspll", NULL, "f9011050.qcom,acpuclk", OFF), |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3290 | }; |
| 3291 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3292 | struct clock_init_data msm8610_rumi_clock_init_data __initdata = { |
| 3293 | .table = msm_clocks_8610_rumi, |
| 3294 | .size = ARRAY_SIZE(msm_clocks_8610_rumi), |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3295 | }; |
| 3296 | |
| 3297 | static struct pll_config_regs gpll0_regs __initdata = { |
| 3298 | .l_reg = (void __iomem *)GPLL0_L_VAL, |
| 3299 | .m_reg = (void __iomem *)GPLL0_M_VAL, |
| 3300 | .n_reg = (void __iomem *)GPLL0_N_VAL, |
| 3301 | .config_reg = (void __iomem *)GPLL0_USER_CTL, |
| 3302 | .mode_reg = (void __iomem *)GPLL0_MODE, |
| 3303 | .base = &virt_bases[GCC_BASE], |
| 3304 | }; |
| 3305 | |
| 3306 | /* GPLL0 at 600 MHz, main output enabled. */ |
| 3307 | static struct pll_config gpll0_config __initdata = { |
| 3308 | .l = 0x1f, |
| 3309 | .m = 0x1, |
| 3310 | .n = 0x4, |
| 3311 | .vco_val = 0x0, |
| 3312 | .vco_mask = BM(21, 20), |
| 3313 | .pre_div_val = 0x0, |
| 3314 | .pre_div_mask = BM(14, 12), |
| 3315 | .post_div_val = 0x0, |
| 3316 | .post_div_mask = BM(9, 8), |
| 3317 | .mn_ena_val = BIT(24), |
| 3318 | .mn_ena_mask = BIT(24), |
| 3319 | .main_output_val = BIT(0), |
| 3320 | .main_output_mask = BIT(0), |
| 3321 | }; |
| 3322 | |
| 3323 | /* MMPLL0 at 800 MHz, main output enabled. */ |
| 3324 | static struct pll_config mmpll0_config __initdata = { |
| 3325 | .l = 0x29, |
| 3326 | .m = 0x2, |
| 3327 | .n = 0x3, |
| 3328 | .vco_val = 0x0, |
| 3329 | .vco_mask = BM(21, 20), |
| 3330 | .pre_div_val = 0x0, |
| 3331 | .pre_div_mask = BM(14, 12), |
| 3332 | .post_div_val = 0x0, |
| 3333 | .post_div_mask = BM(9, 8), |
| 3334 | .mn_ena_val = BIT(24), |
| 3335 | .mn_ena_mask = BIT(24), |
| 3336 | .main_output_val = BIT(0), |
| 3337 | .main_output_mask = BIT(0), |
| 3338 | }; |
| 3339 | |
| 3340 | /* MMPLL1 at 1200 MHz, main output enabled. */ |
| 3341 | static struct pll_config mmpll1_config __initdata = { |
| 3342 | .l = 0x3E, |
| 3343 | .m = 0x1, |
| 3344 | .n = 0x2, |
| 3345 | .vco_val = 0x0, |
| 3346 | .vco_mask = BM(21, 20), |
| 3347 | .pre_div_val = 0x0, |
| 3348 | .pre_div_mask = BM(14, 12), |
| 3349 | .post_div_val = 0x0, |
| 3350 | .post_div_mask = BM(9, 8), |
| 3351 | .mn_ena_val = BIT(24), |
| 3352 | .mn_ena_mask = BIT(24), |
| 3353 | .main_output_val = BIT(0), |
| 3354 | .main_output_mask = BIT(0), |
| 3355 | }; |
| 3356 | |
| 3357 | static struct pll_config_regs lpapll0_regs __initdata = { |
| 3358 | .l_reg = (void __iomem *)LPAAUDIO_PLL_L_VAL, |
| 3359 | .m_reg = (void __iomem *)LPAAUDIO_PLL_M_VAL, |
| 3360 | .n_reg = (void __iomem *)LPAAUDIO_PLL_N_VAL, |
| 3361 | .config_reg = (void __iomem *)LPAAUDIO_PLL_USER_CTL, |
| 3362 | .mode_reg = (void __iomem *)LPAAUDIO_PLL_MODE, |
| 3363 | .base = &virt_bases[LPASS_BASE], |
| 3364 | }; |
| 3365 | |
| 3366 | /* LPAPLL0 at 491.52 MHz, main output enabled. */ |
| 3367 | static struct pll_config lpapll0_config __initdata = { |
| 3368 | .l = 0x33, |
| 3369 | .m = 0x1, |
| 3370 | .n = 0x5, |
| 3371 | .vco_val = 0x0, |
| 3372 | .vco_mask = BM(21, 20), |
| 3373 | .pre_div_val = BVAL(14, 12, 0x1), |
| 3374 | .pre_div_mask = BM(14, 12), |
| 3375 | .post_div_val = 0x0, |
| 3376 | .post_div_mask = BM(9, 8), |
| 3377 | .mn_ena_val = BIT(24), |
| 3378 | .mn_ena_mask = BIT(24), |
| 3379 | .main_output_val = BIT(0), |
| 3380 | .main_output_mask = BIT(0), |
| 3381 | }; |
| 3382 | |
| 3383 | #define PLL_AUX_OUTPUT_BIT 1 |
| 3384 | #define PLL_AUX2_OUTPUT_BIT 2 |
| 3385 | |
| 3386 | #define PWR_ON_MASK BIT(31) |
| 3387 | #define EN_REST_WAIT_MASK (0xF << 20) |
| 3388 | #define EN_FEW_WAIT_MASK (0xF << 16) |
| 3389 | #define CLK_DIS_WAIT_MASK (0xF << 12) |
| 3390 | #define SW_OVERRIDE_MASK BIT(2) |
| 3391 | #define HW_CONTROL_MASK BIT(1) |
| 3392 | #define SW_COLLAPSE_MASK BIT(0) |
| 3393 | |
| 3394 | /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ |
| 3395 | #define EN_REST_WAIT_VAL (0x2 << 20) |
| 3396 | #define EN_FEW_WAIT_VAL (0x2 << 16) |
| 3397 | #define CLK_DIS_WAIT_VAL (0x2 << 12) |
| 3398 | #define GDSC_TIMEOUT_US 50000 |
| 3399 | |
| 3400 | static void __init reg_init(void) |
| 3401 | { |
| 3402 | u32 regval, status; |
| 3403 | int ret; |
| 3404 | |
| 3405 | if (!(readl_relaxed(GCC_REG_BASE(GPLL0_STATUS)) |
| 3406 | & gpll0_clk_src.status_mask)) |
| 3407 | configure_sr_hpm_lp_pll(&gpll0_config, &gpll0_regs, 1); |
| 3408 | |
| 3409 | configure_sr_hpm_lp_pll(&mmpll0_config, &mmpll0_regs, 1); |
| 3410 | configure_sr_hpm_lp_pll(&mmpll1_config, &mmpll1_regs, 1); |
| 3411 | configure_sr_hpm_lp_pll(&lpapll0_config, &lpapll0_regs, 1); |
| 3412 | |
| 3413 | /* Enable GPLL0's aux outputs. */ |
| 3414 | regval = readl_relaxed(GCC_REG_BASE(GPLL0_USER_CTL)); |
| 3415 | regval |= BIT(PLL_AUX_OUTPUT_BIT) | BIT(PLL_AUX2_OUTPUT_BIT); |
| 3416 | writel_relaxed(regval, GCC_REG_BASE(GPLL0_USER_CTL)); |
| 3417 | |
| 3418 | /* Vote for GPLL0 to turn on. Needed by acpuclock. */ |
| 3419 | regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE)); |
| 3420 | regval |= BIT(0); |
| 3421 | writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE)); |
| 3422 | |
| 3423 | /* |
| 3424 | * TODO: Confirm that no clocks need to be voted on in this sleep vote |
| 3425 | * register. |
| 3426 | */ |
| 3427 | writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE)); |
| 3428 | |
| 3429 | /* |
| 3430 | * TODO: The following sequence enables the LPASS audio core GDSC. |
| 3431 | * Remove when this becomes unnecessary. |
| 3432 | */ |
| 3433 | |
| 3434 | /* |
| 3435 | * Disable HW trigger: collapse/restore occur based on registers writes. |
| 3436 | * Disable SW override: Use hardware state-machine for sequencing. |
| 3437 | */ |
| 3438 | regval = readl_relaxed(LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 3439 | regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK); |
| 3440 | |
| 3441 | /* Configure wait time between states. */ |
| 3442 | regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK); |
| 3443 | regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL; |
| 3444 | writel_relaxed(regval, LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 3445 | |
| 3446 | regval = readl_relaxed(LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 3447 | regval &= ~BIT(0); |
| 3448 | writel_relaxed(regval, LPASS_REG_BASE(AUDIO_CORE_GDSCR)); |
| 3449 | |
| 3450 | ret = readl_poll_timeout(LPASS_REG_BASE(AUDIO_CORE_GDSCR), status, |
| 3451 | status & PWR_ON_MASK, 50, GDSC_TIMEOUT_US); |
| 3452 | WARN(ret, "LPASS Audio Core GDSC did not power on.\n"); |
| 3453 | } |
| 3454 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3455 | static void __init msm8610_clock_post_init(void) |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3456 | { |
| 3457 | /* |
| 3458 | * Hold an active set vote for CXO; this is because CXO is expected |
| 3459 | * to remain on whenever CPUs aren't power collapsed. |
| 3460 | */ |
| 3461 | clk_prepare_enable(&gcc_xo_a_clk_src.c); |
| 3462 | |
| 3463 | |
| 3464 | /* Set rates for single-rate clocks. */ |
| 3465 | clk_set_rate(&usb_hs_system_clk_src.c, |
| 3466 | usb_hs_system_clk_src.freq_tbl[0].freq_hz); |
| 3467 | clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz); |
| 3468 | clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz); |
| 3469 | clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz); |
| 3470 | clk_set_rate(&audio_core_slimbus_core_clk_src.c, |
| 3471 | audio_core_slimbus_core_clk_src.freq_tbl[0].freq_hz); |
| 3472 | } |
| 3473 | |
| 3474 | #define GCC_CC_PHYS 0xFC400000 |
| 3475 | #define GCC_CC_SIZE SZ_16K |
| 3476 | |
| 3477 | #define MMSS_CC_PHYS 0xFD8C0000 |
| 3478 | #define MMSS_CC_SIZE SZ_256K |
| 3479 | |
| 3480 | #define LPASS_CC_PHYS 0xFE000000 |
| 3481 | #define LPASS_CC_SIZE SZ_256K |
| 3482 | |
| 3483 | #define APCS_GCC_CC_PHYS 0xF9011000 |
| 3484 | #define APCS_GCC_CC_SIZE SZ_4K |
| 3485 | |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 3486 | #define APCS_KPSS_SH_PLL_PHYS 0xF9016000 |
| 3487 | #define APCS_KPSS_SH_PLL_SIZE SZ_64 |
| 3488 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3489 | static void __init msm8610_clock_pre_init(void) |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3490 | { |
| 3491 | virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE); |
| 3492 | if (!virt_bases[GCC_BASE]) |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3493 | panic("clock-8610: Unable to ioremap GCC memory!"); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3494 | |
| 3495 | virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE); |
| 3496 | if (!virt_bases[MMSS_BASE]) |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3497 | panic("clock-8610: Unable to ioremap MMSS_CC memory!"); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3498 | |
| 3499 | virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE); |
| 3500 | if (!virt_bases[LPASS_BASE]) |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3501 | panic("clock-8610: Unable to ioremap LPASS_CC memory!"); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3502 | |
| 3503 | virt_bases[APCS_BASE] = ioremap(APCS_GCC_CC_PHYS, APCS_GCC_CC_SIZE); |
| 3504 | if (!virt_bases[APCS_BASE]) |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3505 | panic("clock-8610: Unable to ioremap APCS_GCC_CC memory!"); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3506 | |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 3507 | virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS, |
| 3508 | APCS_KPSS_SH_PLL_SIZE); |
| 3509 | if (!virt_bases[APCS_PLL_BASE]) |
| 3510 | panic("clock-8610: Unable to ioremap APCS_GCC_CC memory!"); |
| 3511 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3512 | clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable; |
| 3513 | |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 3514 | vdd_dig_reg = regulator_get(NULL, "vdd_dig"); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3515 | if (IS_ERR(vdd_dig_reg)) |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3516 | panic("clock-8610: Unable to get the vdd_dig regulator!"); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3517 | |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 3518 | vdd_sr2_reg = regulator_get(NULL, "vdd_sr2_pll"); |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 3519 | if (IS_ERR(vdd_sr2_reg)) |
| 3520 | panic("clock-8610: Unable to get the vdd_sr2_pll regulator!"); |
| 3521 | |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 3522 | regulator_set_voltage(vdd_sr2_reg, 1800000, 1800000); |
| 3523 | regulator_enable(vdd_sr2_reg); |
Vikram Mulukutla | 4157cca | 2013-01-24 15:42:41 -0800 | [diff] [blame] | 3524 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3525 | /* |
| 3526 | * TODO: Set a voltage and enable vdd_dig, leaving the voltage high |
| 3527 | * until late_init. This may not be necessary with clock handoff; |
| 3528 | * Investigate this code on a real non-simulator target to determine |
| 3529 | * its necessity. |
| 3530 | */ |
| 3531 | vote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
Vikram Mulukutla | f7c52d3 | 2013-01-31 11:39:58 -0800 | [diff] [blame^] | 3532 | regulator_enable(vdd_dig_reg); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3533 | |
| 3534 | enable_rpm_scaling(); |
| 3535 | |
| 3536 | /* Enable a clock to allow access to MMSS clock registers */ |
| 3537 | clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c), |
| 3538 | |
| 3539 | reg_init(); |
| 3540 | |
Vikram Mulukutla | 82cb844 | 2013-01-28 13:36:51 -0800 | [diff] [blame] | 3541 | /* Maintain the max nominal frequency on the MMSSNOC AHB bus. */ |
| 3542 | clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000); |
| 3543 | clk_prepare_enable(&mmssnoc_ahb_a_clk.c); |
| 3544 | |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3545 | /* TODO: Remove this once the bus driver is in place */ |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3546 | clk_set_rate(&axi_clk_src.c, 200000000); |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3547 | clk_prepare_enable(&mmss_s0_axi_clk.c); |
| 3548 | |
| 3549 | /* TODO: Temporarily enable a clock to allow access to LPASS core |
| 3550 | * registers. |
| 3551 | */ |
| 3552 | clk_prepare_enable(&audio_core_ixfabric_clk.c); |
| 3553 | } |
| 3554 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3555 | static int __init msm8610_clock_late_init(void) |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3556 | { |
| 3557 | return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH); |
| 3558 | } |
| 3559 | |
Syed Rameez Mustafa | 3971c14 | 2013-01-09 19:04:53 -0800 | [diff] [blame] | 3560 | struct clock_init_data msm8610_clock_init_data __initdata = { |
| 3561 | .table = msm_clocks_8610, |
| 3562 | .size = ARRAY_SIZE(msm_clocks_8610), |
| 3563 | .pre_init = msm8610_clock_pre_init, |
| 3564 | .post_init = msm8610_clock_post_init, |
| 3565 | .late_init = msm8610_clock_late_init, |
Vikram Mulukutla | b13abe4 | 2012-10-03 11:38:48 -0700 | [diff] [blame] | 3566 | }; |