blob: 86d39cb35fe29e39e3377a826a2f6f08313b39a7 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +100028#include <linux/firmware.h>
29#include <linux/platform_device.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020030#include "drmP.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000032#include "radeon_asic.h"
Dave Airlie4153e582009-09-18 18:41:24 +100033#include "radeon_drm.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100034#include "rv770d.h"
Jerome Glisse3ce0a232009-09-08 10:10:24 +100035#include "atom.h"
Jerome Glissed39c3b82009-09-28 18:34:43 +020036#include "avivod.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037
Jerome Glisse3ce0a232009-09-08 10:10:24 +100038#define R700_PFP_UCODE_SIZE 848
39#define R700_PM4_UCODE_SIZE 1360
Jerome Glisse771fe6b2009-06-05 14:42:42 +020040
Jerome Glisse3ce0a232009-09-08 10:10:24 +100041static void rv770_gpu_init(struct radeon_device *rdev);
42void rv770_fini(struct radeon_device *rdev);
43
44
45/*
46 * GART
Jerome Glisse771fe6b2009-06-05 14:42:42 +020047 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +100048int rv770_pcie_gart_enable(struct radeon_device *rdev)
49{
50 u32 tmp;
51 int r, i;
52
Jerome Glisse4aac0472009-09-14 18:29:49 +020053 if (rdev->gart.table.vram.robj == NULL) {
54 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
55 return -EINVAL;
Jerome Glisse3ce0a232009-09-08 10:10:24 +100056 }
Jerome Glisse4aac0472009-09-14 18:29:49 +020057 r = radeon_gart_table_vram_pin(rdev);
58 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +100059 return r;
Dave Airlie82568562010-02-05 16:00:07 +100060 radeon_gart_restore(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +100061 /* Setup L2 cache */
62 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
63 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
64 EFFECTIVE_L2_QUEUE_SIZE(7));
65 WREG32(VM_L2_CNTL2, 0);
66 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
67 /* Setup TLB control */
68 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
69 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
70 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
71 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
72 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
73 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
74 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
75 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
76 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
77 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
78 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
79 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
Jerome Glisse1a029b72009-10-06 19:04:30 +020080 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
Jerome Glisse3ce0a232009-09-08 10:10:24 +100081 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
82 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
83 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
84 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
85 (u32)(rdev->dummy_page.addr >> 12));
86 for (i = 1; i < 7; i++)
87 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
88
89 r600_pcie_gart_tlb_flush(rdev);
90 rdev->gart.ready = true;
91 return 0;
92}
93
94void rv770_pcie_gart_disable(struct radeon_device *rdev)
95{
96 u32 tmp;
Jerome Glisse4c788672009-11-20 14:29:23 +010097 int i, r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +100098
Jerome Glisse3ce0a232009-09-08 10:10:24 +100099 /* Disable all tables */
100 for (i = 0; i < 7; i++)
101 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
102
103 /* Setup L2 cache */
104 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
105 EFFECTIVE_L2_QUEUE_SIZE(7));
106 WREG32(VM_L2_CNTL2, 0);
107 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
108 /* Setup TLB control */
109 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
110 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
111 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
112 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
113 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
114 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
115 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
116 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
Jerome Glisse4aac0472009-09-14 18:29:49 +0200117 if (rdev->gart.table.vram.robj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100118 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
119 if (likely(r == 0)) {
120 radeon_bo_kunmap(rdev->gart.table.vram.robj);
121 radeon_bo_unpin(rdev->gart.table.vram.robj);
122 radeon_bo_unreserve(rdev->gart.table.vram.robj);
123 }
Jerome Glisse4aac0472009-09-14 18:29:49 +0200124 }
125}
126
127void rv770_pcie_gart_fini(struct radeon_device *rdev)
128{
129 rv770_pcie_gart_disable(rdev);
130 radeon_gart_table_vram_free(rdev);
131 radeon_gart_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000132}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200133
134
Jerome Glisse1a029b72009-10-06 19:04:30 +0200135void rv770_agp_enable(struct radeon_device *rdev)
136{
137 u32 tmp;
138 int i;
139
140 /* Setup L2 cache */
141 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
142 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
143 EFFECTIVE_L2_QUEUE_SIZE(7));
144 WREG32(VM_L2_CNTL2, 0);
145 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
146 /* Setup TLB control */
147 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
148 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
149 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
150 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
151 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
152 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
153 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
154 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
155 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
156 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
157 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
158 for (i = 0; i < 7; i++)
159 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
160}
161
Jerome Glissea3c19452009-10-01 18:02:13 +0200162static void rv770_mc_program(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163{
Jerome Glissea3c19452009-10-01 18:02:13 +0200164 struct rv515_mc_save save;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000165 u32 tmp;
166 int i, j;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200167
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000168 /* Initialize HDP */
169 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
170 WREG32((0x2c14 + j), 0x00000000);
171 WREG32((0x2c18 + j), 0x00000000);
172 WREG32((0x2c1c + j), 0x00000000);
173 WREG32((0x2c20 + j), 0x00000000);
174 WREG32((0x2c24 + j), 0x00000000);
175 }
176 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200177
Jerome Glissea3c19452009-10-01 18:02:13 +0200178 rv515_mc_stop(rdev, &save);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000179 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +0200180 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200181 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000182 /* Lockout access through VGA aperture*/
183 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000184 /* Update configuration */
Jerome Glisse1a029b72009-10-06 19:04:30 +0200185 if (rdev->flags & RADEON_IS_AGP) {
186 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
187 /* VRAM before AGP */
188 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
189 rdev->mc.vram_start >> 12);
190 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
191 rdev->mc.gtt_end >> 12);
192 } else {
193 /* VRAM after AGP */
194 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
195 rdev->mc.gtt_start >> 12);
196 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
197 rdev->mc.vram_end >> 12);
198 }
199 } else {
200 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
201 rdev->mc.vram_start >> 12);
202 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
203 rdev->mc.vram_end >> 12);
204 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000205 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200206 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000207 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
208 WREG32(MC_VM_FB_LOCATION, tmp);
209 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
210 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
211 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
212 if (rdev->flags & RADEON_IS_AGP) {
Jerome Glisse1a029b72009-10-06 19:04:30 +0200213 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000214 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
215 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
216 } else {
217 WREG32(MC_VM_AGP_BASE, 0);
218 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
219 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
220 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000221 if (r600_mc_wait_for_idle(rdev)) {
Jerome Glissea3c19452009-10-01 18:02:13 +0200222 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000223 }
Jerome Glissea3c19452009-10-01 18:02:13 +0200224 rv515_mc_resume(rdev, &save);
Dave Airlie698443d2009-09-18 14:16:38 +1000225 /* we need to own VRAM, so turn off the VGA renderer here
226 * to stop it overwriting our objects */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200227 rv515_vga_render_disable(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200228}
229
230
231/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000232 * CP.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200233 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000234void r700_cp_stop(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200235{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000236 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200237}
238
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000239
240static int rv770_cp_load_microcode(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200241{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000242 const __be32 *fw_data;
243 int i;
244
245 if (!rdev->me_fw || !rdev->pfp_fw)
246 return -EINVAL;
247
248 r700_cp_stop(rdev);
249 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
250
251 /* Reset cp */
252 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
253 RREG32(GRBM_SOFT_RESET);
254 mdelay(15);
255 WREG32(GRBM_SOFT_RESET, 0);
256
257 fw_data = (const __be32 *)rdev->pfp_fw->data;
258 WREG32(CP_PFP_UCODE_ADDR, 0);
259 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
260 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
261 WREG32(CP_PFP_UCODE_ADDR, 0);
262
263 fw_data = (const __be32 *)rdev->me_fw->data;
264 WREG32(CP_ME_RAM_WADDR, 0);
265 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
266 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
267
268 WREG32(CP_PFP_UCODE_ADDR, 0);
269 WREG32(CP_ME_RAM_WADDR, 0);
270 WREG32(CP_ME_RAM_RADDR, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200271 return 0;
272}
273
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200274
275/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000276 * Core functions
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200277 */
Alex Deucherd03f5d52010-02-19 16:22:31 -0500278static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
279 u32 num_tile_pipes,
280 u32 num_backends,
281 u32 backend_disable_mask)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200282{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000283 u32 backend_map = 0;
284 u32 enabled_backends_mask;
285 u32 enabled_backends_count;
286 u32 cur_pipe;
287 u32 swizzle_pipe[R7XX_MAX_PIPES];
288 u32 cur_backend;
289 u32 i;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500290 bool force_no_swizzle;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000291
292 if (num_tile_pipes > R7XX_MAX_PIPES)
293 num_tile_pipes = R7XX_MAX_PIPES;
294 if (num_tile_pipes < 1)
295 num_tile_pipes = 1;
296 if (num_backends > R7XX_MAX_BACKENDS)
297 num_backends = R7XX_MAX_BACKENDS;
298 if (num_backends < 1)
299 num_backends = 1;
300
301 enabled_backends_mask = 0;
302 enabled_backends_count = 0;
303 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
304 if (((backend_disable_mask >> i) & 1) == 0) {
305 enabled_backends_mask |= (1 << i);
306 ++enabled_backends_count;
307 }
308 if (enabled_backends_count == num_backends)
309 break;
310 }
311
312 if (enabled_backends_count == 0) {
313 enabled_backends_mask = 1;
314 enabled_backends_count = 1;
315 }
316
317 if (enabled_backends_count != num_backends)
318 num_backends = enabled_backends_count;
319
Alex Deucherd03f5d52010-02-19 16:22:31 -0500320 switch (rdev->family) {
321 case CHIP_RV770:
322 case CHIP_RV730:
323 force_no_swizzle = false;
324 break;
325 case CHIP_RV710:
326 case CHIP_RV740:
327 default:
328 force_no_swizzle = true;
329 break;
330 }
331
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000332 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
333 switch (num_tile_pipes) {
334 case 1:
335 swizzle_pipe[0] = 0;
336 break;
337 case 2:
338 swizzle_pipe[0] = 0;
339 swizzle_pipe[1] = 1;
340 break;
341 case 3:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500342 if (force_no_swizzle) {
343 swizzle_pipe[0] = 0;
344 swizzle_pipe[1] = 1;
345 swizzle_pipe[2] = 2;
346 } else {
347 swizzle_pipe[0] = 0;
348 swizzle_pipe[1] = 2;
349 swizzle_pipe[2] = 1;
350 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000351 break;
352 case 4:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500353 if (force_no_swizzle) {
354 swizzle_pipe[0] = 0;
355 swizzle_pipe[1] = 1;
356 swizzle_pipe[2] = 2;
357 swizzle_pipe[3] = 3;
358 } else {
359 swizzle_pipe[0] = 0;
360 swizzle_pipe[1] = 2;
361 swizzle_pipe[2] = 3;
362 swizzle_pipe[3] = 1;
363 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000364 break;
365 case 5:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500366 if (force_no_swizzle) {
367 swizzle_pipe[0] = 0;
368 swizzle_pipe[1] = 1;
369 swizzle_pipe[2] = 2;
370 swizzle_pipe[3] = 3;
371 swizzle_pipe[4] = 4;
372 } else {
373 swizzle_pipe[0] = 0;
374 swizzle_pipe[1] = 2;
375 swizzle_pipe[2] = 4;
376 swizzle_pipe[3] = 1;
377 swizzle_pipe[4] = 3;
378 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000379 break;
380 case 6:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500381 if (force_no_swizzle) {
382 swizzle_pipe[0] = 0;
383 swizzle_pipe[1] = 1;
384 swizzle_pipe[2] = 2;
385 swizzle_pipe[3] = 3;
386 swizzle_pipe[4] = 4;
387 swizzle_pipe[5] = 5;
388 } else {
389 swizzle_pipe[0] = 0;
390 swizzle_pipe[1] = 2;
391 swizzle_pipe[2] = 4;
392 swizzle_pipe[3] = 5;
393 swizzle_pipe[4] = 3;
394 swizzle_pipe[5] = 1;
395 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000396 break;
397 case 7:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500398 if (force_no_swizzle) {
399 swizzle_pipe[0] = 0;
400 swizzle_pipe[1] = 1;
401 swizzle_pipe[2] = 2;
402 swizzle_pipe[3] = 3;
403 swizzle_pipe[4] = 4;
404 swizzle_pipe[5] = 5;
405 swizzle_pipe[6] = 6;
406 } else {
407 swizzle_pipe[0] = 0;
408 swizzle_pipe[1] = 2;
409 swizzle_pipe[2] = 4;
410 swizzle_pipe[3] = 6;
411 swizzle_pipe[4] = 3;
412 swizzle_pipe[5] = 1;
413 swizzle_pipe[6] = 5;
414 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000415 break;
416 case 8:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500417 if (force_no_swizzle) {
418 swizzle_pipe[0] = 0;
419 swizzle_pipe[1] = 1;
420 swizzle_pipe[2] = 2;
421 swizzle_pipe[3] = 3;
422 swizzle_pipe[4] = 4;
423 swizzle_pipe[5] = 5;
424 swizzle_pipe[6] = 6;
425 swizzle_pipe[7] = 7;
426 } else {
427 swizzle_pipe[0] = 0;
428 swizzle_pipe[1] = 2;
429 swizzle_pipe[2] = 4;
430 swizzle_pipe[3] = 6;
431 swizzle_pipe[4] = 3;
432 swizzle_pipe[5] = 1;
433 swizzle_pipe[6] = 7;
434 swizzle_pipe[7] = 5;
435 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000436 break;
437 }
438
439 cur_backend = 0;
440 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
441 while (((1 << cur_backend) & enabled_backends_mask) == 0)
442 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
443
444 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
445
446 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
447 }
448
449 return backend_map;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200450}
451
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000452static void rv770_gpu_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200453{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000454 int i, j, num_qd_pipes;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500455 u32 ta_aux_cntl;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000456 u32 sx_debug_1;
457 u32 smx_dc_ctl0;
Alex Deucherd03f5d52010-02-19 16:22:31 -0500458 u32 db_debug3;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000459 u32 num_gs_verts_per_thread;
460 u32 vgt_gs_per_es;
461 u32 gs_prim_buffer_depth = 0;
462 u32 sq_ms_fifo_sizes;
463 u32 sq_config;
464 u32 sq_thread_resource_mgmt;
465 u32 hdp_host_path_cntl;
466 u32 sq_dyn_gpr_size_simd_ab_0;
467 u32 backend_map;
468 u32 gb_tiling_config = 0;
469 u32 cc_rb_backend_disable = 0;
470 u32 cc_gc_shader_pipe_config = 0;
471 u32 mc_arb_ramcfg;
472 u32 db_debug4;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200473
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000474 /* setup chip specs */
475 switch (rdev->family) {
476 case CHIP_RV770:
477 rdev->config.rv770.max_pipes = 4;
478 rdev->config.rv770.max_tile_pipes = 8;
479 rdev->config.rv770.max_simds = 10;
480 rdev->config.rv770.max_backends = 4;
481 rdev->config.rv770.max_gprs = 256;
482 rdev->config.rv770.max_threads = 248;
483 rdev->config.rv770.max_stack_entries = 512;
484 rdev->config.rv770.max_hw_contexts = 8;
485 rdev->config.rv770.max_gs_threads = 16 * 2;
486 rdev->config.rv770.sx_max_export_size = 128;
487 rdev->config.rv770.sx_max_export_pos_size = 16;
488 rdev->config.rv770.sx_max_export_smx_size = 112;
489 rdev->config.rv770.sq_num_cf_insts = 2;
490
491 rdev->config.rv770.sx_num_of_sets = 7;
492 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
493 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
494 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
495 break;
496 case CHIP_RV730:
497 rdev->config.rv770.max_pipes = 2;
498 rdev->config.rv770.max_tile_pipes = 4;
499 rdev->config.rv770.max_simds = 8;
500 rdev->config.rv770.max_backends = 2;
501 rdev->config.rv770.max_gprs = 128;
502 rdev->config.rv770.max_threads = 248;
503 rdev->config.rv770.max_stack_entries = 256;
504 rdev->config.rv770.max_hw_contexts = 8;
505 rdev->config.rv770.max_gs_threads = 16 * 2;
506 rdev->config.rv770.sx_max_export_size = 256;
507 rdev->config.rv770.sx_max_export_pos_size = 32;
508 rdev->config.rv770.sx_max_export_smx_size = 224;
509 rdev->config.rv770.sq_num_cf_insts = 2;
510
511 rdev->config.rv770.sx_num_of_sets = 7;
512 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
513 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
514 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
515 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
516 rdev->config.rv770.sx_max_export_pos_size -= 16;
517 rdev->config.rv770.sx_max_export_smx_size += 16;
518 }
519 break;
520 case CHIP_RV710:
521 rdev->config.rv770.max_pipes = 2;
522 rdev->config.rv770.max_tile_pipes = 2;
523 rdev->config.rv770.max_simds = 2;
524 rdev->config.rv770.max_backends = 1;
525 rdev->config.rv770.max_gprs = 256;
526 rdev->config.rv770.max_threads = 192;
527 rdev->config.rv770.max_stack_entries = 256;
528 rdev->config.rv770.max_hw_contexts = 4;
529 rdev->config.rv770.max_gs_threads = 8 * 2;
530 rdev->config.rv770.sx_max_export_size = 128;
531 rdev->config.rv770.sx_max_export_pos_size = 16;
532 rdev->config.rv770.sx_max_export_smx_size = 112;
533 rdev->config.rv770.sq_num_cf_insts = 1;
534
535 rdev->config.rv770.sx_num_of_sets = 7;
536 rdev->config.rv770.sc_prim_fifo_size = 0x40;
537 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
538 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
539 break;
540 case CHIP_RV740:
541 rdev->config.rv770.max_pipes = 4;
542 rdev->config.rv770.max_tile_pipes = 4;
543 rdev->config.rv770.max_simds = 8;
544 rdev->config.rv770.max_backends = 4;
545 rdev->config.rv770.max_gprs = 256;
546 rdev->config.rv770.max_threads = 248;
547 rdev->config.rv770.max_stack_entries = 512;
548 rdev->config.rv770.max_hw_contexts = 8;
549 rdev->config.rv770.max_gs_threads = 16 * 2;
550 rdev->config.rv770.sx_max_export_size = 256;
551 rdev->config.rv770.sx_max_export_pos_size = 32;
552 rdev->config.rv770.sx_max_export_smx_size = 224;
553 rdev->config.rv770.sq_num_cf_insts = 2;
554
555 rdev->config.rv770.sx_num_of_sets = 7;
556 rdev->config.rv770.sc_prim_fifo_size = 0x100;
557 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
558 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
559
560 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
561 rdev->config.rv770.sx_max_export_pos_size -= 16;
562 rdev->config.rv770.sx_max_export_smx_size += 16;
563 }
564 break;
565 default:
566 break;
567 }
568
569 /* Initialize HDP */
570 j = 0;
571 for (i = 0; i < 32; i++) {
572 WREG32((0x2c14 + j), 0x00000000);
573 WREG32((0x2c18 + j), 0x00000000);
574 WREG32((0x2c1c + j), 0x00000000);
575 WREG32((0x2c20 + j), 0x00000000);
576 WREG32((0x2c24 + j), 0x00000000);
577 j += 0x18;
578 }
579
580 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
581
582 /* setup tiling, simd, pipe config */
583 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
584
585 switch (rdev->config.rv770.max_tile_pipes) {
586 case 1:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500587 default:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000588 gb_tiling_config |= PIPE_TILING(0);
589 break;
590 case 2:
591 gb_tiling_config |= PIPE_TILING(1);
592 break;
593 case 4:
594 gb_tiling_config |= PIPE_TILING(2);
595 break;
596 case 8:
597 gb_tiling_config |= PIPE_TILING(3);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000598 break;
599 }
Alex Deucherd03f5d52010-02-19 16:22:31 -0500600 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000601
602 if (rdev->family == CHIP_RV770)
603 gb_tiling_config |= BANK_TILING(1);
604 else
Alex Deuchere29649d2009-11-03 10:04:01 -0500605 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
Jerome Glisse961fb592010-02-10 22:30:05 +0000606 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000607
608 gb_tiling_config |= GROUP_SIZE(0);
Jerome Glisse961fb592010-02-10 22:30:05 +0000609 rdev->config.rv770.tiling_group_size = 256;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000610
Alex Deuchere29649d2009-11-03 10:04:01 -0500611 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000612 gb_tiling_config |= ROW_TILING(3);
613 gb_tiling_config |= SAMPLE_SPLIT(3);
614 } else {
615 gb_tiling_config |=
616 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
617 gb_tiling_config |=
618 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
619 }
620
621 gb_tiling_config |= BANK_SWAPS(1);
622
Alex Deucherd03f5d52010-02-19 16:22:31 -0500623 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
624 cc_rb_backend_disable |=
625 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000626
Alex Deucherd03f5d52010-02-19 16:22:31 -0500627 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
628 cc_gc_shader_pipe_config |=
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000629 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
630 cc_gc_shader_pipe_config |=
631 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
632
Alex Deucherd03f5d52010-02-19 16:22:31 -0500633 if (rdev->family == CHIP_RV740)
634 backend_map = 0x28;
635 else
636 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
637 rdev->config.rv770.max_tile_pipes,
638 (R7XX_MAX_BACKENDS -
639 r600_count_pipe_bits((cc_rb_backend_disable &
640 R7XX_MAX_BACKENDS_MASK) >> 16)),
641 (cc_rb_backend_disable >> 16));
642 gb_tiling_config |= BACKEND_MAP(backend_map);
643
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000644
645 WREG32(GB_TILING_CONFIG, gb_tiling_config);
646 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
647 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
648
649 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
650 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
Alex Deucherf867c60d2010-03-05 14:50:37 -0500651 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
Alex Deucherd03f5d52010-02-19 16:22:31 -0500652 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000653
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000654 WREG32(CGTS_SYS_TCC_DISABLE, 0);
655 WREG32(CGTS_TCC_DISABLE, 0);
Alex Deucherf867c60d2010-03-05 14:50:37 -0500656 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
657 WREG32(CGTS_USER_TCC_DISABLE, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000658
659 num_qd_pipes =
Alex Deucherd03f5d52010-02-19 16:22:31 -0500660 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000661 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
662 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
663
664 /* set HW defaults for 3D engine */
665 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
Alex Deuchere29649d2009-11-03 10:04:01 -0500666 ROQ_IB2_START(0x2b)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000667
668 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
669
Alex Deucherd03f5d52010-02-19 16:22:31 -0500670 ta_aux_cntl = RREG32(TA_CNTL_AUX);
671 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000672
673 sx_debug_1 = RREG32(SX_DEBUG_1);
674 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
675 WREG32(SX_DEBUG_1, sx_debug_1);
676
677 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
678 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
679 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
680 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
681
Alex Deucherd03f5d52010-02-19 16:22:31 -0500682 if (rdev->family != CHIP_RV740)
683 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
684 GS_FLUSH_CTL(4) |
685 ACK_FLUSH_CTL(3) |
686 SYNC_FLUSH_CTL));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000687
Alex Deucherd03f5d52010-02-19 16:22:31 -0500688 db_debug3 = RREG32(DB_DEBUG3);
689 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
690 switch (rdev->family) {
691 case CHIP_RV770:
692 case CHIP_RV740:
693 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
694 break;
695 case CHIP_RV710:
696 case CHIP_RV730:
697 default:
698 db_debug3 |= DB_CLK_OFF_DELAY(2);
699 break;
700 }
701 WREG32(DB_DEBUG3, db_debug3);
702
703 if (rdev->family != CHIP_RV770) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000704 db_debug4 = RREG32(DB_DEBUG4);
705 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
706 WREG32(DB_DEBUG4, db_debug4);
707 }
708
709 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
Alex Deuchere29649d2009-11-03 10:04:01 -0500710 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
711 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000712
713 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
Alex Deuchere29649d2009-11-03 10:04:01 -0500714 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
715 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000716
717 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
718
719 WREG32(VGT_NUM_INSTANCES, 1);
720
721 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
722
723 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
724
725 WREG32(CP_PERFMON_CNTL, 0);
726
727 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
728 DONE_FIFO_HIWATER(0xe0) |
729 ALU_UPDATE_FIFO_HIWATER(0x8));
730 switch (rdev->family) {
731 case CHIP_RV770:
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000732 case CHIP_RV730:
733 case CHIP_RV710:
Alex Deucherd03f5d52010-02-19 16:22:31 -0500734 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
735 break;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000736 case CHIP_RV740:
737 default:
738 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
739 break;
740 }
741 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
742
743 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
744 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
745 */
746 sq_config = RREG32(SQ_CONFIG);
747 sq_config &= ~(PS_PRIO(3) |
748 VS_PRIO(3) |
749 GS_PRIO(3) |
750 ES_PRIO(3));
751 sq_config |= (DX9_CONSTS |
752 VC_ENABLE |
753 EXPORT_SRC_C |
754 PS_PRIO(0) |
755 VS_PRIO(1) |
756 GS_PRIO(2) |
757 ES_PRIO(3));
758 if (rdev->family == CHIP_RV710)
759 /* no vertex cache */
760 sq_config &= ~VC_ENABLE;
761
762 WREG32(SQ_CONFIG, sq_config);
763
764 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000765 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
766 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000767
768 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000769 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000770
771 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
772 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
773 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
774 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
775 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
776 else
777 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
778 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
779
780 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
781 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
782
783 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
784 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
785
786 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
787 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
788 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
789 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
790
791 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
792 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
793 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
794 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
795 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
796 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
797 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
798 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
799
800 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000801 FORCE_EOV_MAX_REZ_CNT(255)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000802
803 if (rdev->family == CHIP_RV710)
804 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000805 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000806 else
807 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
Dave Airliefe62e1a2009-09-21 14:06:30 +1000808 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000809
810 switch (rdev->family) {
811 case CHIP_RV770:
812 case CHIP_RV730:
813 case CHIP_RV740:
814 gs_prim_buffer_depth = 384;
815 break;
816 case CHIP_RV710:
817 gs_prim_buffer_depth = 128;
818 break;
819 default:
820 break;
821 }
822
823 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
824 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
825 /* Max value for this is 256 */
826 if (vgt_gs_per_es > 256)
827 vgt_gs_per_es = 256;
828
829 WREG32(VGT_ES_PER_GS, 128);
830 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
831 WREG32(VGT_GS_PER_VS, 2);
832
833 /* more default values. 2D/3D driver should adjust as needed */
834 WREG32(VGT_GS_VERTEX_REUSE, 16);
835 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
836 WREG32(VGT_STRMOUT_EN, 0);
837 WREG32(SX_MISC, 0);
838 WREG32(PA_SC_MODE_CNTL, 0);
839 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
840 WREG32(PA_SC_AA_CONFIG, 0);
841 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
842 WREG32(PA_SC_LINE_STIPPLE, 0);
843 WREG32(SPI_INPUT_Z, 0);
844 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
845 WREG32(CB_COLOR7_FRAG, 0);
846
847 /* clear render buffer base addresses */
848 WREG32(CB_COLOR0_BASE, 0);
849 WREG32(CB_COLOR1_BASE, 0);
850 WREG32(CB_COLOR2_BASE, 0);
851 WREG32(CB_COLOR3_BASE, 0);
852 WREG32(CB_COLOR4_BASE, 0);
853 WREG32(CB_COLOR5_BASE, 0);
854 WREG32(CB_COLOR6_BASE, 0);
855 WREG32(CB_COLOR7_BASE, 0);
856
857 WREG32(TCP_CNTL, 0);
858
859 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
860 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
861
862 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
863
864 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
865 NUM_CLIP_SEQ(3)));
866
867}
868
869int rv770_mc_init(struct radeon_device *rdev)
870{
871 fixed20_12 a;
872 u32 tmp;
Alex Deucher5885b7a2009-10-19 17:23:33 -0400873 int chansize, numchan;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000874
875 /* Get VRAM informations */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000876 rdev->mc.vram_is_ddr = true;
Alex Deucher5885b7a2009-10-19 17:23:33 -0400877 tmp = RREG32(MC_ARB_RAMCFG);
878 if (tmp & CHANSIZE_OVERRIDE) {
879 chansize = 16;
880 } else if (tmp & CHANSIZE_MASK) {
881 chansize = 64;
882 } else {
883 chansize = 32;
884 }
885 tmp = RREG32(MC_SHARED_CHMAP);
886 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
887 case 0:
888 default:
889 numchan = 1;
890 break;
891 case 1:
892 numchan = 2;
893 break;
894 case 2:
895 numchan = 4;
896 break;
897 case 3:
898 numchan = 8;
899 break;
900 }
901 rdev->mc.vram_width = numchan * chansize;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200902 /* Could aper size report 0 ? */
903 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
904 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000905 /* Setup GPU memory space */
906 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
907 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
Jerome Glisse51e5fcd2010-02-19 14:33:54 +0000908 rdev->mc.visible_vram_size = rdev->mc.aper_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000909 /* FIXME remove this once we support unmappable VRAM */
910 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
Alex Deucher974b16e2009-09-25 10:06:39 -0400911 rdev->mc.mc_vram_size = rdev->mc.aper_size;
Alex Deucher974b16e2009-09-25 10:06:39 -0400912 rdev->mc.real_vram_size = rdev->mc.aper_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000913 }
Jerome Glissed594e462010-02-17 21:54:29 +0000914 r600_vram_gtt_location(rdev, &rdev->mc);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000915 /* FIXME: we should enforce default clock in case GPU is not in
916 * default setup
917 */
918 a.full = rfixed_const(100);
919 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
920 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
921 return 0;
922}
Jerome Glissed594e462010-02-17 21:54:29 +0000923
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000924int rv770_gpu_reset(struct radeon_device *rdev)
925{
Dave Airliefe62e1a2009-09-21 14:06:30 +1000926 /* FIXME: implement any rv770 specific bits */
927 return r600_gpu_reset(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000928}
929
Dave Airliefc30b8e2009-09-18 15:19:37 +1000930static int rv770_startup(struct radeon_device *rdev)
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000931{
932 int r;
933
Alex Deucher779720a2009-12-09 19:31:44 -0500934 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
935 r = r600_init_microcode(rdev);
936 if (r) {
937 DRM_ERROR("Failed to load firmware!\n");
938 return r;
939 }
940 }
941
Jerome Glissea3c19452009-10-01 18:02:13 +0200942 rv770_mc_program(rdev);
Jerome Glisse1a029b72009-10-06 19:04:30 +0200943 if (rdev->flags & RADEON_IS_AGP) {
944 rv770_agp_enable(rdev);
945 } else {
946 r = rv770_pcie_gart_enable(rdev);
947 if (r)
948 return r;
949 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000950 rv770_gpu_init(rdev);
Jerome Glissec38c7b62010-02-04 17:27:27 +0100951 r = r600_blit_init(rdev);
952 if (r) {
953 r600_blit_fini(rdev);
954 rdev->asic->copy = NULL;
955 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
956 }
Jerome Glisseff82f052010-01-22 15:19:00 +0100957 /* pin copy shader into vram */
958 if (rdev->r600_blit.shader_obj) {
959 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
960 if (unlikely(r != 0))
961 return r;
962 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
963 &rdev->r600_blit.shader_gpu_addr);
964 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
Alex Deucher7923c612009-12-15 17:15:07 -0500965 if (r) {
Jerome Glisseff82f052010-01-22 15:19:00 +0100966 DRM_ERROR("failed to pin blit object %d\n", r);
Alex Deucher7923c612009-12-15 17:15:07 -0500967 return r;
968 }
969 }
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500970 /* Enable IRQ */
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500971 r = r600_irq_init(rdev);
972 if (r) {
973 DRM_ERROR("radeon: IH init failed (%d).\n", r);
974 radeon_irq_kms_fini(rdev);
975 return r;
976 }
977 r600_irq_set(rdev);
978
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000979 r = radeon_ring_init(rdev, rdev->cp.ring_size);
980 if (r)
981 return r;
982 r = rv770_cp_load_microcode(rdev);
983 if (r)
984 return r;
985 r = r600_cp_resume(rdev);
986 if (r)
987 return r;
Jerome Glisse81cc35b2009-10-01 18:02:12 +0200988 /* write back buffer are not vital so don't worry about failure */
989 r600_wb_enable(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000990 return 0;
991}
992
Dave Airliefc30b8e2009-09-18 15:19:37 +1000993int rv770_resume(struct radeon_device *rdev)
994{
995 int r;
996
Jerome Glisse1a029b72009-10-06 19:04:30 +0200997 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
998 * posting will perform necessary task to bring back GPU into good
999 * shape.
1000 */
Dave Airliefc30b8e2009-09-18 15:19:37 +10001001 /* post card */
Jerome Glissee7d40b92009-10-01 18:02:15 +02001002 atom_asic_init(rdev->mode_info.atom_context);
Dave Airliefc30b8e2009-09-18 15:19:37 +10001003 /* Initialize clocks */
1004 r = radeon_clocks_init(rdev);
1005 if (r) {
1006 return r;
1007 }
1008
1009 r = rv770_startup(rdev);
1010 if (r) {
1011 DRM_ERROR("r600 startup failed on resume\n");
1012 return r;
1013 }
1014
Jerome Glisse62a8ea32009-10-01 18:02:11 +02001015 r = r600_ib_test(rdev);
Dave Airliefc30b8e2009-09-18 15:19:37 +10001016 if (r) {
1017 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1018 return r;
1019 }
Rafał Miłecki8a8c6e72010-03-06 13:03:36 +00001020
1021 r = r600_audio_init(rdev);
1022 if (r) {
1023 dev_err(rdev->dev, "radeon: audio init failed\n");
1024 return r;
1025 }
1026
Dave Airliefc30b8e2009-09-18 15:19:37 +10001027 return r;
1028
1029}
1030
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001031int rv770_suspend(struct radeon_device *rdev)
1032{
Jerome Glisse4c788672009-11-20 14:29:23 +01001033 int r;
1034
Rafał Miłecki8a8c6e72010-03-06 13:03:36 +00001035 r600_audio_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001036 /* FIXME: we should wait for ring to be empty */
1037 r700_cp_stop(rdev);
Dave Airlie4153e582009-09-18 18:41:24 +10001038 rdev->cp.ready = false;
Jerome Glisse0c452492010-01-15 14:44:37 +01001039 r600_irq_suspend(rdev);
Jerome Glisse81cc35b2009-10-01 18:02:12 +02001040 r600_wb_disable(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001041 rv770_pcie_gart_disable(rdev);
Dave Airlie4153e582009-09-18 18:41:24 +10001042 /* unpin shaders bo */
Jerome Glisse30d2d9a2010-01-13 10:29:27 +01001043 if (rdev->r600_blit.shader_obj) {
1044 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1045 if (likely(r == 0)) {
1046 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1047 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1048 }
Jerome Glisse4c788672009-11-20 14:29:23 +01001049 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001050 return 0;
1051}
1052
1053/* Plan is to move initialization in that function and use
1054 * helper function so that radeon_device_init pretty much
1055 * do nothing more than calling asic specific function. This
1056 * should also allow to remove a bunch of callback function
1057 * like vram_info.
1058 */
1059int rv770_init(struct radeon_device *rdev)
1060{
1061 int r;
1062
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001063 r = radeon_dummy_page_init(rdev);
1064 if (r)
1065 return r;
1066 /* This don't do much */
1067 r = radeon_gem_init(rdev);
1068 if (r)
1069 return r;
1070 /* Read BIOS */
1071 if (!radeon_get_bios(rdev)) {
1072 if (ASIC_IS_AVIVO(rdev))
1073 return -EINVAL;
1074 }
1075 /* Must be an ATOMBIOS */
Jerome Glissee7d40b92009-10-01 18:02:15 +02001076 if (!rdev->is_atom_bios) {
1077 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001078 return -EINVAL;
Jerome Glissee7d40b92009-10-01 18:02:15 +02001079 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001080 r = radeon_atombios_init(rdev);
1081 if (r)
1082 return r;
1083 /* Post card if necessary */
Dave Airlie72542d72009-12-01 14:06:31 +10001084 if (!r600_card_posted(rdev)) {
1085 if (!rdev->bios) {
1086 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1087 return -EINVAL;
1088 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001089 DRM_INFO("GPU not posted. posting now...\n");
1090 atom_asic_init(rdev->mode_info.atom_context);
1091 }
1092 /* Initialize scratch registers */
1093 r600_scratch_init(rdev);
1094 /* Initialize surface registers */
1095 radeon_surface_init(rdev);
Rafał Miłecki74338742009-11-03 00:53:02 +01001096 /* Initialize clocks */
Michel Dänzer5e6dde72009-09-17 09:42:28 +02001097 radeon_get_clock_info(rdev->ddev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001098 r = radeon_clocks_init(rdev);
1099 if (r)
1100 return r;
Rafał Miłecki74338742009-11-03 00:53:02 +01001101 /* Initialize power management */
1102 radeon_pm_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001103 /* Fence driver */
1104 r = radeon_fence_driver_init(rdev);
1105 if (r)
1106 return r;
Jerome Glissed594e462010-02-17 21:54:29 +00001107 /* initialize AGP */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001108 if (rdev->flags & RADEON_IS_AGP) {
1109 r = radeon_agp_init(rdev);
1110 if (r)
1111 radeon_agp_disable(rdev);
1112 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001113 r = rv770_mc_init(rdev);
Jerome Glisseb574f252009-10-06 19:04:29 +02001114 if (r)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001115 return r;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001116 /* Memory manager */
Jerome Glisse4c788672009-11-20 14:29:23 +01001117 r = radeon_bo_init(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001118 if (r)
1119 return r;
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001120
1121 r = radeon_irq_kms_init(rdev);
1122 if (r)
1123 return r;
1124
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001125 rdev->cp.ring_obj = NULL;
1126 r600_ring_init(rdev, 1024 * 1024);
1127
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001128 rdev->ih.ring_obj = NULL;
1129 r600_ih_ring_init(rdev, 64 * 1024);
1130
Jerome Glisse4aac0472009-09-14 18:29:49 +02001131 r = r600_pcie_gart_init(rdev);
1132 if (r)
1133 return r;
1134
Alex Deucher779720a2009-12-09 19:31:44 -05001135 rdev->accel_working = true;
Dave Airliefc30b8e2009-09-18 15:19:37 +10001136 r = rv770_startup(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001137 if (r) {
Jerome Glisse655efd32010-02-02 11:51:45 +01001138 dev_err(rdev->dev, "disabling GPU acceleration\n");
1139 r600_cp_fini(rdev);
Jerome Glisse75c81292009-10-01 18:02:14 +02001140 r600_wb_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01001141 r600_irq_fini(rdev);
1142 radeon_irq_kms_fini(rdev);
Jerome Glisse75c81292009-10-01 18:02:14 +02001143 rv770_pcie_gart_fini(rdev);
Jerome Glisse733289c2009-09-16 15:24:21 +02001144 rdev->accel_working = false;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001145 }
Jerome Glisse733289c2009-09-16 15:24:21 +02001146 if (rdev->accel_working) {
Jerome Glisse733289c2009-09-16 15:24:21 +02001147 r = radeon_ib_pool_init(rdev);
1148 if (r) {
Jerome Glissedb963802010-01-17 21:21:56 +01001149 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
Jerome Glisse733289c2009-09-16 15:24:21 +02001150 rdev->accel_working = false;
Jerome Glissedb963802010-01-17 21:21:56 +01001151 } else {
1152 r = r600_ib_test(rdev);
1153 if (r) {
1154 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1155 rdev->accel_working = false;
1156 }
Jerome Glisse733289c2009-09-16 15:24:21 +02001157 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001158 }
Rafał Miłecki8a8c6e72010-03-06 13:03:36 +00001159
1160 r = r600_audio_init(rdev);
1161 if (r) {
1162 dev_err(rdev->dev, "radeon: audio init failed\n");
1163 return r;
1164 }
1165
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001166 return 0;
1167}
1168
1169void rv770_fini(struct radeon_device *rdev)
1170{
Alex Deucher29fb52c2010-03-11 10:01:17 -05001171 radeon_pm_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001172 r600_blit_fini(rdev);
Jerome Glisse655efd32010-02-02 11:51:45 +01001173 r600_cp_fini(rdev);
1174 r600_wb_fini(rdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001175 r600_irq_fini(rdev);
1176 radeon_irq_kms_fini(rdev);
Jerome Glisse4aac0472009-09-14 18:29:49 +02001177 rv770_pcie_gart_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001178 radeon_gem_fini(rdev);
1179 radeon_fence_driver_fini(rdev);
1180 radeon_clocks_fini(rdev);
Jerome Glissed0269ed2010-01-07 16:08:32 +01001181 radeon_agp_fini(rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +01001182 radeon_bo_fini(rdev);
Jerome Glissee7d40b92009-10-01 18:02:15 +02001183 radeon_atombios_fini(rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001184 kfree(rdev->bios);
1185 rdev->bios = NULL;
1186 radeon_dummy_page_fini(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001187}