Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Support for NXT2002 and NXT2004 - VSB/QAM |
| 3 | * |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 4 | * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com> |
| 5 | * Copyright (C) 2006 Michael Krufky <mkrufky@m1k.net> |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 6 | * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net> |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 7 | * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com> |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * NOTES ABOUT THIS DRIVER |
| 27 | * |
| 28 | * This Linux driver supports: |
| 29 | * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002) |
| 30 | * AverTVHD MCE A180 (NXT2004) |
| 31 | * ATI HDTV Wonder (NXT2004) |
| 32 | * |
| 33 | * This driver needs external firmware. Please use the command |
| 34 | * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" or |
| 35 | * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2004" to |
| 36 | * download/extract the appropriate firmware, and then copy it to |
| 37 | * /usr/lib/hotplug/firmware/ or /lib/firmware/ |
| 38 | * (depending on configuration of firmware hotplug). |
| 39 | */ |
| 40 | #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw" |
| 41 | #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw" |
| 42 | #define CRC_CCIT_MASK 0x1021 |
| 43 | |
| 44 | #include <linux/kernel.h> |
| 45 | #include <linux/init.h> |
| 46 | #include <linux/module.h> |
| 47 | #include <linux/moduleparam.h> |
Tim Schmielau | 18e55ee | 2005-12-01 00:51:51 -0800 | [diff] [blame] | 48 | #include <linux/slab.h> |
| 49 | #include <linux/string.h> |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 50 | |
| 51 | #include "dvb_frontend.h" |
| 52 | #include "dvb-pll.h" |
| 53 | #include "nxt200x.h" |
| 54 | |
| 55 | struct nxt200x_state { |
| 56 | |
| 57 | struct i2c_adapter* i2c; |
| 58 | struct dvb_frontend_ops ops; |
| 59 | const struct nxt200x_config* config; |
| 60 | struct dvb_frontend frontend; |
| 61 | |
| 62 | /* demodulator private data */ |
| 63 | nxt_chip_type demod_chip; |
| 64 | u8 initialised:1; |
| 65 | }; |
| 66 | |
| 67 | static int debug; |
| 68 | #define dprintk(args...) \ |
| 69 | do { \ |
| 70 | if (debug) printk(KERN_DEBUG "nxt200x: " args); \ |
| 71 | } while (0) |
| 72 | |
| 73 | static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len) |
| 74 | { |
| 75 | int err; |
| 76 | struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len }; |
| 77 | |
| 78 | if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { |
| 79 | printk (KERN_WARNING "nxt200x: %s: i2c write error (addr 0x%02x, err == %i)\n", |
| 80 | __FUNCTION__, addr, err); |
| 81 | return -EREMOTEIO; |
| 82 | } |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | static u8 i2c_readbytes (struct nxt200x_state* state, u8 addr, u8* buf, u8 len) |
| 87 | { |
| 88 | int err; |
| 89 | struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len }; |
| 90 | |
| 91 | if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { |
| 92 | printk (KERN_WARNING "nxt200x: %s: i2c read error (addr 0x%02x, err == %i)\n", |
| 93 | __FUNCTION__, addr, err); |
| 94 | return -EREMOTEIO; |
| 95 | } |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, u8 *buf, u8 len) |
| 100 | { |
| 101 | u8 buf2 [len+1]; |
| 102 | int err; |
| 103 | struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 }; |
| 104 | |
| 105 | buf2[0] = reg; |
| 106 | memcpy(&buf2[1], buf, len); |
| 107 | |
| 108 | if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) { |
| 109 | printk (KERN_WARNING "nxt200x: %s: i2c write error (addr 0x%02x, err == %i)\n", |
| 110 | __FUNCTION__, state->config->demod_address, err); |
| 111 | return -EREMOTEIO; |
| 112 | } |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | static u8 nxt200x_readbytes (struct nxt200x_state* state, u8 reg, u8* buf, u8 len) |
| 117 | { |
| 118 | u8 reg2 [] = { reg }; |
| 119 | |
| 120 | struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 }, |
| 121 | { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } }; |
| 122 | |
| 123 | int err; |
| 124 | |
| 125 | if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) { |
| 126 | printk (KERN_WARNING "nxt200x: %s: i2c read error (addr 0x%02x, err == %i)\n", |
| 127 | __FUNCTION__, state->config->demod_address, err); |
| 128 | return -EREMOTEIO; |
| 129 | } |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static u16 nxt200x_crc(u16 crc, u8 c) |
| 134 | { |
| 135 | u8 i; |
| 136 | u16 input = (u16) c & 0xFF; |
| 137 | |
| 138 | input<<=8; |
| 139 | for(i=0; i<8; i++) { |
| 140 | if((crc^input) & 0x8000) |
| 141 | crc=(crc<<1)^CRC_CCIT_MASK; |
| 142 | else |
| 143 | crc<<=1; |
| 144 | input<<=1; |
| 145 | } |
| 146 | return crc; |
| 147 | } |
| 148 | |
| 149 | static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) |
| 150 | { |
| 151 | u8 attr, len2, buf; |
| 152 | dprintk("%s\n", __FUNCTION__); |
| 153 | |
| 154 | /* set mutli register register */ |
| 155 | nxt200x_writebytes(state, 0x35, ®, 1); |
| 156 | |
| 157 | /* send the actual data */ |
| 158 | nxt200x_writebytes(state, 0x36, data, len); |
| 159 | |
| 160 | switch (state->demod_chip) { |
| 161 | case NXT2002: |
| 162 | len2 = len; |
| 163 | buf = 0x02; |
| 164 | break; |
| 165 | case NXT2004: |
| 166 | /* probably not right, but gives correct values */ |
| 167 | attr = 0x02; |
| 168 | if (reg & 0x80) { |
| 169 | attr = attr << 1; |
| 170 | if (reg & 0x04) |
| 171 | attr = attr >> 1; |
| 172 | } |
| 173 | /* set write bit */ |
| 174 | len2 = ((attr << 4) | 0x10) | len; |
| 175 | buf = 0x80; |
| 176 | break; |
| 177 | default: |
| 178 | return -EINVAL; |
| 179 | break; |
| 180 | } |
| 181 | |
| 182 | /* set multi register length */ |
| 183 | nxt200x_writebytes(state, 0x34, &len2, 1); |
| 184 | |
| 185 | /* toggle the multireg write bit */ |
| 186 | nxt200x_writebytes(state, 0x21, &buf, 1); |
| 187 | |
| 188 | nxt200x_readbytes(state, 0x21, &buf, 1); |
| 189 | |
| 190 | switch (state->demod_chip) { |
| 191 | case NXT2002: |
| 192 | if ((buf & 0x02) == 0) |
| 193 | return 0; |
| 194 | break; |
| 195 | case NXT2004: |
| 196 | if (buf == 0) |
| 197 | return 0; |
| 198 | break; |
| 199 | default: |
| 200 | return -EINVAL; |
| 201 | break; |
| 202 | } |
| 203 | |
| 204 | printk(KERN_WARNING "nxt200x: Error writing multireg register 0x%02X\n",reg); |
| 205 | |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len) |
| 210 | { |
| 211 | int i; |
| 212 | u8 buf, len2, attr; |
| 213 | dprintk("%s\n", __FUNCTION__); |
| 214 | |
| 215 | /* set mutli register register */ |
| 216 | nxt200x_writebytes(state, 0x35, ®, 1); |
| 217 | |
| 218 | switch (state->demod_chip) { |
| 219 | case NXT2002: |
| 220 | /* set multi register length */ |
| 221 | len2 = len & 0x80; |
| 222 | nxt200x_writebytes(state, 0x34, &len2, 1); |
| 223 | |
| 224 | /* read the actual data */ |
| 225 | nxt200x_readbytes(state, reg, data, len); |
| 226 | return 0; |
| 227 | break; |
| 228 | case NXT2004: |
| 229 | /* probably not right, but gives correct values */ |
| 230 | attr = 0x02; |
| 231 | if (reg & 0x80) { |
| 232 | attr = attr << 1; |
| 233 | if (reg & 0x04) |
| 234 | attr = attr >> 1; |
| 235 | } |
| 236 | |
| 237 | /* set multi register length */ |
| 238 | len2 = (attr << 4) | len; |
| 239 | nxt200x_writebytes(state, 0x34, &len2, 1); |
| 240 | |
| 241 | /* toggle the multireg bit*/ |
| 242 | buf = 0x80; |
| 243 | nxt200x_writebytes(state, 0x21, &buf, 1); |
| 244 | |
Kirk Lapray | f93cf03 | 2005-11-08 21:35:51 -0800 | [diff] [blame] | 245 | /* read the actual data */ |
| 246 | for(i = 0; i < len; i++) { |
| 247 | nxt200x_readbytes(state, 0x36 + i, &data[i], 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 248 | } |
Kirk Lapray | f93cf03 | 2005-11-08 21:35:51 -0800 | [diff] [blame] | 249 | return 0; |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 250 | break; |
| 251 | default: |
| 252 | return -EINVAL; |
| 253 | break; |
| 254 | } |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | static void nxt200x_microcontroller_stop (struct nxt200x_state* state) |
| 258 | { |
| 259 | u8 buf, stopval, counter = 0; |
| 260 | dprintk("%s\n", __FUNCTION__); |
| 261 | |
| 262 | /* set correct stop value */ |
| 263 | switch (state->demod_chip) { |
| 264 | case NXT2002: |
| 265 | stopval = 0x40; |
| 266 | break; |
| 267 | case NXT2004: |
| 268 | stopval = 0x10; |
| 269 | break; |
| 270 | default: |
| 271 | stopval = 0; |
| 272 | break; |
| 273 | } |
| 274 | |
| 275 | buf = 0x80; |
| 276 | nxt200x_writebytes(state, 0x22, &buf, 1); |
| 277 | |
| 278 | while (counter < 20) { |
| 279 | nxt200x_readbytes(state, 0x31, &buf, 1); |
| 280 | if (buf & stopval) |
| 281 | return; |
| 282 | msleep(10); |
| 283 | counter++; |
| 284 | } |
| 285 | |
| 286 | printk(KERN_WARNING "nxt200x: Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n"); |
| 287 | return; |
| 288 | } |
| 289 | |
| 290 | static void nxt200x_microcontroller_start (struct nxt200x_state* state) |
| 291 | { |
| 292 | u8 buf; |
| 293 | dprintk("%s\n", __FUNCTION__); |
| 294 | |
| 295 | buf = 0x00; |
| 296 | nxt200x_writebytes(state, 0x22, &buf, 1); |
| 297 | } |
| 298 | |
| 299 | static void nxt2004_microcontroller_init (struct nxt200x_state* state) |
| 300 | { |
| 301 | u8 buf[9]; |
| 302 | u8 counter = 0; |
| 303 | dprintk("%s\n", __FUNCTION__); |
| 304 | |
| 305 | buf[0] = 0x00; |
| 306 | nxt200x_writebytes(state, 0x2b, buf, 1); |
| 307 | buf[0] = 0x70; |
| 308 | nxt200x_writebytes(state, 0x34, buf, 1); |
| 309 | buf[0] = 0x04; |
| 310 | nxt200x_writebytes(state, 0x35, buf, 1); |
| 311 | buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89; |
| 312 | buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0; |
| 313 | nxt200x_writebytes(state, 0x36, buf, 9); |
| 314 | buf[0] = 0x80; |
| 315 | nxt200x_writebytes(state, 0x21, buf, 1); |
| 316 | |
| 317 | while (counter < 20) { |
| 318 | nxt200x_readbytes(state, 0x21, buf, 1); |
| 319 | if (buf[0] == 0) |
| 320 | return; |
| 321 | msleep(10); |
| 322 | counter++; |
| 323 | } |
| 324 | |
| 325 | printk(KERN_WARNING "nxt200x: Timeout waiting for nxt2004 to init.\n"); |
| 326 | |
| 327 | return; |
| 328 | } |
| 329 | |
| 330 | static int nxt200x_writetuner (struct nxt200x_state* state, u8* data) |
| 331 | { |
| 332 | u8 buf, count = 0; |
| 333 | |
| 334 | dprintk("%s\n", __FUNCTION__); |
| 335 | |
| 336 | dprintk("Tuner Bytes: %02X %02X %02X %02X\n", data[0], data[1], data[2], data[3]); |
| 337 | |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 338 | /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip. |
| 339 | * direct write is required for Philips TUV1236D and ALPS TDHU2 */ |
| 340 | switch (state->demod_chip) { |
| 341 | case NXT2004: |
| 342 | if (i2c_writebytes(state, state->config->pll_address, data, 4)) |
Mauro Carvalho Chehab | 9101e62 | 2005-12-12 00:37:24 -0800 | [diff] [blame] | 343 | printk(KERN_WARNING "nxt200x: error writing to tuner\n"); |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 344 | /* wait until we have a lock */ |
| 345 | while (count < 20) { |
| 346 | i2c_readbytes(state, state->config->pll_address, &buf, 1); |
| 347 | if (buf & 0x40) |
| 348 | return 0; |
| 349 | msleep(100); |
| 350 | count++; |
| 351 | } |
| 352 | printk("nxt2004: timeout waiting for tuner lock\n"); |
| 353 | break; |
| 354 | case NXT2002: |
| 355 | /* set the i2c transfer speed to the tuner */ |
| 356 | buf = 0x03; |
| 357 | nxt200x_writebytes(state, 0x20, &buf, 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 358 | |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 359 | /* setup to transfer 4 bytes via i2c */ |
| 360 | buf = 0x04; |
| 361 | nxt200x_writebytes(state, 0x34, &buf, 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 362 | |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 363 | /* write actual tuner bytes */ |
| 364 | nxt200x_writebytes(state, 0x36, data, 4); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 365 | |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 366 | /* set tuner i2c address */ |
| 367 | buf = state->config->pll_address; |
| 368 | nxt200x_writebytes(state, 0x35, &buf, 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 369 | |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 370 | /* write UC Opmode to begin transfer */ |
| 371 | buf = 0x80; |
| 372 | nxt200x_writebytes(state, 0x21, &buf, 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 373 | |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 374 | while (count < 20) { |
| 375 | nxt200x_readbytes(state, 0x21, &buf, 1); |
| 376 | if ((buf & 0x80)== 0x00) |
| 377 | return 0; |
| 378 | msleep(100); |
| 379 | count++; |
| 380 | } |
| 381 | printk("nxt2002: timeout error writing tuner\n"); |
| 382 | break; |
| 383 | default: |
| 384 | return -EINVAL; |
| 385 | break; |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 386 | } |
Michael Krufky | f0fa86a | 2005-11-08 21:35:49 -0800 | [diff] [blame] | 387 | return 0; |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | static void nxt200x_agc_reset(struct nxt200x_state* state) |
| 391 | { |
| 392 | u8 buf; |
| 393 | dprintk("%s\n", __FUNCTION__); |
| 394 | |
| 395 | switch (state->demod_chip) { |
| 396 | case NXT2002: |
| 397 | buf = 0x08; |
| 398 | nxt200x_writebytes(state, 0x08, &buf, 1); |
| 399 | buf = 0x00; |
| 400 | nxt200x_writebytes(state, 0x08, &buf, 1); |
| 401 | break; |
| 402 | case NXT2004: |
| 403 | nxt200x_readreg_multibyte(state, 0x08, &buf, 1); |
| 404 | buf = 0x08; |
| 405 | nxt200x_writereg_multibyte(state, 0x08, &buf, 1); |
| 406 | buf = 0x00; |
| 407 | nxt200x_writereg_multibyte(state, 0x08, &buf, 1); |
| 408 | break; |
| 409 | default: |
| 410 | break; |
| 411 | } |
| 412 | return; |
| 413 | } |
| 414 | |
| 415 | static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) |
| 416 | { |
| 417 | |
| 418 | struct nxt200x_state* state = fe->demodulator_priv; |
| 419 | u8 buf[3], written = 0, chunkpos = 0; |
| 420 | u16 rambase, position, crc = 0; |
| 421 | |
| 422 | dprintk("%s\n", __FUNCTION__); |
| 423 | dprintk("Firmware is %zu bytes\n", fw->size); |
| 424 | |
| 425 | /* Get the RAM base for this nxt2002 */ |
| 426 | nxt200x_readbytes(state, 0x10, buf, 1); |
| 427 | |
| 428 | if (buf[0] & 0x10) |
| 429 | rambase = 0x1000; |
| 430 | else |
| 431 | rambase = 0x0000; |
| 432 | |
| 433 | dprintk("rambase on this nxt2002 is %04X\n", rambase); |
| 434 | |
| 435 | /* Hold the micro in reset while loading firmware */ |
| 436 | buf[0] = 0x80; |
| 437 | nxt200x_writebytes(state, 0x2B, buf, 1); |
| 438 | |
| 439 | for (position = 0; position < fw->size; position++) { |
| 440 | if (written == 0) { |
| 441 | crc = 0; |
| 442 | chunkpos = 0x28; |
| 443 | buf[0] = ((rambase + position) >> 8); |
| 444 | buf[1] = (rambase + position) & 0xFF; |
| 445 | buf[2] = 0x81; |
| 446 | /* write starting address */ |
| 447 | nxt200x_writebytes(state, 0x29, buf, 3); |
| 448 | } |
| 449 | written++; |
| 450 | chunkpos++; |
| 451 | |
| 452 | if ((written % 4) == 0) |
| 453 | nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4); |
| 454 | |
| 455 | crc = nxt200x_crc(crc, fw->data[position]); |
| 456 | |
| 457 | if ((written == 255) || (position+1 == fw->size)) { |
| 458 | /* write remaining bytes of firmware */ |
| 459 | nxt200x_writebytes(state, chunkpos+4-(written %4), |
| 460 | &fw->data[position-(written %4) + 1], |
| 461 | written %4); |
| 462 | buf[0] = crc << 8; |
| 463 | buf[1] = crc & 0xFF; |
| 464 | |
| 465 | /* write crc */ |
| 466 | nxt200x_writebytes(state, 0x2C, buf, 2); |
| 467 | |
| 468 | /* do a read to stop things */ |
| 469 | nxt200x_readbytes(state, 0x2A, buf, 1); |
| 470 | |
| 471 | /* set transfer mode to complete */ |
| 472 | buf[0] = 0x80; |
| 473 | nxt200x_writebytes(state, 0x2B, buf, 1); |
| 474 | |
| 475 | written = 0; |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | return 0; |
| 480 | }; |
| 481 | |
| 482 | static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw) |
| 483 | { |
| 484 | |
| 485 | struct nxt200x_state* state = fe->demodulator_priv; |
| 486 | u8 buf[3]; |
| 487 | u16 rambase, position, crc=0; |
| 488 | |
| 489 | dprintk("%s\n", __FUNCTION__); |
| 490 | dprintk("Firmware is %zu bytes\n", fw->size); |
| 491 | |
| 492 | /* set rambase */ |
| 493 | rambase = 0x1000; |
| 494 | |
| 495 | /* hold the micro in reset while loading firmware */ |
| 496 | buf[0] = 0x80; |
| 497 | nxt200x_writebytes(state, 0x2B, buf,1); |
| 498 | |
| 499 | /* calculate firmware CRC */ |
| 500 | for (position = 0; position < fw->size; position++) { |
Mauro Carvalho Chehab | 9101e62 | 2005-12-12 00:37:24 -0800 | [diff] [blame] | 501 | crc = nxt200x_crc(crc, fw->data[position]); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | buf[0] = rambase >> 8; |
| 505 | buf[1] = rambase & 0xFF; |
| 506 | buf[2] = 0x81; |
| 507 | /* write starting address */ |
| 508 | nxt200x_writebytes(state,0x29,buf,3); |
| 509 | |
| 510 | for (position = 0; position < fw->size;) { |
| 511 | nxt200x_writebytes(state, 0x2C, &fw->data[position], |
| 512 | fw->size-position > 255 ? 255 : fw->size-position); |
| 513 | position += (fw->size-position > 255 ? 255 : fw->size-position); |
| 514 | } |
| 515 | buf[0] = crc >> 8; |
| 516 | buf[1] = crc & 0xFF; |
| 517 | |
| 518 | dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]); |
| 519 | |
| 520 | /* write crc */ |
| 521 | nxt200x_writebytes(state, 0x2C, buf,2); |
| 522 | |
| 523 | /* do a read to stop things */ |
| 524 | nxt200x_readbytes(state, 0x2C, buf, 1); |
| 525 | |
| 526 | /* set transfer mode to complete */ |
| 527 | buf[0] = 0x80; |
| 528 | nxt200x_writebytes(state, 0x2B, buf,1); |
| 529 | |
| 530 | return 0; |
| 531 | }; |
| 532 | |
| 533 | static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe, |
| 534 | struct dvb_frontend_parameters *p) |
| 535 | { |
| 536 | struct nxt200x_state* state = fe->demodulator_priv; |
| 537 | u8 buf[4]; |
| 538 | |
| 539 | /* stop the micro first */ |
| 540 | nxt200x_microcontroller_stop(state); |
| 541 | |
| 542 | if (state->demod_chip == NXT2004) { |
| 543 | /* make sure demod is set to digital */ |
| 544 | buf[0] = 0x04; |
| 545 | nxt200x_writebytes(state, 0x14, buf, 1); |
| 546 | buf[0] = 0x00; |
| 547 | nxt200x_writebytes(state, 0x17, buf, 1); |
| 548 | } |
| 549 | |
| 550 | /* get tuning information */ |
| 551 | dvb_pll_configure(state->config->pll_desc, buf, p->frequency, 0); |
| 552 | |
| 553 | /* set additional params */ |
| 554 | switch (p->u.vsb.modulation) { |
| 555 | case QAM_64: |
| 556 | case QAM_256: |
| 557 | /* Set punctured clock for QAM */ |
| 558 | /* This is just a guess since I am unable to test it */ |
Michael Krufky | c6dd2d5 | 2005-11-08 21:35:47 -0800 | [diff] [blame] | 559 | if (state->config->set_ts_params) |
| 560 | state->config->set_ts_params(fe, 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 561 | |
Kirk Lapray | cc952d0 | 2005-11-08 21:36:02 -0800 | [diff] [blame] | 562 | /* set input */ |
| 563 | if (state->config->set_pll_input) |
| 564 | state->config->set_pll_input(buf, 1); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 565 | break; |
| 566 | case VSB_8: |
| 567 | /* Set non-punctured clock for VSB */ |
Michael Krufky | c6dd2d5 | 2005-11-08 21:35:47 -0800 | [diff] [blame] | 568 | if (state->config->set_ts_params) |
| 569 | state->config->set_ts_params(fe, 0); |
Kirk Lapray | cc952d0 | 2005-11-08 21:36:02 -0800 | [diff] [blame] | 570 | |
| 571 | /* set input */ |
| 572 | if (state->config->set_pll_input) |
| 573 | state->config->set_pll_input(buf, 0); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 574 | break; |
| 575 | default: |
| 576 | return -EINVAL; |
| 577 | break; |
| 578 | } |
| 579 | |
| 580 | /* write frequency information */ |
| 581 | nxt200x_writetuner(state, buf); |
| 582 | |
| 583 | /* reset the agc now that tuning has been completed */ |
| 584 | nxt200x_agc_reset(state); |
| 585 | |
| 586 | /* set target power level */ |
| 587 | switch (p->u.vsb.modulation) { |
| 588 | case QAM_64: |
| 589 | case QAM_256: |
| 590 | buf[0] = 0x74; |
| 591 | break; |
| 592 | case VSB_8: |
| 593 | buf[0] = 0x70; |
| 594 | break; |
| 595 | default: |
| 596 | return -EINVAL; |
| 597 | break; |
| 598 | } |
| 599 | nxt200x_writebytes(state, 0x42, buf, 1); |
| 600 | |
| 601 | /* configure sdm */ |
| 602 | switch (state->demod_chip) { |
| 603 | case NXT2002: |
| 604 | buf[0] = 0x87; |
| 605 | break; |
| 606 | case NXT2004: |
| 607 | buf[0] = 0x07; |
| 608 | break; |
| 609 | default: |
| 610 | return -EINVAL; |
| 611 | break; |
| 612 | } |
| 613 | nxt200x_writebytes(state, 0x57, buf, 1); |
| 614 | |
| 615 | /* write sdm1 input */ |
| 616 | buf[0] = 0x10; |
| 617 | buf[1] = 0x00; |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 618 | switch (state->demod_chip) { |
| 619 | case NXT2002: |
| 620 | nxt200x_writereg_multibyte(state, 0x58, buf, 2); |
| 621 | break; |
| 622 | case NXT2004: |
| 623 | nxt200x_writebytes(state, 0x58, buf, 2); |
| 624 | break; |
| 625 | default: |
| 626 | return -EINVAL; |
| 627 | break; |
| 628 | } |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 629 | |
| 630 | /* write sdmx input */ |
| 631 | switch (p->u.vsb.modulation) { |
| 632 | case QAM_64: |
| 633 | buf[0] = 0x68; |
| 634 | break; |
| 635 | case QAM_256: |
| 636 | buf[0] = 0x64; |
| 637 | break; |
| 638 | case VSB_8: |
| 639 | buf[0] = 0x60; |
| 640 | break; |
| 641 | default: |
| 642 | return -EINVAL; |
| 643 | break; |
| 644 | } |
| 645 | buf[1] = 0x00; |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 646 | switch (state->demod_chip) { |
| 647 | case NXT2002: |
| 648 | nxt200x_writereg_multibyte(state, 0x5C, buf, 2); |
| 649 | break; |
| 650 | case NXT2004: |
| 651 | nxt200x_writebytes(state, 0x5C, buf, 2); |
| 652 | break; |
| 653 | default: |
| 654 | return -EINVAL; |
| 655 | break; |
| 656 | } |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 657 | |
| 658 | /* write adc power lpf fc */ |
| 659 | buf[0] = 0x05; |
| 660 | nxt200x_writebytes(state, 0x43, buf, 1); |
| 661 | |
| 662 | if (state->demod_chip == NXT2004) { |
| 663 | /* write ??? */ |
| 664 | buf[0] = 0x00; |
| 665 | buf[1] = 0x00; |
| 666 | nxt200x_writebytes(state, 0x46, buf, 2); |
| 667 | } |
| 668 | |
| 669 | /* write accumulator2 input */ |
| 670 | buf[0] = 0x80; |
| 671 | buf[1] = 0x00; |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 672 | switch (state->demod_chip) { |
| 673 | case NXT2002: |
| 674 | nxt200x_writereg_multibyte(state, 0x4B, buf, 2); |
| 675 | break; |
| 676 | case NXT2004: |
| 677 | nxt200x_writebytes(state, 0x4B, buf, 2); |
| 678 | break; |
| 679 | default: |
| 680 | return -EINVAL; |
| 681 | break; |
| 682 | } |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 683 | |
| 684 | /* write kg1 */ |
| 685 | buf[0] = 0x00; |
| 686 | nxt200x_writebytes(state, 0x4D, buf, 1); |
| 687 | |
| 688 | /* write sdm12 lpf fc */ |
| 689 | buf[0] = 0x44; |
| 690 | nxt200x_writebytes(state, 0x55, buf, 1); |
| 691 | |
| 692 | /* write agc control reg */ |
| 693 | buf[0] = 0x04; |
| 694 | nxt200x_writebytes(state, 0x41, buf, 1); |
| 695 | |
| 696 | if (state->demod_chip == NXT2004) { |
| 697 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 698 | buf[0] = 0x24; |
| 699 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 700 | |
| 701 | /* soft reset? */ |
| 702 | nxt200x_readreg_multibyte(state, 0x08, buf, 1); |
| 703 | buf[0] = 0x10; |
| 704 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 705 | nxt200x_readreg_multibyte(state, 0x08, buf, 1); |
| 706 | buf[0] = 0x00; |
| 707 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 708 | |
| 709 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 710 | buf[0] = 0x04; |
| 711 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 712 | buf[0] = 0x00; |
| 713 | nxt200x_writereg_multibyte(state, 0x81, buf, 1); |
| 714 | buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; |
| 715 | nxt200x_writereg_multibyte(state, 0x82, buf, 3); |
| 716 | nxt200x_readreg_multibyte(state, 0x88, buf, 1); |
| 717 | buf[0] = 0x11; |
| 718 | nxt200x_writereg_multibyte(state, 0x88, buf, 1); |
| 719 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 720 | buf[0] = 0x44; |
| 721 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 722 | } |
| 723 | |
| 724 | /* write agc ucgp0 */ |
| 725 | switch (p->u.vsb.modulation) { |
| 726 | case QAM_64: |
| 727 | buf[0] = 0x02; |
| 728 | break; |
| 729 | case QAM_256: |
| 730 | buf[0] = 0x03; |
| 731 | break; |
| 732 | case VSB_8: |
| 733 | buf[0] = 0x00; |
| 734 | break; |
| 735 | default: |
| 736 | return -EINVAL; |
| 737 | break; |
| 738 | } |
| 739 | nxt200x_writebytes(state, 0x30, buf, 1); |
| 740 | |
| 741 | /* write agc control reg */ |
| 742 | buf[0] = 0x00; |
| 743 | nxt200x_writebytes(state, 0x41, buf, 1); |
| 744 | |
| 745 | /* write accumulator2 input */ |
| 746 | buf[0] = 0x80; |
| 747 | buf[1] = 0x00; |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 748 | switch (state->demod_chip) { |
| 749 | case NXT2002: |
| 750 | nxt200x_writereg_multibyte(state, 0x49, buf, 2); |
| 751 | nxt200x_writereg_multibyte(state, 0x4B, buf, 2); |
| 752 | break; |
| 753 | case NXT2004: |
| 754 | nxt200x_writebytes(state, 0x49, buf, 2); |
| 755 | nxt200x_writebytes(state, 0x4B, buf, 2); |
| 756 | break; |
| 757 | default: |
| 758 | return -EINVAL; |
| 759 | break; |
| 760 | } |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 761 | |
| 762 | /* write agc control reg */ |
| 763 | buf[0] = 0x04; |
| 764 | nxt200x_writebytes(state, 0x41, buf, 1); |
| 765 | |
| 766 | nxt200x_microcontroller_start(state); |
| 767 | |
| 768 | if (state->demod_chip == NXT2004) { |
| 769 | nxt2004_microcontroller_init(state); |
| 770 | |
| 771 | /* ???? */ |
| 772 | buf[0] = 0xF0; |
| 773 | buf[1] = 0x00; |
| 774 | nxt200x_writebytes(state, 0x5C, buf, 2); |
| 775 | } |
| 776 | |
| 777 | /* adjacent channel detection should be done here, but I don't |
| 778 | have any stations with this need so I cannot test it */ |
| 779 | |
| 780 | return 0; |
| 781 | } |
| 782 | |
| 783 | static int nxt200x_read_status(struct dvb_frontend* fe, fe_status_t* status) |
| 784 | { |
| 785 | struct nxt200x_state* state = fe->demodulator_priv; |
| 786 | u8 lock; |
| 787 | nxt200x_readbytes(state, 0x31, &lock, 1); |
| 788 | |
| 789 | *status = 0; |
| 790 | if (lock & 0x20) { |
| 791 | *status |= FE_HAS_SIGNAL; |
| 792 | *status |= FE_HAS_CARRIER; |
| 793 | *status |= FE_HAS_VITERBI; |
| 794 | *status |= FE_HAS_SYNC; |
| 795 | *status |= FE_HAS_LOCK; |
| 796 | } |
| 797 | return 0; |
| 798 | } |
| 799 | |
| 800 | static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber) |
| 801 | { |
| 802 | struct nxt200x_state* state = fe->demodulator_priv; |
| 803 | u8 b[3]; |
| 804 | |
| 805 | nxt200x_readreg_multibyte(state, 0xE6, b, 3); |
| 806 | |
| 807 | *ber = ((b[0] << 8) + b[1]) * 8; |
| 808 | |
| 809 | return 0; |
| 810 | } |
| 811 | |
| 812 | static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength) |
| 813 | { |
| 814 | struct nxt200x_state* state = fe->demodulator_priv; |
| 815 | u8 b[2]; |
| 816 | u16 temp = 0; |
| 817 | |
| 818 | /* setup to read cluster variance */ |
| 819 | b[0] = 0x00; |
| 820 | nxt200x_writebytes(state, 0xA1, b, 1); |
| 821 | |
| 822 | /* get multreg val */ |
| 823 | nxt200x_readreg_multibyte(state, 0xA6, b, 2); |
| 824 | |
| 825 | temp = (b[0] << 8) | b[1]; |
| 826 | *strength = ((0x7FFF - temp) & 0x0FFF) * 16; |
| 827 | |
| 828 | return 0; |
| 829 | } |
| 830 | |
| 831 | static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr) |
| 832 | { |
| 833 | |
| 834 | struct nxt200x_state* state = fe->demodulator_priv; |
| 835 | u8 b[2]; |
| 836 | u16 temp = 0, temp2; |
| 837 | u32 snrdb = 0; |
| 838 | |
| 839 | /* setup to read cluster variance */ |
| 840 | b[0] = 0x00; |
| 841 | nxt200x_writebytes(state, 0xA1, b, 1); |
| 842 | |
| 843 | /* get multreg val from 0xA6 */ |
| 844 | nxt200x_readreg_multibyte(state, 0xA6, b, 2); |
| 845 | |
| 846 | temp = (b[0] << 8) | b[1]; |
| 847 | temp2 = 0x7FFF - temp; |
| 848 | |
| 849 | /* snr will be in db */ |
| 850 | if (temp2 > 0x7F00) |
| 851 | snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) ); |
| 852 | else if (temp2 > 0x7EC0) |
| 853 | snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) ); |
| 854 | else if (temp2 > 0x7C00) |
| 855 | snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) ); |
| 856 | else |
| 857 | snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) ); |
| 858 | |
| 859 | /* the value reported back from the frontend will be FFFF=32db 0000=0db */ |
| 860 | *snr = snrdb * (0xFFFF/32000); |
| 861 | |
| 862 | return 0; |
| 863 | } |
| 864 | |
| 865 | static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
| 866 | { |
| 867 | struct nxt200x_state* state = fe->demodulator_priv; |
| 868 | u8 b[3]; |
| 869 | |
| 870 | nxt200x_readreg_multibyte(state, 0xE6, b, 3); |
| 871 | *ucblocks = b[2]; |
| 872 | |
| 873 | return 0; |
| 874 | } |
| 875 | |
| 876 | static int nxt200x_sleep(struct dvb_frontend* fe) |
| 877 | { |
| 878 | return 0; |
| 879 | } |
| 880 | |
| 881 | static int nxt2002_init(struct dvb_frontend* fe) |
| 882 | { |
| 883 | struct nxt200x_state* state = fe->demodulator_priv; |
| 884 | const struct firmware *fw; |
| 885 | int ret; |
| 886 | u8 buf[2]; |
| 887 | |
| 888 | /* request the firmware, this will block until someone uploads it */ |
| 889 | printk("nxt2002: Waiting for firmware upload (%s)...\n", NXT2002_DEFAULT_FIRMWARE); |
| 890 | ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, &state->i2c->dev); |
| 891 | printk("nxt2002: Waiting for firmware upload(2)...\n"); |
| 892 | if (ret) { |
| 893 | printk("nxt2002: No firmware uploaded (timeout or file not found?)\n"); |
| 894 | return ret; |
| 895 | } |
| 896 | |
| 897 | ret = nxt2002_load_firmware(fe, fw); |
| 898 | if (ret) { |
| 899 | printk("nxt2002: Writing firmware to device failed\n"); |
| 900 | release_firmware(fw); |
| 901 | return ret; |
| 902 | } |
| 903 | printk("nxt2002: Firmware upload complete\n"); |
| 904 | |
| 905 | /* Put the micro into reset */ |
| 906 | nxt200x_microcontroller_stop(state); |
| 907 | |
| 908 | /* ensure transfer is complete */ |
| 909 | buf[0]=0x00; |
| 910 | nxt200x_writebytes(state, 0x2B, buf, 1); |
| 911 | |
| 912 | /* Put the micro into reset for real this time */ |
| 913 | nxt200x_microcontroller_stop(state); |
| 914 | |
| 915 | /* soft reset everything (agc,frontend,eq,fec)*/ |
| 916 | buf[0] = 0x0F; |
| 917 | nxt200x_writebytes(state, 0x08, buf, 1); |
| 918 | buf[0] = 0x00; |
| 919 | nxt200x_writebytes(state, 0x08, buf, 1); |
| 920 | |
| 921 | /* write agc sdm configure */ |
| 922 | buf[0] = 0xF1; |
| 923 | nxt200x_writebytes(state, 0x57, buf, 1); |
| 924 | |
| 925 | /* write mod output format */ |
| 926 | buf[0] = 0x20; |
| 927 | nxt200x_writebytes(state, 0x09, buf, 1); |
| 928 | |
| 929 | /* write fec mpeg mode */ |
| 930 | buf[0] = 0x7E; |
| 931 | buf[1] = 0x00; |
| 932 | nxt200x_writebytes(state, 0xE9, buf, 2); |
| 933 | |
| 934 | /* write mux selection */ |
| 935 | buf[0] = 0x00; |
| 936 | nxt200x_writebytes(state, 0xCC, buf, 1); |
| 937 | |
| 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | static int nxt2004_init(struct dvb_frontend* fe) |
| 942 | { |
| 943 | struct nxt200x_state* state = fe->demodulator_priv; |
| 944 | const struct firmware *fw; |
| 945 | int ret; |
| 946 | u8 buf[3]; |
| 947 | |
| 948 | /* ??? */ |
| 949 | buf[0]=0x00; |
| 950 | nxt200x_writebytes(state, 0x1E, buf, 1); |
| 951 | |
| 952 | /* request the firmware, this will block until someone uploads it */ |
| 953 | printk("nxt2004: Waiting for firmware upload (%s)...\n", NXT2004_DEFAULT_FIRMWARE); |
| 954 | ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, &state->i2c->dev); |
| 955 | printk("nxt2004: Waiting for firmware upload(2)...\n"); |
| 956 | if (ret) { |
| 957 | printk("nxt2004: No firmware uploaded (timeout or file not found?)\n"); |
| 958 | return ret; |
| 959 | } |
| 960 | |
| 961 | ret = nxt2004_load_firmware(fe, fw); |
| 962 | if (ret) { |
| 963 | printk("nxt2004: Writing firmware to device failed\n"); |
| 964 | release_firmware(fw); |
| 965 | return ret; |
| 966 | } |
| 967 | printk("nxt2004: Firmware upload complete\n"); |
| 968 | |
| 969 | /* ensure transfer is complete */ |
| 970 | buf[0] = 0x01; |
| 971 | nxt200x_writebytes(state, 0x19, buf, 1); |
| 972 | |
| 973 | nxt2004_microcontroller_init(state); |
| 974 | nxt200x_microcontroller_stop(state); |
| 975 | nxt200x_microcontroller_stop(state); |
| 976 | nxt2004_microcontroller_init(state); |
| 977 | nxt200x_microcontroller_stop(state); |
| 978 | |
| 979 | /* soft reset everything (agc,frontend,eq,fec)*/ |
| 980 | buf[0] = 0xFF; |
| 981 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 982 | buf[0] = 0x00; |
| 983 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 984 | |
| 985 | /* write agc sdm configure */ |
| 986 | buf[0] = 0xD7; |
| 987 | nxt200x_writebytes(state, 0x57, buf, 1); |
| 988 | |
| 989 | /* ???*/ |
| 990 | buf[0] = 0x07; |
| 991 | buf[1] = 0xfe; |
| 992 | nxt200x_writebytes(state, 0x35, buf, 2); |
| 993 | buf[0] = 0x12; |
| 994 | nxt200x_writebytes(state, 0x34, buf, 1); |
| 995 | buf[0] = 0x80; |
| 996 | nxt200x_writebytes(state, 0x21, buf, 1); |
| 997 | |
| 998 | /* ???*/ |
| 999 | buf[0] = 0x21; |
| 1000 | nxt200x_writebytes(state, 0x0A, buf, 1); |
| 1001 | |
| 1002 | /* ???*/ |
| 1003 | buf[0] = 0x01; |
| 1004 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1005 | |
| 1006 | /* write fec mpeg mode */ |
| 1007 | buf[0] = 0x7E; |
| 1008 | buf[1] = 0x00; |
| 1009 | nxt200x_writebytes(state, 0xE9, buf, 2); |
| 1010 | |
| 1011 | /* write mux selection */ |
| 1012 | buf[0] = 0x00; |
| 1013 | nxt200x_writebytes(state, 0xCC, buf, 1); |
| 1014 | |
| 1015 | /* ???*/ |
| 1016 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1017 | buf[0] = 0x00; |
| 1018 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1019 | |
| 1020 | /* soft reset? */ |
| 1021 | nxt200x_readreg_multibyte(state, 0x08, buf, 1); |
| 1022 | buf[0] = 0x10; |
| 1023 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 1024 | nxt200x_readreg_multibyte(state, 0x08, buf, 1); |
| 1025 | buf[0] = 0x00; |
| 1026 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 1027 | |
| 1028 | /* ???*/ |
| 1029 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1030 | buf[0] = 0x01; |
| 1031 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1032 | buf[0] = 0x70; |
| 1033 | nxt200x_writereg_multibyte(state, 0x81, buf, 1); |
| 1034 | buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66; |
| 1035 | nxt200x_writereg_multibyte(state, 0x82, buf, 3); |
| 1036 | |
| 1037 | nxt200x_readreg_multibyte(state, 0x88, buf, 1); |
| 1038 | buf[0] = 0x11; |
| 1039 | nxt200x_writereg_multibyte(state, 0x88, buf, 1); |
| 1040 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1041 | buf[0] = 0x40; |
| 1042 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1043 | |
| 1044 | nxt200x_readbytes(state, 0x10, buf, 1); |
| 1045 | buf[0] = 0x10; |
| 1046 | nxt200x_writebytes(state, 0x10, buf, 1); |
| 1047 | nxt200x_readbytes(state, 0x0A, buf, 1); |
| 1048 | buf[0] = 0x21; |
| 1049 | nxt200x_writebytes(state, 0x0A, buf, 1); |
| 1050 | |
| 1051 | nxt2004_microcontroller_init(state); |
| 1052 | |
| 1053 | buf[0] = 0x21; |
| 1054 | nxt200x_writebytes(state, 0x0A, buf, 1); |
| 1055 | buf[0] = 0x7E; |
| 1056 | nxt200x_writebytes(state, 0xE9, buf, 1); |
| 1057 | buf[0] = 0x00; |
| 1058 | nxt200x_writebytes(state, 0xEA, buf, 1); |
| 1059 | |
| 1060 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1061 | buf[0] = 0x00; |
| 1062 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1063 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1064 | buf[0] = 0x00; |
| 1065 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1066 | |
| 1067 | /* soft reset? */ |
| 1068 | nxt200x_readreg_multibyte(state, 0x08, buf, 1); |
| 1069 | buf[0] = 0x10; |
| 1070 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 1071 | nxt200x_readreg_multibyte(state, 0x08, buf, 1); |
| 1072 | buf[0] = 0x00; |
| 1073 | nxt200x_writereg_multibyte(state, 0x08, buf, 1); |
| 1074 | |
| 1075 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1076 | buf[0] = 0x04; |
| 1077 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1078 | buf[0] = 0x00; |
| 1079 | nxt200x_writereg_multibyte(state, 0x81, buf, 1); |
| 1080 | buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00; |
| 1081 | nxt200x_writereg_multibyte(state, 0x82, buf, 3); |
| 1082 | |
| 1083 | nxt200x_readreg_multibyte(state, 0x88, buf, 1); |
| 1084 | buf[0] = 0x11; |
| 1085 | nxt200x_writereg_multibyte(state, 0x88, buf, 1); |
| 1086 | |
| 1087 | nxt200x_readreg_multibyte(state, 0x80, buf, 1); |
| 1088 | buf[0] = 0x44; |
| 1089 | nxt200x_writereg_multibyte(state, 0x80, buf, 1); |
| 1090 | |
| 1091 | /* initialize tuner */ |
| 1092 | nxt200x_readbytes(state, 0x10, buf, 1); |
| 1093 | buf[0] = 0x12; |
| 1094 | nxt200x_writebytes(state, 0x10, buf, 1); |
| 1095 | buf[0] = 0x04; |
| 1096 | nxt200x_writebytes(state, 0x13, buf, 1); |
| 1097 | buf[0] = 0x00; |
| 1098 | nxt200x_writebytes(state, 0x16, buf, 1); |
| 1099 | buf[0] = 0x04; |
| 1100 | nxt200x_writebytes(state, 0x14, buf, 1); |
| 1101 | buf[0] = 0x00; |
| 1102 | nxt200x_writebytes(state, 0x14, buf, 1); |
| 1103 | nxt200x_writebytes(state, 0x17, buf, 1); |
| 1104 | nxt200x_writebytes(state, 0x14, buf, 1); |
| 1105 | nxt200x_writebytes(state, 0x17, buf, 1); |
| 1106 | |
| 1107 | return 0; |
| 1108 | } |
| 1109 | |
| 1110 | static int nxt200x_init(struct dvb_frontend* fe) |
| 1111 | { |
| 1112 | struct nxt200x_state* state = fe->demodulator_priv; |
| 1113 | int ret = 0; |
| 1114 | |
| 1115 | if (!state->initialised) { |
| 1116 | switch (state->demod_chip) { |
| 1117 | case NXT2002: |
| 1118 | ret = nxt2002_init(fe); |
| 1119 | break; |
| 1120 | case NXT2004: |
| 1121 | ret = nxt2004_init(fe); |
| 1122 | break; |
| 1123 | default: |
| 1124 | return -EINVAL; |
| 1125 | break; |
| 1126 | } |
| 1127 | state->initialised = 1; |
| 1128 | } |
| 1129 | return ret; |
| 1130 | } |
| 1131 | |
| 1132 | static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings) |
| 1133 | { |
| 1134 | fesettings->min_delay_ms = 500; |
| 1135 | fesettings->step_size = 0; |
| 1136 | fesettings->max_drift = 0; |
| 1137 | return 0; |
| 1138 | } |
| 1139 | |
| 1140 | static void nxt200x_release(struct dvb_frontend* fe) |
| 1141 | { |
| 1142 | struct nxt200x_state* state = fe->demodulator_priv; |
| 1143 | kfree(state); |
| 1144 | } |
| 1145 | |
| 1146 | static struct dvb_frontend_ops nxt200x_ops; |
| 1147 | |
| 1148 | struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config, |
| 1149 | struct i2c_adapter* i2c) |
| 1150 | { |
| 1151 | struct nxt200x_state* state = NULL; |
| 1152 | u8 buf [] = {0,0,0,0,0}; |
| 1153 | |
| 1154 | /* allocate memory for the internal state */ |
Panagiotis Issaris | 7408187 | 2006-01-11 19:40:56 -0200 | [diff] [blame] | 1155 | state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 1156 | if (state == NULL) |
| 1157 | goto error; |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 1158 | |
| 1159 | /* setup the state */ |
| 1160 | state->config = config; |
| 1161 | state->i2c = i2c; |
| 1162 | memcpy(&state->ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops)); |
| 1163 | state->initialised = 0; |
| 1164 | |
| 1165 | /* read card id */ |
| 1166 | nxt200x_readbytes(state, 0x00, buf, 5); |
| 1167 | dprintk("NXT info: %02X %02X %02X %02X %02X\n", |
| 1168 | buf[0], buf[1], buf[2], buf[3], buf[4]); |
| 1169 | |
| 1170 | /* set demod chip */ |
| 1171 | switch (buf[0]) { |
| 1172 | case 0x04: |
| 1173 | state->demod_chip = NXT2002; |
| 1174 | printk("nxt200x: NXT2002 Detected\n"); |
| 1175 | break; |
| 1176 | case 0x05: |
| 1177 | state->demod_chip = NXT2004; |
| 1178 | printk("nxt200x: NXT2004 Detected\n"); |
| 1179 | break; |
| 1180 | default: |
| 1181 | goto error; |
| 1182 | } |
| 1183 | |
| 1184 | /* make sure demod chip is supported */ |
| 1185 | switch (state->demod_chip) { |
| 1186 | case NXT2002: |
| 1187 | if (buf[0] != 0x04) goto error; /* device id */ |
| 1188 | if (buf[1] != 0x02) goto error; /* fab id */ |
| 1189 | if (buf[2] != 0x11) goto error; /* month */ |
| 1190 | if (buf[3] != 0x20) goto error; /* year msb */ |
| 1191 | if (buf[4] != 0x00) goto error; /* year lsb */ |
| 1192 | break; |
| 1193 | case NXT2004: |
| 1194 | if (buf[0] != 0x05) goto error; /* device id */ |
| 1195 | break; |
| 1196 | default: |
| 1197 | goto error; |
| 1198 | } |
| 1199 | |
| 1200 | /* create dvb_frontend */ |
| 1201 | state->frontend.ops = &state->ops; |
| 1202 | state->frontend.demodulator_priv = state; |
| 1203 | return &state->frontend; |
| 1204 | |
| 1205 | error: |
Michael Krufky | 6d35ae3 | 2005-11-08 21:35:48 -0800 | [diff] [blame] | 1206 | kfree(state); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 1207 | printk("Unknown/Unsupported NXT chip: %02X %02X %02X %02X %02X\n", |
| 1208 | buf[0], buf[1], buf[2], buf[3], buf[4]); |
| 1209 | return NULL; |
| 1210 | } |
| 1211 | |
| 1212 | static struct dvb_frontend_ops nxt200x_ops = { |
| 1213 | |
| 1214 | .info = { |
| 1215 | .name = "Nextwave NXT200X VSB/QAM frontend", |
| 1216 | .type = FE_ATSC, |
| 1217 | .frequency_min = 54000000, |
| 1218 | .frequency_max = 860000000, |
| 1219 | .frequency_stepsize = 166666, /* stepsize is just a guess */ |
| 1220 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
| 1221 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | |
| 1222 | FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256 |
| 1223 | }, |
| 1224 | |
| 1225 | .release = nxt200x_release, |
| 1226 | |
| 1227 | .init = nxt200x_init, |
| 1228 | .sleep = nxt200x_sleep, |
| 1229 | |
| 1230 | .set_frontend = nxt200x_setup_frontend_parameters, |
| 1231 | .get_tune_settings = nxt200x_get_tune_settings, |
| 1232 | |
| 1233 | .read_status = nxt200x_read_status, |
| 1234 | .read_ber = nxt200x_read_ber, |
| 1235 | .read_signal_strength = nxt200x_read_signal_strength, |
| 1236 | .read_snr = nxt200x_read_snr, |
| 1237 | .read_ucblocks = nxt200x_read_ucblocks, |
| 1238 | }; |
| 1239 | |
| 1240 | module_param(debug, int, 0644); |
| 1241 | MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); |
| 1242 | |
| 1243 | MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); |
Michael Krufky | 46365f3 | 2006-01-23 09:52:39 -0200 | [diff] [blame] | 1244 | MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob"); |
Kirk Lapray | 04a4592 | 2005-11-08 21:35:46 -0800 | [diff] [blame] | 1245 | MODULE_LICENSE("GPL"); |
| 1246 | |
| 1247 | EXPORT_SYMBOL(nxt200x_attach); |
| 1248 | |