blob: 65f86bc30df3f265df9aac813a227b1df3145f30 [file] [log] [blame]
Matt Wagantall292aace2012-01-26 19:12:34 -08001/*
Seemanta Dutta4e2d49c2013-04-05 16:28:11 -07002 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Matt Wagantall292aace2012-01-26 19:12:34 -08003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/io.h>
Matt Wagantall292aace2012-01-26 19:12:34 -080017#include <linux/delay.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/platform_device.h>
Matt Wagantall292aace2012-01-26 19:12:34 -080021#include <linux/clk.h>
Matt Wagantall19ac4fd2012-02-03 20:18:23 -080022#include <linux/smp.h>
Stephen Boydd86214b2012-05-10 15:26:35 -070023#include <linux/miscdevice.h>
24#include <linux/reboot.h>
25#include <linux/interrupt.h>
Matt Wagantall292aace2012-01-26 19:12:34 -080026
Matt Wagantall292aace2012-01-26 19:12:34 -080027#include <mach/msm_xo.h>
Matt Wagantall556d3f72012-02-16 17:36:29 -080028#include <mach/socinfo.h>
Matt Wagantallf3471ef2012-03-09 14:21:54 -080029#include <mach/msm_bus_board.h>
30#include <mach/msm_bus.h>
Stephen Boydd86214b2012-05-10 15:26:35 -070031#include <mach/subsystem_restart.h>
Seemanta Dutta4e2d49c2013-04-05 16:28:11 -070032#include <mach/ramdump.h>
Matt Wagantall292aace2012-01-26 19:12:34 -080033
34#include "peripheral-loader.h"
35#include "scm-pas.h"
Stephen Boydd86214b2012-05-10 15:26:35 -070036#include "smd_private.h"
Matt Wagantall292aace2012-01-26 19:12:34 -080037
38#define GSS_CSR_AHB_CLK_SEL 0x0
39#define GSS_CSR_RESET 0x4
40#define GSS_CSR_CLK_BLK_CONFIG 0x8
41#define GSS_CSR_CLK_ENABLE 0xC
42#define GSS_CSR_BOOT_REMAP 0x14
43#define GSS_CSR_POWER_UP_DOWN 0x18
Matt Wagantall19ac4fd2012-02-03 20:18:23 -080044#define GSS_CSR_CFG_HID 0x2C
Matt Wagantall292aace2012-01-26 19:12:34 -080045
Stephen Boyde24edf52012-07-12 17:46:19 -070046#define GSS_SLP_CLK_CTL 0x2C60
47#define GSS_RESET 0x2C64
48#define GSS_CLAMP_ENA 0x2C68
49#define GSS_CXO_SRC_CTL 0x2C74
Matt Wagantall292aace2012-01-26 19:12:34 -080050
Stephen Boyde24edf52012-07-12 17:46:19 -070051#define PLL5_STATUS 0x30F8
52#define PLL_ENA_GSS 0x3480
Matt Wagantall292aace2012-01-26 19:12:34 -080053
54#define PLL5_VOTE BIT(5)
55#define PLL_STATUS BIT(16)
56#define REMAP_ENABLE BIT(16)
57#define A5_POWER_STATUS BIT(4)
58#define A5_POWER_ENA BIT(0)
59#define NAV_POWER_ENA BIT(1)
60#define XO_CLK_BRANCH_ENA BIT(0)
61#define SLP_CLK_BRANCH_ENA BIT(4)
62#define A5_RESET BIT(0)
63
Matt Wagantall292aace2012-01-26 19:12:34 -080064struct gss_data {
65 void __iomem *base;
Matt Wagantall19ac4fd2012-02-03 20:18:23 -080066 void __iomem *qgic2_base;
Stephen Boyde24edf52012-07-12 17:46:19 -070067 void __iomem *cbase;
Matt Wagantall292aace2012-01-26 19:12:34 -080068 struct clk *xo;
Stephen Boyde83a0a22012-06-29 13:51:27 -070069 struct pil_desc pil_desc;
Stephen Boydd86214b2012-05-10 15:26:35 -070070 struct miscdevice misc_dev;
71 struct subsys_device *subsys;
72 struct subsys_desc subsys_desc;
73 int crash_shutdown;
74 int irq;
Stephen Boyd4684add2012-06-27 12:57:18 -070075 void *subsys_handle;
Stephen Boydd86214b2012-05-10 15:26:35 -070076 struct ramdump_device *ramdump_dev;
77 struct ramdump_device *smem_ramdump_dev;
Matt Wagantall292aace2012-01-26 19:12:34 -080078};
79
Stephen Boydab2b9072012-03-22 10:59:22 -070080static int make_gss_proxy_votes(struct pil_desc *pil)
Matt Wagantall292aace2012-01-26 19:12:34 -080081{
82 int ret;
Stephen Boydab2b9072012-03-22 10:59:22 -070083 struct gss_data *drv = dev_get_drvdata(pil->dev);
Matt Wagantall292aace2012-01-26 19:12:34 -080084
85 ret = clk_prepare_enable(drv->xo);
86 if (ret) {
Stephen Boydab2b9072012-03-22 10:59:22 -070087 dev_err(pil->dev, "Failed to enable XO\n");
Matt Wagantall292aace2012-01-26 19:12:34 -080088 return ret;
89 }
Matt Wagantall292aace2012-01-26 19:12:34 -080090 return 0;
91}
92
Stephen Boydab2b9072012-03-22 10:59:22 -070093static void remove_gss_proxy_votes(struct pil_desc *pil)
Matt Wagantall292aace2012-01-26 19:12:34 -080094{
Stephen Boydab2b9072012-03-22 10:59:22 -070095 struct gss_data *drv = dev_get_drvdata(pil->dev);
Matt Wagantall292aace2012-01-26 19:12:34 -080096 clk_disable_unprepare(drv->xo);
97}
98
Matt Wagantall292aace2012-01-26 19:12:34 -080099static void gss_init(struct gss_data *drv)
100{
101 void __iomem *base = drv->base;
Stephen Boyde24edf52012-07-12 17:46:19 -0700102 void __iomem *cbase = drv->cbase;
Matt Wagantall292aace2012-01-26 19:12:34 -0800103
104 /* Supply clocks to GSS. */
Stephen Boyde24edf52012-07-12 17:46:19 -0700105 writel_relaxed(XO_CLK_BRANCH_ENA, cbase + GSS_CXO_SRC_CTL);
106 writel_relaxed(SLP_CLK_BRANCH_ENA, cbase + GSS_SLP_CLK_CTL);
Matt Wagantall292aace2012-01-26 19:12:34 -0800107
108 /* Deassert GSS reset and clamps. */
Stephen Boyde24edf52012-07-12 17:46:19 -0700109 writel_relaxed(0x0, cbase + GSS_RESET);
110 writel_relaxed(0x0, cbase + GSS_CLAMP_ENA);
Matt Wagantall292aace2012-01-26 19:12:34 -0800111 mb();
112
113 /*
114 * Configure clock source and dividers for 288MHz core, 144MHz AXI and
115 * 72MHz AHB, all derived from the 288MHz PLL.
116 */
117 writel_relaxed(0x341, base + GSS_CSR_CLK_BLK_CONFIG);
118 writel_relaxed(0x1, base + GSS_CSR_AHB_CLK_SEL);
119
120 /* Assert all GSS resets. */
121 writel_relaxed(0x7F, base + GSS_CSR_RESET);
122
123 /* Enable all bus clocks and wait for resets to propagate. */
124 writel_relaxed(0x1F, base + GSS_CSR_CLK_ENABLE);
125 mb();
126 udelay(1);
127
128 /* Release subsystem from reset, but leave A5 in reset. */
129 writel_relaxed(A5_RESET, base + GSS_CSR_RESET);
130}
131
Matt Wagantall556d3f72012-02-16 17:36:29 -0800132static void cfg_qgic2_bus_access(void *data)
Matt Wagantall292aace2012-01-26 19:12:34 -0800133{
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800134 struct gss_data *drv = data;
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800135 int i;
Matt Wagantall292aace2012-01-26 19:12:34 -0800136
Matt Wagantall556d3f72012-02-16 17:36:29 -0800137 /*
138 * Apply a 8064 v1.0 workaround to configure QGIC bus access.
139 * This must be done from Krait 0 to configure the Master ID
140 * correctly.
141 */
142 writel_relaxed(0x2, drv->base + GSS_CSR_CFG_HID);
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800143 for (i = 0; i <= 3; i++)
144 readl_relaxed(drv->qgic2_base);
Matt Wagantall292aace2012-01-26 19:12:34 -0800145}
146
147static int pil_gss_shutdown(struct pil_desc *pil)
148{
149 struct gss_data *drv = dev_get_drvdata(pil->dev);
150 void __iomem *base = drv->base;
Stephen Boyde24edf52012-07-12 17:46:19 -0700151 void __iomem *cbase = drv->cbase;
Matt Wagantall292aace2012-01-26 19:12:34 -0800152 u32 regval;
153 int ret;
154
155 ret = clk_prepare_enable(drv->xo);
156 if (ret) {
157 dev_err(pil->dev, "Failed to enable XO\n");
158 return ret;
159 }
160
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800161 /* Make sure bus port is halted. */
162 msm_bus_axi_porthalt(MSM_BUS_MASTER_GSS_NAV);
163
Matt Wagantall292aace2012-01-26 19:12:34 -0800164 /*
165 * Vote PLL on in GSS's voting register and wait for it to enable.
166 * The PLL must be enable to switch the GFMUX to a low-power source.
167 */
Stephen Boyde24edf52012-07-12 17:46:19 -0700168 writel_relaxed(PLL5_VOTE, cbase + PLL_ENA_GSS);
169 while ((readl_relaxed(cbase + PLL5_STATUS) & PLL_STATUS) == 0)
Matt Wagantall292aace2012-01-26 19:12:34 -0800170 cpu_relax();
171
172 /* Perform one-time GSS initialization. */
173 gss_init(drv);
174
175 /* Assert A5 reset. */
176 regval = readl_relaxed(base + GSS_CSR_RESET);
177 regval |= A5_RESET;
178 writel_relaxed(regval, base + GSS_CSR_RESET);
179
180 /* Power down A5 and NAV. */
181 regval = readl_relaxed(base + GSS_CSR_POWER_UP_DOWN);
182 regval &= ~(A5_POWER_ENA|NAV_POWER_ENA);
183 writel_relaxed(regval, base + GSS_CSR_POWER_UP_DOWN);
184
185 /* Select XO clock source and increase dividers to save power. */
186 regval = readl_relaxed(base + GSS_CSR_CLK_BLK_CONFIG);
187 regval |= 0x3FF;
188 writel_relaxed(regval, base + GSS_CSR_CLK_BLK_CONFIG);
189
190 /* Disable bus clocks. */
191 writel_relaxed(0x1F, base + GSS_CSR_CLK_ENABLE);
192
193 /* Clear GSS PLL votes. */
Stephen Boyde24edf52012-07-12 17:46:19 -0700194 writel_relaxed(0, cbase + PLL_ENA_GSS);
Matt Wagantall292aace2012-01-26 19:12:34 -0800195 mb();
196
197 clk_disable_unprepare(drv->xo);
Matt Wagantall292aace2012-01-26 19:12:34 -0800198
199 return 0;
200}
201
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800202static int pil_gss_reset(struct pil_desc *pil)
203{
204 struct gss_data *drv = dev_get_drvdata(pil->dev);
205 void __iomem *base = drv->base;
Tianyi Gou819851e2013-04-16 16:05:56 -0700206 phys_addr_t start_addr = pil_get_entry_addr(pil);
Stephen Boyde24edf52012-07-12 17:46:19 -0700207 void __iomem *cbase = drv->cbase;
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800208 int ret;
209
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800210 /* Unhalt bus port. */
211 ret = msm_bus_axi_portunhalt(MSM_BUS_MASTER_GSS_NAV);
212 if (ret) {
213 dev_err(pil->dev, "Failed to unhalt bus port\n");
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800214 return ret;
215 }
216
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800217 /* Vote PLL on in GSS's voting register and wait for it to enable. */
Stephen Boyde24edf52012-07-12 17:46:19 -0700218 writel_relaxed(PLL5_VOTE, cbase + PLL_ENA_GSS);
219 while ((readl_relaxed(cbase + PLL5_STATUS) & PLL_STATUS) == 0)
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800220 cpu_relax();
221
222 /* Perform GSS initialization. */
223 gss_init(drv);
224
225 /* Configure boot address and enable remap. */
226 writel_relaxed(REMAP_ENABLE | (start_addr >> 16),
227 base + GSS_CSR_BOOT_REMAP);
228
229 /* Power up A5 core. */
230 writel_relaxed(A5_POWER_ENA, base + GSS_CSR_POWER_UP_DOWN);
231 while (!(readl_relaxed(base + GSS_CSR_POWER_UP_DOWN) & A5_POWER_STATUS))
232 cpu_relax();
233
Matt Wagantall556d3f72012-02-16 17:36:29 -0800234 if (cpu_is_apq8064() &&
235 ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) &&
236 (SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0))) {
237 ret = smp_call_function_single(0, cfg_qgic2_bus_access, drv, 1);
238 if (ret) {
239 pr_err("Failed to configure QGIC2 bus access\n");
240 pil_gss_shutdown(pil);
241 return ret;
242 }
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800243 }
244
245 /* Release A5 from reset. */
246 writel_relaxed(0x0, base + GSS_CSR_RESET);
247
248 return 0;
249}
250
Matt Wagantall292aace2012-01-26 19:12:34 -0800251static struct pil_reset_ops pil_gss_ops = {
Matt Wagantall292aace2012-01-26 19:12:34 -0800252 .auth_and_reset = pil_gss_reset,
253 .shutdown = pil_gss_shutdown,
Stephen Boydab2b9072012-03-22 10:59:22 -0700254 .proxy_vote = make_gss_proxy_votes,
255 .proxy_unvote = remove_gss_proxy_votes,
Matt Wagantall292aace2012-01-26 19:12:34 -0800256};
257
Matt Wagantall11afeee2012-02-07 18:38:59 -0800258static int pil_gss_init_image_trusted(struct pil_desc *pil,
259 const u8 *metadata, size_t size)
260{
261 return pas_init_image(PAS_GSS, metadata, size);
262}
263
Matt Wagantall556d3f72012-02-16 17:36:29 -0800264static int pil_gss_shutdown_trusted(struct pil_desc *pil)
265{
266 struct gss_data *drv = dev_get_drvdata(pil->dev);
267 int ret;
268
Stephen Boyd7663ccc2012-02-21 19:34:55 -0800269 /*
270 * CXO is used in the secure shutdown code to configure the processor
271 * for low power mode.
272 */
273 ret = clk_prepare_enable(drv->xo);
274 if (ret) {
275 dev_err(pil->dev, "Failed to enable XO\n");
Matt Wagantall556d3f72012-02-16 17:36:29 -0800276 return ret;
Stephen Boyd7663ccc2012-02-21 19:34:55 -0800277 }
Matt Wagantall556d3f72012-02-16 17:36:29 -0800278
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800279 msm_bus_axi_porthalt(MSM_BUS_MASTER_GSS_NAV);
Stephen Boyd7663ccc2012-02-21 19:34:55 -0800280 ret = pas_shutdown(PAS_GSS);
281 clk_disable_unprepare(drv->xo);
Matt Wagantall556d3f72012-02-16 17:36:29 -0800282
283 return ret;
284}
285
Matt Wagantall11afeee2012-02-07 18:38:59 -0800286static int pil_gss_reset_trusted(struct pil_desc *pil)
287{
Matt Wagantall11afeee2012-02-07 18:38:59 -0800288 int err;
289
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800290 err = msm_bus_axi_portunhalt(MSM_BUS_MASTER_GSS_NAV);
291 if (err) {
292 dev_err(pil->dev, "Failed to unhalt bus port\n");
Stephen Boydab2b9072012-03-22 10:59:22 -0700293 goto out;
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800294 }
Matt Wagantall11afeee2012-02-07 18:38:59 -0800295
296 err = pas_auth_and_reset(PAS_GSS);
297 if (err)
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800298 goto halt_port;
Matt Wagantall11afeee2012-02-07 18:38:59 -0800299
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800300 return 0;
Matt Wagantall556d3f72012-02-16 17:36:29 -0800301
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800302halt_port:
303 msm_bus_axi_porthalt(MSM_BUS_MASTER_GSS_NAV);
Matt Wagantallf3471ef2012-03-09 14:21:54 -0800304out:
Matt Wagantall11afeee2012-02-07 18:38:59 -0800305 return err;
306}
307
Matt Wagantall11afeee2012-02-07 18:38:59 -0800308static struct pil_reset_ops pil_gss_ops_trusted = {
309 .init_image = pil_gss_init_image_trusted,
Matt Wagantall11afeee2012-02-07 18:38:59 -0800310 .auth_and_reset = pil_gss_reset_trusted,
311 .shutdown = pil_gss_shutdown_trusted,
Stephen Boydab2b9072012-03-22 10:59:22 -0700312 .proxy_vote = make_gss_proxy_votes,
313 .proxy_unvote = remove_gss_proxy_votes,
Matt Wagantall11afeee2012-02-07 18:38:59 -0800314};
315
Stephen Boydd86214b2012-05-10 15:26:35 -0700316#define MAX_SSR_REASON_LEN 81U
317
318static void log_gss_sfr(void)
319{
320 u32 size;
321 char *smem_reason, reason[MAX_SSR_REASON_LEN];
322
323 smem_reason = smem_get_entry(SMEM_SSR_REASON_MSS0, &size);
324 if (!smem_reason || !size) {
325 pr_err("GSS subsystem failure reason: (unknown, smem_get_entry failed).\n");
326 return;
327 }
328 if (!smem_reason[0]) {
329 pr_err("GSS subsystem failure reason: (unknown, init string found).\n");
330 return;
331 }
332
333 size = min(size, MAX_SSR_REASON_LEN-1);
334 memcpy(reason, smem_reason, size);
335 reason[size] = '\0';
336 pr_err("GSS subsystem failure reason: %s.\n", reason);
337
338 smem_reason[0] = '\0';
339 wmb();
340}
341
342static void restart_gss(struct gss_data *drv)
343{
344 log_gss_sfr();
345 subsystem_restart_dev(drv->subsys);
346}
347
348static void smsm_state_cb(void *data, uint32_t old_state, uint32_t new_state)
349{
350 struct gss_data *drv = data;
351
352 /* Ignore if we're the one that set SMSM_RESET */
353 if (drv->crash_shutdown)
354 return;
355
356 if (new_state & SMSM_RESET) {
357 pr_err("GSS SMSM state changed to SMSM_RESET.\n"
358 "Probable err_fatal on the GSS. "
359 "Calling subsystem restart...\n");
360 restart_gss(drv);
361 }
362}
363
Stephen Boyd4684add2012-06-27 12:57:18 -0700364static int gss_start(const struct subsys_desc *desc)
365{
Stephen Boyd4684add2012-06-27 12:57:18 -0700366 struct gss_data *drv;
367
368 drv = container_of(desc, struct gss_data, subsys_desc);
Stephen Boyde83a0a22012-06-29 13:51:27 -0700369 return pil_boot(&drv->pil_desc);
Stephen Boyd4684add2012-06-27 12:57:18 -0700370}
371
372static void gss_stop(const struct subsys_desc *desc)
373{
374 struct gss_data *drv;
375
376 drv = container_of(desc, struct gss_data, subsys_desc);
Stephen Boyde83a0a22012-06-29 13:51:27 -0700377 pil_shutdown(&drv->pil_desc);
Stephen Boyd4684add2012-06-27 12:57:18 -0700378}
379
Stephen Boydd86214b2012-05-10 15:26:35 -0700380static int gss_shutdown(const struct subsys_desc *desc)
381{
382 struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc);
383
Stephen Boyde83a0a22012-06-29 13:51:27 -0700384 pil_shutdown(&drv->pil_desc);
Stephen Boydd86214b2012-05-10 15:26:35 -0700385 disable_irq_nosync(drv->irq);
386
387 return 0;
388}
389
390static int gss_powerup(const struct subsys_desc *desc)
391{
392 struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc);
393
Stephen Boyde83a0a22012-06-29 13:51:27 -0700394 pil_boot(&drv->pil_desc);
Stephen Boydd86214b2012-05-10 15:26:35 -0700395 enable_irq(drv->irq);
396 return 0;
397}
398
399void gss_crash_shutdown(const struct subsys_desc *desc)
400{
401 struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc);
402
403 drv->crash_shutdown = 1;
404 smsm_reset_modem(SMSM_RESET);
405}
406
Stephen Boydd86214b2012-05-10 15:26:35 -0700407static struct ramdump_segment smem_segments[] = {
408 {0x80000000, 0x00200000},
409};
410
411static int gss_ramdump(int enable, const struct subsys_desc *desc)
412{
413 int ret;
414 struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc);
415
Stephen Boyd5eb17ce2012-11-29 15:34:21 -0800416 if (!enable)
417 return 0;
Stephen Boydd86214b2012-05-10 15:26:35 -0700418
Stephen Boyd5eb17ce2012-11-29 15:34:21 -0800419 ret = pil_do_ramdump(&drv->pil_desc, drv->ramdump_dev);
420 if (ret < 0) {
421 pr_err("Unable to dump gss memory\n");
422 return ret;
423 }
424
425 ret = do_elf_ramdump(drv->smem_ramdump_dev, smem_segments,
426 ARRAY_SIZE(smem_segments));
427 if (ret < 0) {
428 pr_err("Unable to dump smem memory (rc = %d).\n", ret);
429 return ret;
Stephen Boydd86214b2012-05-10 15:26:35 -0700430 }
431
432 return 0;
433}
434
435static irqreturn_t gss_wdog_bite_irq(int irq, void *dev_id)
436{
437 struct gss_data *drv = dev_id;
438
439 pr_err("Watchdog bite received from GSS!\n");
440 restart_gss(drv);
441
442 return IRQ_HANDLED;
443}
444
445static int gss_open(struct inode *inode, struct file *filp)
446{
Stephen Boydd86214b2012-05-10 15:26:35 -0700447 struct miscdevice *c = filp->private_data;
448 struct gss_data *drv = container_of(c, struct gss_data, misc_dev);
449
Stephen Boyd4684add2012-06-27 12:57:18 -0700450 drv->subsys_handle = subsystem_get("gss");
Stephen Boyd77db8bb2012-06-27 15:15:16 -0700451 if (IS_ERR(drv->subsys_handle)) {
452 pr_debug("%s - subsystem_get returned error\n", __func__);
453 return PTR_ERR(drv->subsys_handle);
454 }
Stephen Boydd86214b2012-05-10 15:26:35 -0700455
456 return 0;
457}
458
459static int gss_release(struct inode *inode, struct file *filp)
460{
461 struct miscdevice *c = filp->private_data;
462 struct gss_data *drv = container_of(c, struct gss_data, misc_dev);
463
Stephen Boyd4684add2012-06-27 12:57:18 -0700464 subsystem_put(drv->subsys_handle);
465 pr_debug("%s subsystem_put called on GSS\n", __func__);
Stephen Boydd86214b2012-05-10 15:26:35 -0700466
467 return 0;
468}
469
470const struct file_operations gss_file_ops = {
471 .open = gss_open,
472 .release = gss_release,
473 .owner = THIS_MODULE,
474};
475
Matt Wagantall292aace2012-01-26 19:12:34 -0800476static int __devinit pil_gss_probe(struct platform_device *pdev)
477{
478 struct gss_data *drv;
479 struct resource *res;
480 struct pil_desc *desc;
Stephen Boydd86214b2012-05-10 15:26:35 -0700481 int ret;
Matt Wagantall292aace2012-01-26 19:12:34 -0800482
Matt Wagantall292aace2012-01-26 19:12:34 -0800483 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
484 if (!drv)
485 return -ENOMEM;
486 platform_set_drvdata(pdev, drv);
487
Stephen Boydf8f89282012-07-16 18:05:48 -0700488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 drv->base = devm_request_and_ioremap(&pdev->dev, res);
Matt Wagantall292aace2012-01-26 19:12:34 -0800490 if (!drv->base)
491 return -ENOMEM;
492
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800493 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Stephen Boydf8f89282012-07-16 18:05:48 -0700494 drv->qgic2_base = devm_request_and_ioremap(&pdev->dev, res);
Matt Wagantall19ac4fd2012-02-03 20:18:23 -0800495 if (!drv->qgic2_base)
496 return -ENOMEM;
497
Stephen Boyde24edf52012-07-12 17:46:19 -0700498 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
499 if (!res)
500 return -EINVAL;
501 drv->cbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
502 if (!drv->cbase)
503 return -ENOMEM;
504
Stephen Boyd22b04472012-03-23 15:23:10 -0700505 drv->xo = devm_clk_get(&pdev->dev, "xo");
Matt Wagantall292aace2012-01-26 19:12:34 -0800506 if (IS_ERR(drv->xo))
507 return PTR_ERR(drv->xo);
508
Stephen Boydd86214b2012-05-10 15:26:35 -0700509 drv->irq = platform_get_irq(pdev, 0);
510 if (drv->irq < 0)
511 return drv->irq;
512
Stephen Boyde24edf52012-07-12 17:46:19 -0700513 desc = &drv->pil_desc;
Matt Wagantall292aace2012-01-26 19:12:34 -0800514 desc->name = "gss";
515 desc->dev = &pdev->dev;
Stephen Boyd6d67d252011-09-27 11:50:05 -0700516 desc->owner = THIS_MODULE;
Stephen Boydab2b9072012-03-22 10:59:22 -0700517 desc->proxy_timeout = 10000;
Matt Wagantall292aace2012-01-26 19:12:34 -0800518
Matt Wagantall11afeee2012-02-07 18:38:59 -0800519 if (pas_supported(PAS_GSS) > 0) {
520 desc->ops = &pil_gss_ops_trusted;
521 dev_info(&pdev->dev, "using secure boot\n");
522 } else {
523 desc->ops = &pil_gss_ops;
524 dev_info(&pdev->dev, "using non-secure boot\n");
525 }
Stephen Boyde83a0a22012-06-29 13:51:27 -0700526 ret = pil_desc_init(desc);
527 if (ret)
528 return ret;
529
Stephen Boyd95a1c542012-06-21 12:45:11 -0700530 /* Force into low power mode because hardware doesn't do this */
531 desc->ops->shutdown(desc);
Matt Wagantall292aace2012-01-26 19:12:34 -0800532
Stephen Boydd86214b2012-05-10 15:26:35 -0700533 ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET,
534 smsm_state_cb, drv);
535 if (ret < 0)
536 dev_warn(&pdev->dev, "Unable to register SMSM callback\n");
537
538 drv->subsys_desc.name = "gss";
Stephen Boyd4684add2012-06-27 12:57:18 -0700539 drv->subsys_desc.dev = &pdev->dev;
540 drv->subsys_desc.owner = THIS_MODULE;
541 drv->subsys_desc.start = gss_start;
542 drv->subsys_desc.stop = gss_stop;
Stephen Boydd86214b2012-05-10 15:26:35 -0700543 drv->subsys_desc.shutdown = gss_shutdown;
544 drv->subsys_desc.powerup = gss_powerup;
545 drv->subsys_desc.ramdump = gss_ramdump;
546 drv->subsys_desc.crash_shutdown = gss_crash_shutdown;
547
548 drv->subsys = subsys_register(&drv->subsys_desc);
549 if (IS_ERR(drv->subsys)) {
550 ret = PTR_ERR(drv->subsys);
551 goto err_subsys;
552 }
553
554 drv->misc_dev.minor = MISC_DYNAMIC_MINOR;
555 drv->misc_dev.name = "gss";
556 drv->misc_dev.fops = &gss_file_ops;
557 ret = misc_register(&drv->misc_dev);
558 if (ret)
559 goto err_misc;
560
Stephen Boydc1a72612012-07-05 14:07:35 -0700561 drv->ramdump_dev = create_ramdump_device("gss", &pdev->dev);
Stephen Boydd86214b2012-05-10 15:26:35 -0700562 if (!drv->ramdump_dev) {
563 ret = -ENOMEM;
564 goto err_ramdump;
565 }
566
Stephen Boydc1a72612012-07-05 14:07:35 -0700567 drv->smem_ramdump_dev = create_ramdump_device("smem-gss", &pdev->dev);
Stephen Boydd86214b2012-05-10 15:26:35 -0700568 if (!drv->smem_ramdump_dev) {
569 ret = -ENOMEM;
570 goto err_smem;
571 }
572
573 ret = devm_request_irq(&pdev->dev, drv->irq, gss_wdog_bite_irq,
574 IRQF_TRIGGER_RISING, "gss_a5_wdog", drv);
575 if (ret < 0)
576 goto err;
Stephen Boyd6d67d252011-09-27 11:50:05 -0700577 return 0;
Stephen Boydd86214b2012-05-10 15:26:35 -0700578err:
579 destroy_ramdump_device(drv->smem_ramdump_dev);
580err_smem:
581 destroy_ramdump_device(drv->ramdump_dev);
582err_ramdump:
583 misc_deregister(&drv->misc_dev);
584err_misc:
585 subsys_unregister(drv->subsys);
586err_subsys:
Stephen Boyde83a0a22012-06-29 13:51:27 -0700587 pil_desc_release(desc);
Stephen Boydd86214b2012-05-10 15:26:35 -0700588 return ret;
Matt Wagantall292aace2012-01-26 19:12:34 -0800589}
590
591static int __devexit pil_gss_remove(struct platform_device *pdev)
592{
593 struct gss_data *drv = platform_get_drvdata(pdev);
Stephen Boydd86214b2012-05-10 15:26:35 -0700594
595 destroy_ramdump_device(drv->smem_ramdump_dev);
596 destroy_ramdump_device(drv->ramdump_dev);
597 misc_deregister(&drv->misc_dev);
598 subsys_unregister(drv->subsys);
Stephen Boyde83a0a22012-06-29 13:51:27 -0700599 pil_desc_release(&drv->pil_desc);
Stephen Boydd86214b2012-05-10 15:26:35 -0700600
Matt Wagantall292aace2012-01-26 19:12:34 -0800601 return 0;
602}
603
604static struct platform_driver pil_gss_driver = {
605 .probe = pil_gss_probe,
606 .remove = __devexit_p(pil_gss_remove),
607 .driver = {
608 .name = "pil_gss",
609 .owner = THIS_MODULE,
610 },
611};
612
613static int __init pil_gss_init(void)
614{
615 return platform_driver_register(&pil_gss_driver);
616}
617module_init(pil_gss_init);
618
619static void __exit pil_gss_exit(void)
620{
621 platform_driver_unregister(&pil_gss_driver);
622}
623module_exit(pil_gss_exit);
624
625MODULE_DESCRIPTION("Support for booting the GSS processor");
626MODULE_LICENSE("GPL v2");