Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 1 | /* |
Seemanta Dutta | 4e2d49c | 2013-04-05 16:28:11 -0700 | [diff] [blame] | 2 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/io.h> |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 17 | #include <linux/delay.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/platform_device.h> |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 21 | #include <linux/clk.h> |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 22 | #include <linux/smp.h> |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 23 | #include <linux/miscdevice.h> |
| 24 | #include <linux/reboot.h> |
| 25 | #include <linux/interrupt.h> |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 26 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 27 | #include <mach/msm_xo.h> |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 28 | #include <mach/socinfo.h> |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 29 | #include <mach/msm_bus_board.h> |
| 30 | #include <mach/msm_bus.h> |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 31 | #include <mach/subsystem_restart.h> |
Seemanta Dutta | 4e2d49c | 2013-04-05 16:28:11 -0700 | [diff] [blame] | 32 | #include <mach/ramdump.h> |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 33 | |
| 34 | #include "peripheral-loader.h" |
| 35 | #include "scm-pas.h" |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 36 | #include "smd_private.h" |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 37 | |
| 38 | #define GSS_CSR_AHB_CLK_SEL 0x0 |
| 39 | #define GSS_CSR_RESET 0x4 |
| 40 | #define GSS_CSR_CLK_BLK_CONFIG 0x8 |
| 41 | #define GSS_CSR_CLK_ENABLE 0xC |
| 42 | #define GSS_CSR_BOOT_REMAP 0x14 |
| 43 | #define GSS_CSR_POWER_UP_DOWN 0x18 |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 44 | #define GSS_CSR_CFG_HID 0x2C |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 45 | |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 46 | #define GSS_SLP_CLK_CTL 0x2C60 |
| 47 | #define GSS_RESET 0x2C64 |
| 48 | #define GSS_CLAMP_ENA 0x2C68 |
| 49 | #define GSS_CXO_SRC_CTL 0x2C74 |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 50 | |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 51 | #define PLL5_STATUS 0x30F8 |
| 52 | #define PLL_ENA_GSS 0x3480 |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 53 | |
| 54 | #define PLL5_VOTE BIT(5) |
| 55 | #define PLL_STATUS BIT(16) |
| 56 | #define REMAP_ENABLE BIT(16) |
| 57 | #define A5_POWER_STATUS BIT(4) |
| 58 | #define A5_POWER_ENA BIT(0) |
| 59 | #define NAV_POWER_ENA BIT(1) |
| 60 | #define XO_CLK_BRANCH_ENA BIT(0) |
| 61 | #define SLP_CLK_BRANCH_ENA BIT(4) |
| 62 | #define A5_RESET BIT(0) |
| 63 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 64 | struct gss_data { |
| 65 | void __iomem *base; |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 66 | void __iomem *qgic2_base; |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 67 | void __iomem *cbase; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 68 | struct clk *xo; |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 69 | struct pil_desc pil_desc; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 70 | struct miscdevice misc_dev; |
| 71 | struct subsys_device *subsys; |
| 72 | struct subsys_desc subsys_desc; |
| 73 | int crash_shutdown; |
| 74 | int irq; |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 75 | void *subsys_handle; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 76 | struct ramdump_device *ramdump_dev; |
| 77 | struct ramdump_device *smem_ramdump_dev; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 78 | }; |
| 79 | |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 80 | static int make_gss_proxy_votes(struct pil_desc *pil) |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 81 | { |
| 82 | int ret; |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 83 | struct gss_data *drv = dev_get_drvdata(pil->dev); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 84 | |
| 85 | ret = clk_prepare_enable(drv->xo); |
| 86 | if (ret) { |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 87 | dev_err(pil->dev, "Failed to enable XO\n"); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 88 | return ret; |
| 89 | } |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 90 | return 0; |
| 91 | } |
| 92 | |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 93 | static void remove_gss_proxy_votes(struct pil_desc *pil) |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 94 | { |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 95 | struct gss_data *drv = dev_get_drvdata(pil->dev); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 96 | clk_disable_unprepare(drv->xo); |
| 97 | } |
| 98 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 99 | static void gss_init(struct gss_data *drv) |
| 100 | { |
| 101 | void __iomem *base = drv->base; |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 102 | void __iomem *cbase = drv->cbase; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 103 | |
| 104 | /* Supply clocks to GSS. */ |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 105 | writel_relaxed(XO_CLK_BRANCH_ENA, cbase + GSS_CXO_SRC_CTL); |
| 106 | writel_relaxed(SLP_CLK_BRANCH_ENA, cbase + GSS_SLP_CLK_CTL); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 107 | |
| 108 | /* Deassert GSS reset and clamps. */ |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 109 | writel_relaxed(0x0, cbase + GSS_RESET); |
| 110 | writel_relaxed(0x0, cbase + GSS_CLAMP_ENA); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 111 | mb(); |
| 112 | |
| 113 | /* |
| 114 | * Configure clock source and dividers for 288MHz core, 144MHz AXI and |
| 115 | * 72MHz AHB, all derived from the 288MHz PLL. |
| 116 | */ |
| 117 | writel_relaxed(0x341, base + GSS_CSR_CLK_BLK_CONFIG); |
| 118 | writel_relaxed(0x1, base + GSS_CSR_AHB_CLK_SEL); |
| 119 | |
| 120 | /* Assert all GSS resets. */ |
| 121 | writel_relaxed(0x7F, base + GSS_CSR_RESET); |
| 122 | |
| 123 | /* Enable all bus clocks and wait for resets to propagate. */ |
| 124 | writel_relaxed(0x1F, base + GSS_CSR_CLK_ENABLE); |
| 125 | mb(); |
| 126 | udelay(1); |
| 127 | |
| 128 | /* Release subsystem from reset, but leave A5 in reset. */ |
| 129 | writel_relaxed(A5_RESET, base + GSS_CSR_RESET); |
| 130 | } |
| 131 | |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 132 | static void cfg_qgic2_bus_access(void *data) |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 133 | { |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 134 | struct gss_data *drv = data; |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 135 | int i; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 136 | |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 137 | /* |
| 138 | * Apply a 8064 v1.0 workaround to configure QGIC bus access. |
| 139 | * This must be done from Krait 0 to configure the Master ID |
| 140 | * correctly. |
| 141 | */ |
| 142 | writel_relaxed(0x2, drv->base + GSS_CSR_CFG_HID); |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 143 | for (i = 0; i <= 3; i++) |
| 144 | readl_relaxed(drv->qgic2_base); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static int pil_gss_shutdown(struct pil_desc *pil) |
| 148 | { |
| 149 | struct gss_data *drv = dev_get_drvdata(pil->dev); |
| 150 | void __iomem *base = drv->base; |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 151 | void __iomem *cbase = drv->cbase; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 152 | u32 regval; |
| 153 | int ret; |
| 154 | |
| 155 | ret = clk_prepare_enable(drv->xo); |
| 156 | if (ret) { |
| 157 | dev_err(pil->dev, "Failed to enable XO\n"); |
| 158 | return ret; |
| 159 | } |
| 160 | |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 161 | /* Make sure bus port is halted. */ |
| 162 | msm_bus_axi_porthalt(MSM_BUS_MASTER_GSS_NAV); |
| 163 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 164 | /* |
| 165 | * Vote PLL on in GSS's voting register and wait for it to enable. |
| 166 | * The PLL must be enable to switch the GFMUX to a low-power source. |
| 167 | */ |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 168 | writel_relaxed(PLL5_VOTE, cbase + PLL_ENA_GSS); |
| 169 | while ((readl_relaxed(cbase + PLL5_STATUS) & PLL_STATUS) == 0) |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 170 | cpu_relax(); |
| 171 | |
| 172 | /* Perform one-time GSS initialization. */ |
| 173 | gss_init(drv); |
| 174 | |
| 175 | /* Assert A5 reset. */ |
| 176 | regval = readl_relaxed(base + GSS_CSR_RESET); |
| 177 | regval |= A5_RESET; |
| 178 | writel_relaxed(regval, base + GSS_CSR_RESET); |
| 179 | |
| 180 | /* Power down A5 and NAV. */ |
| 181 | regval = readl_relaxed(base + GSS_CSR_POWER_UP_DOWN); |
| 182 | regval &= ~(A5_POWER_ENA|NAV_POWER_ENA); |
| 183 | writel_relaxed(regval, base + GSS_CSR_POWER_UP_DOWN); |
| 184 | |
| 185 | /* Select XO clock source and increase dividers to save power. */ |
| 186 | regval = readl_relaxed(base + GSS_CSR_CLK_BLK_CONFIG); |
| 187 | regval |= 0x3FF; |
| 188 | writel_relaxed(regval, base + GSS_CSR_CLK_BLK_CONFIG); |
| 189 | |
| 190 | /* Disable bus clocks. */ |
| 191 | writel_relaxed(0x1F, base + GSS_CSR_CLK_ENABLE); |
| 192 | |
| 193 | /* Clear GSS PLL votes. */ |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 194 | writel_relaxed(0, cbase + PLL_ENA_GSS); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 195 | mb(); |
| 196 | |
| 197 | clk_disable_unprepare(drv->xo); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 202 | static int pil_gss_reset(struct pil_desc *pil) |
| 203 | { |
| 204 | struct gss_data *drv = dev_get_drvdata(pil->dev); |
| 205 | void __iomem *base = drv->base; |
Tianyi Gou | 819851e | 2013-04-16 16:05:56 -0700 | [diff] [blame] | 206 | phys_addr_t start_addr = pil_get_entry_addr(pil); |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 207 | void __iomem *cbase = drv->cbase; |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 208 | int ret; |
| 209 | |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 210 | /* Unhalt bus port. */ |
| 211 | ret = msm_bus_axi_portunhalt(MSM_BUS_MASTER_GSS_NAV); |
| 212 | if (ret) { |
| 213 | dev_err(pil->dev, "Failed to unhalt bus port\n"); |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 214 | return ret; |
| 215 | } |
| 216 | |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 217 | /* Vote PLL on in GSS's voting register and wait for it to enable. */ |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 218 | writel_relaxed(PLL5_VOTE, cbase + PLL_ENA_GSS); |
| 219 | while ((readl_relaxed(cbase + PLL5_STATUS) & PLL_STATUS) == 0) |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 220 | cpu_relax(); |
| 221 | |
| 222 | /* Perform GSS initialization. */ |
| 223 | gss_init(drv); |
| 224 | |
| 225 | /* Configure boot address and enable remap. */ |
| 226 | writel_relaxed(REMAP_ENABLE | (start_addr >> 16), |
| 227 | base + GSS_CSR_BOOT_REMAP); |
| 228 | |
| 229 | /* Power up A5 core. */ |
| 230 | writel_relaxed(A5_POWER_ENA, base + GSS_CSR_POWER_UP_DOWN); |
| 231 | while (!(readl_relaxed(base + GSS_CSR_POWER_UP_DOWN) & A5_POWER_STATUS)) |
| 232 | cpu_relax(); |
| 233 | |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 234 | if (cpu_is_apq8064() && |
| 235 | ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) && |
| 236 | (SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0))) { |
| 237 | ret = smp_call_function_single(0, cfg_qgic2_bus_access, drv, 1); |
| 238 | if (ret) { |
| 239 | pr_err("Failed to configure QGIC2 bus access\n"); |
| 240 | pil_gss_shutdown(pil); |
| 241 | return ret; |
| 242 | } |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | /* Release A5 from reset. */ |
| 246 | writel_relaxed(0x0, base + GSS_CSR_RESET); |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 251 | static struct pil_reset_ops pil_gss_ops = { |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 252 | .auth_and_reset = pil_gss_reset, |
| 253 | .shutdown = pil_gss_shutdown, |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 254 | .proxy_vote = make_gss_proxy_votes, |
| 255 | .proxy_unvote = remove_gss_proxy_votes, |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 256 | }; |
| 257 | |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 258 | static int pil_gss_init_image_trusted(struct pil_desc *pil, |
| 259 | const u8 *metadata, size_t size) |
| 260 | { |
| 261 | return pas_init_image(PAS_GSS, metadata, size); |
| 262 | } |
| 263 | |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 264 | static int pil_gss_shutdown_trusted(struct pil_desc *pil) |
| 265 | { |
| 266 | struct gss_data *drv = dev_get_drvdata(pil->dev); |
| 267 | int ret; |
| 268 | |
Stephen Boyd | 7663ccc | 2012-02-21 19:34:55 -0800 | [diff] [blame] | 269 | /* |
| 270 | * CXO is used in the secure shutdown code to configure the processor |
| 271 | * for low power mode. |
| 272 | */ |
| 273 | ret = clk_prepare_enable(drv->xo); |
| 274 | if (ret) { |
| 275 | dev_err(pil->dev, "Failed to enable XO\n"); |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 276 | return ret; |
Stephen Boyd | 7663ccc | 2012-02-21 19:34:55 -0800 | [diff] [blame] | 277 | } |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 278 | |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 279 | msm_bus_axi_porthalt(MSM_BUS_MASTER_GSS_NAV); |
Stephen Boyd | 7663ccc | 2012-02-21 19:34:55 -0800 | [diff] [blame] | 280 | ret = pas_shutdown(PAS_GSS); |
| 281 | clk_disable_unprepare(drv->xo); |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 282 | |
| 283 | return ret; |
| 284 | } |
| 285 | |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 286 | static int pil_gss_reset_trusted(struct pil_desc *pil) |
| 287 | { |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 288 | int err; |
| 289 | |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 290 | err = msm_bus_axi_portunhalt(MSM_BUS_MASTER_GSS_NAV); |
| 291 | if (err) { |
| 292 | dev_err(pil->dev, "Failed to unhalt bus port\n"); |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 293 | goto out; |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 294 | } |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 295 | |
| 296 | err = pas_auth_and_reset(PAS_GSS); |
| 297 | if (err) |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 298 | goto halt_port; |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 299 | |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 300 | return 0; |
Matt Wagantall | 556d3f7 | 2012-02-16 17:36:29 -0800 | [diff] [blame] | 301 | |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 302 | halt_port: |
| 303 | msm_bus_axi_porthalt(MSM_BUS_MASTER_GSS_NAV); |
Matt Wagantall | f3471ef | 2012-03-09 14:21:54 -0800 | [diff] [blame] | 304 | out: |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 305 | return err; |
| 306 | } |
| 307 | |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 308 | static struct pil_reset_ops pil_gss_ops_trusted = { |
| 309 | .init_image = pil_gss_init_image_trusted, |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 310 | .auth_and_reset = pil_gss_reset_trusted, |
| 311 | .shutdown = pil_gss_shutdown_trusted, |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 312 | .proxy_vote = make_gss_proxy_votes, |
| 313 | .proxy_unvote = remove_gss_proxy_votes, |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 314 | }; |
| 315 | |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 316 | #define MAX_SSR_REASON_LEN 81U |
| 317 | |
| 318 | static void log_gss_sfr(void) |
| 319 | { |
| 320 | u32 size; |
| 321 | char *smem_reason, reason[MAX_SSR_REASON_LEN]; |
| 322 | |
| 323 | smem_reason = smem_get_entry(SMEM_SSR_REASON_MSS0, &size); |
| 324 | if (!smem_reason || !size) { |
| 325 | pr_err("GSS subsystem failure reason: (unknown, smem_get_entry failed).\n"); |
| 326 | return; |
| 327 | } |
| 328 | if (!smem_reason[0]) { |
| 329 | pr_err("GSS subsystem failure reason: (unknown, init string found).\n"); |
| 330 | return; |
| 331 | } |
| 332 | |
| 333 | size = min(size, MAX_SSR_REASON_LEN-1); |
| 334 | memcpy(reason, smem_reason, size); |
| 335 | reason[size] = '\0'; |
| 336 | pr_err("GSS subsystem failure reason: %s.\n", reason); |
| 337 | |
| 338 | smem_reason[0] = '\0'; |
| 339 | wmb(); |
| 340 | } |
| 341 | |
| 342 | static void restart_gss(struct gss_data *drv) |
| 343 | { |
| 344 | log_gss_sfr(); |
| 345 | subsystem_restart_dev(drv->subsys); |
| 346 | } |
| 347 | |
| 348 | static void smsm_state_cb(void *data, uint32_t old_state, uint32_t new_state) |
| 349 | { |
| 350 | struct gss_data *drv = data; |
| 351 | |
| 352 | /* Ignore if we're the one that set SMSM_RESET */ |
| 353 | if (drv->crash_shutdown) |
| 354 | return; |
| 355 | |
| 356 | if (new_state & SMSM_RESET) { |
| 357 | pr_err("GSS SMSM state changed to SMSM_RESET.\n" |
| 358 | "Probable err_fatal on the GSS. " |
| 359 | "Calling subsystem restart...\n"); |
| 360 | restart_gss(drv); |
| 361 | } |
| 362 | } |
| 363 | |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 364 | static int gss_start(const struct subsys_desc *desc) |
| 365 | { |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 366 | struct gss_data *drv; |
| 367 | |
| 368 | drv = container_of(desc, struct gss_data, subsys_desc); |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 369 | return pil_boot(&drv->pil_desc); |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | static void gss_stop(const struct subsys_desc *desc) |
| 373 | { |
| 374 | struct gss_data *drv; |
| 375 | |
| 376 | drv = container_of(desc, struct gss_data, subsys_desc); |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 377 | pil_shutdown(&drv->pil_desc); |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 378 | } |
| 379 | |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 380 | static int gss_shutdown(const struct subsys_desc *desc) |
| 381 | { |
| 382 | struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc); |
| 383 | |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 384 | pil_shutdown(&drv->pil_desc); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 385 | disable_irq_nosync(drv->irq); |
| 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | static int gss_powerup(const struct subsys_desc *desc) |
| 391 | { |
| 392 | struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc); |
| 393 | |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 394 | pil_boot(&drv->pil_desc); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 395 | enable_irq(drv->irq); |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | void gss_crash_shutdown(const struct subsys_desc *desc) |
| 400 | { |
| 401 | struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc); |
| 402 | |
| 403 | drv->crash_shutdown = 1; |
| 404 | smsm_reset_modem(SMSM_RESET); |
| 405 | } |
| 406 | |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 407 | static struct ramdump_segment smem_segments[] = { |
| 408 | {0x80000000, 0x00200000}, |
| 409 | }; |
| 410 | |
| 411 | static int gss_ramdump(int enable, const struct subsys_desc *desc) |
| 412 | { |
| 413 | int ret; |
| 414 | struct gss_data *drv = container_of(desc, struct gss_data, subsys_desc); |
| 415 | |
Stephen Boyd | 5eb17ce | 2012-11-29 15:34:21 -0800 | [diff] [blame] | 416 | if (!enable) |
| 417 | return 0; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 418 | |
Stephen Boyd | 5eb17ce | 2012-11-29 15:34:21 -0800 | [diff] [blame] | 419 | ret = pil_do_ramdump(&drv->pil_desc, drv->ramdump_dev); |
| 420 | if (ret < 0) { |
| 421 | pr_err("Unable to dump gss memory\n"); |
| 422 | return ret; |
| 423 | } |
| 424 | |
| 425 | ret = do_elf_ramdump(drv->smem_ramdump_dev, smem_segments, |
| 426 | ARRAY_SIZE(smem_segments)); |
| 427 | if (ret < 0) { |
| 428 | pr_err("Unable to dump smem memory (rc = %d).\n", ret); |
| 429 | return ret; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | return 0; |
| 433 | } |
| 434 | |
| 435 | static irqreturn_t gss_wdog_bite_irq(int irq, void *dev_id) |
| 436 | { |
| 437 | struct gss_data *drv = dev_id; |
| 438 | |
| 439 | pr_err("Watchdog bite received from GSS!\n"); |
| 440 | restart_gss(drv); |
| 441 | |
| 442 | return IRQ_HANDLED; |
| 443 | } |
| 444 | |
| 445 | static int gss_open(struct inode *inode, struct file *filp) |
| 446 | { |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 447 | struct miscdevice *c = filp->private_data; |
| 448 | struct gss_data *drv = container_of(c, struct gss_data, misc_dev); |
| 449 | |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 450 | drv->subsys_handle = subsystem_get("gss"); |
Stephen Boyd | 77db8bb | 2012-06-27 15:15:16 -0700 | [diff] [blame] | 451 | if (IS_ERR(drv->subsys_handle)) { |
| 452 | pr_debug("%s - subsystem_get returned error\n", __func__); |
| 453 | return PTR_ERR(drv->subsys_handle); |
| 454 | } |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 455 | |
| 456 | return 0; |
| 457 | } |
| 458 | |
| 459 | static int gss_release(struct inode *inode, struct file *filp) |
| 460 | { |
| 461 | struct miscdevice *c = filp->private_data; |
| 462 | struct gss_data *drv = container_of(c, struct gss_data, misc_dev); |
| 463 | |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 464 | subsystem_put(drv->subsys_handle); |
| 465 | pr_debug("%s subsystem_put called on GSS\n", __func__); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 466 | |
| 467 | return 0; |
| 468 | } |
| 469 | |
| 470 | const struct file_operations gss_file_ops = { |
| 471 | .open = gss_open, |
| 472 | .release = gss_release, |
| 473 | .owner = THIS_MODULE, |
| 474 | }; |
| 475 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 476 | static int __devinit pil_gss_probe(struct platform_device *pdev) |
| 477 | { |
| 478 | struct gss_data *drv; |
| 479 | struct resource *res; |
| 480 | struct pil_desc *desc; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 481 | int ret; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 482 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 483 | drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); |
| 484 | if (!drv) |
| 485 | return -ENOMEM; |
| 486 | platform_set_drvdata(pdev, drv); |
| 487 | |
Stephen Boyd | f8f8928 | 2012-07-16 18:05:48 -0700 | [diff] [blame] | 488 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 489 | drv->base = devm_request_and_ioremap(&pdev->dev, res); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 490 | if (!drv->base) |
| 491 | return -ENOMEM; |
| 492 | |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 493 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
Stephen Boyd | f8f8928 | 2012-07-16 18:05:48 -0700 | [diff] [blame] | 494 | drv->qgic2_base = devm_request_and_ioremap(&pdev->dev, res); |
Matt Wagantall | 19ac4fd | 2012-02-03 20:18:23 -0800 | [diff] [blame] | 495 | if (!drv->qgic2_base) |
| 496 | return -ENOMEM; |
| 497 | |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 498 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
| 499 | if (!res) |
| 500 | return -EINVAL; |
| 501 | drv->cbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
| 502 | if (!drv->cbase) |
| 503 | return -ENOMEM; |
| 504 | |
Stephen Boyd | 22b0447 | 2012-03-23 15:23:10 -0700 | [diff] [blame] | 505 | drv->xo = devm_clk_get(&pdev->dev, "xo"); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 506 | if (IS_ERR(drv->xo)) |
| 507 | return PTR_ERR(drv->xo); |
| 508 | |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 509 | drv->irq = platform_get_irq(pdev, 0); |
| 510 | if (drv->irq < 0) |
| 511 | return drv->irq; |
| 512 | |
Stephen Boyd | e24edf5 | 2012-07-12 17:46:19 -0700 | [diff] [blame] | 513 | desc = &drv->pil_desc; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 514 | desc->name = "gss"; |
| 515 | desc->dev = &pdev->dev; |
Stephen Boyd | 6d67d25 | 2011-09-27 11:50:05 -0700 | [diff] [blame] | 516 | desc->owner = THIS_MODULE; |
Stephen Boyd | ab2b907 | 2012-03-22 10:59:22 -0700 | [diff] [blame] | 517 | desc->proxy_timeout = 10000; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 518 | |
Matt Wagantall | 11afeee | 2012-02-07 18:38:59 -0800 | [diff] [blame] | 519 | if (pas_supported(PAS_GSS) > 0) { |
| 520 | desc->ops = &pil_gss_ops_trusted; |
| 521 | dev_info(&pdev->dev, "using secure boot\n"); |
| 522 | } else { |
| 523 | desc->ops = &pil_gss_ops; |
| 524 | dev_info(&pdev->dev, "using non-secure boot\n"); |
| 525 | } |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 526 | ret = pil_desc_init(desc); |
| 527 | if (ret) |
| 528 | return ret; |
| 529 | |
Stephen Boyd | 95a1c54 | 2012-06-21 12:45:11 -0700 | [diff] [blame] | 530 | /* Force into low power mode because hardware doesn't do this */ |
| 531 | desc->ops->shutdown(desc); |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 532 | |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 533 | ret = smsm_state_cb_register(SMSM_MODEM_STATE, SMSM_RESET, |
| 534 | smsm_state_cb, drv); |
| 535 | if (ret < 0) |
| 536 | dev_warn(&pdev->dev, "Unable to register SMSM callback\n"); |
| 537 | |
| 538 | drv->subsys_desc.name = "gss"; |
Stephen Boyd | 4684add | 2012-06-27 12:57:18 -0700 | [diff] [blame] | 539 | drv->subsys_desc.dev = &pdev->dev; |
| 540 | drv->subsys_desc.owner = THIS_MODULE; |
| 541 | drv->subsys_desc.start = gss_start; |
| 542 | drv->subsys_desc.stop = gss_stop; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 543 | drv->subsys_desc.shutdown = gss_shutdown; |
| 544 | drv->subsys_desc.powerup = gss_powerup; |
| 545 | drv->subsys_desc.ramdump = gss_ramdump; |
| 546 | drv->subsys_desc.crash_shutdown = gss_crash_shutdown; |
| 547 | |
| 548 | drv->subsys = subsys_register(&drv->subsys_desc); |
| 549 | if (IS_ERR(drv->subsys)) { |
| 550 | ret = PTR_ERR(drv->subsys); |
| 551 | goto err_subsys; |
| 552 | } |
| 553 | |
| 554 | drv->misc_dev.minor = MISC_DYNAMIC_MINOR; |
| 555 | drv->misc_dev.name = "gss"; |
| 556 | drv->misc_dev.fops = &gss_file_ops; |
| 557 | ret = misc_register(&drv->misc_dev); |
| 558 | if (ret) |
| 559 | goto err_misc; |
| 560 | |
Stephen Boyd | c1a7261 | 2012-07-05 14:07:35 -0700 | [diff] [blame] | 561 | drv->ramdump_dev = create_ramdump_device("gss", &pdev->dev); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 562 | if (!drv->ramdump_dev) { |
| 563 | ret = -ENOMEM; |
| 564 | goto err_ramdump; |
| 565 | } |
| 566 | |
Stephen Boyd | c1a7261 | 2012-07-05 14:07:35 -0700 | [diff] [blame] | 567 | drv->smem_ramdump_dev = create_ramdump_device("smem-gss", &pdev->dev); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 568 | if (!drv->smem_ramdump_dev) { |
| 569 | ret = -ENOMEM; |
| 570 | goto err_smem; |
| 571 | } |
| 572 | |
| 573 | ret = devm_request_irq(&pdev->dev, drv->irq, gss_wdog_bite_irq, |
| 574 | IRQF_TRIGGER_RISING, "gss_a5_wdog", drv); |
| 575 | if (ret < 0) |
| 576 | goto err; |
Stephen Boyd | 6d67d25 | 2011-09-27 11:50:05 -0700 | [diff] [blame] | 577 | return 0; |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 578 | err: |
| 579 | destroy_ramdump_device(drv->smem_ramdump_dev); |
| 580 | err_smem: |
| 581 | destroy_ramdump_device(drv->ramdump_dev); |
| 582 | err_ramdump: |
| 583 | misc_deregister(&drv->misc_dev); |
| 584 | err_misc: |
| 585 | subsys_unregister(drv->subsys); |
| 586 | err_subsys: |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 587 | pil_desc_release(desc); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 588 | return ret; |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 589 | } |
| 590 | |
| 591 | static int __devexit pil_gss_remove(struct platform_device *pdev) |
| 592 | { |
| 593 | struct gss_data *drv = platform_get_drvdata(pdev); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 594 | |
| 595 | destroy_ramdump_device(drv->smem_ramdump_dev); |
| 596 | destroy_ramdump_device(drv->ramdump_dev); |
| 597 | misc_deregister(&drv->misc_dev); |
| 598 | subsys_unregister(drv->subsys); |
Stephen Boyd | e83a0a2 | 2012-06-29 13:51:27 -0700 | [diff] [blame] | 599 | pil_desc_release(&drv->pil_desc); |
Stephen Boyd | d86214b | 2012-05-10 15:26:35 -0700 | [diff] [blame] | 600 | |
Matt Wagantall | 292aace | 2012-01-26 19:12:34 -0800 | [diff] [blame] | 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | static struct platform_driver pil_gss_driver = { |
| 605 | .probe = pil_gss_probe, |
| 606 | .remove = __devexit_p(pil_gss_remove), |
| 607 | .driver = { |
| 608 | .name = "pil_gss", |
| 609 | .owner = THIS_MODULE, |
| 610 | }, |
| 611 | }; |
| 612 | |
| 613 | static int __init pil_gss_init(void) |
| 614 | { |
| 615 | return platform_driver_register(&pil_gss_driver); |
| 616 | } |
| 617 | module_init(pil_gss_init); |
| 618 | |
| 619 | static void __exit pil_gss_exit(void) |
| 620 | { |
| 621 | platform_driver_unregister(&pil_gss_driver); |
| 622 | } |
| 623 | module_exit(pil_gss_exit); |
| 624 | |
| 625 | MODULE_DESCRIPTION("Support for booting the GSS processor"); |
| 626 | MODULE_LICENSE("GPL v2"); |