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gerrit-public.fairphone.software / kernel / msm / f9d979ce10c98dfd6d8d2a26217c3c4885ef97f6 / . / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blob: cfd95b4e3004705da33d9e27c4ac9b1d899a034a [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]2 * Copyright (c) 2000-2011 LSI Corporation.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]9 * mpi2_cnfg.h Version: 02.00.19
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
116 * in the array.
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
125 * define.
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
Kashyap, Desai9af05d92011-01-04 11:35:41 +0530[diff] [blame]128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
129 * defines.
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
132 * the Pinout field.
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
138 * Added IO Unit Page 8, IO Unit Page 9,
139 * and IO Unit Page 10.
140 * Added SASNotifyPrimitiveMasks field to
141 * MPI2_CONFIG_PAGE_IOC_7.
142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]143 * --------------------------------------------------------------------------
144 */
145
146#ifndef MPI2_CNFG_H
147#define MPI2_CNFG_H
148
149/*****************************************************************************
150* Configuration Page Header and defines
151*****************************************************************************/
152
153/* Config Page Header */
154typedef struct _MPI2_CONFIG_PAGE_HEADER
155{
156 U8 PageVersion; /* 0x00 */
157 U8 PageLength; /* 0x01 */
158 U8 PageNumber; /* 0x02 */
159 U8 PageType; /* 0x03 */
160} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
161 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
162
163typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
164{
165 MPI2_CONFIG_PAGE_HEADER Struct;
166 U8 Bytes[4];
167 U16 Word16[2];
168 U32 Word32;
169} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
170 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
171
172/* Extended Config Page Header */
173typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
174{
175 U8 PageVersion; /* 0x00 */
176 U8 Reserved1; /* 0x01 */
177 U8 PageNumber; /* 0x02 */
178 U8 PageType; /* 0x03 */
179 U16 ExtPageLength; /* 0x04 */
180 U8 ExtPageType; /* 0x06 */
181 U8 Reserved2; /* 0x07 */
182} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
183 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
184 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
185
186typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
187{
188 MPI2_CONFIG_PAGE_HEADER Struct;
189 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
190 U8 Bytes[8];
191 U16 Word16[4];
192 U32 Word32[2];
193} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
194 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
195
196
197/* PageType field values */
198#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
199#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
200#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
201#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
202
203#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
204#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
205#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
206#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
207#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
208#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
209#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
210#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
211
212#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
213
214
215/* ExtPageType field values */
216#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
217#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
218#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
219#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
220#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
221#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
222#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
223#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
224#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]225#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]226#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]227
228
229/*****************************************************************************
230* PageAddress defines
231*****************************************************************************/
232
233/* RAID Volume PageAddress format */
234#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
235#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
236#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
237
238#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
239
240
241/* RAID Physical Disk PageAddress format */
242#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
243#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
244#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
245#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
246
247#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
248#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
249
250
251/* SAS Expander PageAddress format */
252#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
253#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
254#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
255#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
256
257#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
258#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
259#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
260
261
262/* SAS Device PageAddress format */
263#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
264#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
265#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
266
267#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
268
269
270/* SAS PHY PageAddress format */
271#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
272#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
273#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
274
275#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
276#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
277
278
279/* SAS Port PageAddress format */
280#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
281#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
282#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
283
284#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
285
286
287/* SAS Enclosure PageAddress format */
288#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
289#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
290#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
291
292#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
293
294
295/* RAID Configuration PageAddress format */
296#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
297#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
298#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
299#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
300
301#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
302
303
304/* Driver Persistent Mapping PageAddress format */
305#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
306#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
307
308#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
309#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
310#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
311
312
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]313/* Ethernet PageAddress format */
314#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
315#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
316
317#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
318
319
320
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]321/****************************************************************************
322* Configuration messages
323****************************************************************************/
324
325/* Configuration Request Message */
326typedef struct _MPI2_CONFIG_REQUEST
327{
328 U8 Action; /* 0x00 */
329 U8 SGLFlags; /* 0x01 */
330 U8 ChainOffset; /* 0x02 */
331 U8 Function; /* 0x03 */
332 U16 ExtPageLength; /* 0x04 */
333 U8 ExtPageType; /* 0x06 */
334 U8 MsgFlags; /* 0x07 */
335 U8 VP_ID; /* 0x08 */
336 U8 VF_ID; /* 0x09 */
337 U16 Reserved1; /* 0x0A */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]338 U8 Reserved2; /* 0x0C */
339 U8 ProxyVF_ID; /* 0x0D */
340 U16 Reserved4; /* 0x0E */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]341 U32 Reserved3; /* 0x10 */
342 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
343 U32 PageAddress; /* 0x18 */
344 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
345} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
346 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
347
348/* values for the Action field */
349#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
350#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
351#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
352#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
353#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
354#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
355#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
356#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
357
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]358/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]359
360
361/* Config Reply Message */
362typedef struct _MPI2_CONFIG_REPLY
363{
364 U8 Action; /* 0x00 */
365 U8 SGLFlags; /* 0x01 */
366 U8 MsgLength; /* 0x02 */
367 U8 Function; /* 0x03 */
368 U16 ExtPageLength; /* 0x04 */
369 U8 ExtPageType; /* 0x06 */
370 U8 MsgFlags; /* 0x07 */
371 U8 VP_ID; /* 0x08 */
372 U8 VF_ID; /* 0x09 */
373 U16 Reserved1; /* 0x0A */
374 U16 Reserved2; /* 0x0C */
375 U16 IOCStatus; /* 0x0E */
376 U32 IOCLogInfo; /* 0x10 */
377 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
378} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
379 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
380
381
382
383/*****************************************************************************
384*
385* C o n f i g u r a t i o n P a g e s
386*
387*****************************************************************************/
388
389/****************************************************************************
390* Manufacturing Config pages
391****************************************************************************/
392
393#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
394
395/* SAS */
396#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
397#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
398#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
399#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
400#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
401#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
402#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]403
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]404#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
405
Kashyap, Desaidb271362009-09-23 17:24:27 +0530[diff] [blame]406#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
407#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
408#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
409#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
410#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
411#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]412#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
413#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
414#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]415
416
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]417
418
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]419/* Manufacturing Page 0 */
420
421typedef struct _MPI2_CONFIG_PAGE_MAN_0
422{
423 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
424 U8 ChipName[16]; /* 0x04 */
425 U8 ChipRevision[8]; /* 0x14 */
426 U8 BoardName[16]; /* 0x1C */
427 U8 BoardAssembly[16]; /* 0x2C */
428 U8 BoardTracerNumber[16]; /* 0x3C */
429} MPI2_CONFIG_PAGE_MAN_0,
430 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
431 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
432
433#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
434
435
436/* Manufacturing Page 1 */
437
438typedef struct _MPI2_CONFIG_PAGE_MAN_1
439{
440 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
441 U8 VPD[256]; /* 0x04 */
442} MPI2_CONFIG_PAGE_MAN_1,
443 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
444 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
445
446#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
447
448
449typedef struct _MPI2_CHIP_REVISION_ID
450{
451 U16 DeviceID; /* 0x00 */
452 U8 PCIRevisionID; /* 0x02 */
453 U8 Reserved; /* 0x03 */
454} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
455 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
456
457
458/* Manufacturing Page 2 */
459
460/*
461 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
462 * one and check Header.PageLength at runtime.
463 */
464#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
465#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
466#endif
467
468typedef struct _MPI2_CONFIG_PAGE_MAN_2
469{
470 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
471 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
472 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
473} MPI2_CONFIG_PAGE_MAN_2,
474 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
475 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
476
477#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
478
479
480/* Manufacturing Page 3 */
481
482/*
483 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
484 * one and check Header.PageLength at runtime.
485 */
486#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
487#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
488#endif
489
490typedef struct _MPI2_CONFIG_PAGE_MAN_3
491{
492 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
493 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
494 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
495} MPI2_CONFIG_PAGE_MAN_3,
496 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
497 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
498
499#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
500
501
502/* Manufacturing Page 4 */
503
504typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
505{
506 U8 PowerSaveFlags; /* 0x00 */
507 U8 InternalOperationsSleepTime; /* 0x01 */
508 U8 InternalOperationsRunTime; /* 0x02 */
509 U8 HostIdleTime; /* 0x03 */
510} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
511 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
512 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
513
514/* defines for the PowerSaveFlags field */
515#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
516#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
517#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
518#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
519
520typedef struct _MPI2_CONFIG_PAGE_MAN_4
521{
522 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
523 U32 Reserved1; /* 0x04 */
524 U32 Flags; /* 0x08 */
525 U8 InquirySize; /* 0x0C */
526 U8 Reserved2; /* 0x0D */
527 U16 Reserved3; /* 0x0E */
528 U8 InquiryData[56]; /* 0x10 */
529 U32 RAID0VolumeSettings; /* 0x48 */
530 U32 RAID1EVolumeSettings; /* 0x4C */
531 U32 RAID1VolumeSettings; /* 0x50 */
532 U32 RAID10VolumeSettings; /* 0x54 */
533 U32 Reserved4; /* 0x58 */
534 U32 Reserved5; /* 0x5C */
535 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
536 U8 MaxOCEDisks; /* 0x64 */
537 U8 ResyncRate; /* 0x65 */
538 U16 DataScrubDuration; /* 0x66 */
539 U8 MaxHotSpares; /* 0x68 */
540 U8 MaxPhysDisksPerVol; /* 0x69 */
541 U8 MaxPhysDisks; /* 0x6A */
542 U8 MaxVolumes; /* 0x6B */
543} MPI2_CONFIG_PAGE_MAN_4,
544 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
545 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
546
547#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
548
549/* Manufacturing Page 4 Flags field */
550#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
551#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
552
553#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
554#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
555#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
556
557#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
558#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
559#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
560#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
561#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
562
563#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
564#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
565#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
566#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
567
568#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
569#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
570#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
571#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
572#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
573#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
574#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
575#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
576
577
578/* Manufacturing Page 5 */
579
580/*
581 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]582 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]583 */
584#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
585#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
586#endif
587
588typedef struct _MPI2_MANUFACTURING5_ENTRY
589{
590 U64 WWID; /* 0x00 */
591 U64 DeviceName; /* 0x08 */
592} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
593 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
594
595typedef struct _MPI2_CONFIG_PAGE_MAN_5
596{
597 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
598 U8 NumPhys; /* 0x04 */
599 U8 Reserved1; /* 0x05 */
600 U16 Reserved2; /* 0x06 */
601 U32 Reserved3; /* 0x08 */
602 U32 Reserved4; /* 0x0C */
603 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
604} MPI2_CONFIG_PAGE_MAN_5,
605 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
606 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
607
608#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
609
610
611/* Manufacturing Page 6 */
612
613typedef struct _MPI2_CONFIG_PAGE_MAN_6
614{
615 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
616 U32 ProductSpecificInfo;/* 0x04 */
617} MPI2_CONFIG_PAGE_MAN_6,
618 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
619 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
620
621#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
622
623
624/* Manufacturing Page 7 */
625
626typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
627{
628 U32 Pinout; /* 0x00 */
629 U8 Connector[16]; /* 0x04 */
630 U8 Location; /* 0x14 */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]631 U8 ReceptacleID; /* 0x15 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]632 U16 Slot; /* 0x16 */
633 U32 Reserved2; /* 0x18 */
634} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
635 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
636
637/* defines for the Pinout field */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]638#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
639#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
640
641#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
642#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
643#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
644#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
645#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
646#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
647#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
648#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
649#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
650#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
651#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
652#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
653#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
654#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
655#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]656
657/* defines for the Location field */
658#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
659#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
660#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
661#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
662#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
663#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
664#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
665
666/*
667 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]668 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]669 */
670#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
671#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
672#endif
673
674typedef struct _MPI2_CONFIG_PAGE_MAN_7
675{
676 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
677 U32 Reserved1; /* 0x04 */
678 U32 Reserved2; /* 0x08 */
679 U32 Flags; /* 0x0C */
680 U8 EnclosureName[16]; /* 0x10 */
681 U8 NumPhys; /* 0x20 */
682 U8 Reserved3; /* 0x21 */
683 U16 Reserved4; /* 0x22 */
684 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
685} MPI2_CONFIG_PAGE_MAN_7,
686 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
687 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
688
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]689#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]690
691/* defines for the Flags field */
692#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
693
694
695/*
696 * Generic structure to use for product-specific manufacturing pages
697 * (currently Manufacturing Page 8 through Manufacturing Page 31).
698 */
699
700typedef struct _MPI2_CONFIG_PAGE_MAN_PS
701{
702 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
703 U32 ProductSpecificInfo;/* 0x04 */
704} MPI2_CONFIG_PAGE_MAN_PS,
705 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
706 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
707
708#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
709#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
710#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
711#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
712#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
713#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
714#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
715#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
716#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
717#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
718#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
719#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
720#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
721#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
722#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
723#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
724#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
725#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
726#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
727#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
728#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
729#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
730#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
731#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
732
733
734/****************************************************************************
735* IO Unit Config Pages
736****************************************************************************/
737
738/* IO Unit Page 0 */
739
740typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
741{
742 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
743 U64 UniqueValue; /* 0x04 */
744 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
745 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
746} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
747 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
748
749#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
750
751
752/* IO Unit Page 1 */
753
754typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
755{
756 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
757 U32 Flags; /* 0x04 */
758} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
759 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
760
761#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
762
763/* IO Unit Page 1 Flags defines */
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]764#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]765#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]766#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]767#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
768#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
769#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
770#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
771#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
772#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
773#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]774
775
776/* IO Unit Page 3 */
777
778/*
779 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]780 * one and check the value returned for GPIOCount at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]781 */
782#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
783#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
784#endif
785
786typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
787{
788 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
789 U8 GPIOCount; /* 0x04 */
790 U8 Reserved1; /* 0x05 */
791 U16 Reserved2; /* 0x06 */
792 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
793} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
794 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
795
796#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
797
798/* defines for IO Unit Page 3 GPIOVal field */
799#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
800#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
801#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
802#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
803
804
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]805/* IO Unit Page 5 */
806
807/*
808 * Upper layer code (drivers, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]809 * one and check the value returned for NumDmaEngines at runtime.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]810 */
811#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
812#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
813#endif
814
815typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
816 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
817 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
818 U64 RaidAcceleratorBufferSize; /* 0x0C */
819 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
820 U8 RAControlSize; /* 0x1C */
821 U8 NumDmaEngines; /* 0x1D */
822 U8 RAMinControlSize; /* 0x1E */
823 U8 RAMaxControlSize; /* 0x1F */
824 U32 Reserved1; /* 0x20 */
825 U32 Reserved2; /* 0x24 */
826 U32 Reserved3; /* 0x28 */
827 U32 DmaEngineCapabilities
828 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
829} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
830 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
831
832#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
833
834/* defines for IO Unit Page 5 DmaEngineCapabilities field */
835#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
836#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
837
838#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
839#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
840#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
841#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
842
843
844/* IO Unit Page 6 */
845
846typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
847 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
848 U16 Flags; /* 0x04 */
849 U8 RAHostControlSize; /* 0x06 */
850 U8 Reserved0; /* 0x07 */
851 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
852 U32 Reserved1; /* 0x10 */
853 U32 Reserved2; /* 0x14 */
854 U32 Reserved3; /* 0x18 */
855} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
856 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
857
858#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
859
860/* defines for IO Unit Page 6 Flags field */
861#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
862
863
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]864/* IO Unit Page 7 */
865
866typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
867 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
868 U16 Reserved1; /* 0x04 */
869 U8 PCIeWidth; /* 0x06 */
870 U8 PCIeSpeed; /* 0x07 */
871 U32 ProcessorState; /* 0x08 */
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]872 U32 PowerManagementCapabilities; /* 0x0C */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]873 U16 IOCTemperature; /* 0x10 */
874 U8 IOCTemperatureUnits; /* 0x12 */
875 U8 IOCSpeed; /* 0x13 */
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]876 U16 BoardTemperature; /* 0x14 */
877 U8 BoardTemperatureUnits; /* 0x16 */
878 U8 Reserved3; /* 0x17 */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]879} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
880 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
881
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]882#define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]883
884/* defines for IO Unit Page 7 PCIeWidth field */
885#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
886#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
887#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
888#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
889
890/* defines for IO Unit Page 7 PCIeSpeed field */
891#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
892#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
893#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
894
895/* defines for IO Unit Page 7 ProcessorState field */
896#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
897#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
898
899#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
900#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
901#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
902
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]903/* defines for IO Unit Page 7 PowerManagementCapabilities field */
904#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
905#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
906#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
907#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008)
908#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004)
909
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]910/* defines for IO Unit Page 7 IOCTemperatureUnits field */
911#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
912#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
913#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
914
915/* defines for IO Unit Page 7 IOCSpeed field */
916#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
917#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
918#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
919#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
920
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]921/* defines for IO Unit Page 7 BoardTemperatureUnits field */
922#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
923#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
924#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
925
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]926/* IO Unit Page 8 */
927
928#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
929
930typedef struct _MPI2_IOUNIT8_SENSOR {
931 U16 Flags; /* 0x00 */
932 U16 Reserved1; /* 0x02 */
933 U16
934 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
935 U32 Reserved2; /* 0x0C */
936 U32 Reserved3; /* 0x10 */
937 U32 Reserved4; /* 0x14 */
938} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
939Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
940
941/* defines for IO Unit Page 8 Sensor Flags field */
942#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
943#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
944#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
945#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
946
947/*
948 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
949 * one and check the value returned for NumSensors at runtime.
950 */
951#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
952#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
953#endif
954
955typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
956 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
957 U32 Reserved1; /* 0x04 */
958 U32 Reserved2; /* 0x08 */
959 U8 NumSensors; /* 0x0C */
960 U8 PollingInterval; /* 0x0D */
961 U16 Reserved3; /* 0x0E */
962 MPI2_IOUNIT8_SENSOR
963 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
964} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
965Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
966
967#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
968
969
970/* IO Unit Page 9 */
971
972typedef struct _MPI2_IOUNIT9_SENSOR {
973 U16 CurrentTemperature; /* 0x00 */
974 U16 Reserved1; /* 0x02 */
975 U8 Flags; /* 0x04 */
976 U8 Reserved2; /* 0x05 */
977 U16 Reserved3; /* 0x06 */
978 U32 Reserved4; /* 0x08 */
979 U32 Reserved5; /* 0x0C */
980} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
981Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
982
983/* defines for IO Unit Page 9 Sensor Flags field */
984#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
985
986/*
987 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
988 * one and check the value returned for NumSensors at runtime.
989 */
990#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
991#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
992#endif
993
994typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
995 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
996 U32 Reserved1; /* 0x04 */
997 U32 Reserved2; /* 0x08 */
998 U8 NumSensors; /* 0x0C */
999 U8 Reserved4; /* 0x0D */
1000 U16 Reserved3; /* 0x0E */
1001 MPI2_IOUNIT9_SENSOR
1002 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1003} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1004Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1005
1006#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1007
1008
1009/* IO Unit Page 10 */
1010
1011typedef struct _MPI2_IOUNIT10_FUNCTION {
1012 U8 CreditPercent; /* 0x00 */
1013 U8 Reserved1; /* 0x01 */
1014 U16 Reserved2; /* 0x02 */
1015} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1016Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1017
1018/*
1019 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1020 * one and check the value returned for NumFunctions at runtime.
1021 */
1022#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1023#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1024#endif
1025
1026typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1027 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1028 U8 NumFunctions; /* 0x04 */
1029 U8 Reserved1; /* 0x05 */
1030 U16 Reserved2; /* 0x06 */
1031 U32 Reserved3; /* 0x08 */
1032 U32 Reserved4; /* 0x0C */
1033 MPI2_IOUNIT10_FUNCTION
1034 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1035} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1036Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1037
1038#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1039
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1040
1041
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1042/****************************************************************************
1043* IOC Config Pages
1044****************************************************************************/
1045
1046/* IOC Page 0 */
1047
1048typedef struct _MPI2_CONFIG_PAGE_IOC_0
1049{
1050 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1051 U32 Reserved1; /* 0x04 */
1052 U32 Reserved2; /* 0x08 */
1053 U16 VendorID; /* 0x0C */
1054 U16 DeviceID; /* 0x0E */
1055 U8 RevisionID; /* 0x10 */
1056 U8 Reserved3; /* 0x11 */
1057 U16 Reserved4; /* 0x12 */
1058 U32 ClassCode; /* 0x14 */
1059 U16 SubsystemVendorID; /* 0x18 */
1060 U16 SubsystemID; /* 0x1A */
1061} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1062 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1063
1064#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1065
1066
1067/* IOC Page 1 */
1068
1069typedef struct _MPI2_CONFIG_PAGE_IOC_1
1070{
1071 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1072 U32 Flags; /* 0x04 */
1073 U32 CoalescingTimeout; /* 0x08 */
1074 U8 CoalescingDepth; /* 0x0C */
1075 U8 PCISlotNum; /* 0x0D */
1076 U8 PCIBusNum; /* 0x0E */
1077 U8 PCIDomainSegment; /* 0x0F */
1078 U32 Reserved1; /* 0x10 */
1079 U32 Reserved2; /* 0x14 */
1080} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1081 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1082
1083#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1084
1085/* defines for IOC Page 1 Flags field */
1086#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1087
1088#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1089#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1090#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1091
1092/* IOC Page 6 */
1093
1094typedef struct _MPI2_CONFIG_PAGE_IOC_6
1095{
1096 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1097 U32 CapabilitiesFlags; /* 0x04 */
1098 U8 MaxDrivesRAID0; /* 0x08 */
1099 U8 MaxDrivesRAID1; /* 0x09 */
1100 U8 MaxDrivesRAID1E; /* 0x0A */
1101 U8 MaxDrivesRAID10; /* 0x0B */
1102 U8 MinDrivesRAID0; /* 0x0C */
1103 U8 MinDrivesRAID1; /* 0x0D */
1104 U8 MinDrivesRAID1E; /* 0x0E */
1105 U8 MinDrivesRAID10; /* 0x0F */
1106 U32 Reserved1; /* 0x10 */
1107 U8 MaxGlobalHotSpares; /* 0x14 */
1108 U8 MaxPhysDisks; /* 0x15 */
1109 U8 MaxVolumes; /* 0x16 */
1110 U8 MaxConfigs; /* 0x17 */
1111 U8 MaxOCEDisks; /* 0x18 */
1112 U8 Reserved2; /* 0x19 */
1113 U16 Reserved3; /* 0x1A */
1114 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1115 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1116 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1117 U32 Reserved4; /* 0x28 */
1118 U32 Reserved5; /* 0x2C */
1119 U16 DefaultMetadataSize; /* 0x30 */
1120 U16 Reserved6; /* 0x32 */
1121 U16 MaxBadBlockTableEntries; /* 0x34 */
1122 U16 Reserved7; /* 0x36 */
1123 U32 IRNvsramVersion; /* 0x38 */
1124} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1125 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1126
1127#define MPI2_IOCPAGE6_PAGEVERSION (0x04)
1128
1129/* defines for IOC Page 6 CapabilitiesFlags */
1130#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1131#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1132#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1133#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1134#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1135
1136
1137/* IOC Page 7 */
1138
1139#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1140
1141typedef struct _MPI2_CONFIG_PAGE_IOC_7
1142{
1143 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1144 U32 Reserved1; /* 0x04 */
1145 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1146 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]1147 U16 SASNotifyPrimitiveMasks; /* 0x1A */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1148 U32 Reserved3; /* 0x1C */
1149} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1150 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1151
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]1152#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1153
1154
1155/* IOC Page 8 */
1156
1157typedef struct _MPI2_CONFIG_PAGE_IOC_8
1158{
1159 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1160 U8 NumDevsPerEnclosure; /* 0x04 */
1161 U8 Reserved1; /* 0x05 */
1162 U16 Reserved2; /* 0x06 */
1163 U16 MaxPersistentEntries; /* 0x08 */
1164 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1165 U16 Flags; /* 0x0C */
1166 U16 Reserved3; /* 0x0E */
1167 U16 IRVolumeMappingFlags; /* 0x10 */
1168 U16 Reserved4; /* 0x12 */
1169 U32 Reserved5; /* 0x14 */
1170} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1171 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1172
1173#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1174
1175/* defines for IOC Page 8 Flags field */
1176#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1177#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1178
1179#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1180#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1181#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1182
1183#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1184#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1185
1186/* defines for IOC Page 8 IRVolumeMappingFlags */
1187#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1188#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1189#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1190
1191
1192/****************************************************************************
1193* BIOS Config Pages
1194****************************************************************************/
1195
1196/* BIOS Page 1 */
1197
1198typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1199{
1200 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1201 U32 BiosOptions; /* 0x04 */
1202 U32 IOCSettings; /* 0x08 */
1203 U32 Reserved1; /* 0x0C */
1204 U32 DeviceSettings; /* 0x10 */
1205 U16 NumberOfDevices; /* 0x14 */
1206 U16 Reserved2; /* 0x16 */
1207 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1208 U16 IOTimeoutSequential; /* 0x1A */
1209 U16 IOTimeoutOther; /* 0x1C */
1210 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1211} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1212 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1213
1214#define MPI2_BIOSPAGE1_PAGEVERSION (0x04)
1215
1216/* values for BIOS Page 1 BiosOptions field */
1217#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1218
1219/* values for BIOS Page 1 IOCSettings field */
1220#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1221#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1222#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1223
1224#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1225#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1226#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1227#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1228
1229#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1230#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1231#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1232#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1233#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1234
1235#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1236
1237/* values for BIOS Page 1 DeviceSettings field */
1238#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1239#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1240#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1241#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1242#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1243
1244
1245/* BIOS Page 2 */
1246
1247typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1248{
1249 U32 Reserved1; /* 0x00 */
1250 U32 Reserved2; /* 0x04 */
1251 U32 Reserved3; /* 0x08 */
1252 U32 Reserved4; /* 0x0C */
1253 U32 Reserved5; /* 0x10 */
1254 U32 Reserved6; /* 0x14 */
1255} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1256 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1257 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1258
1259typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1260{
1261 U64 SASAddress; /* 0x00 */
1262 U8 LUN[8]; /* 0x08 */
1263 U32 Reserved1; /* 0x10 */
1264 U32 Reserved2; /* 0x14 */
1265} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1266 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1267
1268typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1269{
1270 U64 EnclosureLogicalID; /* 0x00 */
1271 U32 Reserved1; /* 0x08 */
1272 U32 Reserved2; /* 0x0C */
1273 U16 SlotNumber; /* 0x10 */
1274 U16 Reserved3; /* 0x12 */
1275 U32 Reserved4; /* 0x14 */
1276} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1277 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1278 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1279
1280typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1281{
1282 U64 DeviceName; /* 0x00 */
1283 U8 LUN[8]; /* 0x08 */
1284 U32 Reserved1; /* 0x10 */
1285 U32 Reserved2; /* 0x14 */
1286} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1287 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1288
1289typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1290{
1291 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1292 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1293 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1294 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1295} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1296 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1297
1298typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1299{
1300 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1301 U32 Reserved1; /* 0x04 */
1302 U32 Reserved2; /* 0x08 */
1303 U32 Reserved3; /* 0x0C */
1304 U32 Reserved4; /* 0x10 */
1305 U32 Reserved5; /* 0x14 */
1306 U32 Reserved6; /* 0x18 */
1307 U8 ReqBootDeviceForm; /* 0x1C */
1308 U8 Reserved7; /* 0x1D */
1309 U16 Reserved8; /* 0x1E */
1310 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1311 U8 ReqAltBootDeviceForm; /* 0x38 */
1312 U8 Reserved9; /* 0x39 */
1313 U16 Reserved10; /* 0x3A */
1314 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1315 U8 CurrentBootDeviceForm; /* 0x58 */
1316 U8 Reserved11; /* 0x59 */
1317 U16 Reserved12; /* 0x5A */
1318 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1319} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1320 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1321
1322#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1323
1324/* values for BIOS Page 2 BootDeviceForm fields */
1325#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1326#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1327#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1328#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1329#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1330
1331
1332/* BIOS Page 3 */
1333
1334typedef struct _MPI2_ADAPTER_INFO
1335{
1336 U8 PciBusNumber; /* 0x00 */
1337 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1338 U16 AdapterFlags; /* 0x02 */
1339} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1340 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1341
1342#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1343#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1344
1345typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1346{
1347 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1348 U32 GlobalFlags; /* 0x04 */
1349 U32 BiosVersion; /* 0x08 */
1350 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1351 U32 Reserved1; /* 0x1C */
1352} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1353 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1354
1355#define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1356
1357/* values for BIOS Page 3 GlobalFlags */
1358#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1359#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1360#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1361
1362#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1363#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1364#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1365#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1366
1367
1368/* BIOS Page 4 */
1369
1370/*
1371 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1372 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1373 */
1374#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1375#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1376#endif
1377
1378typedef struct _MPI2_BIOS4_ENTRY
1379{
1380 U64 ReassignmentWWID; /* 0x00 */
1381 U64 ReassignmentDeviceName; /* 0x08 */
1382} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1383 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1384
1385typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1386{
1387 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1388 U8 NumPhys; /* 0x04 */
1389 U8 Reserved1; /* 0x05 */
1390 U16 Reserved2; /* 0x06 */
1391 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1392} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1393 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1394
1395#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1396
1397
1398/****************************************************************************
1399* RAID Volume Config Pages
1400****************************************************************************/
1401
1402/* RAID Volume Page 0 */
1403
1404typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1405{
1406 U8 RAIDSetNum; /* 0x00 */
1407 U8 PhysDiskMap; /* 0x01 */
1408 U8 PhysDiskNum; /* 0x02 */
1409 U8 Reserved; /* 0x03 */
1410} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1411 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1412
1413/* defines for the PhysDiskMap field */
1414#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1415#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1416
1417typedef struct _MPI2_RAIDVOL0_SETTINGS
1418{
1419 U16 Settings; /* 0x00 */
1420 U8 HotSparePool; /* 0x01 */
1421 U8 Reserved; /* 0x02 */
1422} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1423 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1424
1425/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1426#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1427#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1428#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1429#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1430#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1431#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1432#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1433#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1434
1435/* RAID Volume Page 0 VolumeSettings defines */
1436#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1437#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1438
1439#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1440#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1441#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1442#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1443
1444/*
1445 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1446 * one and check the value returned for NumPhysDisks at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1447 */
1448#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1449#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1450#endif
1451
1452typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1453{
1454 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1455 U16 DevHandle; /* 0x04 */
1456 U8 VolumeState; /* 0x06 */
1457 U8 VolumeType; /* 0x07 */
1458 U32 VolumeStatusFlags; /* 0x08 */
1459 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1460 U64 MaxLBA; /* 0x10 */
1461 U32 StripeSize; /* 0x18 */
1462 U16 BlockSize; /* 0x1C */
1463 U16 Reserved1; /* 0x1E */
1464 U8 SupportedPhysDisks; /* 0x20 */
1465 U8 ResyncRate; /* 0x21 */
1466 U16 DataScrubDuration; /* 0x22 */
1467 U8 NumPhysDisks; /* 0x24 */
1468 U8 Reserved2; /* 0x25 */
1469 U8 Reserved3; /* 0x26 */
1470 U8 InactiveStatus; /* 0x27 */
1471 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1472} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1473 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1474
1475#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1476
1477/* values for RAID VolumeState */
1478#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1479#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1480#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1481#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1482#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1483#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1484
1485/* values for RAID VolumeType */
1486#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1487#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1488#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1489#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1490#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1491
1492/* values for RAID Volume Page 0 VolumeStatusFlags field */
1493#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1494#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1495#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1496#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1497#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1498#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1499#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1500#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1501#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1502#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1503#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1504#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1505#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1506#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1507#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1508#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1509#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1510#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1511#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1512
1513/* values for RAID Volume Page 0 SupportedPhysDisks field */
1514#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1515#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1516#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1517#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1518
1519/* values for RAID Volume Page 0 InactiveStatus field */
1520#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1521#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1522#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1523#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1524#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1525#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1526#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1527
1528
1529/* RAID Volume Page 1 */
1530
1531typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1532{
1533 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1534 U16 DevHandle; /* 0x04 */
1535 U16 Reserved0; /* 0x06 */
1536 U8 GUID[24]; /* 0x08 */
1537 U8 Name[16]; /* 0x20 */
1538 U64 WWID; /* 0x30 */
1539 U32 Reserved1; /* 0x38 */
1540 U32 Reserved2; /* 0x3C */
1541} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1542 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1543
1544#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1545
1546
1547/****************************************************************************
1548* RAID Physical Disk Config Pages
1549****************************************************************************/
1550
1551/* RAID Physical Disk Page 0 */
1552
1553typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1554{
1555 U16 Reserved1; /* 0x00 */
1556 U8 HotSparePool; /* 0x02 */
1557 U8 Reserved2; /* 0x03 */
1558} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1559 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1560
1561/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1562
1563typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1564{
1565 U8 VendorID[8]; /* 0x00 */
1566 U8 ProductID[16]; /* 0x08 */
1567 U8 ProductRevLevel[4]; /* 0x18 */
1568 U8 SerialNum[32]; /* 0x1C */
1569} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1570 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1571 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1572
1573typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1574{
1575 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1576 U16 DevHandle; /* 0x04 */
1577 U8 Reserved1; /* 0x06 */
1578 U8 PhysDiskNum; /* 0x07 */
1579 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1580 U32 Reserved2; /* 0x0C */
1581 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1582 U32 Reserved3; /* 0x4C */
1583 U8 PhysDiskState; /* 0x50 */
1584 U8 OfflineReason; /* 0x51 */
1585 U8 IncompatibleReason; /* 0x52 */
1586 U8 PhysDiskAttributes; /* 0x53 */
1587 U32 PhysDiskStatusFlags; /* 0x54 */
1588 U64 DeviceMaxLBA; /* 0x58 */
1589 U64 HostMaxLBA; /* 0x60 */
1590 U64 CoercedMaxLBA; /* 0x68 */
1591 U16 BlockSize; /* 0x70 */
1592 U16 Reserved5; /* 0x72 */
1593 U32 Reserved6; /* 0x74 */
1594} MPI2_CONFIG_PAGE_RD_PDISK_0,
1595 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1596 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1597
1598#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1599
1600/* PhysDiskState defines */
1601#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1602#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1603#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1604#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1605#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1606#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1607#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1608#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1609
1610/* OfflineReason defines */
1611#define MPI2_PHYSDISK0_ONLINE (0x00)
1612#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1613#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1614#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1615#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1616#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1617#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1618
1619/* IncompatibleReason defines */
1620#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1621#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1622#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1623#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1624#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1625#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1626#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1627#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1628
1629/* PhysDiskAttributes defines */
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1630#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1631#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1632#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1633
1634#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1635#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1636#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1637
1638/* PhysDiskStatusFlags defines */
1639#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1640#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1641#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1642#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1643#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1644#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1645#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1646#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1647
1648
1649/* RAID Physical Disk Page 1 */
1650
1651/*
1652 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1653 * one and check the value returned for NumPhysDiskPaths at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1654 */
1655#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1656#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1657#endif
1658
1659typedef struct _MPI2_RAIDPHYSDISK1_PATH
1660{
1661 U16 DevHandle; /* 0x00 */
1662 U16 Reserved1; /* 0x02 */
1663 U64 WWID; /* 0x04 */
1664 U64 OwnerWWID; /* 0x0C */
1665 U8 OwnerIdentifier; /* 0x14 */
1666 U8 Reserved2; /* 0x15 */
1667 U16 Flags; /* 0x16 */
1668} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1669 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1670
1671/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1672#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1673#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1674#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1675
1676typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1677{
1678 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1679 U8 NumPhysDiskPaths; /* 0x04 */
1680 U8 PhysDiskNum; /* 0x05 */
1681 U16 Reserved1; /* 0x06 */
1682 U32 Reserved2; /* 0x08 */
1683 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1684} MPI2_CONFIG_PAGE_RD_PDISK_1,
1685 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1686 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1687
1688#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1689
1690
1691/****************************************************************************
1692* values for fields used by several types of SAS Config Pages
1693****************************************************************************/
1694
1695/* values for NegotiatedLinkRates fields */
1696#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1697#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1698#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1699/* link rates used for Negotiated Physical and Logical Link Rate */
1700#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1701#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1702#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1703#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1704#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1705#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1706#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1707#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1708#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1709#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1710
1711
1712/* values for AttachedPhyInfo fields */
1713#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1714#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1715#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1716
1717#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1718#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1719#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1720#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1721#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1722#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1723#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1724#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1725#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1726#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1727
1728
1729/* values for PhyInfo fields */
1730#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1731
1732#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]1733#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1734#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1735#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1736#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1737
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1738#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1739#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1740#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1741#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1742#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1743#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1744
1745#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1746#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1747#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1748#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1749#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1750#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1751#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1752#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1753#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1754#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1755
1756#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1757#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1758#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1759#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1760
1761#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1762#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1763
1764#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1765#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1766#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1767#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1768
1769
1770/* values for SAS ProgrammedLinkRate fields */
1771#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1772#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1773#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1774#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1775#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1776#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1777#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1778#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1779#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1780#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1781
1782
1783/* values for SAS HwLinkRate fields */
1784#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1785#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1786#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1787#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1788#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1789#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1790#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1791#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1792
1793
1794
1795/****************************************************************************
1796* SAS IO Unit Config Pages
1797****************************************************************************/
1798
1799/* SAS IO Unit Page 0 */
1800
1801typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1802{
1803 U8 Port; /* 0x00 */
1804 U8 PortFlags; /* 0x01 */
1805 U8 PhyFlags; /* 0x02 */
1806 U8 NegotiatedLinkRate; /* 0x03 */
1807 U32 ControllerPhyDeviceInfo;/* 0x04 */
1808 U16 AttachedDevHandle; /* 0x08 */
1809 U16 ControllerDevHandle; /* 0x0A */
1810 U32 DiscoveryStatus; /* 0x0C */
1811 U32 Reserved; /* 0x10 */
1812} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1813 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1814
1815/*
1816 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1817 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1818 */
1819#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1820#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1821#endif
1822
1823typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1824{
1825 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1826 U32 Reserved1; /* 0x08 */
1827 U8 NumPhys; /* 0x0C */
1828 U8 Reserved2; /* 0x0D */
1829 U16 Reserved3; /* 0x0E */
1830 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1831} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1832 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1833 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1834
1835#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1836
1837/* values for SAS IO Unit Page 0 PortFlags */
1838#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1839#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1840
1841/* values for SAS IO Unit Page 0 PhyFlags */
1842#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1843#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1844
1845/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1846
1847/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1848
1849/* values for SAS IO Unit Page 0 DiscoveryStatus */
1850#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1851#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1852#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1853#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1854#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1855#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1856#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1857#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1858#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1859#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1860#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1861#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1862#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1863#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1864#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1865#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1866#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1867#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1868#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1869#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1870
1871
1872/* SAS IO Unit Page 1 */
1873
1874typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1875{
1876 U8 Port; /* 0x00 */
1877 U8 PortFlags; /* 0x01 */
1878 U8 PhyFlags; /* 0x02 */
1879 U8 MaxMinLinkRate; /* 0x03 */
1880 U32 ControllerPhyDeviceInfo; /* 0x04 */
1881 U16 MaxTargetPortConnectTime; /* 0x08 */
1882 U16 Reserved1; /* 0x0A */
1883} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1884 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1885
1886/*
1887 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1888 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1889 */
1890#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1891#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1892#endif
1893
1894typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1895{
1896 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1897 U16 ControlFlags; /* 0x08 */
1898 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1899 U16 AdditionalControlFlags; /* 0x0C */
1900 U16 SASWideMaxQueueDepth; /* 0x0E */
1901 U8 NumPhys; /* 0x10 */
1902 U8 SATAMaxQDepth; /* 0x11 */
1903 U8 ReportDeviceMissingDelay; /* 0x12 */
1904 U8 IODeviceMissingDelay; /* 0x13 */
1905 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1906} MPI2_CONFIG_PAGE_SASIOUNIT_1,
1907 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1908 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1909
1910#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1911
1912/* values for SAS IO Unit Page 1 ControlFlags */
1913#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1914#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1915#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1916#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1917
1918#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1919#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1920#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1921#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1922#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1923
1924#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1925#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1926#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1927#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1928#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1929#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1930#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1931#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1932
1933/* values for SAS IO Unit Page 1 AdditionalControlFlags */
1934#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1935#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1936#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1937#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1938#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1939#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1940#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1941#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1942
1943/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1944#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1945#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1946
1947/* values for SAS IO Unit Page 1 PortFlags */
1948#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1949
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1950/* values for SAS IO Unit Page 1 PhyFlags */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1951#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1952#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1953
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1954/* values for SAS IO Unit Page 1 MaxMinLinkRate */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1955#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1956#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1957#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1958#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1959#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1960#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1961#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1962#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1963
1964/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1965
1966
1967/* SAS IO Unit Page 4 */
1968
1969typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1970{
1971 U8 MaxTargetSpinup; /* 0x00 */
1972 U8 SpinupDelay; /* 0x01 */
1973 U16 Reserved1; /* 0x02 */
1974} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1975 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1976
1977/*
1978 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]1979 * one and check the value returned for NumPhys at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1980 */
1981#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1982#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
1983#endif
1984
1985typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1986{
1987 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1988 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
1989 U32 Reserved1; /* 0x18 */
1990 U32 Reserved2; /* 0x1C */
1991 U32 Reserved3; /* 0x20 */
1992 U8 BootDeviceWaitTime; /* 0x24 */
1993 U8 Reserved4; /* 0x25 */
1994 U16 Reserved5; /* 0x26 */
1995 U8 NumPhys; /* 0x28 */
1996 U8 PEInitialSpinupDelay; /* 0x29 */
1997 U8 PEReplyDelay; /* 0x2A */
1998 U8 Flags; /* 0x2B */
1999 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2000} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2001 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2002 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2003
2004#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2005
2006/* defines for Flags field */
2007#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2008
2009/* defines for PHY field */
2010#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2011
2012
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2013/* SAS IO Unit Page 5 */
2014
2015typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2016 U8 ControlFlags; /* 0x00 */
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2017 U8 PortWidthModGroup; /* 0x01 */
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2018 U16 InactivityTimerExponent; /* 0x02 */
2019 U8 SATAPartialTimeout; /* 0x04 */
2020 U8 Reserved2; /* 0x05 */
2021 U8 SATASlumberTimeout; /* 0x06 */
2022 U8 Reserved3; /* 0x07 */
2023 U8 SASPartialTimeout; /* 0x08 */
2024 U8 Reserved4; /* 0x09 */
2025 U8 SASSlumberTimeout; /* 0x0A */
2026 U8 Reserved5; /* 0x0B */
2027} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2028 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2029 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2030
2031/* defines for ControlFlags field */
2032#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2033#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2034#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2035#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2036
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2037/* defines for PortWidthModeGroup field */
2038#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2039
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2040/* defines for InactivityTimerExponent field */
2041#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2042#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2043#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2044#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2045#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2046#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2047#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2048#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2049
2050#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2051#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2052#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2053#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2054#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2055#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2056#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2057#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2058
2059/*
2060 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2061 * one and check the value returned for NumPhys at runtime.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2062 */
2063#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2064#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2065#endif
2066
2067typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2068 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2069 U8 NumPhys; /* 0x08 */
2070 U8 Reserved1; /* 0x09 */
2071 U16 Reserved2; /* 0x0A */
2072 U32 Reserved3; /* 0x0C */
2073 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
2074 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2075} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2076 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2077 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2078
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2079#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2080
2081
2082/* SAS IO Unit Page 6 */
2083
2084typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2085 U8 CurrentStatus; /* 0x00 */
2086 U8 CurrentModulation; /* 0x01 */
2087 U8 CurrentUtilization; /* 0x02 */
2088 U8 Reserved1; /* 0x03 */
2089 U32 Reserved2; /* 0x04 */
2090} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2091 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2092 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2093 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2094
2095/* defines for CurrentStatus field */
2096#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2097#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2098#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2099#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2100#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2101#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2102#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2103#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2104
2105/* defines for CurrentModulation field */
2106#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2107#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2108#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2109#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2110
2111/*
2112 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2113 * one and check the value returned for NumGroups at runtime.
2114 */
2115#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2116#define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2117#endif
2118
2119typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2120 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2121 U32 Reserved1; /* 0x08 */
2122 U32 Reserved2; /* 0x0C */
2123 U8 NumGroups; /* 0x10 */
2124 U8 Reserved3; /* 0x11 */
2125 U16 Reserved4; /* 0x12 */
2126 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2127 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2128} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2129 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2130 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2131
2132#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2133
2134
2135/* SAS IO Unit Page 7 */
2136
2137typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2138 U8 Flags; /* 0x00 */
2139 U8 Reserved1; /* 0x01 */
2140 U16 Reserved2; /* 0x02 */
2141 U8 Threshold75Pct; /* 0x04 */
2142 U8 Threshold50Pct; /* 0x05 */
2143 U8 Threshold25Pct; /* 0x06 */
2144 U8 Reserved3; /* 0x07 */
2145} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2146 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2147 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2148 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2149
2150/* defines for Flags field */
2151#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2152
2153
2154/*
2155 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2156 * one and check the value returned for NumGroups at runtime.
2157 */
2158#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2159#define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2160#endif
2161
2162typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2163 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2164 U8 SamplingInterval; /* 0x08 */
2165 U8 WindowLength; /* 0x09 */
2166 U16 Reserved1; /* 0x0A */
2167 U32 Reserved2; /* 0x0C */
2168 U32 Reserved3; /* 0x10 */
2169 U8 NumGroups; /* 0x14 */
2170 U8 Reserved4; /* 0x15 */
2171 U16 Reserved5; /* 0x16 */
2172 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2173 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2174} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2175 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2176 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2177
2178#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2179
2180
2181/* SAS IO Unit Page 8 */
2182
2183typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2184 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2185 U32 Reserved1; /* 0x08 */
2186 U32 PowerManagementCapabilities;/* 0x0C */
2187 U32 Reserved2; /* 0x10 */
2188} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2189 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2190 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2191
2192#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2193
2194/* defines for PowerManagementCapabilities field */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]2195#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2196#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2197#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2198#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2199#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2200#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2201#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2202#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2203#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2204#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2205
2206
2207
2208
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2209/****************************************************************************
2210* SAS Expander Config Pages
2211****************************************************************************/
2212
2213/* SAS Expander Page 0 */
2214
2215typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2216{
2217 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2218 U8 PhysicalPort; /* 0x08 */
2219 U8 ReportGenLength; /* 0x09 */
2220 U16 EnclosureHandle; /* 0x0A */
2221 U64 SASAddress; /* 0x0C */
2222 U32 DiscoveryStatus; /* 0x14 */
2223 U16 DevHandle; /* 0x18 */
2224 U16 ParentDevHandle; /* 0x1A */
2225 U16 ExpanderChangeCount; /* 0x1C */
2226 U16 ExpanderRouteIndexes; /* 0x1E */
2227 U8 NumPhys; /* 0x20 */
2228 U8 SASLevel; /* 0x21 */
2229 U16 Flags; /* 0x22 */
2230 U16 STPBusInactivityTimeLimit; /* 0x24 */
2231 U16 STPMaxConnectTimeLimit; /* 0x26 */
2232 U16 STP_SMP_NexusLossTime; /* 0x28 */
2233 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2234 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2235 U16 ZoneLockInactivityLimit; /* 0x34 */
2236 U16 Reserved1; /* 0x36 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2237 U8 TimeToReducedFunc; /* 0x38 */
2238 U8 InitialTimeToReducedFunc; /* 0x39 */
2239 U8 MaxReducedFuncTime; /* 0x3A */
2240 U8 Reserved2; /* 0x3B */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2241} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2242 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2243
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2244#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2245
2246/* values for SAS Expander Page 0 DiscoveryStatus field */
2247#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2248#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2249#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2250#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2251#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2252#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2253#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2254#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2255#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2256#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2257#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2258#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2259#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2260#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2261#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2262#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2263#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2264#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2265#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2266#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2267
2268/* values for SAS Expander Page 0 Flags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2269#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2270#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2271#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2272#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2273#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2274#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2275#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2276#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2277#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2278#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2279#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2280
2281
2282/* SAS Expander Page 1 */
2283
2284typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2285{
2286 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2287 U8 PhysicalPort; /* 0x08 */
2288 U8 Reserved1; /* 0x09 */
2289 U16 Reserved2; /* 0x0A */
2290 U8 NumPhys; /* 0x0C */
2291 U8 Phy; /* 0x0D */
2292 U16 NumTableEntriesProgrammed; /* 0x0E */
2293 U8 ProgrammedLinkRate; /* 0x10 */
2294 U8 HwLinkRate; /* 0x11 */
2295 U16 AttachedDevHandle; /* 0x12 */
2296 U32 PhyInfo; /* 0x14 */
2297 U32 AttachedDeviceInfo; /* 0x18 */
2298 U16 ExpanderDevHandle; /* 0x1C */
2299 U8 ChangeCount; /* 0x1E */
2300 U8 NegotiatedLinkRate; /* 0x1F */
2301 U8 PhyIdentifier; /* 0x20 */
2302 U8 AttachedPhyIdentifier; /* 0x21 */
2303 U8 Reserved3; /* 0x22 */
2304 U8 DiscoveryInfo; /* 0x23 */
2305 U32 AttachedPhyInfo; /* 0x24 */
2306 U8 ZoneGroup; /* 0x28 */
2307 U8 SelfConfigStatus; /* 0x29 */
2308 U16 Reserved4; /* 0x2A */
2309} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2310 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2311
2312#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2313
2314/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2315
2316/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2317
2318/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2319
2320/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2321
2322/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2323
2324/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2325
2326/* values for SAS Expander Page 1 DiscoveryInfo field */
2327#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2328#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2329#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2330
2331
2332/****************************************************************************
2333* SAS Device Config Pages
2334****************************************************************************/
2335
2336/* SAS Device Page 0 */
2337
2338typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2339{
2340 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2341 U16 Slot; /* 0x08 */
2342 U16 EnclosureHandle; /* 0x0A */
2343 U64 SASAddress; /* 0x0C */
2344 U16 ParentDevHandle; /* 0x14 */
2345 U8 PhyNum; /* 0x16 */
2346 U8 AccessStatus; /* 0x17 */
2347 U16 DevHandle; /* 0x18 */
2348 U8 AttachedPhyIdentifier; /* 0x1A */
2349 U8 ZoneGroup; /* 0x1B */
2350 U32 DeviceInfo; /* 0x1C */
2351 U16 Flags; /* 0x20 */
2352 U8 PhysicalPort; /* 0x22 */
2353 U8 MaxPortConnections; /* 0x23 */
2354 U64 DeviceName; /* 0x24 */
2355 U8 PortGroups; /* 0x2C */
2356 U8 DmaGroup; /* 0x2D */
2357 U8 ControlGroup; /* 0x2E */
2358 U8 Reserved1; /* 0x2F */
2359 U32 Reserved2; /* 0x30 */
2360 U32 Reserved3; /* 0x34 */
2361} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2362 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2363
2364#define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2365
2366/* values for SAS Device Page 0 AccessStatus field */
2367#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2368#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2369#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2370#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2371#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2372#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2373#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2374#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2375/* specific values for SATA Init failures */
2376#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2377#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2378#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2379#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2380#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2381#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2382#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2383#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2384#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2385#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2386#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2387
2388/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2389
2390/* values for SAS Device Page 0 Flags field */
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame^]2391#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2392#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2393#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2394#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2395#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2396#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2397#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2398#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2399#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2400#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2401#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2402#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2403
2404
2405/* SAS Device Page 1 */
2406
2407typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2408{
2409 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2410 U32 Reserved1; /* 0x08 */
2411 U64 SASAddress; /* 0x0C */
2412 U32 Reserved2; /* 0x14 */
2413 U16 DevHandle; /* 0x18 */
2414 U16 Reserved3; /* 0x1A */
2415 U8 InitialRegDeviceFIS[20];/* 0x1C */
2416} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2417 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2418
2419#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2420
2421
2422/****************************************************************************
2423* SAS PHY Config Pages
2424****************************************************************************/
2425
2426/* SAS PHY Page 0 */
2427
2428typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2429{
2430 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2431 U16 OwnerDevHandle; /* 0x08 */
2432 U16 Reserved1; /* 0x0A */
2433 U16 AttachedDevHandle; /* 0x0C */
2434 U8 AttachedPhyIdentifier; /* 0x0E */
2435 U8 Reserved2; /* 0x0F */
2436 U32 AttachedPhyInfo; /* 0x10 */
2437 U8 ProgrammedLinkRate; /* 0x14 */
2438 U8 HwLinkRate; /* 0x15 */
2439 U8 ChangeCount; /* 0x16 */
2440 U8 Flags; /* 0x17 */
2441 U32 PhyInfo; /* 0x18 */
2442 U8 NegotiatedLinkRate; /* 0x1C */
2443 U8 Reserved3; /* 0x1D */
2444 U16 Reserved4; /* 0x1E */
2445} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2446 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2447
2448#define MPI2_SASPHY0_PAGEVERSION (0x03)
2449
2450/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2451
2452/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2453
2454/* values for SAS PHY Page 0 Flags field */
2455#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2456
2457/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2458
2459/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2460
2461/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2462
2463
2464/* SAS PHY Page 1 */
2465
2466typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2467{
2468 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2469 U32 Reserved1; /* 0x08 */
2470 U32 InvalidDwordCount; /* 0x0C */
2471 U32 RunningDisparityErrorCount; /* 0x10 */
2472 U32 LossDwordSynchCount; /* 0x14 */
2473 U32 PhyResetProblemCount; /* 0x18 */
2474} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2475 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2476
2477#define MPI2_SASPHY1_PAGEVERSION (0x01)
2478
2479
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2480/* SAS PHY Page 2 */
2481
2482typedef struct _MPI2_SASPHY2_PHY_EVENT {
2483 U8 PhyEventCode; /* 0x00 */
2484 U8 Reserved1; /* 0x01 */
2485 U16 Reserved2; /* 0x02 */
2486 U32 PhyEventInfo; /* 0x04 */
2487} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2488 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2489
2490/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2491
2492
2493/*
2494 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2495 * one and check the value returned for NumPhyEvents at runtime.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2496 */
2497#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2498#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2499#endif
2500
2501typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2502 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2503 U32 Reserved1; /* 0x08 */
2504 U8 NumPhyEvents; /* 0x0C */
2505 U8 Reserved2; /* 0x0D */
2506 U16 Reserved3; /* 0x0E */
2507 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2508 /* 0x10 */
2509} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2510 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2511
2512#define MPI2_SASPHY2_PAGEVERSION (0x00)
2513
2514
2515/* SAS PHY Page 3 */
2516
2517typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2518 U8 PhyEventCode; /* 0x00 */
2519 U8 Reserved1; /* 0x01 */
2520 U16 Reserved2; /* 0x02 */
2521 U8 CounterType; /* 0x04 */
2522 U8 ThresholdWindow; /* 0x05 */
2523 U8 TimeUnits; /* 0x06 */
2524 U8 Reserved3; /* 0x07 */
2525 U32 EventThreshold; /* 0x08 */
2526 U16 ThresholdFlags; /* 0x0C */
2527 U16 Reserved4; /* 0x0E */
2528} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2529 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2530
2531/* values for PhyEventCode field */
2532#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2533#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2534#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2535#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2536#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2537#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2538#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2539#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2540#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2541#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2542#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2543#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2544#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2545#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2546#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2547#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2548#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2549#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2550#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2551#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2552#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2553#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2554#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2555#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2556#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2557#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2558#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2559#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2560#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2561#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2562#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2563#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2564#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2565#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2566#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2567#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2568#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2569
2570/* values for the CounterType field */
2571#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2572#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2573#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2574
2575/* values for the TimeUnits field */
2576#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2577#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2578#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2579#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2580
2581/* values for the ThresholdFlags field */
2582#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2583#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2584
2585/*
2586 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2587 * one and check the value returned for NumPhyEvents at runtime.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]2588 */
2589#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2590#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2591#endif
2592
2593typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2594 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2595 U32 Reserved1; /* 0x08 */
2596 U8 NumPhyEvents; /* 0x0C */
2597 U8 Reserved2; /* 0x0D */
2598 U16 Reserved3; /* 0x0E */
2599 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2600 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2601} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2602 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2603
2604#define MPI2_SASPHY3_PAGEVERSION (0x00)
2605
2606
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]2607/* SAS PHY Page 4 */
2608
2609typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2610 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2611 U16 Reserved1; /* 0x08 */
2612 U8 Reserved2; /* 0x0A */
2613 U8 Flags; /* 0x0B */
2614 U8 InitialFrame[28]; /* 0x0C */
2615} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2616 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2617
2618#define MPI2_SASPHY4_PAGEVERSION (0x00)
2619
2620/* values for the Flags field */
2621#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2622#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2623
2624
2625
2626
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2627/****************************************************************************
2628* SAS Port Config Pages
2629****************************************************************************/
2630
2631/* SAS Port Page 0 */
2632
2633typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2634{
2635 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2636 U8 PortNumber; /* 0x08 */
2637 U8 PhysicalPort; /* 0x09 */
2638 U8 PortWidth; /* 0x0A */
2639 U8 PhysicalPortWidth; /* 0x0B */
2640 U8 ZoneGroup; /* 0x0C */
2641 U8 Reserved1; /* 0x0D */
2642 U16 Reserved2; /* 0x0E */
2643 U64 SASAddress; /* 0x10 */
2644 U32 DeviceInfo; /* 0x18 */
2645 U32 Reserved3; /* 0x1C */
2646 U32 Reserved4; /* 0x20 */
2647} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2648 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2649
2650#define MPI2_SASPORT0_PAGEVERSION (0x00)
2651
2652/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2653
2654
2655/****************************************************************************
2656* SAS Enclosure Config Pages
2657****************************************************************************/
2658
2659/* SAS Enclosure Page 0 */
2660
2661typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2662{
2663 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2664 U32 Reserved1; /* 0x08 */
2665 U64 EnclosureLogicalID; /* 0x0C */
2666 U16 Flags; /* 0x14 */
2667 U16 EnclosureHandle; /* 0x16 */
2668 U16 NumSlots; /* 0x18 */
2669 U16 StartSlot; /* 0x1A */
2670 U16 Reserved2; /* 0x1C */
2671 U16 SEPDevHandle; /* 0x1E */
2672 U32 Reserved3; /* 0x20 */
2673 U32 Reserved4; /* 0x24 */
2674} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2675 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2676 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2677
2678#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2679
2680/* values for SAS Enclosure Page 0 Flags field */
2681#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2682#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2683#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2684#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2685#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2686#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2687#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2688
2689
2690/****************************************************************************
2691* Log Config Page
2692****************************************************************************/
2693
2694/* Log Page 0 */
2695
2696/*
2697 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2698 * one and check the value returned for NumLogEntries at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2699 */
2700#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2701#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2702#endif
2703
2704#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2705
2706typedef struct _MPI2_LOG_0_ENTRY
2707{
2708 U64 TimeStamp; /* 0x00 */
2709 U32 Reserved1; /* 0x08 */
2710 U16 LogSequence; /* 0x0C */
2711 U16 LogEntryQualifier; /* 0x0E */
2712 U8 VP_ID; /* 0x10 */
2713 U8 VF_ID; /* 0x11 */
2714 U16 Reserved2; /* 0x12 */
2715 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2716} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2717 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2718
2719/* values for Log Page 0 LogEntry LogEntryQualifier field */
2720#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2721#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2722#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2723#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2724#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2725
2726typedef struct _MPI2_CONFIG_PAGE_LOG_0
2727{
2728 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2729 U32 Reserved1; /* 0x08 */
2730 U32 Reserved2; /* 0x0C */
2731 U16 NumLogEntries; /* 0x10 */
2732 U16 Reserved3; /* 0x12 */
2733 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2734} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2735 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2736
2737#define MPI2_LOG_0_PAGEVERSION (0x02)
2738
2739
2740/****************************************************************************
2741* RAID Config Page
2742****************************************************************************/
2743
2744/* RAID Page 0 */
2745
2746/*
2747 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]2748 * one and check the value returned for NumElements at runtime.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2749 */
2750#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2751#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2752#endif
2753
2754typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2755{
2756 U16 ElementFlags; /* 0x00 */
2757 U16 VolDevHandle; /* 0x02 */
2758 U8 HotSparePool; /* 0x04 */
2759 U8 PhysDiskNum; /* 0x05 */
2760 U16 PhysDiskDevHandle; /* 0x06 */
2761} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2762 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2763 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2764
2765/* values for the ElementFlags field */
2766#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2767#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2768#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2769#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2770#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2771
2772
2773typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2774{
2775 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2776 U8 NumHotSpares; /* 0x08 */
2777 U8 NumPhysDisks; /* 0x09 */
2778 U8 NumVolumes; /* 0x0A */
2779 U8 ConfigNum; /* 0x0B */
2780 U32 Flags; /* 0x0C */
2781 U8 ConfigGUID[24]; /* 0x10 */
2782 U32 Reserved1; /* 0x28 */
2783 U8 NumElements; /* 0x2C */
2784 U8 Reserved2; /* 0x2D */
2785 U16 Reserved3; /* 0x2E */
2786 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2787} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2788 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2789 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2790
2791#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2792
2793/* values for RAID Configuration Page 0 Flags field */
2794#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2795
2796
2797/****************************************************************************
2798* Driver Persistent Mapping Config Pages
2799****************************************************************************/
2800
2801/* Driver Persistent Mapping Page 0 */
2802
2803typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2804{
2805 U64 PhysicalIdentifier; /* 0x00 */
2806 U16 MappingInformation; /* 0x08 */
2807 U16 DeviceIndex; /* 0x0A */
2808 U32 PhysicalBitsMapping; /* 0x0C */
2809 U32 Reserved1; /* 0x10 */
2810} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2811 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2812 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2813
2814typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2815{
2816 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2817 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2818} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2819 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2820 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2821
2822#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2823
2824/* values for Driver Persistent Mapping Page 0 MappingInformation field */
2825#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2826#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2827#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2828
2829
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]2830/****************************************************************************
2831* Ethernet Config Pages
2832****************************************************************************/
2833
2834/* Ethernet Page 0 */
2835
2836/* IP address (union of IPv4 and IPv6) */
2837typedef union _MPI2_ETHERNET_IP_ADDR {
2838 U32 IPv4Addr;
2839 U32 IPv6Addr[4];
2840} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2841 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2842
2843#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2844
2845typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2846 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2847 U8 NumInterfaces; /* 0x08 */
2848 U8 Reserved0; /* 0x09 */
2849 U16 Reserved1; /* 0x0A */
2850 U32 Status; /* 0x0C */
2851 U8 MediaState; /* 0x10 */
2852 U8 Reserved2; /* 0x11 */
2853 U16 Reserved3; /* 0x12 */
2854 U8 MacAddress[6]; /* 0x14 */
2855 U8 Reserved4; /* 0x1A */
2856 U8 Reserved5; /* 0x1B */
2857 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2858 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2859 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2860 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2861 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2862 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2863 U8 HostName
2864 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2865} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2866 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2867
2868#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2869
2870/* values for Ethernet Page 0 Status field */
2871#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2872#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2873#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2874#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2875#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2876#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2877#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2878#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2879#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2880#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2881#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2882#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2883
2884/* values for Ethernet Page 0 MediaState field */
2885#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2886#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2887#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2888
2889#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2890#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2891#define MPI2_ETHPG0_MS_10MBIT (0x01)
2892#define MPI2_ETHPG0_MS_100MBIT (0x02)
2893#define MPI2_ETHPG0_MS_1GBIT (0x03)
2894
2895
2896/* Ethernet Page 1 */
2897
2898typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2899 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2900 U32 Reserved0; /* 0x08 */
2901 U32 Flags; /* 0x0C */
2902 U8 MediaState; /* 0x10 */
2903 U8 Reserved1; /* 0x11 */
2904 U16 Reserved2; /* 0x12 */
2905 U8 MacAddress[6]; /* 0x14 */
2906 U8 Reserved3; /* 0x1A */
2907 U8 Reserved4; /* 0x1B */
2908 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2909 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2910 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2911 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2912 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2913 U32 Reserved5; /* 0x6C */
2914 U32 Reserved6; /* 0x70 */
2915 U32 Reserved7; /* 0x74 */
2916 U32 Reserved8; /* 0x78 */
2917 U8 HostName
2918 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2919} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2920 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2921
2922#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2923
2924/* values for Ethernet Page 1 Flags field */
2925#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2926#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2927#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2928#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2929#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2930#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2931#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2932#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2933#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2934
2935/* values for Ethernet Page 1 MediaState field */
2936#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2937#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2938#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2939
2940#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2941#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2942#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2943#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2944#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2945
2946
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]2947/****************************************************************************
2948* Extended Manufacturing Config Pages
2949****************************************************************************/
2950
2951/*
2952 * Generic structure to use for product-specific extended manufacturing pages
2953 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2954 * Page 60).
2955 */
2956
2957typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
2958 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2959 U32 ProductSpecificInfo; /* 0x08 */
2960} MPI2_CONFIG_PAGE_EXT_MAN_PS,
2961 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2962 Mpi2ExtManufacturingPagePS_t,
2963 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2964
2965/* PageVersion should be provided by product-specific code */
2966
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]2967#endif
2968