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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-v6.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01005 * Modified by Catalin Marinas for noMMU support
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This is the "shell" of the ARMv6 processor support.
12 */
Tim Abbott991da172009-04-27 14:02:22 -040013#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/linkage.h>
15#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020016#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010017#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000018#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <asm/pgtable.h>
20
21#include "proc-macros.S"
22
23#define D_CACHE_LINE_SIZE 32
24
Russell King3747b362006-03-27 16:59:07 +010025#define TTB_C (1 << 0)
26#define TTB_S (1 << 1)
27#define TTB_IMP (1 << 2)
28#define TTB_RGN_NC (0 << 3)
29#define TTB_RGN_WBWA (1 << 3)
30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3)
32
Russell Kingf2131d32007-02-08 20:46:20 +000033#ifndef CONFIG_SMP
34#define TTB_FLAGS TTB_RGN_WBWA
Russell King4b46d642009-11-01 17:44:24 +000035#define PMD_FLAGS PMD_SECT_WB
Russell Kingf2131d32007-02-08 20:46:20 +000036#else
37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
Russell King4b46d642009-11-01 17:44:24 +000038#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
Russell Kingf2131d32007-02-08 20:46:20 +000039#endif
40
Linus Torvalds1da177e2005-04-16 15:20:36 -070041ENTRY(cpu_v6_proc_init)
42 mov pc, lr
43
44ENTRY(cpu_v6_proc_fin)
Tony Lindgren67c5587a2005-10-19 23:00:56 +010045 stmfd sp!, {lr}
46 cpsid if @ disable interrupts
47 bl v6_flush_kern_cache_all
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ldmfd sp!, {pc}
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54/*
55 * cpu_v6_reset(loc)
56 *
57 * Perform a soft reset of the system. Put the CPU into the
58 * same state as it would be if it had been reset, and branch
59 * to what would be the reset vector.
60 *
61 * - loc - location to jump to for soft reset
62 *
63 * It is assumed that:
64 */
65 .align 5
66ENTRY(cpu_v6_reset)
67 mov pc, r0
68
69/*
70 * cpu_v6_do_idle()
71 *
72 * Idle the processor (eg, wait for interrupt).
73 *
74 * IRQs are already disabled.
75 */
76ENTRY(cpu_v6_do_idle)
Catalin Marinas8553cb62008-11-10 14:14:11 +000077 mov r1, #0
78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
80 mov pc, lr
81
82ENTRY(cpu_v6_dcache_clean_area)
83#ifndef TLB_CAN_READ_FROM_L1_CACHE
841: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
85 add r0, r0, #D_CACHE_LINE_SIZE
86 subs r1, r1, #D_CACHE_LINE_SIZE
87 bhi 1b
88#endif
89 mov pc, lr
90
91/*
92 * cpu_arm926_switch_mm(pgd_phys, tsk)
93 *
94 * Set the translation table base pointer to be pgd_phys
95 *
96 * - pgd_phys - physical address of new TTB
97 *
98 * It is assumed that:
99 * - we are not using split page tables
100 */
101ENTRY(cpu_v6_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100102#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103 mov r2, #0
104 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
Russell Kingf2131d32007-02-08 20:46:20 +0000105 orr r0, r0, #TTB_FLAGS
Russell Kingd93742f2005-08-15 16:53:38 +0100106 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
108 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
109 mcr p15, 0, r1, c13, c0, 1 @ set context ID
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100110#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 mov pc, lr
112
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113/*
Russell Kingad1ae2f2006-12-13 14:34:43 +0000114 * cpu_v6_set_pte_ext(ptep, pte, ext)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 *
116 * Set a level 2 translation table entry.
117 *
118 * - ptep - pointer to level 2 translation table entry
119 * (hardware version is stored at -1024 bytes)
120 * - pte - PTE value to store
Russell Kingad1ae2f2006-12-13 14:34:43 +0000121 * - ext - value for extended PTE bits
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 */
Russell King639b0ae2008-09-06 21:07:45 +0100123 armv6_mt_table cpu_v6
124
Russell Kingad1ae2f2006-12-13 14:34:43 +0000125ENTRY(cpu_v6_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100126#ifdef CONFIG_MMU
Russell King639b0ae2008-09-06 21:07:45 +0100127 armv6_set_pte_ext cpu_v6
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100128#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 mov pc, lr
130
131
132
133
134cpu_v6_name:
Russell King94b1e962006-12-08 15:32:25 +0000135 .asciz "ARMv6-compatible processor"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 .align
137
Tim Abbott991da172009-04-27 14:02:22 -0400138 __INIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140/*
141 * __v6_setup
142 *
143 * Initialise TLB, Caches, and MMU state ready to switch the MMU
144 * on. Return in r0 the new CP15 C1 control register setting.
145 *
146 * We automatically detect if we have a Harvard cache, and use the
147 * Harvard cache control instructions insead of the unified cache
148 * control instructions.
149 *
150 * This should be able to cover all ARMv6 cores.
151 *
152 * It is assumed that:
153 * - cache type register is implemented
154 */
155__v6_setup:
Russell King862184f2005-11-07 21:05:42 +0000156#ifdef CONFIG_SMP
Russell King862184f2005-11-07 21:05:42 +0000157 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
158 orr r0, r0, #0x20
159 mcr p15, 0, r0, c1, c0, 1
160#endif
Russell King862184f2005-11-07 21:05:42 +0000161
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 mov r0, #0
163 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
164 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
165 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
166 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100167#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
169 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
Russell Kingf2131d32007-02-08 20:46:20 +0000170 orr r4, r4, #TTB_FLAGS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100172#endif /* CONFIG_MMU */
Russell King22b19082006-06-29 15:09:57 +0100173 adr r5, v6_crval
174 ldmia r5, {r5, r6}
Catalin Marinas26584852009-05-30 14:00:18 +0100175#ifdef CONFIG_CPU_ENDIAN_BE8
176 orr r6, r6, #1 << 25 @ big-endian page tables
177#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178 mrc p15, 0, r0, c1, c0, 0 @ read control register
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 bic r0, r0, r5 @ clear bits them
Russell King22b19082006-06-29 15:09:57 +0100180 orr r0, r0, r6 @ set them
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 mov pc, lr @ return to head.S:__ret
182
183 /*
184 * V X F I D LR
185 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
186 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
187 * 0 110 0011 1.00 .111 1101 < we want
188 */
Russell King22b19082006-06-29 15:09:57 +0100189 .type v6_crval, #object
190v6_crval:
191 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192
193 .type v6_processor_functions, #object
194ENTRY(v6_processor_functions)
195 .word v6_early_abort
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100196 .word v6_pabort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 .word cpu_v6_proc_init
198 .word cpu_v6_proc_fin
199 .word cpu_v6_reset
200 .word cpu_v6_do_idle
201 .word cpu_v6_dcache_clean_area
202 .word cpu_v6_switch_mm
Russell Kingad1ae2f2006-12-13 14:34:43 +0000203 .word cpu_v6_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 .size v6_processor_functions, . - v6_processor_functions
205
206 .type cpu_arch_name, #object
207cpu_arch_name:
208 .asciz "armv6"
209 .size cpu_arch_name, . - cpu_arch_name
210
211 .type cpu_elf_name, #object
212cpu_elf_name:
213 .asciz "v6"
214 .size cpu_elf_name, . - cpu_elf_name
215 .align
216
Ben Dooks02b7dd12005-09-20 16:35:03 +0100217 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219 /*
220 * Match any ARMv6 processor core.
221 */
222 .type __v6_proc_info, #object
223__v6_proc_info:
224 .long 0x0007b000
225 .long 0x0007f000
226 .long PMD_TYPE_SECT | \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 PMD_SECT_AP_WRITE | \
Russell King4b46d642009-11-01 17:44:24 +0000228 PMD_SECT_AP_READ | \
229 PMD_FLAGS
Russell King8799ee92006-06-29 18:24:21 +0100230 .long PMD_TYPE_SECT | \
231 PMD_SECT_XN | \
232 PMD_SECT_AP_WRITE | \
233 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 b __v6_setup
235 .long cpu_arch_name
236 .long cpu_elf_name
Russell Kingefe90d22006-12-08 15:22:20 +0000237 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 .long cpu_v6_name
239 .long v6_processor_functions
240 .long v6wbi_tlb_fns
241 .long v6_user_fns
242 .long v6_cache_fns
243 .size __v6_proc_info, . - __v6_proc_info