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gerrit-public.fairphone.software / kernel / msm / fcdb27ad1d5c66611d3df6400a9b559186f266fe / . / arch / mips / tx4927 / toshiba_rbtx4927 / toshiba_rbtx4927_setup.c
blob: 098132916cc806d0a6335e2742e89df148636d1e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45#include <linux/config.h>
46#include <linux/init.h>
47#include <linux/kernel.h>
48#include <linux/types.h>
49#include <linux/mm.h>
50#include <linux/swap.h>
51#include <linux/ioport.h>
52#include <linux/sched.h>
53#include <linux/interrupt.h>
54#include <linux/pci.h>
55#include <linux/timex.h>
Ralf Baechlefcdb27a2006-01-18 17:37:07 +0000[diff] [blame^]56#include <linux/pm.h>
57
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]58#include <asm/bootinfo.h>
59#include <asm/page.h>
60#include <asm/io.h>
61#include <asm/irq.h>
62#include <asm/processor.h>
63#include <asm/ptrace.h>
64#include <asm/reboot.h>
65#include <asm/time.h>
66#include <linux/bootmem.h>
67#include <linux/blkdev.h>
68#ifdef CONFIG_RTC_DS1742
69#include <linux/ds1742rtc.h>
70#endif
71#ifdef CONFIG_TOSHIBA_FPCIB0
72#include <asm/tx4927/smsc_fdc37m81x.h>
73#endif
74#include <asm/tx4927/toshiba_rbtx4927.h>
75#ifdef CONFIG_PCI
76#include <asm/tx4927/tx4927_pci.h>
77#endif
78#ifdef CONFIG_BLK_DEV_IDEPCI
79#include <linux/hdreg.h>
80#include <linux/ide.h>
81#endif
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000[diff] [blame]82#ifdef CONFIG_SERIAL_TXX9
83#include <linux/tty.h>
84#include <linux/serial.h>
85#include <linux/serial_core.h>
86#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]87
88#undef TOSHIBA_RBTX4927_SETUP_DEBUG
89
90#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
91#define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
92
93#define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
94#define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
95#define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
96
97#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
98#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
99#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
100#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
101#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
102#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
103#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
104#define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
105
106#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
107#endif
108
109#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
110static const u32 toshiba_rbtx4927_setup_debug_flag =
111 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
112 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
113 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
114 TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
115 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
116 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
117#endif
118
119#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
120#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
121 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
122 { \
123 char tmp[100]; \
124 sprintf( tmp, str ); \
125 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
126 }
127#else
128#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
129#endif
130
131/* These functions are used for rebooting or halting the machine*/
132extern void toshiba_rbtx4927_restart(char *command);
133extern void toshiba_rbtx4927_halt(void);
134extern void toshiba_rbtx4927_power_off(void);
135
136int tx4927_using_backplane = 0;
137
138extern void gt64120_time_init(void);
139extern void toshiba_rbtx4927_irq_setup(void);
140
141#ifdef CONFIG_PCI
142#define CONFIG_TX4927BUG_WORKAROUND
143#undef TX4927_SUPPORT_COMMAND_IO
144#undef TX4927_SUPPORT_PCI_66
145int tx4927_cpu_clock = 100000000; /* 100MHz */
146unsigned long mips_pci_io_base;
147unsigned long mips_pci_io_size;
148unsigned long mips_pci_mem_base;
149unsigned long mips_pci_mem_size;
150/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
151unsigned long mips_pci_io_pciaddr = 0;
152unsigned long mips_memory_upper;
153static int tx4927_ccfg_toeon = 1;
154static int tx4927_pcic_trdyto = 0; /* default: disabled */
155unsigned long tx4927_ce_base[8];
156void tx4927_pci_setup(void);
157void tx4927_reset_pci_pcic(void);
158int tx4927_pci66 = 0; /* 0:auto */
159#endif
160
161char *toshiba_name = "";
162
163#ifdef CONFIG_PCI
164static void tx4927_pcierr_interrupt(int irq, void *dev_id,
165 struct pt_regs *regs)
166{
167#ifdef CONFIG_BLK_DEV_IDEPCI
168 /* ignore MasterAbort for ide probing... */
169 if (irq == TX4927_IRQ_IRC_PCIERR &&
170 ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
171 PCI_STATUS_REC_MASTER_ABORT) {
172 tx4927_pcicptr->pcistatus =
173 (tx4927_pcicptr->
174 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
175 << 16);
176
177 return;
178 }
179#endif
180 printk("PCI error interrupt (irq 0x%x).\n", irq);
181
182 printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
183 (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
184 tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
185 printk("ccfg:%08lx, tear:%02lx_%08lx\n",
186 (unsigned long) tx4927_ccfgptr->ccfg,
187 (unsigned long) (tx4927_ccfgptr->tear >> 32),
188 (unsigned long) tx4927_ccfgptr->tear);
189 show_regs(regs);
190}
191
192void __init toshiba_rbtx4927_pci_irq_init(void)
193{
194 return;
195}
196
197void tx4927_reset_pci_pcic(void)
198{
199 /* Reset PCI Bus */
200 *tx4927_pcireset_ptr = 1;
201 /* Reset PCIC */
202 tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
203 udelay(10000);
204 /* clear PCIC reset */
205 tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
206 *tx4927_pcireset_ptr = 0;
207}
208#endif /* CONFIG_PCI */
209
210#ifdef CONFIG_PCI
211void print_pci_status(void)
212{
213 printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
214 printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
215}
216
217extern struct pci_controller tx4927_controller;
218
219static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
220 int top_bus, int busnr, int devfn)
221{
222 static struct pci_dev dev;
223 static struct pci_bus bus;
224
225 dev.sysdata = (void *)hose;
226 dev.devfn = devfn;
227 bus.number = busnr;
228 bus.ops = hose->pci_ops;
229 bus.parent = NULL;
230 dev.bus = &bus;
231
232 return &dev;
233}
234
235#define EARLY_PCI_OP(rw, size, type) \
236static int early_##rw##_config_##size(struct pci_controller *hose, \
237 int top_bus, int bus, int devfn, int offset, type value) \
238{ \
239 return pci_##rw##_config_##size( \
240 fake_pci_dev(hose, top_bus, bus, devfn), \
241 offset, value); \
242}
243
244EARLY_PCI_OP(read, byte, u8 *)
245EARLY_PCI_OP(read, word, u16 *)
246EARLY_PCI_OP(read, dword, u32 *)
247EARLY_PCI_OP(write, byte, u8)
248EARLY_PCI_OP(write, word, u16)
249EARLY_PCI_OP(write, dword, u32)
250
251static int __init tx4927_pcibios_init(void)
252{
253 unsigned int id;
254 u32 pci_devfn;
255 int devfn_start = 0;
256 int devfn_stop = 0xff;
257 int busno = 0; /* One bus on the Toshiba */
258 struct pci_controller *hose = &tx4927_controller;
259
260 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
261 "-\n");
262
263 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
264 early_read_config_dword(hose, busno, busno, pci_devfn,
265 PCI_VENDOR_ID, &id);
266
267 if (id == 0xffffffff) {
268 continue;
269 }
270
271 if (id == 0x94601055) {
272 u8 v08_64;
273 u32 v32_b0;
274 u8 v08_e1;
275 char *s = " sb/isa --";
276
277 TOSHIBA_RBTX4927_SETUP_DPRINTK
278 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
279 s);
280
281 early_read_config_byte(hose, busno, busno,
282 pci_devfn, 0x64, &v08_64);
283 early_read_config_dword(hose, busno, busno,
284 pci_devfn, 0xb0, &v32_b0);
285 early_read_config_byte(hose, busno, busno,
286 pci_devfn, 0xe1, &v08_e1);
287
288 TOSHIBA_RBTX4927_SETUP_DPRINTK
289 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
290 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
291 TOSHIBA_RBTX4927_SETUP_DPRINTK
292 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
293 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
294 TOSHIBA_RBTX4927_SETUP_DPRINTK
295 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
296 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
297
298 /* serial irq control */
299 v08_64 = 0xd0;
300
301 /* serial irq pin */
302 v32_b0 |= 0x00010000;
303
304 /* ide irq on isa14 */
305 v08_e1 &= 0xf0;
306 v08_e1 |= 0x0d;
307
308 TOSHIBA_RBTX4927_SETUP_DPRINTK
309 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
310 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
311 TOSHIBA_RBTX4927_SETUP_DPRINTK
312 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
313 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
314 TOSHIBA_RBTX4927_SETUP_DPRINTK
315 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
316 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
317
318 early_write_config_byte(hose, busno, busno,
319 pci_devfn, 0x64, v08_64);
320 early_write_config_dword(hose, busno, busno,
321 pci_devfn, 0xb0, v32_b0);
322 early_write_config_byte(hose, busno, busno,
323 pci_devfn, 0xe1, v08_e1);
324
325#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
326 {
327 early_read_config_byte(hose, busno, busno,
328 pci_devfn, 0x64,
329 &v08_64);
330 early_read_config_dword(hose, busno, busno,
331 pci_devfn, 0xb0,
332 &v32_b0);
333 early_read_config_byte(hose, busno, busno,
334 pci_devfn, 0xe1,
335 &v08_e1);
336
337 TOSHIBA_RBTX4927_SETUP_DPRINTK
338 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
339 ":%s end 0x64 = 0x%02x\n", s, v08_64);
340 TOSHIBA_RBTX4927_SETUP_DPRINTK
341 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
342 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
343 TOSHIBA_RBTX4927_SETUP_DPRINTK
344 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
345 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
346 }
347#endif
348
349 TOSHIBA_RBTX4927_SETUP_DPRINTK
350 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
351 s);
352 }
353
354 if (id == 0x91301055) {
355 u8 v08_04;
356 u8 v08_09;
357 u8 v08_41;
358 u8 v08_43;
359 u8 v08_5c;
360 char *s = " sb/ide --";
361
362 TOSHIBA_RBTX4927_SETUP_DPRINTK
363 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
364 s);
365
366 early_read_config_byte(hose, busno, busno,
367 pci_devfn, 0x04, &v08_04);
368 early_read_config_byte(hose, busno, busno,
369 pci_devfn, 0x09, &v08_09);
370 early_read_config_byte(hose, busno, busno,
371 pci_devfn, 0x41, &v08_41);
372 early_read_config_byte(hose, busno, busno,
373 pci_devfn, 0x43, &v08_43);
374 early_read_config_byte(hose, busno, busno,
375 pci_devfn, 0x5c, &v08_5c);
376
377 TOSHIBA_RBTX4927_SETUP_DPRINTK
378 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
379 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
380 TOSHIBA_RBTX4927_SETUP_DPRINTK
381 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
382 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
383 TOSHIBA_RBTX4927_SETUP_DPRINTK
384 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
385 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
386 TOSHIBA_RBTX4927_SETUP_DPRINTK
387 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
388 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
389 TOSHIBA_RBTX4927_SETUP_DPRINTK
390 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
391 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
392
393 /* enable ide master/io */
394 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
395
396 /* enable ide native mode */
397 v08_09 |= 0x05;
398
399 /* enable primary ide */
400 v08_41 |= 0x80;
401
402 /* enable secondary ide */
403 v08_43 |= 0x80;
404
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700[diff] [blame]405 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]406 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
407 *
408 * This line of code is intended to provide the user with a work
409 * around solution to the anomalies cited in SMSC's anomaly sheet
410 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
411 *
412 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
413 */
414 v08_5c |= 0x01;
415
416 TOSHIBA_RBTX4927_SETUP_DPRINTK
417 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
418 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
419 TOSHIBA_RBTX4927_SETUP_DPRINTK
420 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
421 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
422 TOSHIBA_RBTX4927_SETUP_DPRINTK
423 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
424 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
425 TOSHIBA_RBTX4927_SETUP_DPRINTK
426 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
427 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
428 TOSHIBA_RBTX4927_SETUP_DPRINTK
429 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
430 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
431
432 early_write_config_byte(hose, busno, busno,
433 pci_devfn, 0x5c, v08_5c);
434 early_write_config_byte(hose, busno, busno,
435 pci_devfn, 0x04, v08_04);
436 early_write_config_byte(hose, busno, busno,
437 pci_devfn, 0x09, v08_09);
438 early_write_config_byte(hose, busno, busno,
439 pci_devfn, 0x41, v08_41);
440 early_write_config_byte(hose, busno, busno,
441 pci_devfn, 0x43, v08_43);
442
443#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
444 {
445 early_read_config_byte(hose, busno, busno,
446 pci_devfn, 0x04,
447 &v08_04);
448 early_read_config_byte(hose, busno, busno,
449 pci_devfn, 0x09,
450 &v08_09);
451 early_read_config_byte(hose, busno, busno,
452 pci_devfn, 0x41,
453 &v08_41);
454 early_read_config_byte(hose, busno, busno,
455 pci_devfn, 0x43,
456 &v08_43);
457 early_read_config_byte(hose, busno, busno,
458 pci_devfn, 0x5c,
459 &v08_5c);
460
461 TOSHIBA_RBTX4927_SETUP_DPRINTK
462 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
463 ":%s end 0x04 = 0x%02x\n", s, v08_04);
464 TOSHIBA_RBTX4927_SETUP_DPRINTK
465 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
466 ":%s end 0x09 = 0x%02x\n", s, v08_09);
467 TOSHIBA_RBTX4927_SETUP_DPRINTK
468 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
469 ":%s end 0x41 = 0x%02x\n", s, v08_41);
470 TOSHIBA_RBTX4927_SETUP_DPRINTK
471 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
472 ":%s end 0x43 = 0x%02x\n", s, v08_43);
473 TOSHIBA_RBTX4927_SETUP_DPRINTK
474 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
475 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
476 }
477#endif
478
479 TOSHIBA_RBTX4927_SETUP_DPRINTK
480 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
481 s);
482 }
483
484 }
485
486 register_pci_controller(&tx4927_controller);
487 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
488 "+\n");
489
490 return 0;
491}
492
493arch_initcall(tx4927_pcibios_init);
494
495extern struct resource pci_io_resource;
496extern struct resource pci_mem_resource;
497
498void tx4927_pci_setup(void)
499{
500 static int called = 0;
501 extern unsigned int tx4927_get_mem_size(void);
502
503 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
504
505 mips_memory_upper = tx4927_get_mem_size() << 20;
506 mips_memory_upper += KSEG0;
507 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
508 "0x%08lx=mips_memory_upper\n",
509 mips_memory_upper);
510 mips_pci_io_base = TX4927_PCIIO;
511 mips_pci_io_size = TX4927_PCIIO_SIZE;
512 mips_pci_mem_base = TX4927_PCIMEM;
513 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
514
515 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
516 "0x%08lx=mips_pci_io_base\n",
517 mips_pci_io_base);
518 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
519 "0x%08lx=mips_pci_io_size\n",
520 mips_pci_io_size);
521 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
522 "0x%08lx=mips_pci_mem_base\n",
523 mips_pci_mem_base);
524 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
525 "0x%08lx=mips_pci_mem_size\n",
526 mips_pci_mem_size);
527 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
528 "0x%08lx=pci_io_resource.start\n",
529 pci_io_resource.start);
530 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
531 "0x%08lx=pci_io_resource.end\n",
532 pci_io_resource.end);
533 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
534 "0x%08lx=pci_mem_resource.start\n",
535 pci_mem_resource.start);
536 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
537 "0x%08lx=pci_mem_resource.end\n",
538 pci_mem_resource.end);
539 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
540 "0x%08lx=mips_io_port_base",
541 mips_io_port_base);
542
543 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
544 "setup pci_io_resource to 0x%08lx 0x%08lx\n",
545 pci_io_resource.start,
546 pci_io_resource.end);
547 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
548 "setup pci_mem_resource to 0x%08lx 0x%08lx\n",
549 pci_mem_resource.start,
550 pci_mem_resource.end);
551
552 if (!called) {
553 printk
554 ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
555 (unsigned short) (tx4927_pcicptr->pciid >> 16),
556 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
557 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
558 (!(tx4927_ccfgptr->
559 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
560 "Internal");
561 called = 1;
562 }
563 printk("%s PCIC --%s PCICLK:",toshiba_name,
564 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
565 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
566 int pciclk = 0;
567 switch ((unsigned long) tx4927_ccfgptr->
568 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
569 case TX4927_CCFG_PCIDIVMODE_2_5:
570 pciclk = tx4927_cpu_clock * 2 / 5;
571 break;
572 case TX4927_CCFG_PCIDIVMODE_3:
573 pciclk = tx4927_cpu_clock / 3;
574 break;
575 case TX4927_CCFG_PCIDIVMODE_5:
576 pciclk = tx4927_cpu_clock / 5;
577 break;
578 case TX4927_CCFG_PCIDIVMODE_6:
579 pciclk = tx4927_cpu_clock / 6;
580 break;
581 }
582 printk("Internal(%dMHz)", pciclk / 1000000);
583 } else {
584 int pciclk = 0;
585 int pciclk_setting = *tx4927_pci_clk_ptr;
586 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
587 case TX4927_PCI_CLK_33:
588 pciclk = 33333333;
589 break;
590 case TX4927_PCI_CLK_25:
591 pciclk = 25000000;
592 break;
593 case TX4927_PCI_CLK_66:
594 pciclk = 66666666;
595 break;
596 case TX4927_PCI_CLK_50:
597 pciclk = 50000000;
598 break;
599 }
600 printk("External(%dMHz)", pciclk / 1000000);
601 }
602 printk("\n");
603
604
605
606 /* GB->PCI mappings */
607 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
608 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
609#ifdef __BIG_ENDIAN
610 TX4927_PCIC_G2PIOGBASE_ECHG
611#else
612 TX4927_PCIC_G2PIOGBASE_BSDIS
613#endif
614 ;
615
616 tx4927_pcicptr->g2piopbase = 0;
617
618 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
619 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
620#ifdef __BIG_ENDIAN
621 TX4927_PCIC_G2PMnGBASE_ECHG
622#else
623 TX4927_PCIC_G2PMnGBASE_BSDIS
624#endif
625 ;
626 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
627
628 tx4927_pcicptr->g2pmmask[1] = 0;
629 tx4927_pcicptr->g2pmgbase[1] = 0;
630 tx4927_pcicptr->g2pmpbase[1] = 0;
631 tx4927_pcicptr->g2pmmask[2] = 0;
632 tx4927_pcicptr->g2pmgbase[2] = 0;
633 tx4927_pcicptr->g2pmpbase[2] = 0;
634
635
636 /* PCI->GB mappings (I/O 256B) */
637 tx4927_pcicptr->p2giopbase = 0; /* 256B */
638
639 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
640 tx4927_pcicptr->p2gm0plbase = 0;
641 tx4927_pcicptr->p2gm0pubase = 0;
642 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
643#ifdef __BIG_ENDIAN
644 TX4927_PCIC_P2GMnGBASE_TECHG
645#else
646 TX4927_PCIC_P2GMnGBASE_TBSDIS
647#endif
648 ;
649
650 /* PCI->GB mappings (MEM 16MB) -not used */
651 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
652#ifdef CONFIG_TX4927BUG_WORKAROUND
653 /*
654 * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
655 * if P2GM0PUBASE was 0.
656 */
657 tx4927_pcicptr->p2gm1pubase = 0;
658#else
659 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
660#endif
661 tx4927_pcicptr->p2gmgbase[1] = 0;
662
663 /* PCI->GB mappings (MEM 1MB) -not used */
664 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
665 tx4927_pcicptr->p2gmgbase[2] = 0;
666
667
668 /* Enable Initiator Memory 0 Space, I/O Space, Config */
669 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
670 tx4927_pcicptr->pciccfg |=
671 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
672 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
673
674
675 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
676 tx4927_pcicptr->pcicfg1 = 0;
677
678 if (tx4927_pcic_trdyto >= 0) {
679 tx4927_pcicptr->g2ptocnt &= ~0xff;
680 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
681 }
682
683 /* Clear All Local Bus Status */
684 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
685 /* Enable All Local Bus Interrupts */
686 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
687 /* Clear All Initiator Status */
688 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
689 /* Enable All Initiator Interrupts */
690 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
691 /* Clear All PCI Status Error */
692 tx4927_pcicptr->pcistatus =
693 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
694 (TX4927_PCIC_PCISTATUS_ALL << 16);
695 /* Enable All PCI Status Error Interrupts */
696 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
697
698 /* PCIC Int => IRC IRQ16 */
699 tx4927_pcicptr->pcicfg2 =
700 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
701
702 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
703 /* XXX */
704 } else {
705 /* Reset Bus Arbiter */
706 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
707 /* Enable Bus Arbiter */
708 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
709 }
710
711 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
712 PCI_COMMAND_MEMORY |
713 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
714
715 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
716 ":pci setup complete:\n");
717 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
718}
719
720#endif /* CONFIG_PCI */
721
722void toshiba_rbtx4927_restart(char *command)
723{
724 printk(KERN_NOTICE "System Rebooting...\n");
725
726 /* enable the s/w reset register */
727 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
728
729 /* wait for enable to be seen */
730 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
731 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
732
733 /* do a s/w reset */
734 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
735
736 /* do something passive while waiting for reset */
737 local_irq_disable();
738 while (1)
739 asm_wait();
740
741 /* no return */
742}
743
744
745void toshiba_rbtx4927_halt(void)
746{
747 printk(KERN_NOTICE "System Halted\n");
748 local_irq_disable();
749 while (1) {
750 asm_wait();
751 }
752 /* no return */
753}
754
755void toshiba_rbtx4927_power_off(void)
756{
757 toshiba_rbtx4927_halt();
758 /* no return */
759}
760
761void __init toshiba_rbtx4927_setup(void)
762{
763 vu32 cp0_config;
764 char *argptr;
765
766 printk("CPU is %s\n", toshiba_name);
767
768 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
769 "-\n");
770
771 /* f/w leaves this on at startup */
772 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
773 ":Clearing STO_ERL.\n");
774 clear_c0_status(ST0_ERL);
775
776 /* enable caches -- HCP5 does this, pmon does not */
777 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
778 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
779 cp0_config = read_c0_config();
780 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
781 write_c0_config(cp0_config);
782
783#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
784 {
785 extern void dump_cp0(char *);
786 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
787 }
788#endif
789
790 /* setup irq stuff */
791 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
792 ":Setting up tx4927 pic.\n");
793 TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
794 TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
795
796 /* setup serial stuff */
797 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
798 ":Setting up tx4927 sio.\n");
799 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
800 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
801
802 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
803 "+\n");
804
805 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
806 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
807 ":mips_io_port_base=0x%08lx\n",
808 mips_io_port_base);
809
810 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
811 ":Resource\n");
812 ioport_resource.end = 0xffffffff;
813 iomem_resource.end = 0xffffffff;
814
815 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
816 ":ResetRoutines\n");
817 _machine_restart = toshiba_rbtx4927_restart;
818 _machine_halt = toshiba_rbtx4927_halt;
Ralf Baechlefcdb27a2006-01-18 17:37:07 +0000[diff] [blame^]819 pm_power_off = toshiba_rbtx4927_power_off;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]820
821#ifdef CONFIG_PCI
822
823 /* PCIC */
824 /*
825 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
826 * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
827 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
828 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
829 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
830 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
831 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
832 */
833 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
834 "ccfg is %lx, DIV is %x\n",
835 (unsigned long) tx4927_ccfgptr->
836 ccfg, TX4927_CCFG_PCIDIVMODE_MASK);
837
838 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
839 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
840 (unsigned long) tx4927_ccfgptr->
841 ccfg & TX4927_CCFG_PCI66,
842 (unsigned long) tx4927_ccfgptr->
843 ccfg & TX4927_CCFG_PCIMIDE,
844 (unsigned long) tx4927_ccfgptr->
845 ccfg & TX4927_CCFG_PCIXARB);
846
847 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
848 "PCIDIVMODE is %lx\n",
849 (unsigned long) tx4927_ccfgptr->
850 ccfg & TX4927_CCFG_PCIDIVMODE_MASK);
851
852 switch ((unsigned long) tx4927_ccfgptr->
853 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
854 case TX4927_CCFG_PCIDIVMODE_2_5:
855 case TX4927_CCFG_PCIDIVMODE_5:
856 tx4927_cpu_clock = 166000000; /* 166MHz */
857 break;
858 default:
859 tx4927_cpu_clock = 200000000; /* 200MHz */
860 }
861
862 /* CCFG */
863 /* enable Timeout BusError */
864 if (tx4927_ccfg_toeon)
865 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
866
867 /* SDRAMC fixup */
868#ifdef CONFIG_TX4927BUG_WORKAROUND
869 /*
870 * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
871 * G-bus timeout error detection is incorrect
872 */
873 if (tx4927_ccfg_toeon)
874 tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */
875#endif
876
877 tx4927_pci_setup();
878 if (tx4927_using_backplane == 1)
879 printk("backplane board IS installed\n");
880 else
881 printk("No Backplane \n");
882
883 /* this is on ISA bus behind PCI bus, so need PCI up first */
884#ifdef CONFIG_TOSHIBA_FPCIB0
885 {
886 if (tx4927_using_backplane) {
887 TOSHIBA_RBTX4927_SETUP_DPRINTK
888 (TOSHIBA_RBTX4927_SETUP_SETUP,
889 ":fpcibo=yes\n");
890
891 TOSHIBA_RBTX4927_SETUP_DPRINTK
892 (TOSHIBA_RBTX4927_SETUP_SETUP,
893 ":smsc_fdc37m81x_init()\n");
894 smsc_fdc37m81x_init(0x3f0);
895
896 TOSHIBA_RBTX4927_SETUP_DPRINTK
897 (TOSHIBA_RBTX4927_SETUP_SETUP,
898 ":smsc_fdc37m81x_config_beg()\n");
899 smsc_fdc37m81x_config_beg();
900
901 TOSHIBA_RBTX4927_SETUP_DPRINTK
902 (TOSHIBA_RBTX4927_SETUP_SETUP,
903 ":smsc_fdc37m81x_config_set(KBD)\n");
904 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
905 SMSC_FDC37M81X_KBD);
906 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
907 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
908 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
909 1);
910
911 smsc_fdc37m81x_config_end();
912 TOSHIBA_RBTX4927_SETUP_DPRINTK
913 (TOSHIBA_RBTX4927_SETUP_SETUP,
914 ":smsc_fdc37m81x_config_end()\n");
915 } else {
916 TOSHIBA_RBTX4927_SETUP_DPRINTK
917 (TOSHIBA_RBTX4927_SETUP_SETUP,
918 ":fpcibo=not_found\n");
919 }
920 }
921#else
922 {
923 TOSHIBA_RBTX4927_SETUP_DPRINTK
924 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
925 }
926#endif
927
928#endif /* CONFIG_PCI */
929
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000[diff] [blame]930#ifdef CONFIG_SERIAL_TXX9
931 {
932 extern int early_serial_txx9_setup(struct uart_port *port);
933 int i;
934 struct uart_port req;
935 for(i = 0; i < 2; i++) {
936 memset(&req, 0, sizeof(req));
937 req.line = i;
938 req.iotype = UPIO_MEM;
939 req.membase = (char *)(0xff1ff300 + i * 0x100);
940 req.mapbase = 0xff1ff300 + i * 0x100;
941 req.irq = 32 + i;
942 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
943 req.uartclk = 50000000;
944 early_serial_txx9_setup(&req);
945 }
946 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]947#ifdef CONFIG_SERIAL_TXX9_CONSOLE
948 argptr = prom_getcmdline();
949 if (strstr(argptr, "console=") == NULL) {
950 strcat(argptr, " console=ttyS0,38400");
951 }
952#endif
Ralf Baechle5eaf7a22005-03-04 17:24:32 +0000[diff] [blame]953#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]954
955#ifdef CONFIG_ROOT_NFS
956 argptr = prom_getcmdline();
957 if (strstr(argptr, "root=") == NULL) {
958 strcat(argptr, " root=/dev/nfs rw");
959 }
960#endif
961
962
963#ifdef CONFIG_IP_PNP
964 argptr = prom_getcmdline();
965 if (strstr(argptr, "ip=") == NULL) {
966 strcat(argptr, " ip=any");
967 }
968#endif
969
970
971 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
972 "+\n");
973}
974
975#ifdef CONFIG_RTC_DS1742
976extern unsigned long rtc_ds1742_get_time(void);
977extern int rtc_ds1742_set_time(unsigned long);
978extern void rtc_ds1742_wait(void);
979#endif
980
981void __init
982toshiba_rbtx4927_time_init(void)
983{
984 u32 c1;
985 u32 c2;
986
987 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
988
989#ifdef CONFIG_RTC_DS1742
990
991 rtc_get_time = rtc_ds1742_get_time;
992 rtc_set_time = rtc_ds1742_set_time;
993
994 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
995 ":rtc_ds1742_init()-\n");
996 rtc_ds1742_init(0xbc010000);
997 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
998 ":rtc_ds1742_init()+\n");
999
1000 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1001 ":Calibrate mips_hpt_frequency-\n");
1002 rtc_ds1742_wait();
1003
1004 /* get the count */
1005 c1 = read_c0_count();
1006
1007 /* wait for the seconds to change again */
1008 rtc_ds1742_wait();
1009
1010 /* get the count again */
1011 c2 = read_c0_count();
1012
1013 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1014 ":Calibrate mips_hpt_frequency+\n");
1015 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1016 ":c1=%12u\n", c1);
1017 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1018 ":c2=%12u\n", c2);
1019
1020 /* this diff is as close as we are going to get to counter ticks per sec */
1021 mips_hpt_frequency = abs(c2 - c1);
1022 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1023 ":f1=%12u\n", mips_hpt_frequency);
1024
1025 /* round to 1/10th of a MHz */
1026 mips_hpt_frequency /= (100 * 1000);
1027 mips_hpt_frequency *= (100 * 1000);
1028 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1029 ":f2=%12u\n", mips_hpt_frequency);
1030
1031 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
1032 ":mips_hpt_frequency=%uHz (%uMHz)\n",
1033 mips_hpt_frequency,
1034 mips_hpt_frequency / 1000000);
1035#else
1036 mips_hpt_frequency = 100000000;
1037#endif
1038
1039 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1040
1041}
1042
1043void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1044{
1045 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1046 "-\n");
1047 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1048 "+\n");
1049}