Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can distribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License (Version 2) as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 12 | * for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 17 | * |
| 18 | * Setting up the clock on the MIPS boards. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <linux/init.h> |
| 23 | #include <linux/kernel_stat.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/time.h> |
| 28 | #include <linux/timex.h> |
| 29 | #include <linux/mc146818rtc.h> |
| 30 | |
| 31 | #include <asm/mipsregs.h> |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 32 | #include <asm/mipsmtregs.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 33 | #include <asm/hardirq.h> |
| 34 | #include <asm/irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/div64.h> |
| 36 | #include <asm/cpu.h> |
| 37 | #include <asm/time.h> |
| 38 | #include <asm/mc146818-time.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 39 | #include <asm/msc01_ic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | |
| 41 | #include <asm/mips-boards/generic.h> |
| 42 | #include <asm/mips-boards/prom.h> |
Maciej W. Rozycki | fc095a9 | 2006-09-12 19:12:18 +0100 | [diff] [blame] | 43 | |
| 44 | #ifdef CONFIG_MIPS_ATLAS |
| 45 | #include <asm/mips-boards/atlasint.h> |
| 46 | #endif |
| 47 | #ifdef CONFIG_MIPS_MALTA |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 48 | #include <asm/mips-boards/maltaint.h> |
Maciej W. Rozycki | fc095a9 | 2006-09-12 19:12:18 +0100 | [diff] [blame] | 49 | #endif |
Atsushi Nemoto | f75f369 | 2007-01-08 01:27:40 +0900 | [diff] [blame] | 50 | #ifdef CONFIG_MIPS_SEAD |
| 51 | #include <asm/mips-boards/seadint.h> |
| 52 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | |
| 54 | unsigned long cpu_khz; |
| 55 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 56 | static int mips_cpu_timer_irq; |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 57 | extern int mipsxx_perfcount_irq; |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 58 | extern void smtc_timer_broadcast(int); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 60 | static void mips_timer_dispatch(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | { |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 62 | do_IRQ(mips_cpu_timer_irq); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 65 | static void mips_perf_dispatch(void) |
| 66 | { |
| 67 | do_IRQ(mipsxx_perfcount_irq); |
| 68 | } |
| 69 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 70 | /* |
| 71 | * Redeclare until I get around mopping the timer code insanity on MIPS. |
| 72 | */ |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 73 | extern int null_perf_irq(void); |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 74 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 75 | extern int (*perf_irq)(void); |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 76 | |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 77 | /* |
| 78 | * Possibly handle a performance counter interrupt. |
| 79 | * Return true if the timer interrupt should not be checked |
| 80 | */ |
| 81 | static inline int handle_perf_irq (int r2) |
| 82 | { |
| 83 | /* |
| 84 | * The performance counter overflow interrupt may be shared with the |
| 85 | * timer interrupt (mipsxx_perfcount_irq < 0). If it is and a |
| 86 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) |
| 87 | * and we can't reliably determine if a counter interrupt has also |
| 88 | * happened (!r2) then don't check for a timer interrupt. |
| 89 | */ |
| 90 | return (mipsxx_perfcount_irq < 0) && |
| 91 | perf_irq() == IRQ_HANDLED && |
| 92 | !r2; |
| 93 | } |
| 94 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 95 | irqreturn_t mips_timer_interrupt(int irq, void *dev_id) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 96 | { |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 97 | int cpu = smp_processor_id(); |
| 98 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 99 | #ifdef CONFIG_MIPS_MT_SMTC |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 100 | /* |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 101 | * In an SMTC system, one Count/Compare set exists per VPE. |
| 102 | * Which TC within a VPE gets the interrupt is essentially |
| 103 | * random - we only know that it shouldn't be one with |
| 104 | * IXMT set. Whichever TC gets the interrupt needs to |
| 105 | * send special interprocessor interrupts to the other |
| 106 | * TCs to make sure that they schedule, etc. |
| 107 | * |
| 108 | * That code is specific to the SMTC kernel, not to |
| 109 | * the a particular platform, so it's invoked from |
| 110 | * the general MIPS timer_interrupt routine. |
| 111 | */ |
| 112 | |
| 113 | /* |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 114 | * We could be here due to timer interrupt, |
| 115 | * perf counter overflow, or both. |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 116 | */ |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 117 | (void) handle_perf_irq(1); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 118 | |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 119 | if (read_c0_cause() & (1 << 30)) { |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 120 | /* |
| 121 | * There are things we only want to do once per tick |
| 122 | * in an "MP" system. One TC of each VPE will take |
| 123 | * the actual timer interrupt. The others will get |
| 124 | * timer broadcast IPIs. We use whoever it is that takes |
| 125 | * the tick on VPE 0 to run the full timer_interrupt(). |
| 126 | */ |
| 127 | if (cpu_data[cpu].vpe_id == 0) { |
Chris Dearman | cf75789 | 2007-05-29 20:01:55 +0100 | [diff] [blame] | 128 | timer_interrupt(irq, NULL); |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 129 | } else { |
| 130 | write_c0_compare(read_c0_count() + |
| 131 | (mips_hpt_frequency/HZ)); |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 132 | local_timer_interrupt(irq, dev_id); |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 133 | } |
Chris Dearman | cf75789 | 2007-05-29 20:01:55 +0100 | [diff] [blame] | 134 | smtc_timer_broadcast(cpu_data[cpu].vpe_id); |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 135 | } |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 136 | #else /* CONFIG_MIPS_MT_SMTC */ |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 137 | int r2 = cpu_has_mips_r2; |
| 138 | |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 139 | if (handle_perf_irq(r2)) |
| 140 | goto out; |
| 141 | |
| 142 | if (r2 && ((read_c0_cause() & (1 << 30)) == 0)) |
| 143 | goto out; |
| 144 | |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 145 | if (cpu == 0) { |
| 146 | /* |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 147 | * CPU 0 handles the global timer interrupt job and process |
| 148 | * accounting resets count/compare registers to trigger next |
| 149 | * timer int. |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 150 | */ |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 151 | timer_interrupt(irq, NULL); |
Ralf Baechle | 11e6df6 | 2005-12-09 12:09:22 +0000 | [diff] [blame] | 152 | } else { |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 153 | /* Everyone else needs to reset the timer int here as |
| 154 | ll_local_timer_interrupt doesn't */ |
| 155 | /* |
| 156 | * FIXME: need to cope with counter underflow. |
| 157 | * More support needs to be added to kernel/time for |
| 158 | * counter/timer interrupts on multiple CPU's |
| 159 | */ |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 160 | write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ)); |
| 161 | |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 162 | /* |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 163 | * Other CPUs should do profiling and process accounting |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 164 | */ |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 165 | local_timer_interrupt(irq, dev_id); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 166 | } |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 167 | out: |
Kevin D. Kissell | 846acaa | 2006-09-12 12:08:08 +0200 | [diff] [blame] | 168 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 169 | return IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* |
Ralf Baechle | 224dc50 | 2006-10-21 02:05:20 +0100 | [diff] [blame] | 173 | * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | */ |
| 175 | static unsigned int __init estimate_cpu_frequency(void) |
| 176 | { |
| 177 | unsigned int prid = read_c0_prid() & 0xffff00; |
| 178 | unsigned int count; |
| 179 | |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 180 | #if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | /* |
| 182 | * The SEAD board doesn't have a real time clock, so we can't |
| 183 | * really calculate the timer frequency |
| 184 | * For now we hardwire the SEAD board frequency to 12MHz. |
| 185 | */ |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 186 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || |
| 188 | (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) |
| 189 | count = 12000000; |
| 190 | else |
| 191 | count = 6000000; |
| 192 | #endif |
| 193 | #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) |
Ralf Baechle | e79f55a | 2006-10-31 19:53:15 +0000 | [diff] [blame] | 194 | unsigned long flags; |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 195 | unsigned int start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | |
| 197 | local_irq_save(flags); |
| 198 | |
| 199 | /* Start counter exactly on falling edge of update flag */ |
| 200 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
| 201 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
| 202 | |
| 203 | /* Start r4k counter. */ |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 204 | start = read_c0_count(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | |
| 206 | /* Read counter exactly on falling edge of update flag */ |
| 207 | while (CMOS_READ(RTC_REG_A) & RTC_UIP); |
| 208 | while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); |
| 209 | |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 210 | count = read_c0_count() - start; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | |
| 212 | /* restore interrupts */ |
| 213 | local_irq_restore(flags); |
| 214 | #endif |
| 215 | |
| 216 | mips_hpt_frequency = count; |
| 217 | if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && |
| 218 | (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) |
| 219 | count *= 2; |
| 220 | |
| 221 | count += 5000; /* round */ |
| 222 | count -= count%10000; |
| 223 | |
| 224 | return count; |
| 225 | } |
| 226 | |
| 227 | unsigned long __init mips_rtc_get_time(void) |
| 228 | { |
| 229 | return mc146818_get_cmos_time(); |
| 230 | } |
| 231 | |
| 232 | void __init mips_time_init(void) |
| 233 | { |
Ralf Baechle | ece2246 | 2006-07-09 22:27:23 +0100 | [diff] [blame] | 234 | unsigned int est_freq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | /* Set Data mode - binary. */ |
| 237 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | |
| 239 | est_freq = estimate_cpu_frequency (); |
| 240 | |
| 241 | printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, |
| 242 | (est_freq%1000000)*100/1000000); |
| 243 | |
| 244 | cpu_khz = est_freq / 1000; |
Ralf Baechle | 79894c7 | 2007-05-16 17:54:08 +0200 | [diff] [blame] | 245 | |
| 246 | mips_scroll_message(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | } |
| 248 | |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 249 | irqreturn_t mips_perf_interrupt(int irq, void *dev_id) |
| 250 | { |
| 251 | return perf_irq(); |
| 252 | } |
| 253 | |
| 254 | static struct irqaction perf_irqaction = { |
| 255 | .handler = mips_perf_interrupt, |
| 256 | .flags = IRQF_DISABLED | IRQF_PERCPU, |
| 257 | .name = "performance", |
| 258 | }; |
| 259 | |
| 260 | void __init plat_perf_setup(struct irqaction *irq) |
| 261 | { |
| 262 | int hwint = 0; |
| 263 | mipsxx_perfcount_irq = -1; |
| 264 | |
| 265 | #ifdef MSC01E_INT_BASE |
| 266 | if (cpu_has_veic) { |
| 267 | set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); |
| 268 | mipsxx_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; |
| 269 | } else |
| 270 | #endif |
| 271 | if (cpu_has_mips_r2) { |
| 272 | /* |
| 273 | * Read IntCtl.IPPCI to determine the performance |
| 274 | * counter interrupt |
| 275 | */ |
| 276 | hwint = (read_c0_intctl () >> 26) & 7; |
| 277 | if (hwint != MIPSCPU_INT_CPUCTR) { |
| 278 | if (cpu_has_vint) |
| 279 | set_vi_handler (hwint, mips_perf_dispatch); |
| 280 | mipsxx_perfcount_irq = MIPSCPU_INT_BASE + hwint; |
| 281 | } |
| 282 | } |
| 283 | if (mipsxx_perfcount_irq >= 0) { |
| 284 | #ifdef CONFIG_MIPS_MT_SMTC |
| 285 | setup_irq_smtc(mipsxx_perfcount_irq, irq, 0x100 << hwint); |
| 286 | #else |
| 287 | setup_irq(mipsxx_perfcount_irq, irq); |
| 288 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 289 | #ifdef CONFIG_SMP |
| 290 | set_irq_handler(mipsxx_perfcount_irq, handle_percpu_irq); |
| 291 | #endif |
| 292 | } |
| 293 | } |
| 294 | |
Ralf Baechle | 54d0a21 | 2006-07-09 21:38:56 +0100 | [diff] [blame] | 295 | void __init plat_timer_setup(struct irqaction *irq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | { |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 297 | int hwint = 0; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 298 | if (cpu_has_veic) { |
| 299 | set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); |
| 300 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 301 | } |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 302 | else { |
| 303 | if (cpu_has_mips_r2) |
| 304 | /* |
| 305 | * Read IntCtl.IPTI to determine the timer interrupt |
| 306 | */ |
| 307 | hwint = (read_c0_intctl () >> 29) & 7; |
| 308 | else |
| 309 | hwint = MIPSCPU_INT_CPUCTR; |
| 310 | if (cpu_has_vint) |
| 311 | set_vi_handler (hwint, mips_timer_dispatch); |
| 312 | mips_cpu_timer_irq = MIPSCPU_INT_BASE + hwint; |
| 313 | } |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 314 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | /* we are using the cpu counter for timer interrupts */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 316 | irq->handler = mips_timer_interrupt; /* we use our own handler */ |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 317 | #ifdef CONFIG_MIPS_MT_SMTC |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 318 | setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << hwint); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 319 | #else |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 320 | setup_irq(mips_cpu_timer_irq, irq); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 321 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 322 | #ifdef CONFIG_SMP |
Atsushi Nemoto | 1417836 | 2006-11-14 01:13:18 +0900 | [diff] [blame] | 323 | set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 324 | #endif |
Chris Dearman | ffe9ee4 | 2007-05-24 22:24:20 +0100 | [diff] [blame^] | 325 | |
| 326 | plat_perf_setup(&perf_irqaction); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | } |