| commit | fce18fe8a3c6989736f491144a1db1602034a946 | [log] [tgz] |
|---|---|---|
| author | Artem Serov <artem.serov@linaro.org> | Mon Jul 11 14:00:46 2016 +0100 |
| committer | Meninblack007 <sanyam.53jain@gmail.com> | Thu Jun 15 18:13:27 2017 +0530 |
| tree | f36ede911525e6970486a1ae64dde540a2e7ddf7 | |
| parent | 15a2eb0de3e5d66595350426bdd50905c46a0fb0 [diff] |
ARM: Fix shifted register offset mem address mode for load signed. For example 'ldrsh r0, [sp, r1, LSL #2]' previously was assembled as 'ldrh'. Test: New test in assembler_thumb2_test.cc . Change-Id: I1d30724f0c2745b131876bffefdc0a780d76f6a1